sys/dev/drm2/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <dev/drm2/drmP.h>
  31 #include <dev/drm2/drm.h>
  32 #include <dev/drm2/i915/i915_drm.h>
  33 #include <dev/drm2/i915/i915_drv.h>
  34 #include <dev/drm2/i915/intel_drv.h>
  35 #include <dev/drm2/drm_edid.h>
  36 #include <dev/drm2/drm_dp_helper.h>
  37 #include <dev/drm2/drm_crtc_helper.h>
  38 #include <sys/limits.h>
  39
  40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41
  42 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc);
  44 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45
  46 typedef struct {
  47         /* given values */
  48         int n;
  49         int m1, m2;
  50         int p1, p2;
  51         /* derived values */
  52         int     dot;
  53         int     vco;
  54         int     m;
  55         int     p;
  56 } intel_clock_t;
  57
  58 typedef struct {
  59         int     min, max;
  60 } intel_range_t;
  61
  62 typedef struct {
  63         int     dot_limit;
  64         int     p2_slow, p2_fast;
  65 } intel_p2_t;
  66
  67 #define INTEL_P2_NUM                  2
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  73                         int, int, intel_clock_t *, intel_clock_t *);
  74 };
  75
  76 /* FDI */
  77 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  78
  79 static bool
  80 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  81                     int target, int refclk, intel_clock_t *match_clock,
  82                     intel_clock_t *best_clock);
  83 static bool
  84 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                         int target, int refclk, intel_clock_t *match_clock,
  86                         intel_clock_t *best_clock);
  87
  88 static bool
  89 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  90                       int target, int refclk, intel_clock_t *match_clock,
  91                       intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *match_clock,
  95                            intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2, .max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 359 {
 360         u32 val = 0;
 361
 362         mtx_lock(&dev_priv->dpio_lock);
 363         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 364                 DRM_ERROR("DPIO idle wait timed out\n");
 365                 goto out_unlock;
 366         }
 367
 368         I915_WRITE(DPIO_REG, reg);
 369         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 370                    DPIO_BYTE);
 371         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 372                 DRM_ERROR("DPIO read wait timed out\n");
 373                 goto out_unlock;
 374         }
 375         val = I915_READ(DPIO_DATA);
 376
 377 out_unlock:
 378         mtx_unlock(&dev_priv->dpio_lock);
 379         return val;
 380 }
 381
 382 #if 0
 383 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 384                              u32 val)
 385 {
 386
 387         mtx_lock(&dev_priv->dpio_lock);
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 goto out_unlock;
 391         }
 392
 393         I915_WRITE(DPIO_DATA, val);
 394         I915_WRITE(DPIO_REG, reg);
 395         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 396                    DPIO_BYTE);
 397         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 398                 DRM_ERROR("DPIO write wait timed out\n");
 399
 400 out_unlock:
 401         mtx_unlock(&dev_priv->dpio_lock);
 402 }
 403 #endif
 404
 405 static void vlv_init_dpio(struct drm_device *dev)
 406 {
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408
 409         /* Reset the DPIO config */
 410         I915_WRITE(DPIO_CTL, 0);
 411         POSTING_READ(DPIO_CTL);
 412         I915_WRITE(DPIO_CTL, 1);
 413         POSTING_READ(DPIO_CTL);
 414 }
 415
 416 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 417 {
 418         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 419         return 1;
 420 }
 421
 422 static const struct dmi_system_id intel_dual_link_lvds[] = {
 423         {
 424                 .callback = intel_dual_link_lvds_callback,
 425                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 426                 .matches = {
 427                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 428                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 429                 },
 430         },
 431         { }     /* terminating entry */
 432 };
 433
 434 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 435                               unsigned int reg)
 436 {
 437         unsigned int val;
 438
 439         /* use the module option value if specified */
 440         if (i915_lvds_channel_mode > 0)
 441                 return i915_lvds_channel_mode == 2;
 442
 443         if (dmi_check_system(intel_dual_link_lvds))
 444                 return true;
 445
 446         if (dev_priv->lvds_val)
 447                 val = dev_priv->lvds_val;
 448         else {
 449                 /* BIOS should set the proper LVDS register value at boot, but
 450                  * in reality, it doesn't set the value when the lid is closed;
 451                  * we need to check "the value to be set" in VBT when LVDS
 452                  * register is uninitialized.
 453                  */
 454                 val = I915_READ(reg);
 455                 if (!(val & ~LVDS_DETECTED))
 456                         val = dev_priv->bios_lvds_val;
 457                 dev_priv->lvds_val = val;
 458         }
 459         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 460 }
 461
 462 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 463                                                 int refclk)
 464 {
 465         struct drm_device *dev = crtc->dev;
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467         const intel_limit_t *limit;
 468
 469         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 470                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 471                         /* LVDS dual channel */
 472                         if (refclk == 100000)
 473                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 474                         else
 475                                 limit = &intel_limits_ironlake_dual_lvds;
 476                 } else {
 477                         if (refclk == 100000)
 478                                 limit = &intel_limits_ironlake_single_lvds_100m;
 479                         else
 480                                 limit = &intel_limits_ironlake_single_lvds;
 481                 }
 482         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 483                         HAS_eDP)
 484                 limit = &intel_limits_ironlake_display_port;
 485         else
 486                 limit = &intel_limits_ironlake_dac;
 487
 488         return limit;
 489 }
 490
 491 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 492 {
 493         struct drm_device *dev = crtc->dev;
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495         const intel_limit_t *limit;
 496
 497         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 498                 if (is_dual_link_lvds(dev_priv, LVDS))
 499                         /* LVDS with dual channel */
 500                         limit = &intel_limits_g4x_dual_channel_lvds;
 501                 else
 502                         /* LVDS with dual channel */
 503                         limit = &intel_limits_g4x_single_channel_lvds;
 504         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 505                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 506                 limit = &intel_limits_g4x_hdmi;
 507         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 508                 limit = &intel_limits_g4x_sdvo;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 510                 limit = &intel_limits_g4x_display_port;
 511         } else /* The option is for other outputs */
 512                 limit = &intel_limits_i9xx_sdvo;
 513
 514         return limit;
 515 }
 516
 517 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         const intel_limit_t *limit;
 521
 522         if (HAS_PCH_SPLIT(dev))
 523                 limit = intel_ironlake_limit(crtc, refclk);
 524         else if (IS_G4X(dev)) {
 525                 limit = intel_g4x_limit(crtc);
 526         } else if (IS_PINEVIEW(dev)) {
 527                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 528                         limit = &intel_limits_pineview_lvds;
 529                 else
 530                         limit = &intel_limits_pineview_sdvo;
 531         } else if (!IS_GEN2(dev)) {
 532                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 533                         limit = &intel_limits_i9xx_lvds;
 534                 else
 535                         limit = &intel_limits_i9xx_sdvo;
 536         } else {
 537                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 538                         limit = &intel_limits_i8xx_lvds;
 539                 else
 540                         limit = &intel_limits_i8xx_dvo;
 541         }
 542         return limit;
 543 }
 544
 545 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 546 static void pineview_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m2 + 2;
 549         clock->p = clock->p1 * clock->p2;
 550         clock->vco = refclk * clock->m / clock->n;
 551         clock->dot = clock->vco / clock->p;
 552 }
 553
 554 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 555 {
 556         if (IS_PINEVIEW(dev)) {
 557                 pineview_clock(refclk, clock);
 558                 return;
 559         }
 560         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 561         clock->p = clock->p1 * clock->p2;
 562         clock->vco = refclk * clock->m / (clock->n + 2);
 563         clock->dot = clock->vco / clock->p;
 564 }
 565
 566 /**
 567  * Returns whether any output on the specified pipe is of the specified type
 568  */
 569 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 570 {
 571         struct drm_device *dev = crtc->dev;
 572         struct drm_mode_config *mode_config = &dev->mode_config;
 573         struct intel_encoder *encoder;
 574
 575         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 576                 if (encoder->base.crtc == crtc && encoder->type == type)
 577                         return true;
 578
 579         return false;
 580 }
 581
 582 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 583 /**
 584  * Returns whether the given set of divisors are valid for a given refclk with
 585  * the given connectors.
 586  */
 587
 588 static bool intel_PLL_is_valid(struct drm_device *dev,
 589                                const intel_limit_t *limit,
 590                                const intel_clock_t *clock)
 591 {
 592         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 593                 INTELPllInvalid("p1 out of range\n");
 594         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 595                 INTELPllInvalid("p out of range\n");
 596         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 597                 INTELPllInvalid("m2 out of range\n");
 598         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 599                 INTELPllInvalid("m1 out of range\n");
 600         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 601                 INTELPllInvalid("m1 <= m2\n");
 602         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 603                 INTELPllInvalid("m out of range\n");
 604         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 605                 INTELPllInvalid("n out of range\n");
 606         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 607                 INTELPllInvalid("vco out of range\n");
 608         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 609          * connector, etc., rather than just a single range.
 610          */
 611         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 612                 INTELPllInvalid("dot out of range\n");
 613
 614         return true;
 615 }
 616
 617 static bool
 618 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                     int target, int refclk, intel_clock_t *match_clock,
 620                     intel_clock_t *best_clock)
 621
 622 {
 623         struct drm_device *dev = crtc->dev;
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         intel_clock_t clock;
 626         int err = target;
 627
 628         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 629             (I915_READ(LVDS)) != 0) {
 630                 /*
 631                  * For LVDS, if the panel is on, just rely on its current
 632                  * settings for dual-channel.  We haven't figured out how to
 633                  * reliably set up different single/dual channel state, if we
 634                  * even can.
 635                  */
 636                 if (is_dual_link_lvds(dev_priv, LVDS))
 637                         clock.p2 = limit->p2.p2_fast;
 638                 else
 639                         clock.p2 = limit->p2.p2_slow;
 640         } else {
 641                 if (target < limit->p2.dot_limit)
 642                         clock.p2 = limit->p2.p2_slow;
 643                 else
 644                         clock.p2 = limit->p2.p2_fast;
 645         }
 646
 647         memset(best_clock, 0, sizeof(*best_clock));
 648
 649         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 650              clock.m1++) {
 651                 for (clock.m2 = limit->m2.min;
 652                      clock.m2 <= limit->m2.max; clock.m2++) {
 653                         /* m1 is always 0 in Pineview */
 654                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 655                                 break;
 656                         for (clock.n = limit->n.min;
 657                              clock.n <= limit->n.max; clock.n++) {
 658                                 for (clock.p1 = limit->p1.min;
 659                                         clock.p1 <= limit->p1.max; clock.p1++) {
 660                                         int this_err;
 661
 662                                         intel_clock(dev, refclk, &clock);
 663                                         if (!intel_PLL_is_valid(dev, limit,
 664                                                                 &clock))
 665                                                 continue;
 666                                         if (match_clock &&
 667                                             clock.p != match_clock->p)
 668                                                 continue;
 669
 670                                         this_err = abs(clock.dot - target);
 671                                         if (this_err < err) {
 672                                                 *best_clock = clock;
 673                                                 err = this_err;
 674                                         }
 675                                 }
 676                         }
 677                 }
 678         }
 679
 680         return (err != target);
 681 }
 682
 683 static bool
 684 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 685                         int target, int refclk, intel_clock_t *match_clock,
 686                         intel_clock_t *best_clock)
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         intel_clock_t clock;
 691         int max_n;
 692         bool found;
 693         /* approximately equals target * 0.00585 */
 694         int err_most = (target >> 8) + (target >> 9);
 695         found = false;
 696
 697         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 698                 int lvds_reg;
 699
 700                 if (HAS_PCH_SPLIT(dev))
 701                         lvds_reg = PCH_LVDS;
 702                 else
 703                         lvds_reg = LVDS;
 704                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 705                     LVDS_CLKB_POWER_UP)
 706                         clock.p2 = limit->p2.p2_fast;
 707                 else
 708                         clock.p2 = limit->p2.p2_slow;
 709         } else {
 710                 if (target < limit->p2.dot_limit)
 711                         clock.p2 = limit->p2.p2_slow;
 712                 else
 713                         clock.p2 = limit->p2.p2_fast;
 714         }
 715
 716         memset(best_clock, 0, sizeof(*best_clock));
 717         max_n = limit->n.max;
 718         /* based on hardware requirement, prefer smaller n to precision */
 719         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 720                 /* based on hardware requirement, prefere larger m1,m2 */
 721                 for (clock.m1 = limit->m1.max;
 722                      clock.m1 >= limit->m1.min; clock.m1--) {
 723                         for (clock.m2 = limit->m2.max;
 724                              clock.m2 >= limit->m2.min; clock.m2--) {
 725                                 for (clock.p1 = limit->p1.max;
 726                                      clock.p1 >= limit->p1.min; clock.p1--) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err_most) {
 739                                                 *best_clock = clock;
 740                                                 err_most = this_err;
 741                                                 max_n = clock.n;
 742                                                 found = true;
 743                                         }
 744                                 }
 745                         }
 746                 }
 747         }
 748         return found;
 749 }
 750
 751 static bool
 752 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 753                            int target, int refclk, intel_clock_t *match_clock,
 754                            intel_clock_t *best_clock)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         intel_clock_t clock;
 758
 759         if (target < 200000) {
 760                 clock.n = 1;
 761                 clock.p1 = 2;
 762                 clock.p2 = 10;
 763                 clock.m1 = 12;
 764                 clock.m2 = 9;
 765         } else {
 766                 clock.n = 2;
 767                 clock.p1 = 1;
 768                 clock.p2 = 10;
 769                 clock.m1 = 14;
 770                 clock.m2 = 8;
 771         }
 772         intel_clock(dev, refclk, &clock);
 773         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 774         return true;
 775 }
 776
 777 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 778 static bool
 779 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 780                       int target, int refclk, intel_clock_t *match_clock,
 781                       intel_clock_t *best_clock)
 782 {
 783         intel_clock_t clock;
 784         if (target < 200000) {
 785                 clock.p1 = 2;
 786                 clock.p2 = 10;
 787                 clock.n = 2;
 788                 clock.m1 = 23;
 789                 clock.m2 = 8;
 790         } else {
 791                 clock.p1 = 1;
 792                 clock.p2 = 10;
 793                 clock.n = 1;
 794                 clock.m1 = 14;
 795                 clock.m2 = 2;
 796         }
 797         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 798         clock.p = (clock.p1 * clock.p2);
 799         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 800         clock.vco = 0;
 801         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 802         return true;
 803 }
 804
 805 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         u32 frame, frame_reg = PIPEFRAME(pipe);
 809
 810         frame = I915_READ(frame_reg);
 811
 812         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 813                 DRM_DEBUG_KMS("vblank wait timed out\n");
 814 }
 815
 816 /**
 817  * intel_wait_for_vblank - wait for vblank on a given pipe
 818  * @dev: drm device
 819  * @pipe: pipe to wait for
 820  *
 821  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 822  * mode setting code.
 823  */
 824 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 825 {
 826         struct drm_i915_private *dev_priv = dev->dev_private;
 827         int pipestat_reg = PIPESTAT(pipe);
 828
 829         if (INTEL_INFO(dev)->gen >= 5) {
 830                 ironlake_wait_for_vblank(dev, pipe);
 831                 return;
 832         }
 833
 834         /* Clear existing vblank status. Note this will clear any other
 835          * sticky status fields as well.
 836          *
 837          * This races with i915_driver_irq_handler() with the result
 838          * that either function could miss a vblank event.  Here it is not
 839          * fatal, as we will either wait upon the next vblank interrupt or
 840          * timeout.  Generally speaking intel_wait_for_vblank() is only
 841          * called during modeset at which time the GPU should be idle and
 842          * should *not* be performing page flips and thus not waiting on
 843          * vblanks...
 844          * Currently, the result of us stealing a vblank from the irq
 845          * handler is that a single frame will be skipped during swapbuffers.
 846          */
 847         I915_WRITE(pipestat_reg,
 848                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 849
 850         /* Wait for vblank interrupt bit to set */
 851         if (_intel_wait_for(dev,
 852             I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
 853             50, 1, "915vbl"))
 854                 DRM_DEBUG_KMS("vblank wait timed out\n");
 855 }
 856
 857 /*
 858  * intel_wait_for_pipe_off - wait for pipe to turn off
 859  * @dev: drm device
 860  * @pipe: pipe to wait for
 861  *
 862  * After disabling a pipe, we can't wait for vblank in the usual way,
 863  * spinning on the vblank interrupt status bit, since we won't actually
 864  * see an interrupt when the pipe is disabled.
 865  *
 866  * On Gen4 and above:
 867  *   wait for the pipe register state bit to turn off
 868  *
 869  * Otherwise:
 870  *   wait for the display line value to settle (it usually
 871  *   ends up stopping at the start of the next frame).
 872  *
 873  */
 874 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 875 {
 876         struct drm_i915_private *dev_priv = dev->dev_private;
 877
 878         if (INTEL_INFO(dev)->gen >= 4) {
 879                 int reg = PIPECONF(pipe);
 880
 881                 /* Wait for the Pipe State to go off */
 882                 if (_intel_wait_for(dev,
 883                     (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
 884                     1, "915pip"))
 885                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 886         } else {
 887                 u32 last_line, line_mask;
 888                 int reg = PIPEDSL(pipe);
 889                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 890
 891                 if (IS_GEN2(dev))
 892                         line_mask = DSL_LINEMASK_GEN2;
 893                 else
 894                         line_mask = DSL_LINEMASK_GEN3;
 895
 896                 /* Wait for the display line to settle */
 897                 do {
 898                         last_line = I915_READ(reg) & line_mask;
 899                         DELAY(5000);
 900                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 901                          time_after(timeout, jiffies));
 902                 if (time_after(jiffies, timeout))
 903                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 904         }
 905 }
 906
 907 static const char *state_string(bool enabled)
 908 {
 909         return enabled ? "on" : "off";
 910 }
 911
 912 /* Only for pre-ILK configs */
 913 static void assert_pll(struct drm_i915_private *dev_priv,
 914                        enum pipe pipe, bool state)
 915 {
 916         int reg;
 917         u32 val;
 918         bool cur_state;
 919
 920         reg = DPLL(pipe);
 921         val = I915_READ(reg);
 922         cur_state = !!(val & DPLL_VCO_ENABLE);
 923         if (cur_state != state)
 924                 printf("PLL state assertion failure (expected %s, current %s)\n",
 925                     state_string(state), state_string(cur_state));
 926 }
 927 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 928 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 929
 930 /* For ILK+ */
 931 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 932                            struct intel_crtc *intel_crtc,
 933                            bool state)
 934 {
 935         int reg;
 936         u32 val;
 937         bool cur_state;
 938
 939         if (HAS_PCH_LPT(dev_priv->dev)) {
 940                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 941                 return;
 942         }
 943
 944         if (!intel_crtc->pch_pll) {
 945                 printf("asserting PCH PLL enabled with no PLL\n");
 946                 return;
 947         }
 948
 949         if (HAS_PCH_CPT(dev_priv->dev)) {
 950                 u32 pch_dpll;
 951
 952                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 953
 954                 /* Make sure the selected PLL is enabled to the transcoder */
 955                 KASSERT(((pch_dpll >> (4 * intel_crtc->pipe)) & 8) != 0,
 956                     ("transcoder %d PLL not enabled\n", intel_crtc->pipe));
 957         }
 958
 959         reg = intel_crtc->pch_pll->pll_reg;
 960         val = I915_READ(reg);
 961         cur_state = !!(val & DPLL_VCO_ENABLE);
 962         if (cur_state != state)
 963                 printf("PCH PLL state assertion failure (expected %s, current %s)\n",
 964                     state_string(state), state_string(cur_state));
 965 }
 966 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 967 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 968
 969 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 970                           enum pipe pipe, bool state)
 971 {
 972         int reg;
 973         u32 val;
 974         bool cur_state;
 975
 976         if (IS_HASWELL(dev_priv->dev)) {
 977                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
 978                 reg = TRANS_DDI_FUNC_CTL(pipe);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 981         } else {
 982                 reg = FDI_TX_CTL(pipe);
 983                 val = I915_READ(reg);
 984                 cur_state = !!(val & FDI_TX_ENABLE);
 985         }
 986         if (cur_state != state)
 987                 printf("FDI TX state assertion failure (expected %s, current %s)\n",
 988                     state_string(state), state_string(cur_state));
 989 }
 990 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 991 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 992
 993 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 994                           enum pipe pipe, bool state)
 995 {
 996         int reg;
 997         u32 val;
 998         bool cur_state;
 999
1000         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1001                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1002                         return;
1003         } else {
1004                 reg = FDI_RX_CTL(pipe);
1005                 val = I915_READ(reg);
1006                 cur_state = !!(val & FDI_RX_ENABLE);
1007         }
1008         if (cur_state != state)
1009                 printf("FDI RX state assertion failure (expected %s, current %s)\n",
1010                     state_string(state), state_string(cur_state));
1011 }
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016                                       enum pipe pipe)
1017 {
1018         int reg;
1019         u32 val;
1020
1021         /* ILK FDI PLL is always enabled */
1022         if (dev_priv->info->gen == 5)
1023                 return;
1024
1025         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026         if (IS_HASWELL(dev_priv->dev))
1027                 return;
1028
1029         reg = FDI_TX_CTL(pipe);
1030         val = I915_READ(reg);
1031         if (!(val & FDI_TX_PLL_ENABLE))
1032                 printf("FDI TX PLL assertion failure, should be active but is disabled\n");
1033 }
1034
1035 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1036                                       enum pipe pipe)
1037 {
1038         int reg;
1039         u32 val;
1040
1041         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1042                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1043                 return;
1044         }
1045         reg = FDI_RX_CTL(pipe);
1046         val = I915_READ(reg);
1047         if (!(val & FDI_RX_PLL_ENABLE))
1048                 printf("FDI RX PLL assertion failure, should be active but is disabled\n");
1049 }
1050
1051 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1052                                   enum pipe pipe)
1053 {
1054         int pp_reg, lvds_reg;
1055         u32 val;
1056         enum pipe panel_pipe = PIPE_A;
1057         bool locked = true;
1058
1059         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1060                 pp_reg = PCH_PP_CONTROL;
1061                 lvds_reg = PCH_LVDS;
1062         } else {
1063                 pp_reg = PP_CONTROL;
1064                 lvds_reg = LVDS;
1065         }
1066
1067         val = I915_READ(pp_reg);
1068         if (!(val & PANEL_POWER_ON) ||
1069             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1070                 locked = false;
1071
1072         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1073                 panel_pipe = PIPE_B;
1074
1075         if (panel_pipe == pipe && locked)
1076                 printf("panel assertion failure, pipe %c regs locked\n",
1077              pipe_name(pipe));
1078 }
1079
1080 void assert_pipe(struct drm_i915_private *dev_priv,
1081                  enum pipe pipe, bool state)
1082 {
1083         int reg;
1084         u32 val;
1085         bool cur_state;
1086
1087         /* if we need the pipe A quirk it must be always on */
1088         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1089                 state = true;
1090
1091         reg = PIPECONF(pipe);
1092         val = I915_READ(reg);
1093         cur_state = !!(val & PIPECONF_ENABLE);
1094         if (cur_state != state)
1095                 printf("pipe %c assertion failure (expected %s, current %s)\n",
1096                     pipe_name(pipe), state_string(state), state_string(cur_state));
1097 }
1098
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100                          enum plane plane, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105
1106         reg = DSPCNTR(plane);
1107         val = I915_READ(reg);
1108         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109         if (cur_state != state)
1110                 printf("plane %c assertion failure, (expected %s, current %s)\n",
1111                        plane_name(plane), state_string(state), state_string(cur_state));
1112 }
1113
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118                                    enum pipe pipe)
1119 {
1120         int reg, i;
1121         u32 val;
1122         int cur_pipe;
1123
1124         /* Planes are fixed to pipes on ILK+ */
1125         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1126                 reg = DSPCNTR(pipe);
1127                 val = I915_READ(reg);
1128                 if ((val & DISPLAY_PLANE_ENABLE) != 0)
1129                         printf("plane %c assertion failure, should be disabled but not\n",
1130                                plane_name(pipe));
1131                 return;
1132         }
1133
1134         /* Need to check both planes against the pipe */
1135         for (i = 0; i < 2; i++) {
1136                 reg = DSPCNTR(i);
1137                 val = I915_READ(reg);
1138                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1139                         DISPPLANE_SEL_PIPE_SHIFT;
1140                 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1141                         printf("plane %c assertion failure, should be off on pipe %c but is still active\n",
1142                      plane_name(i), pipe_name(pipe));
1143         }
1144 }
1145
1146 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1147 {
1148         u32 val;
1149         bool enabled;
1150
1151         if (HAS_PCH_LPT(dev_priv->dev)) {
1152                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1153                 return;
1154         }
1155
1156         val = I915_READ(PCH_DREF_CONTROL);
1157         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1158                             DREF_SUPERSPREAD_SOURCE_MASK));
1159         if (!enabled)
1160                 printf("PCH refclk assertion failure, should be active but is disabled\n");
1161 }
1162
1163 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1164                                        enum pipe pipe)
1165 {
1166         int reg;
1167         u32 val;
1168         bool enabled;
1169
1170         reg = TRANSCONF(pipe);
1171         val = I915_READ(reg);
1172         enabled = !!(val & TRANS_ENABLE);
1173         if (enabled)
1174                 printf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1179                             enum pipe pipe, u32 port_sel, u32 val)
1180 {
1181         if ((val & DP_PORT_EN) == 0)
1182                 return false;
1183
1184         if (HAS_PCH_CPT(dev_priv->dev)) {
1185                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1186                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1187                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1188                         return false;
1189         } else {
1190                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1191                         return false;
1192         }
1193         return true;
1194 }
1195
1196 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1197                               enum pipe pipe, u32 val)
1198 {
1199         if ((val & PORT_ENABLE) == 0)
1200                 return false;
1201
1202         if (HAS_PCH_CPT(dev_priv->dev)) {
1203                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1204                         return false;
1205         } else {
1206                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1207                         return false;
1208         }
1209         return true;
1210 }
1211
1212 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1213                               enum pipe pipe, u32 val)
1214 {
1215         if ((val & LVDS_PORT_EN) == 0)
1216                 return false;
1217
1218         if (HAS_PCH_CPT(dev_priv->dev)) {
1219                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1220                         return false;
1221         } else {
1222                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1223                         return false;
1224         }
1225         return true;
1226 }
1227
1228 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1229                               enum pipe pipe, u32 val)
1230 {
1231         if ((val & ADPA_DAC_ENABLE) == 0)
1232                 return false;
1233         if (HAS_PCH_CPT(dev_priv->dev)) {
1234                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1235                         return false;
1236         } else {
1237                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1238                         return false;
1239         }
1240         return true;
1241 }
1242
1243 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1244                                    enum pipe pipe, int reg, u32 port_sel)
1245 {
1246         u32 val = I915_READ(reg);
1247         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1248                 printf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1249              reg, pipe_name(pipe));
1250 }
1251
1252 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1253                                      enum pipe pipe, int reg)
1254 {
1255         u32 val = I915_READ(reg);
1256         if (hdmi_pipe_enabled(dev_priv, val, pipe))
1257                 printf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1258              reg, pipe_name(pipe));
1259 }
1260
1261 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1262                                       enum pipe pipe)
1263 {
1264         int reg;
1265         u32 val;
1266
1267         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1268         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1269         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1270
1271         reg = PCH_ADPA;
1272         val = I915_READ(reg);
1273         if (adpa_pipe_enabled(dev_priv, val, pipe))
1274                 printf("PCH VGA enabled on transcoder %c, should be disabled\n",
1275              pipe_name(pipe));
1276
1277         reg = PCH_LVDS;
1278         val = I915_READ(reg);
1279         if (lvds_pipe_enabled(dev_priv, val, pipe))
1280                 printf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1281              pipe_name(pipe));
1282
1283         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1284         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1285         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1286 }
1287
1288 /**
1289  * intel_enable_pll - enable a PLL
1290  * @dev_priv: i915 private structure
1291  * @pipe: pipe PLL to enable
1292  *
1293  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1294  * make sure the PLL reg is writable first though, since the panel write
1295  * protect mechanism may be enabled.
1296  *
1297  * Note!  This is for pre-ILK only.
1298  */
1299 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1300 {
1301         int reg;
1302         u32 val;
1303
1304         /* No really, not for ILK+ */
1305         KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1306
1307         /* PLL is protected by panel, make sure we can write it */
1308         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1309                 assert_panel_unlocked(dev_priv, pipe);
1310
1311         reg = DPLL(pipe);
1312         val = I915_READ(reg);
1313         val |= DPLL_VCO_ENABLE;
1314
1315         /* We do this three times for luck */
1316         I915_WRITE(reg, val);
1317         POSTING_READ(reg);
1318         DELAY(150); /* wait for warmup */
1319         I915_WRITE(reg, val);
1320         POSTING_READ(reg);
1321         DELAY(150); /* wait for warmup */
1322         I915_WRITE(reg, val);
1323         POSTING_READ(reg);
1324         DELAY(150); /* wait for warmup */
1325 }
1326
1327 /**
1328  * intel_disable_pll - disable a PLL
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe PLL to disable
1331  *
1332  * Disable the PLL for @pipe, making sure the pipe is off first.
1333  *
1334  * Note!  This is for pre-ILK only.
1335  */
1336 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1337 {
1338         int reg;
1339         u32 val;
1340
1341         /* Don't disable pipe A or pipe A PLLs if needed */
1342         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1343                 return;
1344
1345         /* Make sure the pipe isn't still relying on us */
1346         assert_pipe_disabled(dev_priv, pipe);
1347
1348         reg = DPLL(pipe);
1349         val = I915_READ(reg);
1350         val &= ~DPLL_VCO_ENABLE;
1351         I915_WRITE(reg, val);
1352         POSTING_READ(reg);
1353 }
1354
1355 /* SBI access */
1356 static void
1357 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1358 {
1359
1360         mtx_lock(&dev_priv->dpio_lock);
1361         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, 100)) {
1362                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1363                 goto out_unlock;
1364         }
1365
1366         I915_WRITE(SBI_ADDR, (reg << 16));
1367         I915_WRITE(SBI_DATA, value);
1368         I915_WRITE(SBI_CTL_STAT,
1369                         SBI_BUSY |
1370                         SBI_CTL_OP_CRWR);
1371
1372         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1373                                 100)) {
1374                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1375                 goto out_unlock;
1376         }
1377
1378 out_unlock:
1379         mtx_unlock(&dev_priv->dpio_lock);
1380 }
1381
1382 static u32
1383 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1384 {
1385         u32 value = 0;
1386
1387         mtx_lock(&dev_priv->dpio_lock);
1388         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, 100)) {
1389                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1390                 goto out_unlock;
1391         }
1392
1393         I915_WRITE(SBI_ADDR, (reg << 16));
1394         I915_WRITE(SBI_CTL_STAT,
1395                         SBI_BUSY |
1396                         SBI_CTL_OP_CRRD);
1397
1398         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1399                                 100)) {
1400                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1401                 goto out_unlock;
1402         }
1403
1404         value = I915_READ(SBI_DATA);
1405
1406 out_unlock:
1407         mtx_unlock(&dev_priv->dpio_lock);
1408         return value;
1409 }
1410
1411 /**
1412  * intel_enable_pch_pll - enable PCH PLL
1413  * @dev_priv: i915 private structure
1414  * @pipe: pipe PLL to enable
1415  *
1416  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1417  * drives the transcoder clock.
1418  */
1419 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1420 {
1421         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1422         struct intel_pch_pll *pll;
1423         int reg;
1424         u32 val;
1425
1426         /* PCH PLLs only available on ILK, SNB and IVB */
1427         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1428         pll = intel_crtc->pch_pll;
1429         if (pll == NULL)
1430                 return;
1431
1432         if (pll->refcount == 0) {
1433                 DRM_DEBUG_KMS("pll->refcount == 0\n");
1434                 return;
1435         }
1436
1437         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1438                       pll->pll_reg, pll->active, pll->on,
1439                       intel_crtc->base.base.id);
1440
1441         /* PCH refclock must be enabled first */
1442         assert_pch_refclk_enabled(dev_priv);
1443
1444         if (pll->active++ && pll->on) {
1445                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1446                 return;
1447         }
1448
1449         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1450
1451         reg = pll->pll_reg;
1452         val = I915_READ(reg);
1453         val |= DPLL_VCO_ENABLE;
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         DELAY(200);
1457
1458         pll->on = true;
1459 }
1460
1461 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1462 {
1463         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1464         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1465         int reg;
1466         u32 val;
1467
1468         /* PCH only available on ILK+ */
1469         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1470         if (pll == NULL)
1471                 return;
1472
1473         if (pll->refcount == 0) {
1474                 DRM_DEBUG_KMS("pll->refcount == 0\n");
1475                 return;
1476         }
1477
1478         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1479                       pll->pll_reg, pll->active, pll->on,
1480                       intel_crtc->base.base.id);
1481
1482         if (pll->active == 0) {
1483                 DRM_DEBUG_KMS("pll->active == 0\n");
1484                 assert_pch_pll_disabled(dev_priv, intel_crtc);
1485                 return;
1486         }
1487
1488         if (--pll->active) {
1489                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1490                 return;
1491         }
1492
1493         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1494
1495         /* Make sure transcoder isn't still depending on us */
1496         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1497
1498         reg = pll->pll_reg;
1499         val = I915_READ(reg);
1500         val &= ~DPLL_VCO_ENABLE;
1501         I915_WRITE(reg, val);
1502         POSTING_READ(reg);
1503         DELAY(200);
1504
1505         pll->on = false;
1506 }
1507
1508 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1509                                            enum pipe pipe)
1510 {
1511         int reg;
1512         u32 val, pipeconf_val;
1513         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1514
1515         /* PCH only available on ILK+ */
1516         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1517
1518         /* Make sure PCH DPLL is enabled */
1519         assert_pch_pll_enabled(dev_priv,
1520                                to_intel_crtc(crtc));
1521
1522         /* FDI must be feeding us bits for PCH ports */
1523         assert_fdi_tx_enabled(dev_priv, pipe);
1524         assert_fdi_rx_enabled(dev_priv, pipe);
1525
1526         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1527                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1528                 return;
1529         }
1530
1531         reg = TRANSCONF(pipe);
1532         val = I915_READ(reg);
1533         pipeconf_val = I915_READ(PIPECONF(pipe));
1534
1535         if (HAS_PCH_IBX(dev_priv->dev)) {
1536                 /*
1537                  * make the BPC in transcoder be consistent with
1538                  * that in pipeconf reg.
1539                  */
1540                 val &= ~PIPE_BPC_MASK;
1541                 val |= pipeconf_val & PIPE_BPC_MASK;
1542         }
1543
1544         val &= ~TRANS_INTERLACE_MASK;
1545         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1546                 if (HAS_PCH_IBX(dev_priv->dev) &&
1547                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1548                         val |= TRANS_LEGACY_INTERLACED_ILK;
1549                 else
1550                         val |= TRANS_INTERLACED;
1551         else
1552                 val |= TRANS_PROGRESSIVE;
1553
1554         I915_WRITE(reg, val | TRANS_ENABLE);
1555         if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1556             100, 1, "915trc"))
1557                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1558 }
1559
1560 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe)
1562 {
1563         int reg;
1564         u32 val;
1565
1566         /* FDI relies on the transcoder */
1567         assert_fdi_tx_disabled(dev_priv, pipe);
1568         assert_fdi_rx_disabled(dev_priv, pipe);
1569
1570         /* Ports must be off as well */
1571         assert_pch_ports_disabled(dev_priv, pipe);
1572
1573         reg = TRANSCONF(pipe);
1574         val = I915_READ(reg);
1575         val &= ~TRANS_ENABLE;
1576         I915_WRITE(reg, val);
1577         /* wait for PCH transcoder off, transcoder state */
1578         if (_intel_wait_for(dev_priv->dev,
1579             (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1580             1, "915trd"))
1581                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1582 }
1583
1584 /**
1585  * intel_enable_pipe - enable a pipe, asserting requirements
1586  * @dev_priv: i915 private structure
1587  * @pipe: pipe to enable
1588  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1589  *
1590  * Enable @pipe, making sure that various hardware specific requirements
1591  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1592  *
1593  * @pipe should be %PIPE_A or %PIPE_B.
1594  *
1595  * Will wait until the pipe is actually running (i.e. first vblank) before
1596  * returning.
1597  */
1598 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1599                               bool pch_port)
1600 {
1601         int reg;
1602         u32 val;
1603
1604         /*
1605          * A pipe without a PLL won't actually be able to drive bits from
1606          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1607          * need the check.
1608          */
1609         if (!HAS_PCH_SPLIT(dev_priv->dev))
1610                 assert_pll_enabled(dev_priv, pipe);
1611         else {
1612                 if (pch_port) {
1613                         /* if driving the PCH, we need FDI enabled */
1614                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1615                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1616                 }
1617                 /* FIXME: assert CPU port conditions for SNB+ */
1618         }
1619
1620         reg = PIPECONF(pipe);
1621         val = I915_READ(reg);
1622         if (val & PIPECONF_ENABLE)
1623                 return;
1624
1625         I915_WRITE(reg, val | PIPECONF_ENABLE);
1626         intel_wait_for_vblank(dev_priv->dev, pipe);
1627 }
1628
1629 /**
1630  * intel_disable_pipe - disable a pipe, asserting requirements
1631  * @dev_priv: i915 private structure
1632  * @pipe: pipe to disable
1633  *
1634  * Disable @pipe, making sure that various hardware specific requirements
1635  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1636  *
1637  * @pipe should be %PIPE_A or %PIPE_B.
1638  *
1639  * Will wait until the pipe has shut down before returning.
1640  */
1641 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1642                                enum pipe pipe)
1643 {
1644         int reg;
1645         u32 val;
1646
1647         /*
1648          * Make sure planes won't keep trying to pump pixels to us,
1649          * or we might hang the display.
1650          */
1651         assert_planes_disabled(dev_priv, pipe);
1652
1653         /* Don't disable pipe A or pipe A PLLs if needed */
1654         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1655                 return;
1656
1657         reg = PIPECONF(pipe);
1658         val = I915_READ(reg);
1659         if ((val & PIPECONF_ENABLE) == 0)
1660                 return;
1661
1662         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1663         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1664 }
1665
1666 /*
1667  * Plane regs are double buffered, going from enabled->disabled needs a
1668  * trigger in order to latch.  The display address reg provides this.
1669  */
1670 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1671                                       enum plane plane)
1672 {
1673         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1674         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1675 }
1676
1677 /**
1678  * intel_enable_plane - enable a display plane on a given pipe
1679  * @dev_priv: i915 private structure
1680  * @plane: plane to enable
1681  * @pipe: pipe being fed
1682  *
1683  * Enable @plane on @pipe, making sure that @pipe is running first.
1684  */
1685 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1686                                enum plane plane, enum pipe pipe)
1687 {
1688         int reg;
1689         u32 val;
1690
1691         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1692         assert_pipe_enabled(dev_priv, pipe);
1693
1694         reg = DSPCNTR(plane);
1695         val = I915_READ(reg);
1696         if (val & DISPLAY_PLANE_ENABLE)
1697                 return;
1698
1699         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1700         intel_flush_display_plane(dev_priv, plane);
1701         intel_wait_for_vblank(dev_priv->dev, pipe);
1702 }
1703
1704 /**
1705  * intel_disable_plane - disable a display plane
1706  * @dev_priv: i915 private structure
1707  * @plane: plane to disable
1708  * @pipe: pipe consuming the data
1709  *
1710  * Disable @plane; should be an independent operation.
1711  */
1712 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1713                                 enum plane plane, enum pipe pipe)
1714 {
1715         int reg;
1716         u32 val;
1717
1718         reg = DSPCNTR(plane);
1719         val = I915_READ(reg);
1720         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1721                 return;
1722
1723         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1724         intel_flush_display_plane(dev_priv, plane);
1725         intel_wait_for_vblank(dev_priv->dev, pipe);
1726 }
1727
1728 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1729                            enum pipe pipe, int reg, u32 port_sel)
1730 {
1731         u32 val = I915_READ(reg);
1732         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1733                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1734                 I915_WRITE(reg, val & ~DP_PORT_EN);
1735         }
1736 }
1737
1738 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1739                              enum pipe pipe, int reg)
1740 {
1741         u32 val = I915_READ(reg);
1742         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1743                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1744                               reg, pipe);
1745                 I915_WRITE(reg, val & ~PORT_ENABLE);
1746         }
1747 }
1748
1749 /* Disable any ports connected to this transcoder */
1750 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1751                                     enum pipe pipe)
1752 {
1753         u32 reg, val;
1754
1755         val = I915_READ(PCH_PP_CONTROL);
1756         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1757
1758         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1759         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1760         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1761
1762         reg = PCH_ADPA;
1763         val = I915_READ(reg);
1764         if (adpa_pipe_enabled(dev_priv, val, pipe))
1765                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1766
1767         reg = PCH_LVDS;
1768         val = I915_READ(reg);
1769         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1770                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1771                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1772                 POSTING_READ(reg);
1773                 DELAY(100);
1774         }
1775
1776         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1777         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1778         disable_pch_hdmi(dev_priv, pipe, HDMID);
1779 }
1780
1781 int
1782 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1783                            struct drm_i915_gem_object *obj,
1784                            struct intel_ring_buffer *pipelined)
1785 {
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         u32 alignment;
1788         int ret;
1789
1790         alignment = 0; /* shut gcc */
1791         switch (obj->tiling_mode) {
1792         case I915_TILING_NONE:
1793                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1794                         alignment = 128 * 1024;
1795                 else if (INTEL_INFO(dev)->gen >= 4)
1796                         alignment = 4 * 1024;
1797                 else
1798                         alignment = 64 * 1024;
1799                 break;
1800         case I915_TILING_X:
1801                 /* pin() will align the object as required by fence */
1802                 alignment = 0;
1803                 break;
1804         case I915_TILING_Y:
1805                 /* FIXME: Is this true? */
1806                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1807                 return -EINVAL;
1808         default:
1809                 KASSERT(0, ("Wrong tiling for fb obj"));
1810         }
1811
1812         dev_priv->mm.interruptible = false;
1813         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1814         if (ret)
1815                 goto err_interruptible;
1816
1817         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1818          * fence, whereas 965+ only requires a fence if using
1819          * framebuffer compression.  For simplicity, we always install
1820          * a fence as the cost is not that onerous.
1821          */
1822         ret = i915_gem_object_get_fence(obj);
1823         if (ret)
1824                 goto err_unpin;
1825
1826         i915_gem_object_pin_fence(obj);
1827
1828         dev_priv->mm.interruptible = true;
1829         return 0;
1830
1831 err_unpin:
1832         i915_gem_object_unpin_from_display_plane(obj);
1833 err_interruptible:
1834         dev_priv->mm.interruptible = true;
1835         return ret;
1836 }
1837
1838 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1839 {
1840         i915_gem_object_unpin_fence(obj);
1841         i915_gem_object_unpin_from_display_plane(obj);
1842 }
1843
1844 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1845                              int x, int y)
1846 {
1847         struct drm_device *dev = crtc->dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850         struct intel_framebuffer *intel_fb;
1851         struct drm_i915_gem_object *obj;
1852         int plane = intel_crtc->plane;
1853         unsigned long Start, Offset;
1854         u32 dspcntr;
1855         u32 reg;
1856
1857         switch (plane) {
1858         case 0:
1859         case 1:
1860                 break;
1861         default:
1862                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1863                 return -EINVAL;
1864         }
1865
1866         intel_fb = to_intel_framebuffer(fb);
1867         obj = intel_fb->obj;
1868
1869         reg = DSPCNTR(plane);
1870         dspcntr = I915_READ(reg);
1871         /* Mask out pixel format bits in case we change it */
1872         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1873         switch (fb->bits_per_pixel) {
1874         case 8:
1875                 dspcntr |= DISPPLANE_8BPP;
1876                 break;
1877         case 16:
1878                 if (fb->depth == 15)
1879                         dspcntr |= DISPPLANE_BGRX555;
1880                 else
1881                         dspcntr |= DISPPLANE_BGRX565;
1882                 break;
1883         case 24:
1884         case 32:
1885                 dspcntr |= DISPPLANE_BGRX888;
1886                 break;
1887         default:
1888                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1889                 return -EINVAL;
1890         }
1891
1892         if (INTEL_INFO(dev)->gen >= 4) {
1893                 if (obj->tiling_mode != I915_TILING_NONE)
1894                         dspcntr |= DISPPLANE_TILED;
1895                 else
1896                         dspcntr &= ~DISPPLANE_TILED;
1897         }
1898
1899         I915_WRITE(reg, dspcntr);
1900
1901         Start = obj->gtt_offset;
1902         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1903
1904         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1905                       Start, Offset, x, y, fb->pitches[0]);
1906         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1907         if (INTEL_INFO(dev)->gen >= 4) {
1908                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1909                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1910                 I915_WRITE(DSPADDR(plane), Offset);
1911         } else
1912                 I915_WRITE(DSPADDR(plane), Start + Offset);
1913         POSTING_READ(reg);
1914
1915         return 0;
1916 }
1917
1918 static int ironlake_update_plane(struct drm_crtc *crtc,
1919                                  struct drm_framebuffer *fb, int x, int y)
1920 {
1921         struct drm_device *dev = crtc->dev;
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924         struct intel_framebuffer *intel_fb;
1925         struct drm_i915_gem_object *obj;
1926         int plane = intel_crtc->plane;
1927         unsigned long Start, Offset;
1928         u32 dspcntr;
1929         u32 reg;
1930
1931         switch (plane) {
1932         case 0:
1933         case 1:
1934         case 2:
1935                 break;
1936         default:
1937                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1938                 return -EINVAL;
1939         }
1940
1941         intel_fb = to_intel_framebuffer(fb);
1942         obj = intel_fb->obj;
1943
1944         reg = DSPCNTR(plane);
1945         dspcntr = I915_READ(reg);
1946         /* Mask out pixel format bits in case we change it */
1947         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948         switch (fb->bits_per_pixel) {
1949         case 8:
1950                 dspcntr |= DISPPLANE_8BPP;
1951                 break;
1952         case 16:
1953                 if (fb->depth != 16) {
1954                         DRM_ERROR("bpp 16, depth %d\n", fb->depth);
1955                         return -EINVAL;
1956                 }
1957
1958                 dspcntr |= DISPPLANE_BGRX565;
1959                 break;
1960         case 24:
1961         case 32:
1962                 if (fb->depth == 24)
1963                         dspcntr |= DISPPLANE_BGRX888;
1964                 else if (fb->depth == 30)
1965                         dspcntr |= DISPPLANE_BGRX101010;
1966                 else {
1967                         DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
1968                             fb->depth);
1969                         return -EINVAL;
1970                 }
1971                 break;
1972         default:
1973                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1974                 return -EINVAL;
1975         }
1976
1977         if (obj->tiling_mode != I915_TILING_NONE)
1978                 dspcntr |= DISPPLANE_TILED;
1979         else
1980                 dspcntr &= ~DISPPLANE_TILED;
1981
1982         /* must disable */
1983         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1984
1985         I915_WRITE(reg, dspcntr);
1986
1987         Start = obj->gtt_offset;
1988         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1989
1990         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1991                       Start, Offset, x, y, fb->pitches[0]);
1992         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1993         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1994         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1995         I915_WRITE(DSPADDR(plane), Offset);
1996         POSTING_READ(reg);
1997
1998         return 0;
1999 }
2000
2001 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2002 static int
2003 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2004                            int x, int y, enum mode_set_atomic state)
2005 {
2006         struct drm_device *dev = crtc->dev;
2007         struct drm_i915_private *dev_priv = dev->dev_private;
2008
2009         if (dev_priv->display.disable_fbc)
2010                 dev_priv->display.disable_fbc(dev);
2011         intel_increase_pllclock(crtc);
2012
2013         return dev_priv->display.update_plane(crtc, fb, x, y);
2014 }
2015
2016 static int
2017 intel_finish_fb(struct drm_framebuffer *old_fb)
2018 {
2019         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2020         struct drm_device *dev = obj->base.dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         bool was_interruptible = dev_priv->mm.interruptible;
2023         int ret;
2024
2025         mtx_lock(&dev->event_lock);
2026         while (!atomic_load_acq_int(&dev_priv->mm.wedged) &&
2027             atomic_load_acq_int(&obj->pending_flip) != 0) {
2028                 msleep(&obj->pending_flip, &dev->event_lock,
2029                     0, "915flp", 0);
2030         }
2031         mtx_unlock(&dev->event_lock);
2032
2033         /* Big Hammer, we also need to ensure that any pending
2034          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2035          * current scanout is retired before unpinning the old
2036          * framebuffer.
2037          *
2038          * This should only fail upon a hung GPU, in which case we
2039          * can safely continue.
2040          */
2041         dev_priv->mm.interruptible = false;
2042         ret = i915_gem_object_finish_gpu(obj);
2043         dev_priv->mm.interruptible = was_interruptible;
2044
2045         return ret;
2046 }
2047
2048 static int
2049 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2050                     struct drm_framebuffer *old_fb)
2051 {
2052         struct drm_device *dev = crtc->dev;
2053         struct drm_i915_private *dev_priv = dev->dev_private;
2054         struct drm_i915_master_private *master_priv;
2055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056         int ret;
2057
2058         /* no fb bound */
2059         if (!crtc->fb) {
2060                 DRM_ERROR("No FB bound\n");
2061                 return 0;
2062         }
2063
2064         if(intel_crtc->plane > dev_priv->num_pipe) {
2065                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2066                                 intel_crtc->plane,
2067                                 dev_priv->num_pipe);
2068                 return -EINVAL;
2069         }
2070
2071         DRM_LOCK(dev);
2072         ret = intel_pin_and_fence_fb_obj(dev,
2073                                          to_intel_framebuffer(crtc->fb)->obj,
2074                                          NULL);
2075         if (ret != 0) {
2076                 DRM_UNLOCK(dev);
2077                 DRM_ERROR("pin & fence failed\n");
2078                 return ret;
2079         }
2080
2081         if (old_fb)
2082                 intel_finish_fb(old_fb);
2083
2084         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2085         if (ret) {
2086                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2087                 DRM_UNLOCK(dev);
2088                 DRM_ERROR("failed to update base address\n");
2089                 return ret;
2090         }
2091
2092         if (old_fb) {
2093                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2094                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2095         }
2096
2097         intel_update_fbc(dev);
2098         DRM_UNLOCK(dev);
2099
2100         if (!dev->primary->master)
2101                 return 0;
2102
2103         master_priv = dev->primary->master->driver_priv;
2104         if (!master_priv->sarea_priv)
2105                 return 0;
2106
2107         if (intel_crtc->pipe) {
2108                 master_priv->sarea_priv->pipeB_x = x;
2109                 master_priv->sarea_priv->pipeB_y = y;
2110         } else {
2111                 master_priv->sarea_priv->pipeA_x = x;
2112                 master_priv->sarea_priv->pipeA_y = y;
2113         }
2114
2115         return 0;
2116 }
2117
2118 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2119 {
2120         struct drm_device *dev = crtc->dev;
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         u32 dpa_ctl;
2123
2124         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2125         dpa_ctl = I915_READ(DP_A);
2126         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2127
2128         if (clock < 200000) {
2129                 u32 temp;
2130                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2131                 /* workaround for 160Mhz:
2132                    1) program 0x4600c bits 15:0 = 0x8124
2133                    2) program 0x46010 bit 0 = 1
2134                    3) program 0x46034 bit 24 = 1
2135                    4) program 0x64000 bit 14 = 1
2136                    */
2137                 temp = I915_READ(0x4600c);
2138                 temp &= 0xffff0000;
2139                 I915_WRITE(0x4600c, temp | 0x8124);
2140
2141                 temp = I915_READ(0x46010);
2142                 I915_WRITE(0x46010, temp | 1);
2143
2144                 temp = I915_READ(0x46034);
2145                 I915_WRITE(0x46034, temp | (1 << 24));
2146         } else {
2147                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2148         }
2149         I915_WRITE(DP_A, dpa_ctl);
2150
2151         POSTING_READ(DP_A);
2152         DELAY(500);
2153 }
2154
2155 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2156 {
2157         struct drm_device *dev = crtc->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160         int pipe = intel_crtc->pipe;
2161         u32 reg, temp;
2162
2163         /* enable normal train */
2164         reg = FDI_TX_CTL(pipe);
2165         temp = I915_READ(reg);
2166         if (IS_IVYBRIDGE(dev)) {
2167                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2168                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2169         } else {
2170                 temp &= ~FDI_LINK_TRAIN_NONE;
2171                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2172         }
2173         I915_WRITE(reg, temp);
2174
2175         reg = FDI_RX_CTL(pipe);
2176         temp = I915_READ(reg);
2177         if (HAS_PCH_CPT(dev)) {
2178                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2179                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2180         } else {
2181                 temp &= ~FDI_LINK_TRAIN_NONE;
2182                 temp |= FDI_LINK_TRAIN_NONE;
2183         }
2184         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2185
2186         /* wait one idle pattern time */
2187         POSTING_READ(reg);
2188         DELAY(1000);
2189
2190         /* IVB wants error correction enabled */
2191         if (IS_IVYBRIDGE(dev))
2192                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2193                            FDI_FE_ERRC_ENABLE);
2194 }
2195
2196 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2197 {
2198         struct drm_i915_private *dev_priv = dev->dev_private;
2199         u32 flags = I915_READ(SOUTH_CHICKEN1);
2200
2201         flags |= FDI_PHASE_SYNC_OVR(pipe);
2202         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2203         flags |= FDI_PHASE_SYNC_EN(pipe);
2204         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2205         POSTING_READ(SOUTH_CHICKEN1);
2206 }
2207
2208 /* The FDI link training functions for ILK/Ibexpeak. */
2209 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2210 {
2211         struct drm_device *dev = crtc->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214         int pipe = intel_crtc->pipe;
2215         int plane = intel_crtc->plane;
2216         u32 reg, temp, tries;
2217
2218         /* FDI needs bits from pipe & plane first */
2219         assert_pipe_enabled(dev_priv, pipe);
2220         assert_plane_enabled(dev_priv, plane);
2221
2222         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2223            for train result */
2224         reg = FDI_RX_IMR(pipe);
2225         temp = I915_READ(reg);
2226         temp &= ~FDI_RX_SYMBOL_LOCK;
2227         temp &= ~FDI_RX_BIT_LOCK;
2228         I915_WRITE(reg, temp);
2229         I915_READ(reg);
2230         DELAY(150);
2231
2232         /* enable CPU FDI TX and PCH FDI RX */
2233         reg = FDI_TX_CTL(pipe);
2234         temp = I915_READ(reg);
2235         temp &= ~(7 << 19);
2236         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2237         temp &= ~FDI_LINK_TRAIN_NONE;
2238         temp |= FDI_LINK_TRAIN_PATTERN_1;
2239         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2240
2241         reg = FDI_RX_CTL(pipe);
2242         temp = I915_READ(reg);
2243         temp &= ~FDI_LINK_TRAIN_NONE;
2244         temp |= FDI_LINK_TRAIN_PATTERN_1;
2245         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2246
2247         POSTING_READ(reg);
2248         DELAY(150);
2249
2250         /* Ironlake workaround, enable clock pointer after FDI enable*/
2251         if (HAS_PCH_IBX(dev)) {
2252                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2253                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2254                            FDI_RX_PHASE_SYNC_POINTER_EN);
2255         }
2256
2257         reg = FDI_RX_IIR(pipe);
2258         for (tries = 0; tries < 5; tries++) {
2259                 temp = I915_READ(reg);
2260                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2261
2262                 if ((temp & FDI_RX_BIT_LOCK)) {
2263                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2264                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2265                         break;
2266                 }
2267         }
2268         if (tries == 5)
2269                 DRM_ERROR("FDI train 1 fail!\n");
2270
2271         /* Train 2 */
2272         reg = FDI_TX_CTL(pipe);
2273         temp = I915_READ(reg);
2274         temp &= ~FDI_LINK_TRAIN_NONE;
2275         temp |= FDI_LINK_TRAIN_PATTERN_2;
2276         I915_WRITE(reg, temp);
2277
2278         reg = FDI_RX_CTL(pipe);
2279         temp = I915_READ(reg);
2280         temp &= ~FDI_LINK_TRAIN_NONE;
2281         temp |= FDI_LINK_TRAIN_PATTERN_2;
2282         I915_WRITE(reg, temp);
2283
2284         POSTING_READ(reg);
2285         DELAY(150);
2286
2287         reg = FDI_RX_IIR(pipe);
2288         for (tries = 0; tries < 5; tries++) {
2289                 temp = I915_READ(reg);
2290                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2291
2292                 if (temp & FDI_RX_SYMBOL_LOCK) {
2293                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2294                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2295                         break;
2296                 }
2297         }
2298         if (tries == 5)
2299                 DRM_ERROR("FDI train 2 fail!\n");
2300
2301         DRM_DEBUG_KMS("FDI train done\n");
2302
2303 }
2304
2305 static const int snb_b_fdi_train_param[] = {
2306         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2307         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2308         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2309         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2310 };
2311
2312 /* The FDI link training functions for SNB/Cougarpoint. */
2313 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2314 {
2315         struct drm_device *dev = crtc->dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318         int pipe = intel_crtc->pipe;
2319         u32 reg, temp, i, retry;
2320
2321         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2322            for train result */
2323         reg = FDI_RX_IMR(pipe);
2324         temp = I915_READ(reg);
2325         temp &= ~FDI_RX_SYMBOL_LOCK;
2326         temp &= ~FDI_RX_BIT_LOCK;
2327         I915_WRITE(reg, temp);
2328
2329         POSTING_READ(reg);
2330         DELAY(150);
2331
2332         /* enable CPU FDI TX and PCH FDI RX */
2333         reg = FDI_TX_CTL(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~(7 << 19);
2336         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2337         temp &= ~FDI_LINK_TRAIN_NONE;
2338         temp |= FDI_LINK_TRAIN_PATTERN_1;
2339         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2340         /* SNB-B */
2341         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2342         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2343
2344         reg = FDI_RX_CTL(pipe);
2345         temp = I915_READ(reg);
2346         if (HAS_PCH_CPT(dev)) {
2347                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2348                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2349         } else {
2350                 temp &= ~FDI_LINK_TRAIN_NONE;
2351                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2352         }
2353         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2354
2355         POSTING_READ(reg);
2356         DELAY(150);
2357
2358         if (HAS_PCH_CPT(dev))
2359                 cpt_phase_pointer_enable(dev, pipe);
2360
2361         for (i = 0; i < 4; i++) {
2362                 reg = FDI_TX_CTL(pipe);
2363                 temp = I915_READ(reg);
2364                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2365                 temp |= snb_b_fdi_train_param[i];
2366                 I915_WRITE(reg, temp);
2367
2368                 POSTING_READ(reg);
2369                 DELAY(500);
2370
2371                 for (retry = 0; retry < 5; retry++) {
2372                         reg = FDI_RX_IIR(pipe);
2373                         temp = I915_READ(reg);
2374                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2375
2376                         if (temp & FDI_RX_BIT_LOCK) {
2377                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2378                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2379                                 break;
2380                         }
2381                         DELAY(50);
2382                 }
2383                 if (retry < 5)
2384                         break;
2385         }
2386         if (i == 4)
2387                 DRM_ERROR("FDI train 1 fail!\n");
2388
2389         /* Train 2 */
2390         reg = FDI_TX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         temp &= ~FDI_LINK_TRAIN_NONE;
2393         temp |= FDI_LINK_TRAIN_PATTERN_2;
2394         if (IS_GEN6(dev)) {
2395                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2396                 /* SNB-B */
2397                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2398         }
2399         I915_WRITE(reg, temp);
2400
2401         reg = FDI_RX_CTL(pipe);
2402         temp = I915_READ(reg);
2403         if (HAS_PCH_CPT(dev)) {
2404                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2406         } else {
2407                 temp &= ~FDI_LINK_TRAIN_NONE;
2408                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2409         }
2410         I915_WRITE(reg, temp);
2411
2412         POSTING_READ(reg);
2413         DELAY(150);
2414
2415         for (i = 0; i < 4; i++) {
2416                 reg = FDI_TX_CTL(pipe);
2417                 temp = I915_READ(reg);
2418                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2419                 temp |= snb_b_fdi_train_param[i];
2420                 I915_WRITE(reg, temp);
2421
2422                 POSTING_READ(reg);
2423                 DELAY(500);
2424
2425                 for (retry = 0; retry < 5; retry++) {
2426                         reg = FDI_RX_IIR(pipe);
2427                         temp = I915_READ(reg);
2428                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430                         if (temp & FDI_RX_SYMBOL_LOCK) {
2431                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2433                                 break;
2434                         }
2435                         DELAY(50);
2436                 }
2437                 if (retry < 5)
2438                         break;
2439         }
2440         if (i == 4)
2441                 DRM_ERROR("FDI train 2 fail!\n");
2442
2443         DRM_DEBUG_KMS("FDI train done.\n");
2444 }
2445
2446 /* Manual link training for Ivy Bridge A0 parts */
2447 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2448 {
2449         struct drm_device *dev = crtc->dev;
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2452         int pipe = intel_crtc->pipe;
2453         u32 reg, temp, i;
2454
2455         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2456            for train result */
2457         reg = FDI_RX_IMR(pipe);
2458         temp = I915_READ(reg);
2459         temp &= ~FDI_RX_SYMBOL_LOCK;
2460         temp &= ~FDI_RX_BIT_LOCK;
2461         I915_WRITE(reg, temp);
2462
2463         POSTING_READ(reg);
2464         DELAY(150);
2465
2466         /* enable CPU FDI TX and PCH FDI RX */
2467         reg = FDI_TX_CTL(pipe);
2468         temp = I915_READ(reg);
2469         temp &= ~(7 << 19);
2470         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2471         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2472         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2473         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2475         temp |= FDI_COMPOSITE_SYNC;
2476         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2477
2478         reg = FDI_RX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_LINK_TRAIN_AUTO;
2481         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2482         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2483         temp |= FDI_COMPOSITE_SYNC;
2484         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2485
2486         POSTING_READ(reg);
2487         DELAY(150);
2488
2489         for (i = 0; i < 4; i++) {
2490                 reg = FDI_TX_CTL(pipe);
2491                 temp = I915_READ(reg);
2492                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493                 temp |= snb_b_fdi_train_param[i];
2494                 I915_WRITE(reg, temp);
2495
2496                 POSTING_READ(reg);
2497                 DELAY(500);
2498
2499                 reg = FDI_RX_IIR(pipe);
2500                 temp = I915_READ(reg);
2501                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2502
2503                 if (temp & FDI_RX_BIT_LOCK ||
2504                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2505                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         break;
2508                 }
2509         }
2510         if (i == 4)
2511                 DRM_ERROR("FDI train 1 fail!\n");
2512
2513         /* Train 2 */
2514         reg = FDI_TX_CTL(pipe);
2515         temp = I915_READ(reg);
2516         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2517         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2518         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2520         I915_WRITE(reg, temp);
2521
2522         reg = FDI_RX_CTL(pipe);
2523         temp = I915_READ(reg);
2524         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2526         I915_WRITE(reg, temp);
2527
2528         POSTING_READ(reg);
2529         DELAY(150);
2530
2531         for (i = 0; i < 4; i++) {
2532                 reg = FDI_TX_CTL(pipe);
2533                 temp = I915_READ(reg);
2534                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2535                 temp |= snb_b_fdi_train_param[i];
2536                 I915_WRITE(reg, temp);
2537
2538                 POSTING_READ(reg);
2539                 DELAY(500);
2540
2541                 reg = FDI_RX_IIR(pipe);
2542                 temp = I915_READ(reg);
2543                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545                 if (temp & FDI_RX_SYMBOL_LOCK) {
2546                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2547                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2548                         break;
2549                 }
2550         }
2551         if (i == 4)
2552                 DRM_ERROR("FDI train 2 fail!\n");
2553
2554         DRM_DEBUG_KMS("FDI train done.\n");
2555 }
2556
2557 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2558 {
2559         struct drm_device *dev = crtc->dev;
2560         struct drm_i915_private *dev_priv = dev->dev_private;
2561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562         int pipe = intel_crtc->pipe;
2563         u32 reg, temp;
2564
2565         /* Write the TU size bits so error detection works */
2566         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2567                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2568
2569         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2570         reg = FDI_RX_CTL(pipe);
2571         temp = I915_READ(reg);
2572         temp &= ~((0x7 << 19) | (0x7 << 16));
2573         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2574         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2575         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2576
2577         POSTING_READ(reg);
2578         DELAY(200);
2579
2580         /* Switch from Rawclk to PCDclk */
2581         temp = I915_READ(reg);
2582         I915_WRITE(reg, temp | FDI_PCDCLK);
2583
2584         POSTING_READ(reg);
2585         DELAY(200);
2586
2587         /* On Haswell, the PLL configuration for ports and pipes is handled
2588          * separately, as part of DDI setup */
2589         if (!IS_HASWELL(dev)) {
2590                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2591                 reg = FDI_TX_CTL(pipe);
2592                 temp = I915_READ(reg);
2593                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2594                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2595
2596                         POSTING_READ(reg);
2597                         DELAY(100);
2598                 }
2599         }
2600 }
2601
2602 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2603 {
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         u32 flags = I915_READ(SOUTH_CHICKEN1);
2606
2607         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2608         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2609         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2610         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2611         POSTING_READ(SOUTH_CHICKEN1);
2612 }
2613
2614 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619         int pipe = intel_crtc->pipe;
2620         u32 reg, temp;
2621
2622         /* disable CPU FDI tx and PCH FDI rx */
2623         reg = FDI_TX_CTL(pipe);
2624         temp = I915_READ(reg);
2625         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2626         POSTING_READ(reg);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~(0x7 << 16);
2631         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2632         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2633
2634         POSTING_READ(reg);
2635         DELAY(100);
2636
2637         /* Ironlake workaround, disable clock pointer after downing FDI */
2638         if (HAS_PCH_IBX(dev)) {
2639                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2640                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2641                            I915_READ(FDI_RX_CHICKEN(pipe) &
2642                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2643         } else if (HAS_PCH_CPT(dev)) {
2644                 cpt_phase_pointer_disable(dev, pipe);
2645         }
2646
2647         /* still set train pattern 1 */
2648         reg = FDI_TX_CTL(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_LINK_TRAIN_NONE;
2651         temp |= FDI_LINK_TRAIN_PATTERN_1;
2652         I915_WRITE(reg, temp);
2653
2654         reg = FDI_RX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         if (HAS_PCH_CPT(dev)) {
2657                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2659         } else {
2660                 temp &= ~FDI_LINK_TRAIN_NONE;
2661                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2662         }
2663         /* BPC in FDI rx is consistent with that in PIPECONF */
2664         temp &= ~(0x07 << 16);
2665         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2666         I915_WRITE(reg, temp);
2667
2668         POSTING_READ(reg);
2669         DELAY(100);
2670 }
2671
2672 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2673 {
2674         struct drm_device *dev = crtc->dev;
2675
2676         if (crtc->fb == NULL)
2677                 return;
2678
2679         DRM_LOCK(dev);
2680         intel_finish_fb(crtc->fb);
2681         DRM_UNLOCK(dev);
2682 }
2683
2684 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2685 {
2686         struct drm_device *dev = crtc->dev;
2687         struct drm_mode_config *mode_config = &dev->mode_config;
2688         struct intel_encoder *encoder;
2689
2690         /*
2691          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2692          * must be driven by its own crtc; no sharing is possible.
2693          */
2694         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2695                 if (encoder->base.crtc != crtc)
2696                         continue;
2697
2698                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2699                  * CPU handles all others */
2700                 if (IS_HASWELL(dev)) {
2701                         /* It is still unclear how this will work on PPT, so throw up a warning */
2702                         if (!HAS_PCH_LPT(dev))
2703                                 DRM_DEBUG_KMS("Haswell: PPT\n");
2704
2705                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2706                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2707                                 return true;
2708                         } else {
2709                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2710                                                 encoder->type);
2711                                 return false;
2712                         }
2713                 }
2714
2715                 switch (encoder->type) {
2716                 case INTEL_OUTPUT_EDP:
2717                         if (!intel_encoder_is_pch_edp(&encoder->base))
2718                                 return false;
2719                         continue;
2720                 }
2721         }
2722
2723         return true;
2724 }
2725
2726 /* Program iCLKIP clock to the desired frequency */
2727 static void lpt_program_iclkip(struct drm_crtc *crtc)
2728 {
2729         struct drm_device *dev = crtc->dev;
2730         struct drm_i915_private *dev_priv = dev->dev_private;
2731         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2732         u32 temp;
2733
2734         /* It is necessary to ungate the pixclk gate prior to programming
2735          * the divisors, and gate it back when it is done.
2736          */
2737         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2738
2739         /* Disable SSCCTL */
2740         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2741                         intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2742                                 SBI_SSCCTL_DISABLE);
2743
2744         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2745         if (crtc->mode.clock == 20000) {
2746                 auxdiv = 1;
2747                 divsel = 0x41;
2748                 phaseinc = 0x20;
2749         } else {
2750                 /* The iCLK virtual clock root frequency is in MHz,
2751                  * but the crtc->mode.clock in in KHz. To get the divisors,
2752                  * it is necessary to divide one by another, so we
2753                  * convert the virtual clock precision to KHz here for higher
2754                  * precision.
2755                  */
2756                 u32 iclk_virtual_root_freq = 172800 * 1000;
2757                 u32 iclk_pi_range = 64;
2758                 u32 desired_divisor, msb_divisor_value, pi_value;
2759
2760                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2761                 msb_divisor_value = desired_divisor / iclk_pi_range;
2762                 pi_value = desired_divisor % iclk_pi_range;
2763
2764                 auxdiv = 0;
2765                 divsel = msb_divisor_value - 2;
2766                 phaseinc = pi_value;
2767         }
2768
2769         /* This should not happen with any sane values */
2770         if ((SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2771              ~SBI_SSCDIVINTPHASE_DIVSEL_MASK))
2772                 DRM_DEBUG_KMS("DIVSEL_MASK");
2773         if ((SBI_SSCDIVINTPHASE_DIR(phasedir) &
2774              ~SBI_SSCDIVINTPHASE_INCVAL_MASK))
2775                 DRM_DEBUG_KMS("INCVAL_MASK");
2776
2777         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2778                         crtc->mode.clock,
2779                         auxdiv,
2780                         divsel,
2781                         phasedir,
2782                         phaseinc);
2783
2784         /* Program SSCDIVINTPHASE6 */
2785         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2786         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2787         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2788         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2789         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2790         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2791         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2792
2793         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp);
2794
2795         /* Program SSCAUXDIV */
2796         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2797         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2798         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2799         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp);
2800
2801         /* Enable modulator and associated divider */
2802         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2803         temp &= ~SBI_SSCCTL_DISABLE;
2804         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp);
2805
2806         /* Wait for initialization time */
2807         DELAY(24);
2808
2809         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2810 }
2811
2812 /*
2813  * Enable PCH resources required for PCH ports:
2814  *   - PCH PLLs
2815  *   - FDI training & RX/TX
2816  *   - update transcoder timings
2817  *   - DP transcoding bits
2818  *   - transcoder
2819  */
2820 static void ironlake_pch_enable(struct drm_crtc *crtc)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825         int pipe = intel_crtc->pipe;
2826         u32 reg, temp;
2827
2828         assert_transcoder_disabled(dev_priv, pipe);
2829
2830         /* For PCH output, training FDI link */
2831         dev_priv->display.fdi_link_train(crtc);
2832
2833         intel_enable_pch_pll(intel_crtc);
2834
2835         if (HAS_PCH_LPT(dev)) {
2836                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2837                 lpt_program_iclkip(crtc);
2838         } else if (HAS_PCH_CPT(dev)) {
2839                 u32 sel;
2840
2841                 temp = I915_READ(PCH_DPLL_SEL);
2842                 switch (pipe) {
2843                 default:
2844                 case 0:
2845                         temp |= TRANSA_DPLL_ENABLE;
2846                         sel = TRANSA_DPLLB_SEL;
2847                         break;
2848                 case 1:
2849                         temp |= TRANSB_DPLL_ENABLE;
2850                         sel = TRANSB_DPLLB_SEL;
2851                         break;
2852                 case 2:
2853                         temp |= TRANSC_DPLL_ENABLE;
2854                         sel = TRANSC_DPLLB_SEL;
2855                         break;
2856                 }
2857                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2858                         temp |= sel;
2859                 else
2860                         temp &= ~sel;
2861                 I915_WRITE(PCH_DPLL_SEL, temp);
2862         }
2863
2864         /* set transcoder timing, panel must allow it */
2865         assert_panel_unlocked(dev_priv, pipe);
2866         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2867         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2868         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2869
2870         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2871         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2872         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2873         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2874
2875         if (!IS_HASWELL(dev))
2876                 intel_fdi_normal_train(crtc);
2877
2878         /* For PCH DP, enable TRANS_DP_CTL */
2879         if (HAS_PCH_CPT(dev) &&
2880             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2881              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2882                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2883                 reg = TRANS_DP_CTL(pipe);
2884                 temp = I915_READ(reg);
2885                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2886                           TRANS_DP_SYNC_MASK |
2887                           TRANS_DP_BPC_MASK);
2888                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2889                          TRANS_DP_ENH_FRAMING);
2890                 temp |= bpc << 9; /* same format but at 11:9 */
2891
2892                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2893                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2894                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2895                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2896
2897                 switch (intel_trans_dp_port_sel(crtc)) {
2898                 case PCH_DP_B:
2899                         temp |= TRANS_DP_PORT_SEL_B;
2900                         break;
2901                 case PCH_DP_C:
2902                         temp |= TRANS_DP_PORT_SEL_C;
2903                         break;
2904                 case PCH_DP_D:
2905                         temp |= TRANS_DP_PORT_SEL_D;
2906                         break;
2907                 default:
2908                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2909                         temp |= TRANS_DP_PORT_SEL_B;
2910                         break;
2911                 }
2912
2913                 I915_WRITE(reg, temp);
2914         }
2915
2916         intel_enable_transcoder(dev_priv, pipe);
2917 }
2918
2919 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2920 {
2921         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2922
2923         if (pll == NULL)
2924                 return;
2925
2926         if (pll->refcount == 0) {
2927                 printf("bad PCH PLL refcount\n");
2928                 return;
2929         }
2930
2931         --pll->refcount;
2932         intel_crtc->pch_pll = NULL;
2933 }
2934
2935 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2936 {
2937         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2938         struct intel_pch_pll *pll;
2939         int i;
2940
2941         pll = intel_crtc->pch_pll;
2942         if (pll) {
2943                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2944                               intel_crtc->base.base.id, pll->pll_reg);
2945                 goto prepare;
2946         }
2947
2948         if (HAS_PCH_IBX(dev_priv->dev)) {
2949                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2950                 i = intel_crtc->pipe;
2951                 pll = &dev_priv->pch_plls[i];
2952
2953                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2954                               intel_crtc->base.base.id, pll->pll_reg);
2955
2956                 goto found;
2957         }
2958
2959         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2960                 pll = &dev_priv->pch_plls[i];
2961
2962                 /* Only want to check enabled timings first */
2963                 if (pll->refcount == 0)
2964                         continue;
2965
2966                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2967                     fp == I915_READ(pll->fp0_reg)) {
2968                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2969                                       intel_crtc->base.base.id,
2970                                       pll->pll_reg, pll->refcount, pll->active);
2971
2972                         goto found;
2973                 }
2974         }
2975
2976         /* Ok no matching timings, maybe there's a free one? */
2977         for (i = 0; i < dev_priv->num_pch_pll; i++) { /* XXXKIB: HACK */
2978                 pll = &dev_priv->pch_plls[i];
2979                 if (pll->refcount == 0) {
2980                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2981                                       intel_crtc->base.base.id, pll->pll_reg);
2982                         goto found;
2983                 }
2984         }
2985
2986         return NULL;
2987
2988 found:
2989         intel_crtc->pch_pll = pll;
2990         pll->refcount++;
2991         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2992 prepare: /* separate function? */
2993         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2994
2995         /* Wait for the clocks to stabilize before rewriting the regs */
2996         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2997         POSTING_READ(pll->pll_reg);
2998         DELAY(150);
2999
3000         I915_WRITE(pll->fp0_reg, fp);
3001         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3002         pll->on = false;
3003         return pll;
3004 }
3005
3006 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3010         u32 temp;
3011
3012         temp = I915_READ(dslreg);
3013         DELAY(500);
3014         if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1, "915cp1")) {
3015                 /* Without this, mode sets may fail silently on FDI */
3016                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3017                 DELAY(250);
3018                 I915_WRITE(tc2reg, 0);
3019                 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1,
3020                     "915cp2"))
3021                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3022         }
3023 }
3024
3025 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3026 {
3027         struct drm_device *dev = crtc->dev;
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3030         int pipe = intel_crtc->pipe;
3031         int plane = intel_crtc->plane;
3032         u32 temp;
3033         bool is_pch_port;
3034
3035         if (intel_crtc->active)
3036                 return;
3037
3038         intel_crtc->active = true;
3039         intel_update_watermarks(dev);
3040
3041         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3042                 temp = I915_READ(PCH_LVDS);
3043                 if ((temp & LVDS_PORT_EN) == 0)
3044                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3045         }
3046
3047         is_pch_port = intel_crtc_driving_pch(crtc);
3048
3049         if (is_pch_port) {
3050                 ironlake_fdi_pll_enable(crtc);
3051         } else {
3052                 ironlake_fdi_disable(crtc);
3053         }
3054
3055         /* Enable panel fitting for LVDS */
3056         if (dev_priv->pch_pf_size &&
3057             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3058                 /* Force use of hard-coded filter coefficients
3059                  * as some pre-programmed values are broken,
3060                  * e.g. x201.
3061                  */
3062                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3063                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3064                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3065         }
3066
3067         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3068         intel_enable_plane(dev_priv, plane, pipe);
3069
3070         if (is_pch_port)
3071                 ironlake_pch_enable(crtc);
3072
3073         intel_crtc_load_lut(crtc);
3074
3075         DRM_LOCK(dev);
3076         intel_update_fbc(dev);
3077         DRM_UNLOCK(dev);
3078
3079         intel_crtc_update_cursor(crtc, true);
3080 }
3081
3082 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089         u32 reg, temp;
3090
3091         if (!intel_crtc->active)
3092                 return;
3093
3094         intel_crtc_wait_for_pending_flips(crtc);
3095         drm_vblank_off(dev, pipe);
3096         intel_crtc_update_cursor(crtc, false);
3097
3098         intel_disable_plane(dev_priv, plane, pipe);
3099
3100         if (dev_priv->cfb_plane == plane)
3101                 intel_disable_fbc(dev);
3102
3103         intel_disable_pipe(dev_priv, pipe);
3104
3105         /* Disable PF */
3106         I915_WRITE(PF_CTL(pipe), 0);
3107         I915_WRITE(PF_WIN_SZ(pipe), 0);
3108
3109         ironlake_fdi_disable(crtc);
3110
3111         /* This is a horrible layering violation; we should be doing this in
3112          * the connector/encoder ->prepare instead, but we don't always have
3113          * enough information there about the config to know whether it will
3114          * actually be necessary or just cause undesired flicker.
3115          */
3116         intel_disable_pch_ports(dev_priv, pipe);
3117
3118         intel_disable_transcoder(dev_priv, pipe);
3119
3120         if (HAS_PCH_CPT(dev)) {
3121                 /* disable TRANS_DP_CTL */
3122                 reg = TRANS_DP_CTL(pipe);
3123                 temp = I915_READ(reg);
3124                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3125                 temp |= TRANS_DP_PORT_SEL_NONE;
3126                 I915_WRITE(reg, temp);
3127
3128                 /* disable DPLL_SEL */
3129                 temp = I915_READ(PCH_DPLL_SEL);
3130                 switch (pipe) {
3131                 case 0:
3132                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3133                         break;
3134                 case 1:
3135                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3136                         break;
3137                 case 2:
3138                         /* C shares PLL A or B */
3139                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3140                         break;
3141                 default:
3142                         KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
3143                 }
3144                 I915_WRITE(PCH_DPLL_SEL, temp);
3145         }
3146
3147         /* disable PCH DPLL */
3148         intel_disable_pch_pll(intel_crtc);
3149
3150         /* Switch from PCDclk to Rawclk */
3151         reg = FDI_RX_CTL(pipe);
3152         temp = I915_READ(reg);
3153         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3154
3155         /* Disable CPU FDI TX PLL */
3156         reg = FDI_TX_CTL(pipe);
3157         temp = I915_READ(reg);
3158         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3159
3160         POSTING_READ(reg);
3161         DELAY(100);
3162
3163         reg = FDI_RX_CTL(pipe);
3164         temp = I915_READ(reg);
3165         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3166
3167         /* Wait for the clocks to turn off. */
3168         POSTING_READ(reg);
3169         DELAY(100);
3170
3171         intel_crtc->active = false;
3172         intel_update_watermarks(dev);
3173
3174         DRM_LOCK(dev);
3175         intel_update_fbc(dev);
3176         DRM_UNLOCK(dev);
3177 }
3178
3179 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3180 {
3181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182         int pipe = intel_crtc->pipe;
3183         int plane = intel_crtc->plane;
3184
3185         /* XXX: When our outputs are all unaware of DPMS modes other than off
3186          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3187          */
3188         switch (mode) {
3189         case DRM_MODE_DPMS_ON:
3190         case DRM_MODE_DPMS_STANDBY:
3191         case DRM_MODE_DPMS_SUSPEND:
3192                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3193                 ironlake_crtc_enable(crtc);
3194                 break;
3195
3196         case DRM_MODE_DPMS_OFF:
3197                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3198                 ironlake_crtc_disable(crtc);
3199                 break;
3200         }
3201 }
3202
3203 static void ironlake_crtc_off(struct drm_crtc *crtc)
3204 {
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         intel_put_pch_pll(intel_crtc);
3207 }
3208
3209 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3210 {
3211         if (!enable && intel_crtc->overlay) {
3212                 struct drm_device *dev = intel_crtc->base.dev;
3213                 struct drm_i915_private *dev_priv = dev->dev_private;
3214
3215                 DRM_LOCK(dev);
3216                 dev_priv->mm.interruptible = false;
3217                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3218                 dev_priv->mm.interruptible = true;
3219                 DRM_UNLOCK(dev);
3220         }
3221
3222         /* Let userspace switch the overlay on again. In most cases userspace
3223          * has to recompute where to put it anyway.
3224          */
3225 }
3226
3227 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3228 {
3229         struct drm_device *dev = crtc->dev;
3230         struct drm_i915_private *dev_priv = dev->dev_private;
3231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232         int pipe = intel_crtc->pipe;
3233         int plane = intel_crtc->plane;
3234
3235         if (intel_crtc->active)
3236                 return;
3237
3238         intel_crtc->active = true;
3239         intel_update_watermarks(dev);
3240
3241         intel_enable_pll(dev_priv, pipe);
3242         intel_enable_pipe(dev_priv, pipe, false);
3243         intel_enable_plane(dev_priv, plane, pipe);
3244
3245         intel_crtc_load_lut(crtc);
3246         intel_update_fbc(dev);
3247
3248         /* Give the overlay scaler a chance to enable if it's on this pipe */
3249         intel_crtc_dpms_overlay(intel_crtc, true);
3250         intel_crtc_update_cursor(crtc, true);
3251 }
3252
3253 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3254 {
3255         struct drm_device *dev = crtc->dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258         int pipe = intel_crtc->pipe;
3259         int plane = intel_crtc->plane;
3260
3261         if (!intel_crtc->active)
3262                 return;
3263
3264         /* Give the overlay scaler a chance to disable if it's on this pipe */
3265         intel_crtc_wait_for_pending_flips(crtc);
3266         drm_vblank_off(dev, pipe);
3267         intel_crtc_dpms_overlay(intel_crtc, false);
3268         intel_crtc_update_cursor(crtc, false);
3269
3270         if (dev_priv->cfb_plane == plane)
3271                 intel_disable_fbc(dev);
3272
3273         intel_disable_plane(dev_priv, plane, pipe);
3274         intel_disable_pipe(dev_priv, pipe);
3275         intel_disable_pll(dev_priv, pipe);
3276
3277         intel_crtc->active = false;
3278         intel_update_fbc(dev);
3279         intel_update_watermarks(dev);
3280 }
3281
3282 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3283 {
3284         /* XXX: When our outputs are all unaware of DPMS modes other than off
3285          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3286          */
3287         switch (mode) {
3288         case DRM_MODE_DPMS_ON:
3289         case DRM_MODE_DPMS_STANDBY:
3290         case DRM_MODE_DPMS_SUSPEND:
3291                 i9xx_crtc_enable(crtc);
3292                 break;
3293         case DRM_MODE_DPMS_OFF:
3294                 i9xx_crtc_disable(crtc);
3295                 break;
3296         }
3297 }
3298
3299 static void i9xx_crtc_off(struct drm_crtc *crtc)
3300 {
3301 }
3302
3303 /**
3304  * Sets the power management mode of the pipe and plane.
3305  */
3306 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3307 {
3308         struct drm_device *dev = crtc->dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         struct drm_i915_master_private *master_priv;
3311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312         int pipe = intel_crtc->pipe;
3313         bool enabled;
3314
3315         if (intel_crtc->dpms_mode == mode)
3316                 return;
3317
3318         intel_crtc->dpms_mode = mode;
3319
3320         dev_priv->display.dpms(crtc, mode);
3321
3322         if (!dev->primary->master)
3323                 return;
3324
3325         master_priv = dev->primary->master->driver_priv;
3326         if (!master_priv->sarea_priv)
3327                 return;
3328
3329         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3330
3331         switch (pipe) {
3332         case 0:
3333                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3334                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3335                 break;
3336         case 1:
3337                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3338                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3339                 break;
3340         default:
3341                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3342                 break;
3343         }
3344 }
3345
3346 static void intel_crtc_disable(struct drm_crtc *crtc)
3347 {
3348         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3349         struct drm_device *dev = crtc->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351
3352         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3353         dev_priv->display.off(crtc);
3354
3355         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3356         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3357
3358         if (crtc->fb) {
3359                 DRM_LOCK(dev);
3360                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3361                 DRM_UNLOCK(dev);
3362         }
3363 }
3364
3365 /* Prepare for a mode set.
3366  *
3367  * Note we could be a lot smarter here.  We need to figure out which outputs
3368  * will be enabled, which disabled (in short, how the config will changes)
3369  * and perform the minimum necessary steps to accomplish that, e.g. updating
3370  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3371  * panel fitting is in the proper state, etc.
3372  */
3373 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3374 {
3375         i9xx_crtc_disable(crtc);
3376 }
3377
3378 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3379 {
3380         i9xx_crtc_enable(crtc);
3381 }
3382
3383 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3384 {
3385         ironlake_crtc_disable(crtc);
3386 }
3387
3388 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3389 {
3390         ironlake_crtc_enable(crtc);
3391 }
3392
3393 void intel_encoder_prepare(struct drm_encoder *encoder)
3394 {
3395         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3396         /* lvds has its own version of prepare see intel_lvds_prepare */
3397         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3398 }
3399
3400 void intel_encoder_commit(struct drm_encoder *encoder)
3401 {
3402         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3403         struct drm_device *dev = encoder->dev;
3404         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3405
3406         /* lvds has its own version of commit see intel_lvds_commit */
3407         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3408
3409         if (HAS_PCH_CPT(dev))
3410                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3411 }
3412
3413 void intel_encoder_destroy(struct drm_encoder *encoder)
3414 {
3415         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3416
3417         drm_encoder_cleanup(encoder);
3418         free(intel_encoder, DRM_MEM_KMS);
3419 }
3420
3421 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3422                                   const struct drm_display_mode *mode,
3423                                   struct drm_display_mode *adjusted_mode)
3424 {
3425         struct drm_device *dev = crtc->dev;
3426
3427         if (HAS_PCH_SPLIT(dev)) {
3428                 /* FDI link clock is fixed at 2.7G */
3429                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3430                         return false;
3431         }
3432
3433         /* All interlaced capable intel hw wants timings in frames. Note though
3434          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3435          * timings, so we need to be careful not to clobber these.*/
3436         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3437                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3438
3439         return true;
3440 }
3441
3442 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3443 {
3444         return 400000; /* FIXME */
3445 }
3446
3447 static int i945_get_display_clock_speed(struct drm_device *dev)
3448 {
3449         return 400000;
3450 }
3451
3452 static int i915_get_display_clock_speed(struct drm_device *dev)
3453 {
3454         return 333000;
3455 }
3456
3457 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3458 {
3459         return 200000;
3460 }
3461
3462 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3463 {
3464         u16 gcfgc = 0;
3465
3466         gcfgc = pci_read_config(dev->dev, GCFGC, 2);
3467
3468         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3469                 return 133000;
3470         else {
3471                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3472                 case GC_DISPLAY_CLOCK_333_MHZ:
3473                         return 333000;
3474                 default:
3475                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3476                         return 190000;
3477                 }
3478         }
3479 }
3480
3481 static int i865_get_display_clock_speed(struct drm_device *dev)
3482 {
3483         return 266000;
3484 }
3485
3486 static int i855_get_display_clock_speed(struct drm_device *dev)
3487 {
3488         u16 hpllcc = 0;
3489         /* Assume that the hardware is in the high speed state.  This
3490          * should be the default.
3491          */
3492         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3493         case GC_CLOCK_133_200:
3494         case GC_CLOCK_100_200:
3495                 return 200000;
3496         case GC_CLOCK_166_250:
3497                 return 250000;
3498         case GC_CLOCK_100_133:
3499                 return 133000;
3500         }
3501
3502         /* Shouldn't happen */
3503         return 0;
3504 }
3505
3506 static int i830_get_display_clock_speed(struct drm_device *dev)
3507 {
3508         return 133000;
3509 }
3510
3511 struct fdi_m_n {
3512         u32        tu;
3513         u32        gmch_m;
3514         u32        gmch_n;
3515         u32        link_m;
3516         u32        link_n;
3517 };
3518
3519 static void
3520 fdi_reduce_ratio(u32 *num, u32 *den)
3521 {
3522         while (*num > 0xffffff || *den > 0xffffff) {
3523                 *num >>= 1;
3524                 *den >>= 1;
3525         }
3526 }
3527
3528 static void
3529 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3530                      int link_clock, struct fdi_m_n *m_n)
3531 {
3532         m_n->tu = 64; /* default size */
3533
3534         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3535         m_n->gmch_m = bits_per_pixel * pixel_clock;
3536         m_n->gmch_n = link_clock * nlanes * 8;
3537         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3538
3539         m_n->link_m = pixel_clock;
3540         m_n->link_n = link_clock;
3541         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3542 }
3543
3544 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3545 {
3546         if (i915_panel_use_ssc >= 0)
3547                 return i915_panel_use_ssc != 0;
3548         return dev_priv->lvds_use_ssc
3549                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3550 }
3551
3552 /**
3553  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3554  * @crtc: CRTC structure
3555  * @mode: requested mode
3556  *
3557  * A pipe may be connected to one or more outputs.  Based on the depth of the
3558  * attached framebuffer, choose a good color depth to use on the pipe.
3559  *
3560  * If possible, match the pipe depth to the fb depth.  In some cases, this
3561  * isn't ideal, because the connected output supports a lesser or restricted
3562  * set of depths.  Resolve that here:
3563  *    LVDS typically supports only 6bpc, so clamp down in that case
3564  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3565  *    Displays may support a restricted set as well, check EDID and clamp as
3566  *      appropriate.
3567  *    DP may want to dither down to 6bpc to fit larger modes
3568  *
3569  * RETURNS:
3570  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3571  * true if they don't match).
3572  */
3573 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3574                                          unsigned int *pipe_bpp,
3575                                          struct drm_display_mode *mode)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct drm_encoder *encoder;
3580         struct drm_connector *connector;
3581         unsigned int display_bpc = UINT_MAX, bpc;
3582
3583         /* Walk the encoders & connectors on this crtc, get min bpc */
3584         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3585                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3586
3587                 if (encoder->crtc != crtc)
3588                         continue;
3589
3590                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3591                         unsigned int lvds_bpc;
3592
3593                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3594                             LVDS_A3_POWER_UP)
3595                                 lvds_bpc = 8;
3596                         else
3597                                 lvds_bpc = 6;
3598
3599                         if (lvds_bpc < display_bpc) {
3600                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3601                                 display_bpc = lvds_bpc;
3602                         }
3603                         continue;
3604                 }
3605
3606                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3607                         /* Use VBT settings if we have an eDP panel */
3608                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3609
3610                         if (edp_bpc < display_bpc) {
3611                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3612                                 display_bpc = edp_bpc;
3613                         }
3614                         continue;
3615                 }
3616
3617                 /* Not one of the known troublemakers, check the EDID */
3618                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3619                                     head) {
3620                         if (connector->encoder != encoder)
3621                                 continue;
3622
3623                         /* Don't use an invalid EDID bpc value */
3624                         if (connector->display_info.bpc &&
3625                             connector->display_info.bpc < display_bpc) {
3626                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3627                                 display_bpc = connector->display_info.bpc;
3628                         }
3629                 }
3630
3631                 /*
3632                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3633                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3634                  */
3635                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3636                         if (display_bpc > 8 && display_bpc < 12) {
3637                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3638                                 display_bpc = 12;
3639                         } else {
3640                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3641                                 display_bpc = 8;
3642                         }
3643                 }
3644         }
3645
3646         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3647                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3648                 display_bpc = 6;
3649         }
3650
3651         /*
3652          * We could just drive the pipe at the highest bpc all the time and
3653          * enable dithering as needed, but that costs bandwidth.  So choose
3654          * the minimum value that expresses the full color range of the fb but
3655          * also stays within the max display bpc discovered above.
3656          */
3657
3658         switch (crtc->fb->depth) {
3659         case 8:
3660                 bpc = 8; /* since we go through a colormap */
3661                 break;
3662         case 15:
3663         case 16:
3664                 bpc = 6; /* min is 18bpp */
3665                 break;
3666         case 24:
3667                 bpc = 8;
3668                 break;
3669         case 30:
3670                 bpc = 10;
3671                 break;
3672         case 48:
3673                 bpc = 12;
3674                 break;
3675         default:
3676                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3677                 bpc = min((unsigned int)8, display_bpc);
3678                 break;
3679         }
3680
3681         display_bpc = min(display_bpc, bpc);
3682
3683         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3684                       bpc, display_bpc);
3685
3686         *pipe_bpp = display_bpc * 3;
3687
3688         return display_bpc != bpc;
3689 }
3690
3691 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         int refclk;
3696
3697         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3698             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3699                 refclk = dev_priv->lvds_ssc_freq * 1000;
3700                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3701                               refclk / 1000);
3702         } else if (!IS_GEN2(dev)) {
3703                 refclk = 96000;
3704         } else {
3705                 refclk = 48000;
3706         }
3707
3708         return refclk;
3709 }
3710
3711 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3712                                       intel_clock_t *clock)
3713 {
3714         /* SDVO TV has fixed PLL values depend on its clock range,
3715            this mirrors vbios setting. */
3716         if (adjusted_mode->clock >= 100000
3717             && adjusted_mode->clock < 140500) {
3718                 clock->p1 = 2;
3719                 clock->p2 = 10;
3720                 clock->n = 3;
3721                 clock->m1 = 16;
3722                 clock->m2 = 8;
3723         } else if (adjusted_mode->clock >= 140500
3724                    && adjusted_mode->clock <= 200000) {
3725                 clock->p1 = 1;
3726                 clock->p2 = 10;
3727                 clock->n = 6;
3728                 clock->m1 = 12;
3729                 clock->m2 = 8;
3730         }
3731 }
3732
3733 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3734                                      intel_clock_t *clock,
3735                                      intel_clock_t *reduced_clock)
3736 {
3737         struct drm_device *dev = crtc->dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         int pipe = intel_crtc->pipe;
3741         u32 fp, fp2 = 0;
3742
3743         if (IS_PINEVIEW(dev)) {
3744                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3745                 if (reduced_clock)
3746                         fp2 = (1 << reduced_clock->n) << 16 |
3747                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3748         } else {
3749                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3750                 if (reduced_clock)
3751                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3752                                 reduced_clock->m2;
3753         }
3754
3755         I915_WRITE(FP0(pipe), fp);
3756
3757         intel_crtc->lowfreq_avail = false;
3758         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3759             reduced_clock && i915_powersave) {
3760                 I915_WRITE(FP1(pipe), fp2);
3761                 intel_crtc->lowfreq_avail = true;
3762         } else {
3763                 I915_WRITE(FP1(pipe), fp);
3764         }
3765 }
3766
3767 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3768                               struct drm_display_mode *adjusted_mode)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773         int pipe = intel_crtc->pipe;
3774         u32 temp;
3775
3776         temp = I915_READ(LVDS);
3777         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3778         if (pipe == 1) {
3779                 temp |= LVDS_PIPEB_SELECT;
3780         } else {
3781                 temp &= ~LVDS_PIPEB_SELECT;
3782         }
3783         /* set the corresponsding LVDS_BORDER bit */
3784         temp |= dev_priv->lvds_border_bits;
3785         /* Set the B0-B3 data pairs corresponding to whether we're going to
3786          * set the DPLLs for dual-channel mode or not.
3787          */
3788         if (clock->p2 == 7)
3789                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3790         else
3791                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3792
3793         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3794          * appropriately here, but we need to look more thoroughly into how
3795          * panels behave in the two modes.
3796          */
3797         /* set the dithering flag on LVDS as needed */
3798         if (INTEL_INFO(dev)->gen >= 4) {
3799                 if (dev_priv->lvds_dither)
3800                         temp |= LVDS_ENABLE_DITHER;
3801                 else
3802                         temp &= ~LVDS_ENABLE_DITHER;
3803         }
3804         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3805         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3806                 temp |= LVDS_HSYNC_POLARITY;
3807         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3808                 temp |= LVDS_VSYNC_POLARITY;
3809         I915_WRITE(LVDS, temp);
3810 }
3811
3812 static void i9xx_update_pll(struct drm_crtc *crtc,
3813                             struct drm_display_mode *mode,
3814                             struct drm_display_mode *adjusted_mode,
3815                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3816                             int num_connectors)
3817 {
3818         struct drm_device *dev = crtc->dev;
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3821         int pipe = intel_crtc->pipe;
3822         u32 dpll;
3823         bool is_sdvo;
3824
3825         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3826                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3827
3828         dpll = DPLL_VGA_MODE_DIS;
3829
3830         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3831                 dpll |= DPLLB_MODE_LVDS;
3832         else
3833                 dpll |= DPLLB_MODE_DAC_SERIAL;
3834         if (is_sdvo) {
3835                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3836                 if (pixel_multiplier > 1) {
3837                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3838                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3839                 }
3840                 dpll |= DPLL_DVO_HIGH_SPEED;
3841         }
3842         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3843                 dpll |= DPLL_DVO_HIGH_SPEED;
3844
3845         /* compute bitmask from p1 value */
3846         if (IS_PINEVIEW(dev))
3847                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3848         else {
3849                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3850                 if (IS_G4X(dev) && reduced_clock)
3851                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3852         }
3853         switch (clock->p2) {
3854         case 5:
3855                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3856                 break;
3857         case 7:
3858                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3859                 break;
3860         case 10:
3861                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3862                 break;
3863         case 14:
3864                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3865                 break;
3866         }
3867         if (INTEL_INFO(dev)->gen >= 4)
3868                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3869
3870         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3871                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3872         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3873                 /* XXX: just matching BIOS for now */
3874                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3875                 dpll |= 3;
3876         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3877                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3878                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3879         else
3880                 dpll |= PLL_REF_INPUT_DREFCLK;
3881
3882         dpll |= DPLL_VCO_ENABLE;
3883         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3884         POSTING_READ(DPLL(pipe));
3885         DELAY(150);
3886
3887         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3888          * This is an exception to the general rule that mode_set doesn't turn
3889          * things on.
3890          */
3891         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3892                 intel_update_lvds(crtc, clock, adjusted_mode);
3893
3894         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3895                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3896
3897         I915_WRITE(DPLL(pipe), dpll);
3898
3899         /* Wait for the clocks to stabilize. */
3900         POSTING_READ(DPLL(pipe));
3901         DELAY(150);
3902
3903         if (INTEL_INFO(dev)->gen >= 4) {
3904                 u32 temp = 0;
3905                 if (is_sdvo) {
3906                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3907                         if (temp > 1)
3908                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3909                         else
3910                                 temp = 0;
3911                 }
3912                 I915_WRITE(DPLL_MD(pipe), temp);
3913         } else {
3914                 /* The pixel multiplier can only be updated once the
3915                  * DPLL is enabled and the clocks are stable.
3916                  *
3917                  * So write it again.
3918                  */
3919                 I915_WRITE(DPLL(pipe), dpll);
3920         }
3921 }
3922
3923 static void i8xx_update_pll(struct drm_crtc *crtc,
3924                             struct drm_display_mode *adjusted_mode,
3925                             intel_clock_t *clock,
3926                             int num_connectors)
3927 {
3928         struct drm_device *dev = crtc->dev;
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931         int pipe = intel_crtc->pipe;
3932         u32 dpll;
3933
3934         dpll = DPLL_VGA_MODE_DIS;
3935
3936         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3937                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3938         } else {
3939                 if (clock->p1 == 2)
3940                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3941                 else
3942                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3943                 if (clock->p2 == 4)
3944                         dpll |= PLL_P2_DIVIDE_BY_4;
3945         }
3946
3947         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3948                 /* XXX: just matching BIOS for now */
3949                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3950                 dpll |= 3;
3951         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3952                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3953                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3954         else
3955                 dpll |= PLL_REF_INPUT_DREFCLK;
3956
3957         dpll |= DPLL_VCO_ENABLE;
3958         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3959         POSTING_READ(DPLL(pipe));
3960         DELAY(150);
3961
3962         I915_WRITE(DPLL(pipe), dpll);
3963
3964         /* Wait for the clocks to stabilize. */
3965         POSTING_READ(DPLL(pipe));
3966         DELAY(150);
3967
3968         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3969          * This is an exception to the general rule that mode_set doesn't turn
3970          * things on.
3971          */
3972         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3973                 intel_update_lvds(crtc, clock, adjusted_mode);
3974
3975         /* The pixel multiplier can only be updated once the
3976          * DPLL is enabled and the clocks are stable.
3977          *
3978          * So write it again.
3979          */
3980         I915_WRITE(DPLL(pipe), dpll);
3981 }
3982
3983 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3984                               struct drm_display_mode *mode,
3985                               struct drm_display_mode *adjusted_mode,
3986                               int x, int y,
3987                               struct drm_framebuffer *old_fb)
3988 {
3989         struct drm_device *dev = crtc->dev;
3990         struct drm_i915_private *dev_priv = dev->dev_private;
3991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992         int pipe = intel_crtc->pipe;
3993         int plane = intel_crtc->plane;
3994         int refclk, num_connectors = 0;
3995         intel_clock_t clock, reduced_clock;
3996         u32 dspcntr, pipeconf, vsyncshift;
3997         bool ok, has_reduced_clock = false, is_sdvo = false;
3998         bool is_lvds = false, is_tv = false, is_dp = false;
3999         struct drm_mode_config *mode_config = &dev->mode_config;
4000         struct intel_encoder *encoder;
4001         const intel_limit_t *limit;
4002         int ret;
4003
4004         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4005                 if (encoder->base.crtc != crtc)
4006                         continue;
4007
4008                 switch (encoder->type) {
4009                 case INTEL_OUTPUT_LVDS:
4010                         is_lvds = true;
4011                         break;
4012                 case INTEL_OUTPUT_SDVO:
4013                 case INTEL_OUTPUT_HDMI:
4014                         is_sdvo = true;
4015                         if (encoder->needs_tv_clock)
4016                                 is_tv = true;
4017                         break;
4018                 case INTEL_OUTPUT_TVOUT:
4019                         is_tv = true;
4020                         break;
4021                 case INTEL_OUTPUT_DISPLAYPORT:
4022                         is_dp = true;
4023                         break;
4024                 }
4025
4026                 num_connectors++;
4027         }
4028
4029         refclk = i9xx_get_refclk(crtc, num_connectors);
4030
4031         /*
4032          * Returns a set of divisors for the desired target clock with the given
4033          * refclk, or false.  The returned values represent the clock equation:
4034          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4035          */
4036         limit = intel_limit(crtc, refclk);
4037         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4038                              &clock);
4039         if (!ok) {
4040                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4041                 return -EINVAL;
4042         }
4043
4044         /* Ensure that the cursor is valid for the new mode before changing... */
4045         intel_crtc_update_cursor(crtc, true);
4046
4047         if (is_lvds && dev_priv->lvds_downclock_avail) {
4048                 /*
4049                  * Ensure we match the reduced clock's P to the target clock.
4050                  * If the clocks don't match, we can't switch the display clock
4051                  * by using the FP0/FP1. In such case we will disable the LVDS
4052                  * downclock feature.
4053                 */
4054                 has_reduced_clock = limit->find_pll(limit, crtc,
4055                                                     dev_priv->lvds_downclock,
4056                                                     refclk,
4057                                                     &clock,
4058                                                     &reduced_clock);
4059         }
4060
4061         if (is_sdvo && is_tv)
4062                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4063
4064         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4065                                  &reduced_clock : NULL);
4066
4067         if (IS_GEN2(dev))
4068                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4069         else
4070                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4071                                 has_reduced_clock ? &reduced_clock : NULL,
4072                                 num_connectors);
4073
4074         /* setup pipeconf */
4075         pipeconf = I915_READ(PIPECONF(pipe));
4076
4077         /* Set up the display plane register */
4078         dspcntr = DISPPLANE_GAMMA_ENABLE;
4079
4080         if (pipe == 0)
4081                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4082         else
4083                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4084
4085         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4086                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4087                  * core speed.
4088                  *
4089                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4090                  * pipe == 0 check?
4091                  */
4092                 if (mode->clock >
4093                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4094                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4095                 else
4096                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4097         }
4098
4099         /* default to 8bpc */
4100         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4101         if (is_dp) {
4102                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4103                         pipeconf |= PIPECONF_BPP_6 |
4104                                     PIPECONF_DITHER_EN |
4105                                     PIPECONF_DITHER_TYPE_SP;
4106                 }
4107         }
4108
4109         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4110         drm_mode_debug_printmodeline(mode);
4111
4112         if (HAS_PIPE_CXSR(dev)) {
4113                 if (intel_crtc->lowfreq_avail) {
4114                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4115                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4116                 } else {
4117                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4118                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4119                 }
4120         }
4121
4122         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4123         if (!IS_GEN2(dev) &&
4124             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4125                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4126                 /* the chip adds 2 halflines automatically */
4127                 adjusted_mode->crtc_vtotal -= 1;
4128                 adjusted_mode->crtc_vblank_end -= 1;
4129                 vsyncshift = adjusted_mode->crtc_hsync_start
4130                              - adjusted_mode->crtc_htotal/2;
4131         } else {
4132                 pipeconf |= PIPECONF_PROGRESSIVE;
4133                 vsyncshift = 0;
4134         }
4135
4136         if (!IS_GEN3(dev))
4137                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4138
4139         I915_WRITE(HTOTAL(pipe),
4140                    (adjusted_mode->crtc_hdisplay - 1) |
4141                    ((adjusted_mode->crtc_htotal - 1) << 16));
4142         I915_WRITE(HBLANK(pipe),
4143                    (adjusted_mode->crtc_hblank_start - 1) |
4144                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4145         I915_WRITE(HSYNC(pipe),
4146                    (adjusted_mode->crtc_hsync_start - 1) |
4147                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4148
4149         I915_WRITE(VTOTAL(pipe),
4150                    (adjusted_mode->crtc_vdisplay - 1) |
4151                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4152         I915_WRITE(VBLANK(pipe),
4153                    (adjusted_mode->crtc_vblank_start - 1) |
4154                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4155         I915_WRITE(VSYNC(pipe),
4156                    (adjusted_mode->crtc_vsync_start - 1) |
4157                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4158
4159         /* pipesrc and dspsize control the size that is scaled from,
4160          * which should always be the user's requested size.
4161          */
4162         I915_WRITE(DSPSIZE(plane),
4163                    ((mode->vdisplay - 1) << 16) |
4164                    (mode->hdisplay - 1));
4165         I915_WRITE(DSPPOS(plane), 0);
4166         I915_WRITE(PIPESRC(pipe),
4167                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4168
4169         I915_WRITE(PIPECONF(pipe), pipeconf);
4170         POSTING_READ(PIPECONF(pipe));
4171         intel_enable_pipe(dev_priv, pipe, false);
4172
4173         intel_wait_for_vblank(dev, pipe);
4174
4175         I915_WRITE(DSPCNTR(plane), dspcntr);
4176         POSTING_READ(DSPCNTR(plane));
4177
4178         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4179
4180         intel_update_watermarks(dev);
4181
4182         return ret;
4183 }
4184
4185 /*
4186  * Initialize reference clocks when the driver loads
4187  */
4188 void ironlake_init_pch_refclk(struct drm_device *dev)
4189 {
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct drm_mode_config *mode_config = &dev->mode_config;
4192         struct intel_encoder *encoder;
4193         u32 temp;
4194         bool has_lvds = false;
4195         bool has_cpu_edp = false;
4196         bool has_pch_edp = false;
4197         bool has_panel = false;
4198         bool has_ck505 = false;
4199         bool can_ssc = false;
4200
4201         /* We need to take the global config into account */
4202         list_for_each_entry(encoder, &mode_config->encoder_list,
4203                             base.head) {
4204                 switch (encoder->type) {
4205                 case INTEL_OUTPUT_LVDS:
4206                         has_panel = true;
4207                         has_lvds = true;
4208                         break;
4209                 case INTEL_OUTPUT_EDP:
4210                         has_panel = true;
4211                         if (intel_encoder_is_pch_edp(&encoder->base))
4212                                 has_pch_edp = true;
4213                         else
4214                                 has_cpu_edp = true;
4215                         break;
4216                 }
4217         }
4218
4219         if (HAS_PCH_IBX(dev)) {
4220                 has_ck505 = dev_priv->display_clock_mode;
4221                 can_ssc = has_ck505;
4222         } else {
4223                 has_ck505 = false;
4224                 can_ssc = true;
4225         }
4226
4227         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4228                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4229                       has_ck505);
4230
4231         /* Ironlake: try to setup display ref clock before DPLL
4232          * enabling. This is only under driver's control after
4233          * PCH B stepping, previous chipset stepping should be
4234          * ignoring this setting.
4235          */
4236         temp = I915_READ(PCH_DREF_CONTROL);
4237         /* Always enable nonspread source */
4238         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4239
4240         if (has_ck505)
4241                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4242         else
4243                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4244
4245         if (has_panel) {
4246                 temp &= ~DREF_SSC_SOURCE_MASK;
4247                 temp |= DREF_SSC_SOURCE_ENABLE;
4248
4249                 /* SSC must be turned on before enabling the CPU output  */
4250                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4251                         DRM_DEBUG_KMS("Using SSC on panel\n");
4252                         temp |= DREF_SSC1_ENABLE;
4253                 } else
4254                         temp &= ~DREF_SSC1_ENABLE;
4255
4256                 /* Get SSC going before enabling the outputs */
4257                 I915_WRITE(PCH_DREF_CONTROL, temp);
4258                 POSTING_READ(PCH_DREF_CONTROL);
4259                 DELAY(200);
4260
4261                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4262
4263                 /* Enable CPU source on CPU attached eDP */
4264                 if (has_cpu_edp) {
4265                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4266                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4267                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4268                         }
4269                         else
4270                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4271                 } else
4272                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4273
4274                 I915_WRITE(PCH_DREF_CONTROL, temp);
4275                 POSTING_READ(PCH_DREF_CONTROL);
4276                 DELAY(200);
4277         } else {
4278                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4279
4280                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4281
4282                 /* Turn off CPU output */
4283                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4284
4285                 I915_WRITE(PCH_DREF_CONTROL, temp);
4286                 POSTING_READ(PCH_DREF_CONTROL);
4287                 DELAY(200);
4288
4289                 /* Turn off the SSC source */
4290                 temp &= ~DREF_SSC_SOURCE_MASK;
4291                 temp |= DREF_SSC_SOURCE_DISABLE;
4292
4293                 /* Turn off SSC1 */
4294                 temp &= ~ DREF_SSC1_ENABLE;
4295
4296                 I915_WRITE(PCH_DREF_CONTROL, temp);
4297                 POSTING_READ(PCH_DREF_CONTROL);
4298                 DELAY(200);
4299         }
4300 }
4301
4302 static int ironlake_get_refclk(struct drm_crtc *crtc)
4303 {
4304         struct drm_device *dev = crtc->dev;
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         struct intel_encoder *encoder;
4307         struct drm_mode_config *mode_config = &dev->mode_config;
4308         struct intel_encoder *edp_encoder = NULL;
4309         int num_connectors = 0;
4310         bool is_lvds = false;
4311
4312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4313                 if (encoder->base.crtc != crtc)
4314                         continue;
4315
4316                 switch (encoder->type) {
4317                 case INTEL_OUTPUT_LVDS:
4318                         is_lvds = true;
4319                         break;
4320                 case INTEL_OUTPUT_EDP:
4321                         edp_encoder = encoder;
4322                         break;
4323                 }
4324                 num_connectors++;
4325         }
4326
4327         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4328                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4329                               dev_priv->lvds_ssc_freq);
4330                 return dev_priv->lvds_ssc_freq * 1000;
4331         }
4332
4333         return 120000;
4334 }
4335
4336 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4337                                   struct drm_display_mode *mode,
4338                                   struct drm_display_mode *adjusted_mode,
4339                                   int x, int y,
4340                                   struct drm_framebuffer *old_fb)
4341 {
4342         struct drm_device *dev = crtc->dev;
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4345         int pipe = intel_crtc->pipe;
4346         int plane = intel_crtc->plane;
4347         int refclk, num_connectors = 0;
4348         intel_clock_t clock, reduced_clock;
4349         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4350         bool ok, has_reduced_clock = false, is_sdvo = false;
4351         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4352         struct drm_mode_config *mode_config = &dev->mode_config;
4353         struct intel_encoder *encoder, *edp_encoder = NULL;
4354         const intel_limit_t *limit;
4355         int ret;
4356         struct fdi_m_n m_n = {0};
4357         u32 temp;
4358         int target_clock, pixel_multiplier, lane, link_bw, factor;
4359         unsigned int pipe_bpp;
4360         bool dither;
4361         bool is_cpu_edp = false, is_pch_edp = false;
4362
4363         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4364                 if (encoder->base.crtc != crtc)
4365                         continue;
4366
4367                 switch (encoder->type) {
4368                 case INTEL_OUTPUT_LVDS:
4369                         is_lvds = true;
4370                         break;
4371                 case INTEL_OUTPUT_SDVO:
4372                 case INTEL_OUTPUT_HDMI:
4373                         is_sdvo = true;
4374                         if (encoder->needs_tv_clock)
4375                                 is_tv = true;
4376                         break;
4377                 case INTEL_OUTPUT_TVOUT:
4378                         is_tv = true;
4379                         break;
4380                 case INTEL_OUTPUT_ANALOG:
4381                         is_crt = true;
4382                         break;
4383                 case INTEL_OUTPUT_DISPLAYPORT:
4384                         is_dp = true;
4385                         break;
4386                 case INTEL_OUTPUT_EDP:
4387                         is_dp = true;
4388                         if (intel_encoder_is_pch_edp(&encoder->base))
4389                                 is_pch_edp = true;
4390                         else
4391                                 is_cpu_edp = true;
4392                         edp_encoder = encoder;
4393                         break;
4394                 }
4395
4396                 num_connectors++;
4397         }
4398
4399         refclk = ironlake_get_refclk(crtc);
4400
4401         /*
4402          * Returns a set of divisors for the desired target clock with the given
4403          * refclk, or false.  The returned values represent the clock equation:
4404          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4405          */
4406         limit = intel_limit(crtc, refclk);
4407         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4408                              &clock);
4409         if (!ok) {
4410                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4411                 return -EINVAL;
4412         }
4413
4414         /* Ensure that the cursor is valid for the new mode before changing... */
4415         intel_crtc_update_cursor(crtc, true);
4416
4417         if (is_lvds && dev_priv->lvds_downclock_avail) {
4418                 /*
4419                  * Ensure we match the reduced clock's P to the target clock.
4420                  * If the clocks don't match, we can't switch the display clock
4421                  * by using the FP0/FP1. In such case we will disable the LVDS
4422                  * downclock feature.
4423                 */
4424                 has_reduced_clock = limit->find_pll(limit, crtc,
4425                                                     dev_priv->lvds_downclock,
4426                                                     refclk,
4427                                                     &clock,
4428                                                     &reduced_clock);
4429         }
4430         /* SDVO TV has fixed PLL values depend on its clock range,
4431            this mirrors vbios setting. */
4432         if (is_sdvo && is_tv) {
4433                 if (adjusted_mode->clock >= 100000
4434                     && adjusted_mode->clock < 140500) {
4435                         clock.p1 = 2;
4436                         clock.p2 = 10;
4437                         clock.n = 3;
4438                         clock.m1 = 16;
4439                         clock.m2 = 8;
4440                 } else if (adjusted_mode->clock >= 140500
4441                            && adjusted_mode->clock <= 200000) {
4442                         clock.p1 = 1;
4443                         clock.p2 = 10;
4444                         clock.n = 6;
4445                         clock.m1 = 12;
4446                         clock.m2 = 8;
4447                 }
4448         }
4449
4450         /* FDI link */
4451         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4452         lane = 0;
4453         /* CPU eDP doesn't require FDI link, so just set DP M/N
4454            according to current link config */
4455         if (is_cpu_edp) {
4456                 target_clock = mode->clock;
4457                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4458         } else {
4459                 /* [e]DP over FDI requires target mode clock
4460                    instead of link clock */
4461                 if (is_dp)
4462                         target_clock = mode->clock;
4463                 else
4464                         target_clock = adjusted_mode->clock;
4465
4466                 /* FDI is a binary signal running at ~2.7GHz, encoding
4467                  * each output octet as 10 bits. The actual frequency
4468                  * is stored as a divider into a 100MHz clock, and the
4469                  * mode pixel clock is stored in units of 1KHz.
4470                  * Hence the bw of each lane in terms of the mode signal
4471                  * is:
4472                  */
4473                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4474         }
4475
4476         /* determine panel color depth */
4477         temp = I915_READ(PIPECONF(pipe));
4478         temp &= ~PIPE_BPC_MASK;
4479         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4480         switch (pipe_bpp) {
4481         case 18:
4482                 temp |= PIPE_6BPC;
4483                 break;
4484         case 24:
4485                 temp |= PIPE_8BPC;
4486                 break;
4487         case 30:
4488                 temp |= PIPE_10BPC;
4489                 break;
4490         case 36:
4491                 temp |= PIPE_12BPC;
4492                 break;
4493         default:
4494                 printf("intel_choose_pipe_bpp returned invalid value %d\n",
4495                         pipe_bpp);
4496                 temp |= PIPE_8BPC;
4497                 pipe_bpp = 24;
4498                 break;
4499         }
4500
4501         intel_crtc->bpp = pipe_bpp;
4502         I915_WRITE(PIPECONF(pipe), temp);
4503
4504         if (!lane) {
4505                 /*
4506                  * Account for spread spectrum to avoid
4507                  * oversubscribing the link. Max center spread
4508                  * is 2.5%; use 5% for safety's sake.
4509                  */
4510                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4511                 lane = bps / (link_bw * 8) + 1;
4512         }
4513
4514         intel_crtc->fdi_lanes = lane;
4515
4516         if (pixel_multiplier > 1)
4517                 link_bw *= pixel_multiplier;
4518         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4519                              &m_n);
4520
4521         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4522         if (has_reduced_clock)
4523                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4524                         reduced_clock.m2;
4525
4526         /* Enable autotuning of the PLL clock (if permissible) */
4527         factor = 21;
4528         if (is_lvds) {
4529                 if ((intel_panel_use_ssc(dev_priv) &&
4530                      dev_priv->lvds_ssc_freq == 100) ||
4531                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4532                         factor = 25;
4533         } else if (is_sdvo && is_tv)
4534                 factor = 20;
4535
4536         if (clock.m < factor * clock.n)
4537                 fp |= FP_CB_TUNE;
4538
4539         dpll = 0;
4540
4541         if (is_lvds)
4542                 dpll |= DPLLB_MODE_LVDS;
4543         else
4544                 dpll |= DPLLB_MODE_DAC_SERIAL;
4545         if (is_sdvo) {
4546                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4547                 if (pixel_multiplier > 1) {
4548                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4549                 }
4550                 dpll |= DPLL_DVO_HIGH_SPEED;
4551         }
4552         if (is_dp && !is_cpu_edp)
4553                 dpll |= DPLL_DVO_HIGH_SPEED;
4554
4555         /* compute bitmask from p1 value */
4556         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557         /* also FPA1 */
4558         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559
4560         switch (clock.p2) {
4561         case 5:
4562                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563                 break;
4564         case 7:
4565                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566                 break;
4567         case 10:
4568                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569                 break;
4570         case 14:
4571                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572                 break;
4573         }
4574
4575         if (is_sdvo && is_tv)
4576                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4577         else if (is_tv)
4578                 /* XXX: just matching BIOS for now */
4579                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4580                 dpll |= 3;
4581         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4582                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4583         else
4584                 dpll |= PLL_REF_INPUT_DREFCLK;
4585
4586         /* setup pipeconf */
4587         pipeconf = I915_READ(PIPECONF(pipe));
4588
4589         /* Set up the display plane register */
4590         dspcntr = DISPPLANE_GAMMA_ENABLE;
4591         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4592         drm_mode_debug_printmodeline(mode);
4593
4594         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4595          * pre-Haswell/LPT generation */
4596         if (HAS_PCH_LPT(dev)) {
4597                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4598                                 pipe);
4599         } else if (!is_cpu_edp) {
4600                 struct intel_pch_pll *pll;
4601
4602                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4603                 if (pll == NULL) {
4604                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4605                                          pipe);
4606                         return -EINVAL;
4607                 }
4608         } else
4609                 intel_put_pch_pll(intel_crtc);
4610
4611         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4612          * This is an exception to the general rule that mode_set doesn't turn
4613          * things on.
4614          */
4615         if (is_lvds) {
4616                 temp = I915_READ(PCH_LVDS);
4617                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4618                 if (HAS_PCH_CPT(dev)) {
4619                         temp &= ~PORT_TRANS_SEL_MASK;
4620                         temp |= PORT_TRANS_SEL_CPT(pipe);
4621                 } else {
4622                         if (pipe == 1)
4623                                 temp |= LVDS_PIPEB_SELECT;
4624                         else
4625                                 temp &= ~LVDS_PIPEB_SELECT;
4626                 }
4627
4628                 /* set the corresponsding LVDS_BORDER bit */
4629                 temp |= dev_priv->lvds_border_bits;
4630                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4631                  * set the DPLLs for dual-channel mode or not.
4632                  */
4633                 if (clock.p2 == 7)
4634                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4635                 else
4636                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4637
4638                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4639                  * appropriately here, but we need to look more thoroughly into how
4640                  * panels behave in the two modes.
4641                  */
4642                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4643                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4644                         temp |= LVDS_HSYNC_POLARITY;
4645                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4646                         temp |= LVDS_VSYNC_POLARITY;
4647                 I915_WRITE(PCH_LVDS, temp);
4648         }
4649
4650         pipeconf &= ~PIPECONF_DITHER_EN;
4651         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4652         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4653                 pipeconf |= PIPECONF_DITHER_EN;
4654                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4655         }
4656         if (is_dp && !is_cpu_edp) {
4657                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4658         } else {
4659                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4660                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4661                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4662                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4663                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4664         }
4665
4666         if (intel_crtc->pch_pll) {
4667                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4668
4669                 /* Wait for the clocks to stabilize. */
4670                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4671                 DELAY(150);
4672
4673                 /* The pixel multiplier can only be updated once the
4674                  * DPLL is enabled and the clocks are stable.
4675                  *
4676                  * So write it again.
4677                  */
4678                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4679         }
4680
4681         intel_crtc->lowfreq_avail = false;
4682         if (intel_crtc->pch_pll) {
4683                 if (is_lvds && has_reduced_clock && i915_powersave) {
4684                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4685                         intel_crtc->lowfreq_avail = true;
4686                         if (HAS_PIPE_CXSR(dev)) {
4687                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4688                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4689                         }
4690                 } else {
4691                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4692                         if (HAS_PIPE_CXSR(dev)) {
4693                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4694                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4695                         }
4696                 }
4697         }
4698
4699         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4700         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4701                 pipeconf |= PIPECONF_INTERLACED_ILK;
4702                 /* the chip adds 2 halflines automatically */
4703                 adjusted_mode->crtc_vtotal -= 1;
4704                 adjusted_mode->crtc_vblank_end -= 1;
4705                 I915_WRITE(VSYNCSHIFT(pipe),
4706                            adjusted_mode->crtc_hsync_start
4707                            - adjusted_mode->crtc_htotal/2);
4708         } else {
4709                 pipeconf |= PIPECONF_PROGRESSIVE;
4710                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4711         }
4712
4713         I915_WRITE(HTOTAL(pipe),
4714                    (adjusted_mode->crtc_hdisplay - 1) |
4715                    ((adjusted_mode->crtc_htotal - 1) << 16));
4716         I915_WRITE(HBLANK(pipe),
4717                    (adjusted_mode->crtc_hblank_start - 1) |
4718                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4719         I915_WRITE(HSYNC(pipe),
4720                    (adjusted_mode->crtc_hsync_start - 1) |
4721                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4722
4723         I915_WRITE(VTOTAL(pipe),
4724                    (adjusted_mode->crtc_vdisplay - 1) |
4725                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4726         I915_WRITE(VBLANK(pipe),
4727                    (adjusted_mode->crtc_vblank_start - 1) |
4728                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4729         I915_WRITE(VSYNC(pipe),
4730                    (adjusted_mode->crtc_vsync_start - 1) |
4731                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4732
4733         /* pipesrc controls the size that is scaled from, which should
4734          * always be the user's requested size.
4735          */
4736         I915_WRITE(PIPESRC(pipe),
4737                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4738
4739         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4740         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4741         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4742         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4743
4744         if (is_cpu_edp)
4745                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4746
4747         I915_WRITE(PIPECONF(pipe), pipeconf);
4748         POSTING_READ(PIPECONF(pipe));
4749
4750         intel_wait_for_vblank(dev, pipe);
4751
4752         I915_WRITE(DSPCNTR(plane), dspcntr);
4753         POSTING_READ(DSPCNTR(plane));
4754
4755         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4756
4757         intel_update_watermarks(dev);
4758
4759         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4760
4761         return ret;
4762 }
4763
4764 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4765                                struct drm_display_mode *mode,
4766                                struct drm_display_mode *adjusted_mode,
4767                                int x, int y,
4768                                struct drm_framebuffer *old_fb)
4769 {
4770         struct drm_device *dev = crtc->dev;
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4773         int pipe = intel_crtc->pipe;
4774         int ret;
4775
4776         drm_vblank_pre_modeset(dev, pipe);
4777
4778         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4779                                               x, y, old_fb);
4780         drm_vblank_post_modeset(dev, pipe);
4781
4782         if (ret)
4783                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4784         else
4785                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4786
4787         return ret;
4788 }
4789
4790 static bool intel_eld_uptodate(struct drm_connector *connector,
4791                                int reg_eldv, uint32_t bits_eldv,
4792                                int reg_elda, uint32_t bits_elda,
4793                                int reg_edid)
4794 {
4795         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4796         uint8_t *eld = connector->eld;
4797         uint32_t i;
4798
4799         i = I915_READ(reg_eldv);
4800         i &= bits_eldv;
4801
4802         if (!eld[0])
4803                 return !i;
4804
4805         if (!i)
4806                 return false;
4807
4808         i = I915_READ(reg_elda);
4809         i &= ~bits_elda;
4810         I915_WRITE(reg_elda, i);
4811
4812         for (i = 0; i < eld[2]; i++)
4813                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4814                         return false;
4815
4816         return true;
4817 }
4818
4819 static void g4x_write_eld(struct drm_connector *connector,
4820                           struct drm_crtc *crtc)
4821 {
4822         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4823         uint8_t *eld = connector->eld;
4824         uint32_t eldv;
4825         uint32_t len;
4826         uint32_t i;
4827
4828         i = I915_READ(G4X_AUD_VID_DID);
4829
4830         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4831                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4832         else
4833                 eldv = G4X_ELDV_DEVCTG;
4834
4835         if (intel_eld_uptodate(connector,
4836                                G4X_AUD_CNTL_ST, eldv,
4837                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4838                                G4X_HDMIW_HDMIEDID))
4839                 return;
4840
4841         i = I915_READ(G4X_AUD_CNTL_ST);
4842         i &= ~(eldv | G4X_ELD_ADDR);
4843         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4844         I915_WRITE(G4X_AUD_CNTL_ST, i);
4845
4846         if (!eld[0])
4847                 return;
4848
4849         if (eld[2] < (uint8_t)len)
4850                 len = eld[2];
4851         DRM_DEBUG_KMS("ELD size %d\n", len);
4852         for (i = 0; i < len; i++)
4853                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4854
4855         i = I915_READ(G4X_AUD_CNTL_ST);
4856         i |= eldv;
4857         I915_WRITE(G4X_AUD_CNTL_ST, i);
4858 }
4859
4860 static void ironlake_write_eld(struct drm_connector *connector,
4861                                      struct drm_crtc *crtc)
4862 {
4863         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4864         uint8_t *eld = connector->eld;
4865         uint32_t eldv;
4866         uint32_t i;
4867         int len;
4868         int hdmiw_hdmiedid;
4869         int aud_config;
4870         int aud_cntl_st;
4871         int aud_cntrl_st2;
4872
4873         if (HAS_PCH_IBX(connector->dev)) {
4874                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4875                 aud_config = IBX_AUD_CONFIG_A;
4876                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4877                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4878         } else {
4879                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4880                 aud_config = CPT_AUD_CONFIG_A;
4881                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4882                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4883         }
4884
4885         i = to_intel_crtc(crtc)->pipe;
4886         hdmiw_hdmiedid += i * 0x100;
4887         aud_cntl_st += i * 0x100;
4888         aud_config += i * 0x100;
4889
4890         DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
4891
4892         i = I915_READ(aud_cntl_st);
4893         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4894         if (!i) {
4895                 DRM_DEBUG_KMS("Audio directed to unknown port\n");
4896                 /* operate blindly on all ports */
4897                 eldv = IBX_ELD_VALIDB;
4898                 eldv |= IBX_ELD_VALIDB << 4;
4899                 eldv |= IBX_ELD_VALIDB << 8;
4900         } else {
4901                 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
4902                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4903         }
4904
4905         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4906                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4907                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4908                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4909         } else
4910                 I915_WRITE(aud_config, 0);
4911
4912         if (intel_eld_uptodate(connector,
4913                                aud_cntrl_st2, eldv,
4914                                aud_cntl_st, IBX_ELD_ADDRESS,
4915                                hdmiw_hdmiedid))
4916                 return;
4917
4918         i = I915_READ(aud_cntrl_st2);
4919         i &= ~eldv;
4920         I915_WRITE(aud_cntrl_st2, i);
4921
4922         if (!eld[0])
4923                 return;
4924
4925         i = I915_READ(aud_cntl_st);
4926         i &= ~IBX_ELD_ADDRESS;
4927         I915_WRITE(aud_cntl_st, i);
4928
4929         /* 84 bytes of hw ELD buffer */
4930         len = 21;
4931         if (eld[2] < (uint8_t)len)
4932                 len = eld[2];
4933         DRM_DEBUG_KMS("ELD size %d\n", len);
4934         for (i = 0; i < len; i++)
4935                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4936
4937         i = I915_READ(aud_cntrl_st2);
4938         i |= eldv;
4939         I915_WRITE(aud_cntrl_st2, i);
4940 }
4941
4942 void intel_write_eld(struct drm_encoder *encoder,
4943                      struct drm_display_mode *mode)
4944 {
4945         struct drm_crtc *crtc = encoder->crtc;
4946         struct drm_connector *connector;
4947         struct drm_device *dev = encoder->dev;
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949
4950         connector = drm_select_eld(encoder, mode);
4951         if (!connector)
4952                 return;
4953
4954         DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4955                          connector->base.id,
4956                          drm_get_connector_name(connector),
4957                          connector->encoder->base.id,
4958                          drm_get_encoder_name(connector->encoder));
4959
4960         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4961
4962         if (dev_priv->display.write_eld)
4963                 dev_priv->display.write_eld(connector, crtc);
4964 }
4965
4966 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4967 void intel_crtc_load_lut(struct drm_crtc *crtc)
4968 {
4969         struct drm_device *dev = crtc->dev;
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972         int palreg = PALETTE(intel_crtc->pipe);
4973         int i;
4974
4975         /* The clocks have to be on to load the palette. */
4976         if (!crtc->enabled || !intel_crtc->active)
4977                 return;
4978
4979         /* use legacy palette for Ironlake */
4980         if (HAS_PCH_SPLIT(dev))
4981                 palreg = LGC_PALETTE(intel_crtc->pipe);
4982
4983         for (i = 0; i < 256; i++) {
4984                 I915_WRITE(palreg + 4 * i,
4985                            (intel_crtc->lut_r[i] << 16) |
4986                            (intel_crtc->lut_g[i] << 8) |
4987                            intel_crtc->lut_b[i]);
4988         }
4989 }
4990
4991 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4992 {
4993         struct drm_device *dev = crtc->dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4996         bool visible = base != 0;
4997         u32 cntl;
4998
4999         if (intel_crtc->cursor_visible == visible)
5000                 return;
5001
5002         cntl = I915_READ(_CURACNTR);
5003         if (visible) {
5004                 /* On these chipsets we can only modify the base whilst
5005                  * the cursor is disabled.
5006                  */
5007                 I915_WRITE(_CURABASE, base);
5008
5009                 cntl &= ~(CURSOR_FORMAT_MASK);
5010                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5011                 cntl |= CURSOR_ENABLE |
5012                         CURSOR_GAMMA_ENABLE |
5013                         CURSOR_FORMAT_ARGB;
5014         } else
5015                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5016         I915_WRITE(_CURACNTR, cntl);
5017
5018         intel_crtc->cursor_visible = visible;
5019 }
5020
5021 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5022 {
5023         struct drm_device *dev = crtc->dev;
5024         struct drm_i915_private *dev_priv = dev->dev_private;
5025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026         int pipe = intel_crtc->pipe;
5027         bool visible = base != 0;
5028
5029         if (intel_crtc->cursor_visible != visible) {
5030                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5031                 if (base) {
5032                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5033                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5034                         cntl |= pipe << 28; /* Connect to correct pipe */
5035                 } else {
5036                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5037                         cntl |= CURSOR_MODE_DISABLE;
5038                 }
5039                 I915_WRITE(CURCNTR(pipe), cntl);
5040
5041                 intel_crtc->cursor_visible = visible;
5042         }
5043         /* and commit changes on next vblank */
5044         I915_WRITE(CURBASE(pipe), base);
5045 }
5046
5047 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5048 {
5049         struct drm_device *dev = crtc->dev;
5050         struct drm_i915_private *dev_priv = dev->dev_private;
5051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5052         int pipe = intel_crtc->pipe;
5053         bool visible = base != 0;
5054
5055         if (intel_crtc->cursor_visible != visible) {
5056                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5057                 if (base) {
5058                         cntl &= ~CURSOR_MODE;
5059                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5060                 } else {
5061                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5062                         cntl |= CURSOR_MODE_DISABLE;
5063                 }
5064                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5065
5066                 intel_crtc->cursor_visible = visible;
5067         }
5068         /* and commit changes on next vblank */
5069         I915_WRITE(CURBASE_IVB(pipe), base);
5070 }
5071
5072 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5073 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5074                                      bool on)
5075 {
5076         struct drm_device *dev = crtc->dev;
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079         int pipe = intel_crtc->pipe;
5080         int x = intel_crtc->cursor_x;
5081         int y = intel_crtc->cursor_y;
5082         u32 base, pos;
5083         bool visible;
5084
5085         pos = 0;
5086
5087         if (on && crtc->enabled && crtc->fb) {
5088                 base = intel_crtc->cursor_addr;
5089                 if (x > (int) crtc->fb->width)
5090                         base = 0;
5091
5092                 if (y > (int) crtc->fb->height)
5093                         base = 0;
5094         } else
5095                 base = 0;
5096
5097         if (x < 0) {
5098                 if (x + intel_crtc->cursor_width < 0)
5099                         base = 0;
5100
5101                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5102                 x = -x;
5103         }
5104         pos |= x << CURSOR_X_SHIFT;
5105
5106         if (y < 0) {
5107                 if (y + intel_crtc->cursor_height < 0)
5108                         base = 0;
5109
5110                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5111                 y = -y;
5112         }
5113         pos |= y << CURSOR_Y_SHIFT;
5114
5115         visible = base != 0;
5116         if (!visible && !intel_crtc->cursor_visible)
5117                 return;
5118
5119         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5120                 I915_WRITE(CURPOS_IVB(pipe), pos);
5121                 ivb_update_cursor(crtc, base);
5122         } else {
5123                 I915_WRITE(CURPOS(pipe), pos);
5124                 if (IS_845G(dev) || IS_I865G(dev))
5125                         i845_update_cursor(crtc, base);
5126                 else
5127                         i9xx_update_cursor(crtc, base);
5128         }
5129 }
5130
5131 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5132                                  struct drm_file *file,
5133                                  uint32_t handle,
5134                                  uint32_t width, uint32_t height)
5135 {
5136         struct drm_device *dev = crtc->dev;
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139         struct drm_i915_gem_object *obj;
5140         uint32_t addr;
5141         int ret;
5142
5143         DRM_DEBUG_KMS("\n");
5144
5145         /* if we want to turn off the cursor ignore width and height */
5146         if (!handle) {
5147                 DRM_DEBUG_KMS("cursor off\n");
5148                 addr = 0;
5149                 obj = NULL;
5150                 DRM_LOCK(dev);
5151                 goto finish;
5152         }
5153
5154         /* Currently we only support 64x64 cursors */
5155         if (width != 64 || height != 64) {
5156                 DRM_ERROR("we currently only support 64x64 cursors\n");
5157                 return -EINVAL;
5158         }
5159
5160         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5161         if (&obj->base == NULL)
5162                 return -ENOENT;
5163
5164         if (obj->base.size < width * height * 4) {
5165                 DRM_ERROR("buffer is to small\n");
5166                 ret = -ENOMEM;
5167                 goto fail;
5168         }
5169
5170         /* we only need to pin inside GTT if cursor is non-phy */
5171         DRM_LOCK(dev);
5172         if (!dev_priv->info->cursor_needs_physical) {
5173                 if (obj->tiling_mode) {
5174                         DRM_ERROR("cursor cannot be tiled\n");
5175                         ret = -EINVAL;
5176                         goto fail_locked;
5177                 }
5178
5179                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5180                 if (ret) {
5181                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5182                         goto fail_locked;
5183                 }
5184
5185                 ret = i915_gem_object_put_fence(obj);
5186                 if (ret) {
5187                         DRM_ERROR("failed to release fence for cursor\n");
5188                         goto fail_unpin;
5189                 }
5190
5191                 addr = obj->gtt_offset;
5192         } else {
5193                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5194                 ret = i915_gem_attach_phys_object(dev, obj,
5195                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5196                                                   align);
5197                 if (ret) {
5198                         DRM_ERROR("failed to attach phys object\n");
5199                         goto fail_locked;
5200                 }
5201                 addr = obj->phys_obj->handle->busaddr;
5202         }
5203
5204         if (IS_GEN2(dev))
5205                 I915_WRITE(CURSIZE, (height << 12) | width);
5206
5207  finish:
5208         if (intel_crtc->cursor_bo) {
5209                 if (dev_priv->info->cursor_needs_physical) {
5210                         if (intel_crtc->cursor_bo != obj)
5211                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5212                 } else
5213                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
5214                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5215         }
5216
5217         DRM_UNLOCK(dev);
5218
5219         intel_crtc->cursor_addr = addr;
5220         intel_crtc->cursor_bo = obj;
5221         intel_crtc->cursor_width = width;
5222         intel_crtc->cursor_height = height;
5223
5224         intel_crtc_update_cursor(crtc, true);
5225
5226         return 0;
5227 fail_unpin:
5228         i915_gem_object_unpin_from_display_plane(obj);
5229 fail_locked:
5230         DRM_UNLOCK(dev);
5231 fail:
5232         drm_gem_object_unreference_unlocked(&obj->base);
5233         return ret;
5234 }
5235
5236 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5237 {
5238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5239
5240         intel_crtc->cursor_x = x;
5241         intel_crtc->cursor_y = y;
5242
5243         intel_crtc_update_cursor(crtc, true);
5244
5245         return 0;
5246 }
5247
5248 /** Sets the color ramps on behalf of RandR */
5249 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5250                                  u16 blue, int regno)
5251 {
5252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253
5254         intel_crtc->lut_r[regno] = red >> 8;
5255         intel_crtc->lut_g[regno] = green >> 8;
5256         intel_crtc->lut_b[regno] = blue >> 8;
5257 }
5258
5259 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5260                              u16 *blue, int regno)
5261 {
5262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5263
5264         *red = intel_crtc->lut_r[regno] << 8;
5265         *green = intel_crtc->lut_g[regno] << 8;
5266         *blue = intel_crtc->lut_b[regno] << 8;
5267 }
5268
5269 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5270                                  u16 *blue, uint32_t start, uint32_t size)
5271 {
5272         int end = (start + size > 256) ? 256 : start + size, i;
5273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5274
5275         for (i = start; i < end; i++) {
5276                 intel_crtc->lut_r[i] = red[i] >> 8;
5277                 intel_crtc->lut_g[i] = green[i] >> 8;
5278                 intel_crtc->lut_b[i] = blue[i] >> 8;
5279         }
5280
5281         intel_crtc_load_lut(crtc);
5282 }
5283
5284 /**
5285  * Get a pipe with a simple mode set on it for doing load-based monitor
5286  * detection.
5287  *
5288  * It will be up to the load-detect code to adjust the pipe as appropriate for
5289  * its requirements.  The pipe will be connected to no other encoders.
5290  *
5291  * Currently this code will only succeed if there is a pipe with no encoders
5292  * configured for it.  In the future, it could choose to temporarily disable
5293  * some outputs to free up a pipe for its use.
5294  *
5295  * \return crtc, or NULL if no pipes are available.
5296  */
5297
5298 /* VESA 640x480x72Hz mode to set on the pipe */
5299 static struct drm_display_mode load_detect_mode = {
5300         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5301                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5302 };
5303
5304 static int
5305 intel_framebuffer_create(struct drm_device *dev,
5306                          struct drm_mode_fb_cmd2 *mode_cmd,
5307                          struct drm_i915_gem_object *obj,
5308                          struct drm_framebuffer **res)
5309 {
5310         struct intel_framebuffer *intel_fb;
5311         int ret;
5312
5313         intel_fb = malloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5314         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5315         if (ret) {
5316                 drm_gem_object_unreference_unlocked(&obj->base);
5317                 free(intel_fb, DRM_MEM_KMS);
5318                 return ret;
5319         }
5320
5321         *res = &intel_fb->base;
5322         return 0;
5323 }
5324
5325 static u32
5326 intel_framebuffer_pitch_for_width(int width, int bpp)
5327 {
5328         u32 pitch = howmany(width * bpp, 8);
5329         return roundup2(pitch, 64);
5330 }
5331
5332 static u32
5333 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5334 {
5335         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5336         return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
5337 }
5338
5339 static int
5340 intel_framebuffer_create_for_mode(struct drm_device *dev,
5341                                   struct drm_display_mode *mode,
5342                                   int depth, int bpp,
5343                                   struct drm_framebuffer **res)
5344 {
5345         struct drm_i915_gem_object *obj;
5346         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
5347
5348         obj = i915_gem_alloc_object(dev,
5349                                     intel_framebuffer_size_for_mode(mode, bpp));
5350         if (obj == NULL)
5351                 return -ENOMEM;
5352
5353         mode_cmd.width = mode->hdisplay;
5354         mode_cmd.height = mode->vdisplay;
5355         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5356                                                                 bpp);
5357         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5358
5359         return intel_framebuffer_create(dev, &mode_cmd, obj, res);
5360 }
5361
5362 static int
5363 mode_fits_in_fbdev(struct drm_device *dev,
5364                    struct drm_display_mode *mode,
5365                    struct drm_framebuffer **res)
5366 {
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368         struct drm_i915_gem_object *obj;
5369         struct drm_framebuffer *fb;
5370
5371         if (dev_priv->fbdev == NULL) {
5372                 *res = NULL;
5373                 return 0;
5374         }
5375
5376         obj = dev_priv->fbdev->ifb.obj;
5377         if (obj == NULL) {
5378                 *res = NULL;
5379                 return 0;
5380         }
5381
5382         fb = &dev_priv->fbdev->ifb.base;
5383         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5384             fb->bits_per_pixel)) {
5385                 *res = NULL;
5386                 return 0;
5387         }
5388
5389         if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
5390                 *res = NULL;
5391                 return 0;
5392         }
5393
5394         *res = fb;
5395         return 0;
5396 }
5397
5398 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5399                                 struct drm_connector *connector,
5400                                 struct drm_display_mode *mode,
5401                                 struct intel_load_detect_pipe *old)
5402 {
5403         struct intel_crtc *intel_crtc;
5404         struct drm_crtc *possible_crtc;
5405         struct drm_encoder *encoder = &intel_encoder->base;
5406         struct drm_crtc *crtc = NULL;
5407         struct drm_device *dev = encoder->dev;
5408         struct drm_framebuffer *old_fb;
5409         int i = -1;
5410         int ret;
5411
5412         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5413                       connector->base.id, drm_get_connector_name(connector),
5414                       encoder->base.id, drm_get_encoder_name(encoder));
5415
5416         /*
5417          * Algorithm gets a little messy:
5418          *
5419          *   - if the connector already has an assigned crtc, use it (but make
5420          *     sure it's on first)
5421          *
5422          *   - try to find the first unused crtc that can drive this connector,
5423          *     and use that if we find one
5424          */
5425
5426         /* See if we already have a CRTC for this connector */
5427         if (encoder->crtc) {
5428                 crtc = encoder->crtc;
5429
5430                 intel_crtc = to_intel_crtc(crtc);
5431                 old->dpms_mode = intel_crtc->dpms_mode;
5432                 old->load_detect_temp = false;
5433
5434                 /* Make sure the crtc and connector are running */
5435                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5436                         struct drm_encoder_helper_funcs *encoder_funcs;
5437                         struct drm_crtc_helper_funcs *crtc_funcs;
5438
5439                         crtc_funcs = crtc->helper_private;
5440                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5441
5442                         encoder_funcs = encoder->helper_private;
5443                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5444                 }
5445
5446                 return true;
5447         }
5448
5449         /* Find an unused one (if possible) */
5450         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5451                 i++;
5452                 if (!(encoder->possible_crtcs & (1 << i)))
5453                         continue;
5454                 if (!possible_crtc->enabled) {
5455                         crtc = possible_crtc;
5456                         break;
5457                 }
5458         }
5459
5460         /*
5461          * If we didn't find an unused CRTC, don't use any.
5462          */
5463         if (!crtc) {
5464                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5465                 return false;
5466         }
5467
5468         encoder->crtc = crtc;
5469         connector->encoder = encoder;
5470
5471         intel_crtc = to_intel_crtc(crtc);
5472         old->dpms_mode = intel_crtc->dpms_mode;
5473         old->load_detect_temp = true;
5474         old->release_fb = NULL;
5475
5476         if (!mode)
5477                 mode = &load_detect_mode;
5478
5479         old_fb = crtc->fb;
5480
5481         /* We need a framebuffer large enough to accommodate all accesses
5482          * that the plane may generate whilst we perform load detection.
5483          * We can not rely on the fbcon either being present (we get called
5484          * during its initialisation to detect all boot displays, or it may
5485          * not even exist) or that it is large enough to satisfy the
5486          * requested mode.
5487          */
5488         ret = mode_fits_in_fbdev(dev, mode, &crtc->fb);
5489         if (crtc->fb == NULL) {
5490                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5491                 ret = intel_framebuffer_create_for_mode(dev, mode, 24, 32,
5492                     &crtc->fb);
5493                 old->release_fb = crtc->fb;
5494         } else
5495                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5496         if (ret) {
5497                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5498                 crtc->fb = old_fb;
5499                 return false;
5500         }
5501
5502         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5503                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5504                 if (old->release_fb)
5505                         old->release_fb->funcs->destroy(old->release_fb);
5506                 crtc->fb = old_fb;
5507                 return false;
5508         }
5509
5510         /* let the connector get through one full cycle before testing */
5511         intel_wait_for_vblank(dev, intel_crtc->pipe);
5512         return true;
5513 }
5514
5515 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5516                                     struct drm_connector *connector,
5517                                     struct intel_load_detect_pipe *old)
5518 {
5519         struct drm_encoder *encoder = &intel_encoder->base;
5520         struct drm_device *dev = encoder->dev;
5521         struct drm_crtc *crtc = encoder->crtc;
5522         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5523         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5524
5525         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5526                       connector->base.id, drm_get_connector_name(connector),
5527                       encoder->base.id, drm_get_encoder_name(encoder));
5528
5529         if (old->load_detect_temp) {
5530                 connector->encoder = NULL;
5531                 drm_helper_disable_unused_functions(dev);
5532
5533                 if (old->release_fb)
5534                         old->release_fb->funcs->destroy(old->release_fb);
5535
5536                 return;
5537         }
5538
5539         /* Switch crtc and encoder back off if necessary */
5540         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5541                 encoder_funcs->dpms(encoder, old->dpms_mode);
5542                 crtc_funcs->dpms(crtc, old->dpms_mode);
5543         }
5544 }
5545
5546 /* Returns the clock of the currently programmed mode of the given pipe. */
5547 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5548 {
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5551         int pipe = intel_crtc->pipe;
5552         u32 dpll = I915_READ(DPLL(pipe));
5553         u32 fp;
5554         intel_clock_t clock;
5555
5556         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5557                 fp = I915_READ(FP0(pipe));
5558         else
5559                 fp = I915_READ(FP1(pipe));
5560
5561         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5562         if (IS_PINEVIEW(dev)) {
5563                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5564                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5565         } else {
5566                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5567                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5568         }
5569
5570         if (!IS_GEN2(dev)) {
5571                 if (IS_PINEVIEW(dev))
5572                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5573                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5574                 else
5575                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5576                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5577
5578                 switch (dpll & DPLL_MODE_MASK) {
5579                 case DPLLB_MODE_DAC_SERIAL:
5580                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5581                                 5 : 10;
5582                         break;
5583                 case DPLLB_MODE_LVDS:
5584                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5585                                 7 : 14;
5586                         break;
5587                 default:
5588                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5589                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5590                         return 0;
5591                 }
5592
5593                 /* XXX: Handle the 100Mhz refclk */
5594                 intel_clock(dev, 96000, &clock);
5595         } else {
5596                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5597
5598                 if (is_lvds) {
5599                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5600                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5601                         clock.p2 = 14;
5602
5603                         if ((dpll & PLL_REF_INPUT_MASK) ==
5604                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5605                                 /* XXX: might not be 66MHz */
5606                                 intel_clock(dev, 66000, &clock);
5607                         } else
5608                                 intel_clock(dev, 48000, &clock);
5609                 } else {
5610                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5611                                 clock.p1 = 2;
5612                         else {
5613                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5614                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5615                         }
5616                         if (dpll & PLL_P2_DIVIDE_BY_4)
5617                                 clock.p2 = 4;
5618                         else
5619                                 clock.p2 = 2;
5620
5621                         intel_clock(dev, 48000, &clock);
5622                 }
5623         }
5624
5625         /* XXX: It would be nice to validate the clocks, but we can't reuse
5626          * i830PllIsValid() because it relies on the xf86_config connector
5627          * configuration being accurate, which it isn't necessarily.
5628          */
5629
5630         return clock.dot;
5631 }
5632
5633 /** Returns the currently programmed mode of the given pipe. */
5634 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5635                                              struct drm_crtc *crtc)
5636 {
5637         struct drm_i915_private *dev_priv = dev->dev_private;
5638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5639         int pipe = intel_crtc->pipe;
5640         struct drm_display_mode *mode;
5641         int htot = I915_READ(HTOTAL(pipe));
5642         int hsync = I915_READ(HSYNC(pipe));
5643         int vtot = I915_READ(VTOTAL(pipe));
5644         int vsync = I915_READ(VSYNC(pipe));
5645
5646         mode = malloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5647
5648         mode->clock = intel_crtc_clock_get(dev, crtc);
5649         mode->hdisplay = (htot & 0xffff) + 1;
5650         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5651         mode->hsync_start = (hsync & 0xffff) + 1;
5652         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5653         mode->vdisplay = (vtot & 0xffff) + 1;
5654         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5655         mode->vsync_start = (vsync & 0xffff) + 1;
5656         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5657
5658         drm_mode_set_name(mode);
5659
5660         return mode;
5661 }
5662
5663 #define GPU_IDLE_TIMEOUT (500 /* ms */ * 1000 / hz)
5664
5665 /* When this timer fires, we've been idle for awhile */
5666 static void intel_gpu_idle_timer(void *arg)
5667 {
5668         struct drm_device *dev = arg;
5669         drm_i915_private_t *dev_priv = dev->dev_private;
5670
5671         if (!list_empty(&dev_priv->mm.active_list)) {
5672                 /* Still processing requests, so just re-arm the timer. */
5673                 callout_schedule(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT);
5674                 return;
5675         }
5676
5677         dev_priv->busy = false;
5678         taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
5679 }
5680
5681 #define CRTC_IDLE_TIMEOUT (1000 /* ms */ * 1000 / hz)
5682
5683 static void intel_crtc_idle_timer(void *arg)
5684 {
5685         struct intel_crtc *intel_crtc = arg;
5686         struct drm_crtc *crtc = &intel_crtc->base;
5687         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5688         struct intel_framebuffer *intel_fb;
5689
5690         intel_fb = to_intel_framebuffer(crtc->fb);
5691         if (intel_fb && intel_fb->obj->active) {
5692                 /* The framebuffer is still being accessed by the GPU. */
5693                 callout_schedule(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT);
5694                 return;
5695         }
5696
5697         intel_crtc->busy = false;
5698         taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
5699 }
5700
5701 static void intel_increase_pllclock(struct drm_crtc *crtc)
5702 {
5703         struct drm_device *dev = crtc->dev;
5704         drm_i915_private_t *dev_priv = dev->dev_private;
5705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5706         int pipe = intel_crtc->pipe;
5707         int dpll_reg = DPLL(pipe);
5708         int dpll;
5709
5710         if (HAS_PCH_SPLIT(dev))
5711                 return;
5712
5713         if (!dev_priv->lvds_downclock_avail)
5714                 return;
5715
5716         dpll = I915_READ(dpll_reg);
5717         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5718                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5719
5720                 assert_panel_unlocked(dev_priv, pipe);
5721
5722                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5723                 I915_WRITE(dpll_reg, dpll);
5724                 intel_wait_for_vblank(dev, pipe);
5725
5726                 dpll = I915_READ(dpll_reg);
5727                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5728                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5729         }
5730
5731         /* Schedule downclock */
5732         callout_reset(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT,
5733             intel_crtc_idle_timer, intel_crtc);
5734 }
5735
5736 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5737 {
5738         struct drm_device *dev = crtc->dev;
5739         drm_i915_private_t *dev_priv = dev->dev_private;
5740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5741
5742         if (HAS_PCH_SPLIT(dev))
5743                 return;
5744
5745         if (!dev_priv->lvds_downclock_avail)
5746                 return;
5747
5748         /*
5749          * Since this is called by a timer, we should never get here in
5750          * the manual case.
5751          */
5752         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5753                 int pipe = intel_crtc->pipe;
5754                 int dpll_reg = DPLL(pipe);
5755                 int dpll;
5756
5757                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5758
5759                 assert_panel_unlocked(dev_priv, pipe);
5760
5761                 dpll = I915_READ(dpll_reg);
5762                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5763                 I915_WRITE(dpll_reg, dpll);
5764                 intel_wait_for_vblank(dev, pipe);
5765                 dpll = I915_READ(dpll_reg);
5766                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5767                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5768         }
5769
5770 }
5771
5772 /**
5773  * intel_idle_update - adjust clocks for idleness
5774  * @work: work struct
5775  *
5776  * Either the GPU or display (or both) went idle.  Check the busy status
5777  * here and adjust the CRTC and GPU clocks as necessary.
5778  */
5779 static void intel_idle_update(void *arg, int pending)
5780 {
5781         drm_i915_private_t *dev_priv = arg;
5782         struct drm_device *dev = dev_priv->dev;
5783         struct drm_crtc *crtc;
5784         struct intel_crtc *intel_crtc;
5785
5786         if (!i915_powersave)
5787                 return;
5788
5789         DRM_LOCK(dev);
5790
5791         i915_update_gfx_val(dev_priv);
5792
5793         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5794                 /* Skip inactive CRTCs */
5795                 if (!crtc->fb)
5796                         continue;
5797
5798                 intel_crtc = to_intel_crtc(crtc);
5799                 if (!intel_crtc->busy)
5800                         intel_decrease_pllclock(crtc);
5801         }
5802
5803         DRM_UNLOCK(dev);
5804 }
5805
5806 /**
5807  * intel_mark_busy - mark the GPU and possibly the display busy
5808  * @dev: drm device
5809  * @obj: object we're operating on
5810  *
5811  * Callers can use this function to indicate that the GPU is busy processing
5812  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5813  * buffer), we'll also mark the display as busy, so we know to increase its
5814  * clock frequency.
5815  */
5816 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5817 {
5818         drm_i915_private_t *dev_priv = dev->dev_private;
5819         struct drm_crtc *crtc = NULL;
5820         struct intel_framebuffer *intel_fb;
5821         struct intel_crtc *intel_crtc;
5822
5823         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5824                 return;
5825
5826         if (!dev_priv->busy) {
5827                 intel_sanitize_pm(dev);
5828                 dev_priv->busy = true;
5829         } else
5830                 callout_reset(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT,
5831                     intel_gpu_idle_timer, dev);
5832
5833         if (obj == NULL)
5834                 return;
5835
5836         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5837                 if (!crtc->fb)
5838                         continue;
5839
5840                 intel_crtc = to_intel_crtc(crtc);
5841                 intel_fb = to_intel_framebuffer(crtc->fb);
5842                 if (intel_fb->obj == obj) {
5843                         if (!intel_crtc->busy) {
5844                                 /* Non-busy -> busy, upclock */
5845                                 intel_increase_pllclock(crtc);
5846                                 intel_crtc->busy = true;
5847                         } else {
5848                                 /* Busy -> busy, put off timer */
5849                                 callout_reset(&intel_crtc->idle_callout,
5850                                     CRTC_IDLE_TIMEOUT, intel_crtc_idle_timer,
5851                                     intel_crtc);
5852                         }
5853                 }
5854         }
5855 }
5856
5857 static void intel_crtc_destroy(struct drm_crtc *crtc)
5858 {
5859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860         struct drm_device *dev = crtc->dev;
5861         struct drm_i915_private *dev_priv = dev->dev_private;
5862         struct intel_unpin_work *work;
5863
5864         mtx_lock(&dev->event_lock);
5865         work = intel_crtc->unpin_work;
5866         intel_crtc->unpin_work = NULL;
5867         mtx_unlock(&dev->event_lock);
5868
5869         if (work) {
5870                 taskqueue_cancel(dev_priv->tq, &work->task, NULL);
5871                 taskqueue_drain(dev_priv->tq, &work->task);
5872                 free(work, DRM_MEM_KMS);
5873         }
5874
5875         drm_crtc_cleanup(crtc);
5876
5877         free(intel_crtc, DRM_MEM_KMS);
5878 }
5879
5880 static void intel_unpin_work_fn(void *arg, int pending)
5881 {
5882         struct intel_unpin_work *work =
5883                 arg;
5884         struct drm_device *dev = work->dev;
5885
5886         DRM_LOCK(dev);
5887         intel_unpin_fb_obj(work->old_fb_obj);
5888         drm_gem_object_unreference(&work->pending_flip_obj->base);
5889         drm_gem_object_unreference(&work->old_fb_obj->base);
5890
5891         intel_update_fbc(dev);
5892         DRM_UNLOCK(dev);
5893         free(work, DRM_MEM_KMS);
5894 }
5895
5896 static void do_intel_finish_page_flip(struct drm_device *dev,
5897                                       struct drm_crtc *crtc)
5898 {
5899         drm_i915_private_t *dev_priv = dev->dev_private;
5900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901         struct intel_unpin_work *work;
5902         struct drm_i915_gem_object *obj;
5903         struct drm_pending_vblank_event *e;
5904         struct timeval tnow, tvbl;
5905
5906         /* Ignore early vblank irqs */
5907         if (intel_crtc == NULL)
5908                 return;
5909
5910         microtime(&tnow);
5911
5912         mtx_lock(&dev->event_lock);
5913         work = intel_crtc->unpin_work;
5914         if (work == NULL || !work->pending) {
5915                 mtx_unlock(&dev->event_lock);
5916                 return;
5917         }
5918
5919         intel_crtc->unpin_work = NULL;
5920
5921         if (work->event) {
5922                 e = work->event;
5923                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5924
5925                 /* Called before vblank count and timestamps have
5926                  * been updated for the vblank interval of flip
5927                  * completion? Need to increment vblank count and
5928                  * add one videorefresh duration to returned timestamp
5929                  * to account for this. We assume this happened if we
5930                  * get called over 0.9 frame durations after the last
5931                  * timestamped vblank.
5932                  *
5933                  * This calculation can not be used with vrefresh rates
5934                  * below 5Hz (10Hz to be on the safe side) without
5935                  * promoting to 64 integers.
5936                  */
5937                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5938                     9 * crtc->framedur_ns) {
5939                         e->event.sequence++;
5940                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5941                                              crtc->framedur_ns);
5942                 }
5943
5944                 e->event.tv_sec = tvbl.tv_sec;
5945                 e->event.tv_usec = tvbl.tv_usec;
5946
5947                 list_add_tail(&e->base.link,
5948                               &e->base.file_priv->event_list);
5949                 drm_event_wakeup(&e->base);
5950         }
5951
5952         drm_vblank_put(dev, intel_crtc->pipe);
5953
5954         obj = work->old_fb_obj;
5955
5956         atomic_clear_int(&obj->pending_flip, 1 << intel_crtc->plane);
5957         if (atomic_load_acq_int(&obj->pending_flip) == 0)
5958                 wakeup(&obj->pending_flip);
5959         mtx_unlock(&dev->event_lock);
5960
5961         taskqueue_enqueue(dev_priv->tq, &work->task);
5962
5963         CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
5964             work->pending_flip_obj);
5965 }
5966
5967 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5968 {
5969         drm_i915_private_t *dev_priv = dev->dev_private;
5970         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5971
5972         do_intel_finish_page_flip(dev, crtc);
5973 }
5974
5975 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5976 {
5977         drm_i915_private_t *dev_priv = dev->dev_private;
5978         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5979
5980         do_intel_finish_page_flip(dev, crtc);
5981 }
5982
5983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5984 {
5985         drm_i915_private_t *dev_priv = dev->dev_private;
5986         struct intel_crtc *intel_crtc =
5987                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5988
5989         mtx_lock(&dev->event_lock);
5990         if (intel_crtc->unpin_work) {
5991                 if ((++intel_crtc->unpin_work->pending) > 1)
5992                         DRM_ERROR("Prepared flip multiple times\n");
5993         } else {
5994                 DRM_DEBUG("preparing flip with no unpin work?\n");
5995         }
5996         mtx_unlock(&dev->event_lock);
5997 }
5998
5999 static int intel_gen2_queue_flip(struct drm_device *dev,
6000                                  struct drm_crtc *crtc,
6001                                  struct drm_framebuffer *fb,
6002                                  struct drm_i915_gem_object *obj)
6003 {
6004         struct drm_i915_private *dev_priv = dev->dev_private;
6005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6006         unsigned long offset;
6007         u32 flip_mask;
6008         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6009         int ret;
6010
6011         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6012         if (ret)
6013                 goto err;
6014
6015         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6016         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6017
6018         ret = intel_ring_begin(ring, 6);
6019         if (ret)
6020                 goto err_unpin;
6021
6022         /* Can't queue multiple flips, so wait for the previous
6023          * one to finish before executing the next.
6024          */
6025         if (intel_crtc->plane)
6026                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6027         else
6028                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6029         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6030         intel_ring_emit(ring, MI_NOOP);
6031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6033         intel_ring_emit(ring, fb->pitches[0]);
6034         intel_ring_emit(ring, obj->gtt_offset + offset);
6035         intel_ring_emit(ring, 0); /* aux display base address, unused */
6036         intel_ring_advance(ring);
6037         return 0;
6038
6039 err_unpin:
6040         intel_unpin_fb_obj(obj);
6041 err:
6042         return ret;
6043 }
6044
6045 static int intel_gen3_queue_flip(struct drm_device *dev,
6046                                  struct drm_crtc *crtc,
6047                                  struct drm_framebuffer *fb,
6048                                  struct drm_i915_gem_object *obj)
6049 {
6050         struct drm_i915_private *dev_priv = dev->dev_private;
6051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052         unsigned long offset;
6053         u32 flip_mask;
6054         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6055         int ret;
6056
6057         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6058         if (ret)
6059                 goto err;
6060
6061         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6062         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6063
6064         ret = intel_ring_begin(ring, 6);
6065         if (ret)
6066                 goto err_unpin;
6067
6068         if (intel_crtc->plane)
6069                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6070         else
6071                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6072         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6073         intel_ring_emit(ring, MI_NOOP);
6074         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6075                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6076         intel_ring_emit(ring, fb->pitches[0]);
6077         intel_ring_emit(ring, obj->gtt_offset + offset);
6078         intel_ring_emit(ring, MI_NOOP);
6079
6080         intel_ring_advance(ring);
6081         return 0;
6082
6083 err_unpin:
6084         intel_unpin_fb_obj(obj);
6085 err:
6086         return ret;
6087 }
6088
6089 static int intel_gen4_queue_flip(struct drm_device *dev,
6090                                  struct drm_crtc *crtc,
6091                                  struct drm_framebuffer *fb,
6092                                  struct drm_i915_gem_object *obj)
6093 {
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096         uint32_t pf, pipesrc;
6097         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6098         int ret;
6099
6100         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6101         if (ret)
6102                 goto err;
6103
6104         ret = intel_ring_begin(ring, 4);
6105         if (ret)
6106                 goto err_unpin;
6107
6108         /* i965+ uses the linear or tiled offsets from the
6109          * Display Registers (which do not change across a page-flip)
6110          * so we need only reprogram the base address.
6111          */
6112         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6113                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6114         intel_ring_emit(ring, fb->pitches[0]);
6115         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6116
6117         /* XXX Enabling the panel-fitter across page-flip is so far
6118          * untested on non-native modes, so ignore it for now.
6119          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6120          */
6121         pf = 0;
6122         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6123         intel_ring_emit(ring, pf | pipesrc);
6124         intel_ring_advance(ring);
6125         return 0;
6126
6127 err_unpin:
6128         intel_unpin_fb_obj(obj);
6129 err:
6130         return ret;
6131 }
6132
6133 static int intel_gen6_queue_flip(struct drm_device *dev,
6134                                  struct drm_crtc *crtc,
6135                                  struct drm_framebuffer *fb,
6136                                  struct drm_i915_gem_object *obj)
6137 {
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6141         uint32_t pf, pipesrc;
6142         int ret;
6143
6144         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6145         if (ret)
6146                 goto err;
6147
6148         ret = intel_ring_begin(ring, 4);
6149         if (ret)
6150                 goto err_unpin;
6151
6152         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6153                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6155         intel_ring_emit(ring, obj->gtt_offset);
6156
6157         /* Contrary to the suggestions in the documentation,
6158          * "Enable Panel Fitter" does not seem to be required when page
6159          * flipping with a non-native mode, and worse causes a normal
6160          * modeset to fail.
6161          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6162          */
6163         pf = 0;
6164         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6165         intel_ring_emit(ring, pf | pipesrc);
6166         intel_ring_advance(ring);
6167         return 0;
6168
6169 err_unpin:
6170         intel_unpin_fb_obj(obj);
6171 err:
6172         return ret;
6173 }
6174
6175 /*
6176  * On gen7 we currently use the blit ring because (in early silicon at least)
6177  * the render ring doesn't give us interrpts for page flip completion, which
6178  * means clients will hang after the first flip is queued.  Fortunately the
6179  * blit ring generates interrupts properly, so use it instead.
6180  */
6181 static int intel_gen7_queue_flip(struct drm_device *dev,
6182                                  struct drm_crtc *crtc,
6183                                  struct drm_framebuffer *fb,
6184                                  struct drm_i915_gem_object *obj)
6185 {
6186         struct drm_i915_private *dev_priv = dev->dev_private;
6187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6188         struct intel_ring_buffer *ring = &dev_priv->rings[BCS];
6189         int ret;
6190
6191         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6192         if (ret)
6193                 goto err;
6194
6195         ret = intel_ring_begin(ring, 4);
6196         if (ret)
6197                 goto err_unpin;
6198
6199         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6200         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6201         intel_ring_emit(ring, (obj->gtt_offset));
6202         intel_ring_emit(ring, (MI_NOOP));
6203         intel_ring_advance(ring);
6204         return 0;
6205
6206 err_unpin:
6207         intel_unpin_fb_obj(obj);
6208 err:
6209         return ret;
6210 }
6211
6212 static int intel_default_queue_flip(struct drm_device *dev,
6213                                     struct drm_crtc *crtc,
6214                                     struct drm_framebuffer *fb,
6215                                     struct drm_i915_gem_object *obj)
6216 {
6217         return -ENODEV;
6218 }
6219
6220 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6221                                 struct drm_framebuffer *fb,
6222                                 struct drm_pending_vblank_event *event)
6223 {
6224         struct drm_device *dev = crtc->dev;
6225         struct drm_i915_private *dev_priv = dev->dev_private;
6226         struct intel_framebuffer *intel_fb;
6227         struct drm_i915_gem_object *obj;
6228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6229         struct intel_unpin_work *work;
6230         int ret;
6231
6232         work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
6233
6234         work->event = event;
6235         work->dev = crtc->dev;
6236         intel_fb = to_intel_framebuffer(crtc->fb);
6237         work->old_fb_obj = intel_fb->obj;
6238         TASK_INIT(&work->task, 0, intel_unpin_work_fn, work);
6239
6240         ret = drm_vblank_get(dev, intel_crtc->pipe);
6241         if (ret)
6242                 goto free_work;
6243
6244         /* We borrow the event spin lock for protecting unpin_work */
6245         mtx_lock(&dev->event_lock);
6246         if (intel_crtc->unpin_work) {
6247                 mtx_unlock(&dev->event_lock);
6248                 free(work, DRM_MEM_KMS);
6249                 drm_vblank_put(dev, intel_crtc->pipe);
6250
6251                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6252                 return -EBUSY;
6253         }
6254         intel_crtc->unpin_work = work;
6255         mtx_unlock(&dev->event_lock);
6256
6257         intel_fb = to_intel_framebuffer(fb);
6258         obj = intel_fb->obj;
6259
6260         DRM_LOCK(dev);
6261
6262         /* Reference the objects for the scheduled work. */
6263         drm_gem_object_reference(&work->old_fb_obj->base);
6264         drm_gem_object_reference(&obj->base);
6265
6266         crtc->fb = fb;
6267
6268         work->pending_flip_obj = obj;
6269
6270         work->enable_stall_check = true;
6271
6272         /* Block clients from rendering to the new back buffer until
6273          * the flip occurs and the object is no longer visible.
6274          */
6275         atomic_set_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6276
6277         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6278         if (ret)
6279                 goto cleanup_pending;
6280         intel_disable_fbc(dev);
6281         intel_mark_busy(dev, obj);
6282         DRM_UNLOCK(dev);
6283
6284         CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
6285
6286         return 0;
6287
6288 cleanup_pending:
6289         atomic_clear_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6290         drm_gem_object_unreference(&work->old_fb_obj->base);
6291         drm_gem_object_unreference(&obj->base);
6292         DRM_UNLOCK(dev);
6293
6294         mtx_lock(&dev->event_lock);
6295         intel_crtc->unpin_work = NULL;
6296         mtx_unlock(&dev->event_lock);
6297
6298         drm_vblank_put(dev, intel_crtc->pipe);
6299 free_work:
6300         free(work, DRM_MEM_KMS);
6301
6302         return ret;
6303 }
6304
6305 static void intel_sanitize_modesetting(struct drm_device *dev,
6306                                        int pipe, int plane)
6307 {
6308         struct drm_i915_private *dev_priv = dev->dev_private;
6309         u32 reg, val;
6310         int i;
6311
6312         /* Clear any frame start delays used for debugging left by the BIOS */
6313         for_each_pipe(i) {
6314                 reg = PIPECONF(i);
6315                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6316         }
6317
6318         if (HAS_PCH_SPLIT(dev))
6319                 return;
6320
6321         /* Who knows what state these registers were left in by the BIOS or
6322          * grub?
6323          *
6324          * If we leave the registers in a conflicting state (e.g. with the
6325          * display plane reading from the other pipe than the one we intend
6326          * to use) then when we attempt to teardown the active mode, we will
6327          * not disable the pipes and planes in the correct order -- leaving
6328          * a plane reading from a disabled pipe and possibly leading to
6329          * undefined behaviour.
6330          */
6331
6332         reg = DSPCNTR(plane);
6333         val = I915_READ(reg);
6334
6335         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6336                 return;
6337         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6338                 return;
6339
6340         /* This display plane is active and attached to the other CPU pipe. */
6341         pipe = !pipe;
6342
6343         /* Disable the plane and wait for it to stop reading from the pipe. */
6344         intel_disable_plane(dev_priv, plane, pipe);
6345         intel_disable_pipe(dev_priv, pipe);
6346 }
6347
6348 static void intel_crtc_reset(struct drm_crtc *crtc)
6349 {
6350         struct drm_device *dev = crtc->dev;
6351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352
6353         /* Reset flags back to the 'unknown' status so that they
6354          * will be correctly set on the initial modeset.
6355          */
6356         intel_crtc->dpms_mode = -1;
6357
6358         /* We need to fix up any BIOS configuration that conflicts with
6359          * our expectations.
6360          */
6361         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6362 }
6363
6364 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6365         .dpms = intel_crtc_dpms,
6366         .mode_fixup = intel_crtc_mode_fixup,
6367         .mode_set = intel_crtc_mode_set,
6368         .mode_set_base = intel_pipe_set_base,
6369         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6370         .load_lut = intel_crtc_load_lut,
6371         .disable = intel_crtc_disable,
6372 };
6373
6374 static const struct drm_crtc_funcs intel_crtc_funcs = {
6375         .reset = intel_crtc_reset,
6376         .cursor_set = intel_crtc_cursor_set,
6377         .cursor_move = intel_crtc_cursor_move,
6378         .gamma_set = intel_crtc_gamma_set,
6379         .set_config = drm_crtc_helper_set_config,
6380         .destroy = intel_crtc_destroy,
6381         .page_flip = intel_crtc_page_flip,
6382 };
6383
6384 static void intel_pch_pll_init(struct drm_device *dev)
6385 {
6386         drm_i915_private_t *dev_priv = dev->dev_private;
6387         int i;
6388
6389         if (dev_priv->num_pch_pll == 0) {
6390                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6391                 return;
6392         }
6393
6394         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6395                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6396                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6397                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6398         }
6399 }
6400
6401 static void intel_crtc_init(struct drm_device *dev, int pipe)
6402 {
6403         drm_i915_private_t *dev_priv = dev->dev_private;
6404         struct intel_crtc *intel_crtc;
6405         int i;
6406
6407         intel_crtc = malloc(sizeof(struct intel_crtc) +
6408             (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
6409             DRM_MEM_KMS, M_WAITOK | M_ZERO);
6410
6411         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6412
6413         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6414         for (i = 0; i < 256; i++) {
6415                 intel_crtc->lut_r[i] = i;
6416                 intel_crtc->lut_g[i] = i;
6417                 intel_crtc->lut_b[i] = i;
6418         }
6419
6420         /* Swap pipes & planes for FBC on pre-965 */
6421         intel_crtc->pipe = pipe;
6422         intel_crtc->plane = pipe;
6423         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6424                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6425                 intel_crtc->plane = !pipe;
6426         }
6427
6428         KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
6429             dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
6430             ("plane_to_crtc is already initialized"));
6431         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6432         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6433
6434         intel_crtc_reset(&intel_crtc->base);
6435         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6436         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6437
6438         if (HAS_PCH_SPLIT(dev)) {
6439                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6440                 intel_helper_funcs.commit = ironlake_crtc_commit;
6441         } else {
6442                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6443                 intel_helper_funcs.commit = i9xx_crtc_commit;
6444         }
6445
6446         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6447
6448         intel_crtc->busy = false;
6449
6450         callout_init(&intel_crtc->idle_callout, 1);
6451 }
6452
6453 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6454                                 struct drm_file *file)
6455 {
6456         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6457         struct drm_mode_object *drmmode_obj;
6458         struct intel_crtc *crtc;
6459
6460         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6461                 return -ENODEV;
6462
6463         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6464                         DRM_MODE_OBJECT_CRTC);
6465
6466         if (!drmmode_obj) {
6467                 DRM_ERROR("no such CRTC id\n");
6468                 return -EINVAL;
6469         }
6470
6471         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6472         pipe_from_crtc_id->pipe = crtc->pipe;
6473
6474         return 0;
6475 }
6476
6477 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6478 {
6479         struct intel_encoder *encoder;
6480         int index_mask = 0;
6481         int entry = 0;
6482
6483         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6484                 if (type_mask & encoder->clone_mask)
6485                         index_mask |= (1 << entry);
6486                 entry++;
6487         }
6488
6489         return index_mask;
6490 }
6491
6492 static bool has_edp_a(struct drm_device *dev)
6493 {
6494         struct drm_i915_private *dev_priv = dev->dev_private;
6495
6496         if (!IS_MOBILE(dev))
6497                 return false;
6498
6499         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6500                 return false;
6501
6502         if (IS_GEN5(dev) &&
6503             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6504                 return false;
6505
6506         return true;
6507 }
6508
6509 static void intel_setup_outputs(struct drm_device *dev)
6510 {
6511         struct drm_i915_private *dev_priv = dev->dev_private;
6512         struct intel_encoder *encoder;
6513         bool dpd_is_edp = false;
6514         bool has_lvds;
6515
6516         has_lvds = intel_lvds_init(dev);
6517         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6518                 /* disable the panel fitter on everything but LVDS */
6519                 I915_WRITE(PFIT_CONTROL, 0);
6520         }
6521
6522         if (HAS_PCH_SPLIT(dev)) {
6523                 dpd_is_edp = intel_dpd_is_edp(dev);
6524
6525                 if (has_edp_a(dev))
6526                         intel_dp_init(dev, DP_A);
6527
6528                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6529                         intel_dp_init(dev, PCH_DP_D);
6530         }
6531
6532         intel_crt_init(dev);
6533
6534         if (IS_HASWELL(dev)) {
6535                 int found;
6536
6537                 /* Haswell uses DDI functions to detect digital outputs */
6538                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6539                 /* DDI A only supports eDP */
6540                 if (found)
6541                         intel_ddi_init(dev, PORT_A);
6542
6543                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6544                  * register */
6545                 found = I915_READ(SFUSE_STRAP);
6546
6547                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6548                         intel_ddi_init(dev, PORT_B);
6549                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6550                         intel_ddi_init(dev, PORT_C);
6551                 if (found & SFUSE_STRAP_DDID_DETECTED)
6552                         intel_ddi_init(dev, PORT_D);
6553         } else if (HAS_PCH_SPLIT(dev)) {
6554                 int found;
6555
6556                 DRM_DEBUG_KMS(
6557 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
6558                     (I915_READ(HDMIB) & PORT_DETECTED) != 0,
6559                     (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
6560                     (I915_READ(HDMIC) & PORT_DETECTED) != 0,
6561                     (I915_READ(HDMID) & PORT_DETECTED) != 0,
6562                     (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
6563                     (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
6564                     (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
6565
6566                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6567                         /* PCH SDVOB multiplex with HDMIB */
6568                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6569                         if (!found)
6570                                 intel_hdmi_init(dev, HDMIB);
6571                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6572                                 intel_dp_init(dev, PCH_DP_B);
6573                 }
6574
6575                 if (I915_READ(HDMIC) & PORT_DETECTED)
6576                         intel_hdmi_init(dev, HDMIC);
6577
6578                 if (I915_READ(HDMID) & PORT_DETECTED)
6579                         intel_hdmi_init(dev, HDMID);
6580
6581                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6582                         intel_dp_init(dev, PCH_DP_C);
6583
6584                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6585                         intel_dp_init(dev, PCH_DP_D);
6586
6587         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6588                 bool found = false;
6589
6590                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6591                         DRM_DEBUG_KMS("probing SDVOB\n");
6592                         found = intel_sdvo_init(dev, SDVOB, true);
6593                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6594                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6595                                 intel_hdmi_init(dev, SDVOB);
6596                         }
6597
6598                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6599                                 DRM_DEBUG_KMS("probing DP_B\n");
6600                                 intel_dp_init(dev, DP_B);
6601                         }
6602                 }
6603
6604                 /* Before G4X SDVOC doesn't have its own detect register */
6605
6606                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6607                         DRM_DEBUG_KMS("probing SDVOC\n");
6608                         found = intel_sdvo_init(dev, SDVOC, false);
6609                 }
6610
6611                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6612
6613                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6614                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6615                                 intel_hdmi_init(dev, SDVOC);
6616                         }
6617                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6618                                 DRM_DEBUG_KMS("probing DP_C\n");
6619                                 intel_dp_init(dev, DP_C);
6620                         }
6621                 }
6622
6623                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6624                     (I915_READ(DP_D) & DP_DETECTED)) {
6625                         DRM_DEBUG_KMS("probing DP_D\n");
6626                         intel_dp_init(dev, DP_D);
6627                 }
6628         } else if (IS_GEN2(dev)) {
6629 #if 1
6630                 KIB_NOTYET();
6631 #else
6632                 intel_dvo_init(dev);
6633 #endif
6634         }
6635
6636         if (SUPPORTS_TV(dev))
6637                 intel_tv_init(dev);
6638
6639         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6640                 encoder->base.possible_crtcs = encoder->crtc_mask;
6641                 encoder->base.possible_clones =
6642                         intel_encoder_clones(dev, encoder->clone_mask);
6643         }
6644
6645         /* disable all the possible outputs/crtcs before entering KMS mode */
6646         drm_helper_disable_unused_functions(dev);
6647
6648         if (HAS_PCH_SPLIT(dev))
6649                 ironlake_init_pch_refclk(dev);
6650 }
6651
6652 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6653 {
6654         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6655
6656         drm_framebuffer_cleanup(fb);
6657         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6658
6659         free(intel_fb, DRM_MEM_KMS);
6660 }
6661
6662 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6663                                                 struct drm_file *file,
6664                                                 unsigned int *handle)
6665 {
6666         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6667         struct drm_i915_gem_object *obj = intel_fb->obj;
6668
6669         return drm_gem_handle_create(file, &obj->base, handle);
6670 }
6671
6672 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6673         .destroy = intel_user_framebuffer_destroy,
6674         .create_handle = intel_user_framebuffer_create_handle,
6675 };
6676
6677 int intel_framebuffer_init(struct drm_device *dev,
6678                            struct intel_framebuffer *intel_fb,
6679                            struct drm_mode_fb_cmd2 *mode_cmd,
6680                            struct drm_i915_gem_object *obj)
6681 {
6682         int ret;
6683
6684         if (obj->tiling_mode == I915_TILING_Y)
6685                 return -EINVAL;
6686
6687         if (mode_cmd->pitches[0] & 63)
6688                 return -EINVAL;
6689
6690         switch (mode_cmd->pixel_format) {
6691         case DRM_FORMAT_RGB332:
6692         case DRM_FORMAT_RGB565:
6693         case DRM_FORMAT_XRGB8888:
6694         case DRM_FORMAT_XBGR8888:
6695         case DRM_FORMAT_ARGB8888:
6696         case DRM_FORMAT_XRGB2101010:
6697         case DRM_FORMAT_ARGB2101010:
6698                 /* RGB formats are common across chipsets */
6699                 break;
6700         case DRM_FORMAT_YUYV:
6701         case DRM_FORMAT_UYVY:
6702         case DRM_FORMAT_YVYU:
6703         case DRM_FORMAT_VYUY:
6704                 break;
6705         default:
6706                 DRM_DEBUG("unsupported pixel format %u\n", mode_cmd->pixel_format);
6707                 return -EINVAL;
6708         }
6709
6710         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6711         if (ret) {
6712                 DRM_ERROR("framebuffer init failed %d\n", ret);
6713                 return ret;
6714         }
6715
6716         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6717         intel_fb->obj = obj;
6718         return 0;
6719 }
6720
6721 static int
6722 intel_user_framebuffer_create(struct drm_device *dev,
6723                               struct drm_file *filp,
6724                               struct drm_mode_fb_cmd2 *mode_cmd,
6725                               struct drm_framebuffer **res)
6726 {
6727         struct drm_i915_gem_object *obj;
6728
6729         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6730                                                 mode_cmd->handles[0]));
6731         if (&obj->base == NULL)
6732                 return -ENOENT;
6733
6734         return intel_framebuffer_create(dev, mode_cmd, obj, res);
6735 }
6736
6737 static const struct drm_mode_config_funcs intel_mode_funcs = {
6738         .fb_create = intel_user_framebuffer_create,
6739         .output_poll_changed = intel_fb_output_poll_changed,
6740 };
6741
6742 /* Set up chip specific display functions */
6743 static void intel_init_display(struct drm_device *dev)
6744 {
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746
6747         /* We always want a DPMS function */
6748         if (HAS_PCH_SPLIT(dev)) {
6749                 dev_priv->display.dpms = ironlake_crtc_dpms;
6750                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6751                 dev_priv->display.off = ironlake_crtc_off;
6752                 dev_priv->display.update_plane = ironlake_update_plane;
6753         } else {
6754                 dev_priv->display.dpms = i9xx_crtc_dpms;
6755                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6756                 dev_priv->display.off = i9xx_crtc_off;
6757                 dev_priv->display.update_plane = i9xx_update_plane;
6758         }
6759
6760         /* Returns the core display clock speed */
6761         if (IS_VALLEYVIEW(dev))
6762                 dev_priv->display.get_display_clock_speed =
6763                         valleyview_get_display_clock_speed;
6764         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6765                 dev_priv->display.get_display_clock_speed =
6766                         i945_get_display_clock_speed;
6767         else if (IS_I915G(dev))
6768                 dev_priv->display.get_display_clock_speed =
6769                         i915_get_display_clock_speed;
6770         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6771                 dev_priv->display.get_display_clock_speed =
6772                         i9xx_misc_get_display_clock_speed;
6773         else if (IS_I915GM(dev))
6774                 dev_priv->display.get_display_clock_speed =
6775                         i915gm_get_display_clock_speed;
6776         else if (IS_I865G(dev))
6777                 dev_priv->display.get_display_clock_speed =
6778                         i865_get_display_clock_speed;
6779         else if (IS_I85X(dev))
6780                 dev_priv->display.get_display_clock_speed =
6781                         i855_get_display_clock_speed;
6782         else /* 852, 830 */
6783                 dev_priv->display.get_display_clock_speed =
6784                         i830_get_display_clock_speed;
6785
6786         if (HAS_PCH_SPLIT(dev)) {
6787                 if (IS_GEN5(dev)) {
6788                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6789                         dev_priv->display.write_eld = ironlake_write_eld;
6790                 } else if (IS_GEN6(dev)) {
6791                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6792                         dev_priv->display.write_eld = ironlake_write_eld;
6793                 } else if (IS_IVYBRIDGE(dev)) {
6794                         /* FIXME: detect B0+ stepping and use auto training */
6795                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6796                         dev_priv->display.write_eld = ironlake_write_eld;
6797                 } else if (IS_HASWELL(dev)) {
6798                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6799                         dev_priv->display.write_eld = ironlake_write_eld;
6800                 } else
6801                         dev_priv->display.update_wm = NULL;
6802         } else if (IS_VALLEYVIEW(dev)) {
6803                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6804                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6805         } else if (IS_G4X(dev)) {
6806                 dev_priv->display.write_eld = g4x_write_eld;
6807         }
6808
6809         /* Default just returns -ENODEV to indicate unsupported */
6810         dev_priv->display.queue_flip = intel_default_queue_flip;
6811
6812         switch (INTEL_INFO(dev)->gen) {
6813         case 2:
6814                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6815                 break;
6816
6817         case 3:
6818                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6819                 break;
6820
6821         case 4:
6822         case 5:
6823                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6824                 break;
6825
6826         case 6:
6827                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6828                 break;
6829         case 7:
6830                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6831                 break;
6832         }
6833 }
6834
6835 /*
6836  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6837  * resume, or other times.  This quirk makes sure that's the case for
6838  * affected systems.
6839  */
6840 static void quirk_pipea_force(struct drm_device *dev)
6841 {
6842         struct drm_i915_private *dev_priv = dev->dev_private;
6843
6844         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6845         DRM_INFO("applying pipe a force quirk\n");
6846 }
6847
6848 /*
6849  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6850  */
6851 static void quirk_ssc_force_disable(struct drm_device *dev)
6852 {
6853         struct drm_i915_private *dev_priv = dev->dev_private;
6854         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6855         DRM_INFO("applying lvds SSC disable quirk\n");
6856 }
6857
6858 /*
6859  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6860  * brightness value
6861  */
6862 static void quirk_invert_brightness(struct drm_device *dev)
6863 {
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6866         DRM_INFO("applying inverted panel brightness quirk\n");
6867 }
6868
6869 struct intel_quirk {
6870         int device;
6871         int subsystem_vendor;
6872         int subsystem_device;
6873         void (*hook)(struct drm_device *dev);
6874 };
6875
6876 #define PCI_ANY_ID      (~0u)
6877
6878 static struct intel_quirk intel_quirks[] = {
6879         /* HP Mini needs pipe A force quirk (LP: #322104) */
6880         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6881
6882         /* Thinkpad R31 needs pipe A force quirk */
6883         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6884         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6885         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6886
6887         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6888         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6889         /* ThinkPad X40 needs pipe A force quirk */
6890
6891         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6892         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6893
6894         /* 855 & before need to leave pipe A & dpll A up */
6895         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6896         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6897
6898         /* Lenovo U160 cannot use SSC on LVDS */
6899         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6900
6901         /* Sony Vaio Y cannot use SSC on LVDS */
6902         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6903
6904         /* Acer Aspire 5734Z must invert backlight brightness */
6905         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6906 };
6907
6908 static void intel_init_quirks(struct drm_device *dev)
6909 {
6910         struct intel_quirk *q;
6911         device_t d;
6912         int i;
6913
6914         d = dev->dev;
6915         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6916                 q = &intel_quirks[i];
6917                 if (pci_get_device(d) == q->device &&
6918                     (pci_get_subvendor(d) == q->subsystem_vendor ||
6919                      q->subsystem_vendor == PCI_ANY_ID) &&
6920                     (pci_get_subdevice(d) == q->subsystem_device ||
6921                      q->subsystem_device == PCI_ANY_ID))
6922                         q->hook(dev);
6923         }
6924 }
6925
6926 /* Disable the VGA plane that we never use */
6927 static void i915_disable_vga(struct drm_device *dev)
6928 {
6929         struct drm_i915_private *dev_priv = dev->dev_private;
6930         u8 sr1;
6931         u32 vga_reg;
6932
6933         if (HAS_PCH_SPLIT(dev))
6934                 vga_reg = CPU_VGACNTRL;
6935         else
6936                 vga_reg = VGACNTRL;
6937
6938 #if 0
6939         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6940 #endif
6941         outb(VGA_SR_INDEX, SR01);
6942         sr1 = inb(VGA_SR_DATA);
6943         outb(VGA_SR_DATA, sr1 | 1<<5);
6944 #if 0
6945         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6946 #endif
6947         DELAY(300);
6948
6949         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6950         POSTING_READ(vga_reg);
6951 }
6952
6953 static void ivb_pch_pwm_override(struct drm_device *dev)
6954 {
6955         struct drm_i915_private *dev_priv = dev->dev_private;
6956
6957         /*
6958          * IVB has CPU eDP backlight regs too, set things up to let the
6959          * PCH regs control the backlight
6960          */
6961         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6962         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6963         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE);
6964 }
6965
6966 void intel_modeset_init_hw(struct drm_device *dev)
6967 {
6968         struct drm_i915_private *dev_priv = dev->dev_private;
6969
6970         intel_init_clock_gating(dev);
6971
6972         if (IS_IRONLAKE_M(dev)) {
6973                 ironlake_enable_drps(dev);
6974                 ironlake_enable_rc6(dev);
6975                 intel_init_emon(dev);
6976         }
6977
6978         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6979                 gen6_enable_rps(dev_priv);
6980                 gen6_update_ring_freq(dev_priv);
6981         }
6982
6983         if (IS_IVYBRIDGE(dev))
6984                 ivb_pch_pwm_override(dev);
6985 }
6986
6987 void intel_modeset_init(struct drm_device *dev)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990         int i, ret;
6991
6992         drm_mode_config_init(dev);
6993
6994         dev->mode_config.min_width = 0;
6995         dev->mode_config.min_height = 0;
6996
6997         dev->mode_config.preferred_depth = 24;
6998         dev->mode_config.prefer_shadow = 1;
6999
7000         dev->mode_config.funcs = &intel_mode_funcs;
7001
7002         intel_init_quirks(dev);
7003
7004         intel_init_pm(dev);
7005
7006         intel_prepare_ddi(dev);
7007
7008         intel_init_display(dev);
7009
7010         if (IS_GEN2(dev)) {
7011                 dev->mode_config.max_width = 2048;
7012                 dev->mode_config.max_height = 2048;
7013         } else if (IS_GEN3(dev)) {
7014                 dev->mode_config.max_width = 4096;
7015                 dev->mode_config.max_height = 4096;
7016         } else {
7017                 dev->mode_config.max_width = 8192;
7018                 dev->mode_config.max_height = 8192;
7019         }
7020         dev->mode_config.fb_base = dev->agp->base;
7021
7022         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7023                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7024
7025         for (i = 0; i < dev_priv->num_pipe; i++) {
7026                 intel_crtc_init(dev, i);
7027                 ret = intel_plane_init(dev, i);
7028                 if (ret)
7029                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7030         }
7031
7032         intel_pch_pll_init(dev);
7033
7034         /* Just disable it once at startup */
7035         i915_disable_vga(dev);
7036         intel_setup_outputs(dev);
7037
7038         TASK_INIT(&dev_priv->idle_task, 0, intel_idle_update, dev_priv);
7039         callout_init(&dev_priv->idle_callout, 1);
7040 }
7041
7042 void intel_modeset_gem_init(struct drm_device *dev)
7043 {
7044         intel_modeset_init_hw(dev);
7045
7046         intel_setup_overlay(dev);
7047 }
7048
7049 void intel_modeset_cleanup(struct drm_device *dev)
7050 {
7051         struct drm_i915_private *dev_priv = dev->dev_private;
7052         struct drm_crtc *crtc;
7053         struct intel_crtc *intel_crtc;
7054
7055         drm_kms_helper_poll_fini(dev);
7056         DRM_LOCK(dev);
7057
7058 #if 0
7059         intel_unregister_dsm_handler();
7060 #endif
7061
7062
7063         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7064                 /* Skip inactive CRTCs */
7065                 if (!crtc->fb)
7066                         continue;
7067
7068                 intel_crtc = to_intel_crtc(crtc);
7069                 intel_increase_pllclock(crtc);
7070         }
7071
7072         intel_disable_fbc(dev);
7073
7074         if (IS_IRONLAKE_M(dev))
7075                 ironlake_disable_drps(dev);
7076         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7077                 gen6_disable_rps(dev);
7078
7079         if (IS_IRONLAKE_M(dev))
7080                 ironlake_disable_rc6(dev);
7081
7082         if (IS_VALLEYVIEW(dev))
7083                 vlv_init_dpio(dev);
7084
7085         DRM_UNLOCK(dev);
7086
7087         /* Disable the irq before mode object teardown, for the irq might
7088          * enqueue unpin/hotplug work. */
7089         drm_irq_uninstall(dev);
7090         if (taskqueue_cancel(dev_priv->tq, &dev_priv->hotplug_task, NULL))
7091                 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
7092         if (taskqueue_cancel(dev_priv->tq, &dev_priv->rps_task, NULL))
7093                 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
7094
7095         /* Shut off idle work before the crtcs get freed. */
7096         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7097                 intel_crtc = to_intel_crtc(crtc);
7098                 callout_drain(&intel_crtc->idle_callout);
7099         }
7100         callout_drain(&dev_priv->idle_callout);
7101         if (taskqueue_cancel(dev_priv->tq, &dev_priv->idle_task, NULL))
7102                 taskqueue_drain(dev_priv->tq, &dev_priv->idle_task);
7103
7104         drm_mode_config_cleanup(dev);
7105 }
7106
7107 /*
7108  * Return which encoder is currently attached for connector.
7109  */
7110 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7111 {
7112         return &intel_attached_encoder(connector)->base;
7113 }
7114
7115 void intel_connector_attach_encoder(struct intel_connector *connector,
7116                                     struct intel_encoder *encoder)
7117 {
7118         connector->encoder = encoder;
7119         drm_mode_connector_attach_encoder(&connector->base,
7120                                           &encoder->base);
7121 }
7122
7123 /*
7124  * set vga decode state - true == enable VGA decode
7125  */
7126 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7127 {
7128         device_t bridge_dev;
7129         u16 gmch_ctrl;
7130
7131         bridge_dev = intel_gtt_get_bridge_device();
7132         gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
7133         if (state)
7134                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7135         else
7136                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7137         pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
7138         return 0;
7139 }
7140
7141 struct intel_display_error_state {
7142         struct intel_cursor_error_state {
7143                 u32 control;
7144                 u32 position;
7145                 u32 base;
7146                 u32 size;
7147         } cursor[2];
7148
7149         struct intel_pipe_error_state {
7150                 u32 conf;
7151                 u32 source;
7152
7153                 u32 htotal;
7154                 u32 hblank;
7155                 u32 hsync;
7156                 u32 vtotal;
7157                 u32 vblank;
7158                 u32 vsync;
7159         } pipe[2];
7160
7161         struct intel_plane_error_state {
7162                 u32 control;
7163                 u32 stride;
7164                 u32 size;
7165                 u32 pos;
7166                 u32 addr;
7167                 u32 surface;
7168                 u32 tile_offset;
7169         } plane[2];
7170 };
7171
7172 struct intel_display_error_state *
7173 intel_display_capture_error_state(struct drm_device *dev)
7174 {
7175         drm_i915_private_t *dev_priv = dev->dev_private;
7176         struct intel_display_error_state *error;
7177         int i;
7178
7179         error = malloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
7180         if (error == NULL)
7181                 return NULL;
7182
7183         for (i = 0; i < 2; i++) {
7184                 error->cursor[i].control = I915_READ(CURCNTR(i));
7185                 error->cursor[i].position = I915_READ(CURPOS(i));
7186                 error->cursor[i].base = I915_READ(CURBASE(i));
7187
7188                 error->plane[i].control = I915_READ(DSPCNTR(i));
7189                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7190                 error->plane[i].size = I915_READ(DSPSIZE(i));
7191                 error->plane[i].pos = I915_READ(DSPPOS(i));
7192                 error->plane[i].addr = I915_READ(DSPADDR(i));
7193                 if (INTEL_INFO(dev)->gen >= 4) {
7194                         error->plane[i].surface = I915_READ(DSPSURF(i));
7195                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7196                 }
7197
7198                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7199                 error->pipe[i].source = I915_READ(PIPESRC(i));
7200                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7201                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7202                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7203                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7204                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7205                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7206         }
7207
7208         return error;
7209 }
7210
7211 void
7212 intel_display_print_error_state(struct sbuf *m,
7213                                 struct drm_device *dev,
7214                                 struct intel_display_error_state *error)
7215 {
7216         int i;
7217
7218         for (i = 0; i < 2; i++) {
7219                 sbuf_printf(m, "Pipe [%d]:\n", i);
7220                 sbuf_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7221                 sbuf_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7222                 sbuf_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7223                 sbuf_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7224                 sbuf_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7225                 sbuf_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7226                 sbuf_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7227                 sbuf_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7228
7229                 sbuf_printf(m, "Plane [%d]:\n", i);
7230                 sbuf_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7231                 sbuf_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7232                 sbuf_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7233                 sbuf_printf(m, "  POS: %08x\n", error->plane[i].pos);
7234                 sbuf_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7235                 if (INTEL_INFO(dev)->gen >= 4) {
7236                         sbuf_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7237                         sbuf_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7238                 }
7239
7240                 sbuf_printf(m, "Cursor [%d]:\n", i);
7241                 sbuf_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7242                 sbuf_printf(m, "  POS: %08x\n", error->cursor[i].position);
7243                 sbuf_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7244         }
7245 }