sys/dev/drm2/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <dev/drm2/drmP.h>
  31 #include <dev/drm2/drm.h>
  32 #include <dev/drm2/i915/i915_drm.h>
  33 #include <dev/drm2/i915/i915_drv.h>
  34 #include <dev/drm2/i915/intel_drv.h>
  35 #include <dev/drm2/drm_edid.h>
  36 #include <dev/drm2/drm_dp_helper.h>
  37 #include <dev/drm2/drm_crtc_helper.h>
  38 #include <sys/limits.h>
  39
  40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41
  42 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc);
  44 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45
  46 typedef struct {
  47         /* given values */
  48         int n;
  49         int m1, m2;
  50         int p1, p2;
  51         /* derived values */
  52         int     dot;
  53         int     vco;
  54         int     m;
  55         int     p;
  56 } intel_clock_t;
  57
  58 typedef struct {
  59         int     min, max;
  60 } intel_range_t;
  61
  62 typedef struct {
  63         int     dot_limit;
  64         int     p2_slow, p2_fast;
  65 } intel_p2_t;
  66
  67 #define INTEL_P2_NUM                  2
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  73                         int, int, intel_clock_t *, intel_clock_t *);
  74 };
  75
  76 /* FDI */
  77 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  78
  79 static bool
  80 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  81                     int target, int refclk, intel_clock_t *match_clock,
  82                     intel_clock_t *best_clock);
  83 static bool
  84 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                         int target, int refclk, intel_clock_t *match_clock,
  86                         intel_clock_t *best_clock);
  87
  88 static bool
  89 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  90                       int target, int refclk, intel_clock_t *match_clock,
  91                       intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *match_clock,
  95                            intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2, .max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 359 {
 360         u32 val = 0;
 361
 362         mtx_lock(&dev_priv->dpio_lock);
 363         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 364                 DRM_ERROR("DPIO idle wait timed out\n");
 365                 goto out_unlock;
 366         }
 367
 368         I915_WRITE(DPIO_REG, reg);
 369         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 370                    DPIO_BYTE);
 371         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 372                 DRM_ERROR("DPIO read wait timed out\n");
 373                 goto out_unlock;
 374         }
 375         val = I915_READ(DPIO_DATA);
 376
 377 out_unlock:
 378         mtx_unlock(&dev_priv->dpio_lock);
 379         return val;
 380 }
 381
 382 #if 0
 383 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 384                              u32 val)
 385 {
 386
 387         mtx_lock(&dev_priv->dpio_lock);
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 goto out_unlock;
 391         }
 392
 393         I915_WRITE(DPIO_DATA, val);
 394         I915_WRITE(DPIO_REG, reg);
 395         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 396                    DPIO_BYTE);
 397         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 398                 DRM_ERROR("DPIO write wait timed out\n");
 399
 400 out_unlock:
 401         mtx_unlock(&dev_priv->dpio_lock);
 402 }
 403 #endif
 404
 405 static void vlv_init_dpio(struct drm_device *dev)
 406 {
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408
 409         /* Reset the DPIO config */
 410         I915_WRITE(DPIO_CTL, 0);
 411         POSTING_READ(DPIO_CTL);
 412         I915_WRITE(DPIO_CTL, 1);
 413         POSTING_READ(DPIO_CTL);
 414 }
 415
 416 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 417 {
 418         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 419         return 1;
 420 }
 421
 422 static const struct dmi_system_id intel_dual_link_lvds[] = {
 423         {
 424                 .callback = intel_dual_link_lvds_callback,
 425                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 426                 .matches = {
 427                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 428                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 429                 },
 430         },
 431         { }     /* terminating entry */
 432 };
 433
 434 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 435                               unsigned int reg)
 436 {
 437         unsigned int val;
 438
 439         /* use the module option value if specified */
 440         if (i915_lvds_channel_mode > 0)
 441                 return i915_lvds_channel_mode == 2;
 442
 443         if (dmi_check_system(intel_dual_link_lvds))
 444                 return true;
 445
 446         if (dev_priv->lvds_val)
 447                 val = dev_priv->lvds_val;
 448         else {
 449                 /* BIOS should set the proper LVDS register value at boot, but
 450                  * in reality, it doesn't set the value when the lid is closed;
 451                  * we need to check "the value to be set" in VBT when LVDS
 452                  * register is uninitialized.
 453                  */
 454                 val = I915_READ(reg);
 455                 if (!(val & ~LVDS_DETECTED))
 456                         val = dev_priv->bios_lvds_val;
 457                 dev_priv->lvds_val = val;
 458         }
 459         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 460 }
 461
 462 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 463                                                 int refclk)
 464 {
 465         struct drm_device *dev = crtc->dev;
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467         const intel_limit_t *limit;
 468
 469         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 470                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 471                         /* LVDS dual channel */
 472                         if (refclk == 100000)
 473                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 474                         else
 475                                 limit = &intel_limits_ironlake_dual_lvds;
 476                 } else {
 477                         if (refclk == 100000)
 478                                 limit = &intel_limits_ironlake_single_lvds_100m;
 479                         else
 480                                 limit = &intel_limits_ironlake_single_lvds;
 481                 }
 482         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 483                         HAS_eDP)
 484                 limit = &intel_limits_ironlake_display_port;
 485         else
 486                 limit = &intel_limits_ironlake_dac;
 487
 488         return limit;
 489 }
 490
 491 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 492 {
 493         struct drm_device *dev = crtc->dev;
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495         const intel_limit_t *limit;
 496
 497         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 498                 if (is_dual_link_lvds(dev_priv, LVDS))
 499                         /* LVDS with dual channel */
 500                         limit = &intel_limits_g4x_dual_channel_lvds;
 501                 else
 502                         /* LVDS with dual channel */
 503                         limit = &intel_limits_g4x_single_channel_lvds;
 504         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 505                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 506                 limit = &intel_limits_g4x_hdmi;
 507         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 508                 limit = &intel_limits_g4x_sdvo;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 510                 limit = &intel_limits_g4x_display_port;
 511         } else /* The option is for other outputs */
 512                 limit = &intel_limits_i9xx_sdvo;
 513
 514         return limit;
 515 }
 516
 517 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         const intel_limit_t *limit;
 521
 522         if (HAS_PCH_SPLIT(dev))
 523                 limit = intel_ironlake_limit(crtc, refclk);
 524         else if (IS_G4X(dev)) {
 525                 limit = intel_g4x_limit(crtc);
 526         } else if (IS_PINEVIEW(dev)) {
 527                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 528                         limit = &intel_limits_pineview_lvds;
 529                 else
 530                         limit = &intel_limits_pineview_sdvo;
 531         } else if (!IS_GEN2(dev)) {
 532                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 533                         limit = &intel_limits_i9xx_lvds;
 534                 else
 535                         limit = &intel_limits_i9xx_sdvo;
 536         } else {
 537                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 538                         limit = &intel_limits_i8xx_lvds;
 539                 else
 540                         limit = &intel_limits_i8xx_dvo;
 541         }
 542         return limit;
 543 }
 544
 545 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 546 static void pineview_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m2 + 2;
 549         clock->p = clock->p1 * clock->p2;
 550         clock->vco = refclk * clock->m / clock->n;
 551         clock->dot = clock->vco / clock->p;
 552 }
 553
 554 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 555 {
 556         if (IS_PINEVIEW(dev)) {
 557                 pineview_clock(refclk, clock);
 558                 return;
 559         }
 560         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 561         clock->p = clock->p1 * clock->p2;
 562         clock->vco = refclk * clock->m / (clock->n + 2);
 563         clock->dot = clock->vco / clock->p;
 564 }
 565
 566 /**
 567  * Returns whether any output on the specified pipe is of the specified type
 568  */
 569 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 570 {
 571         struct drm_device *dev = crtc->dev;
 572         struct drm_mode_config *mode_config = &dev->mode_config;
 573         struct intel_encoder *encoder;
 574
 575         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 576                 if (encoder->base.crtc == crtc && encoder->type == type)
 577                         return true;
 578
 579         return false;
 580 }
 581
 582 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 583 /**
 584  * Returns whether the given set of divisors are valid for a given refclk with
 585  * the given connectors.
 586  */
 587
 588 static bool intel_PLL_is_valid(struct drm_device *dev,
 589                                const intel_limit_t *limit,
 590                                const intel_clock_t *clock)
 591 {
 592         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 593                 INTELPllInvalid("p1 out of range\n");
 594         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 595                 INTELPllInvalid("p out of range\n");
 596         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 597                 INTELPllInvalid("m2 out of range\n");
 598         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 599                 INTELPllInvalid("m1 out of range\n");
 600         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 601                 INTELPllInvalid("m1 <= m2\n");
 602         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 603                 INTELPllInvalid("m out of range\n");
 604         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 605                 INTELPllInvalid("n out of range\n");
 606         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 607                 INTELPllInvalid("vco out of range\n");
 608         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 609          * connector, etc., rather than just a single range.
 610          */
 611         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 612                 INTELPllInvalid("dot out of range\n");
 613
 614         return true;
 615 }
 616
 617 static bool
 618 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                     int target, int refclk, intel_clock_t *match_clock,
 620                     intel_clock_t *best_clock)
 621
 622 {
 623         struct drm_device *dev = crtc->dev;
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         intel_clock_t clock;
 626         int err = target;
 627
 628         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 629             (I915_READ(LVDS)) != 0) {
 630                 /*
 631                  * For LVDS, if the panel is on, just rely on its current
 632                  * settings for dual-channel.  We haven't figured out how to
 633                  * reliably set up different single/dual channel state, if we
 634                  * even can.
 635                  */
 636                 if (is_dual_link_lvds(dev_priv, LVDS))
 637                         clock.p2 = limit->p2.p2_fast;
 638                 else
 639                         clock.p2 = limit->p2.p2_slow;
 640         } else {
 641                 if (target < limit->p2.dot_limit)
 642                         clock.p2 = limit->p2.p2_slow;
 643                 else
 644                         clock.p2 = limit->p2.p2_fast;
 645         }
 646
 647         memset(best_clock, 0, sizeof(*best_clock));
 648
 649         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 650              clock.m1++) {
 651                 for (clock.m2 = limit->m2.min;
 652                      clock.m2 <= limit->m2.max; clock.m2++) {
 653                         /* m1 is always 0 in Pineview */
 654                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 655                                 break;
 656                         for (clock.n = limit->n.min;
 657                              clock.n <= limit->n.max; clock.n++) {
 658                                 for (clock.p1 = limit->p1.min;
 659                                         clock.p1 <= limit->p1.max; clock.p1++) {
 660                                         int this_err;
 661
 662                                         intel_clock(dev, refclk, &clock);
 663                                         if (!intel_PLL_is_valid(dev, limit,
 664                                                                 &clock))
 665                                                 continue;
 666                                         if (match_clock &&
 667                                             clock.p != match_clock->p)
 668                                                 continue;
 669
 670                                         this_err = abs(clock.dot - target);
 671                                         if (this_err < err) {
 672                                                 *best_clock = clock;
 673                                                 err = this_err;
 674                                         }
 675                                 }
 676                         }
 677                 }
 678         }
 679
 680         return (err != target);
 681 }
 682
 683 static bool
 684 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 685                         int target, int refclk, intel_clock_t *match_clock,
 686                         intel_clock_t *best_clock)
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         intel_clock_t clock;
 691         int max_n;
 692         bool found;
 693         /* approximately equals target * 0.00585 */
 694         int err_most = (target >> 8) + (target >> 9);
 695         found = false;
 696
 697         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 698                 int lvds_reg;
 699
 700                 if (HAS_PCH_SPLIT(dev))
 701                         lvds_reg = PCH_LVDS;
 702                 else
 703                         lvds_reg = LVDS;
 704                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 705                     LVDS_CLKB_POWER_UP)
 706                         clock.p2 = limit->p2.p2_fast;
 707                 else
 708                         clock.p2 = limit->p2.p2_slow;
 709         } else {
 710                 if (target < limit->p2.dot_limit)
 711                         clock.p2 = limit->p2.p2_slow;
 712                 else
 713                         clock.p2 = limit->p2.p2_fast;
 714         }
 715
 716         memset(best_clock, 0, sizeof(*best_clock));
 717         max_n = limit->n.max;
 718         /* based on hardware requirement, prefer smaller n to precision */
 719         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 720                 /* based on hardware requirement, prefere larger m1,m2 */
 721                 for (clock.m1 = limit->m1.max;
 722                      clock.m1 >= limit->m1.min; clock.m1--) {
 723                         for (clock.m2 = limit->m2.max;
 724                              clock.m2 >= limit->m2.min; clock.m2--) {
 725                                 for (clock.p1 = limit->p1.max;
 726                                      clock.p1 >= limit->p1.min; clock.p1--) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err_most) {
 739                                                 *best_clock = clock;
 740                                                 err_most = this_err;
 741                                                 max_n = clock.n;
 742                                                 found = true;
 743                                         }
 744                                 }
 745                         }
 746                 }
 747         }
 748         return found;
 749 }
 750
 751 static bool
 752 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 753                            int target, int refclk, intel_clock_t *match_clock,
 754                            intel_clock_t *best_clock)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         intel_clock_t clock;
 758
 759         if (target < 200000) {
 760                 clock.n = 1;
 761                 clock.p1 = 2;
 762                 clock.p2 = 10;
 763                 clock.m1 = 12;
 764                 clock.m2 = 9;
 765         } else {
 766                 clock.n = 2;
 767                 clock.p1 = 1;
 768                 clock.p2 = 10;
 769                 clock.m1 = 14;
 770                 clock.m2 = 8;
 771         }
 772         intel_clock(dev, refclk, &clock);
 773         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 774         return true;
 775 }
 776
 777 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 778 static bool
 779 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 780                       int target, int refclk, intel_clock_t *match_clock,
 781                       intel_clock_t *best_clock)
 782 {
 783         intel_clock_t clock;
 784         if (target < 200000) {
 785                 clock.p1 = 2;
 786                 clock.p2 = 10;
 787                 clock.n = 2;
 788                 clock.m1 = 23;
 789                 clock.m2 = 8;
 790         } else {
 791                 clock.p1 = 1;
 792                 clock.p2 = 10;
 793                 clock.n = 1;
 794                 clock.m1 = 14;
 795                 clock.m2 = 2;
 796         }
 797         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 798         clock.p = (clock.p1 * clock.p2);
 799         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 800         clock.vco = 0;
 801         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 802         return true;
 803 }
 804
 805 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         u32 frame, frame_reg = PIPEFRAME(pipe);
 809
 810         frame = I915_READ(frame_reg);
 811
 812         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 813                 DRM_DEBUG_KMS("vblank wait timed out\n");
 814 }
 815
 816 /**
 817  * intel_wait_for_vblank - wait for vblank on a given pipe
 818  * @dev: drm device
 819  * @pipe: pipe to wait for
 820  *
 821  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 822  * mode setting code.
 823  */
 824 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 825 {
 826         struct drm_i915_private *dev_priv = dev->dev_private;
 827         int pipestat_reg = PIPESTAT(pipe);
 828
 829         if (INTEL_INFO(dev)->gen >= 5) {
 830                 ironlake_wait_for_vblank(dev, pipe);
 831                 return;
 832         }
 833
 834         /* Clear existing vblank status. Note this will clear any other
 835          * sticky status fields as well.
 836          *
 837          * This races with i915_driver_irq_handler() with the result
 838          * that either function could miss a vblank event.  Here it is not
 839          * fatal, as we will either wait upon the next vblank interrupt or
 840          * timeout.  Generally speaking intel_wait_for_vblank() is only
 841          * called during modeset at which time the GPU should be idle and
 842          * should *not* be performing page flips and thus not waiting on
 843          * vblanks...
 844          * Currently, the result of us stealing a vblank from the irq
 845          * handler is that a single frame will be skipped during swapbuffers.
 846          */
 847         I915_WRITE(pipestat_reg,
 848                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 849
 850         /* Wait for vblank interrupt bit to set */
 851         if (_intel_wait_for(dev,
 852             I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
 853             50, 1, "915vbl"))
 854                 DRM_DEBUG_KMS("vblank wait timed out\n");
 855 }
 856
 857 /*
 858  * intel_wait_for_pipe_off - wait for pipe to turn off
 859  * @dev: drm device
 860  * @pipe: pipe to wait for
 861  *
 862  * After disabling a pipe, we can't wait for vblank in the usual way,
 863  * spinning on the vblank interrupt status bit, since we won't actually
 864  * see an interrupt when the pipe is disabled.
 865  *
 866  * On Gen4 and above:
 867  *   wait for the pipe register state bit to turn off
 868  *
 869  * Otherwise:
 870  *   wait for the display line value to settle (it usually
 871  *   ends up stopping at the start of the next frame).
 872  *
 873  */
 874 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 875 {
 876         struct drm_i915_private *dev_priv = dev->dev_private;
 877
 878         if (INTEL_INFO(dev)->gen >= 4) {
 879                 int reg = PIPECONF(pipe);
 880
 881                 /* Wait for the Pipe State to go off */
 882                 if (_intel_wait_for(dev,
 883                     (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
 884                     1, "915pip"))
 885                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 886         } else {
 887                 u32 last_line, line_mask;
 888                 int reg = PIPEDSL(pipe);
 889                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 890
 891                 if (IS_GEN2(dev))
 892                         line_mask = DSL_LINEMASK_GEN2;
 893                 else
 894                         line_mask = DSL_LINEMASK_GEN3;
 895
 896                 /* Wait for the display line to settle */
 897                 do {
 898                         last_line = I915_READ(reg) & line_mask;
 899                         DELAY(5000);
 900                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 901                          time_after(timeout, jiffies));
 902                 if (time_after(jiffies, timeout))
 903                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 904         }
 905 }
 906
 907 static const char *state_string(bool enabled)
 908 {
 909         return enabled ? "on" : "off";
 910 }
 911
 912 /* Only for pre-ILK configs */
 913 static void assert_pll(struct drm_i915_private *dev_priv,
 914                        enum pipe pipe, bool state)
 915 {
 916         int reg;
 917         u32 val;
 918         bool cur_state;
 919
 920         reg = DPLL(pipe);
 921         val = I915_READ(reg);
 922         cur_state = !!(val & DPLL_VCO_ENABLE);
 923         if (cur_state != state)
 924                 printf("PLL state assertion failure (expected %s, current %s)\n",
 925                     state_string(state), state_string(cur_state));
 926 }
 927 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 928 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 929
 930 /* For ILK+ */
 931 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 932                            struct intel_crtc *intel_crtc,
 933                            bool state)
 934 {
 935         int reg;
 936         u32 val;
 937         bool cur_state;
 938
 939         if (HAS_PCH_LPT(dev_priv->dev)) {
 940                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 941                 return;
 942         }
 943
 944         if (!intel_crtc->pch_pll) {
 945                 printf("asserting PCH PLL enabled with no PLL\n");
 946                 return;
 947         }
 948
 949         if (HAS_PCH_CPT(dev_priv->dev)) {
 950                 u32 pch_dpll;
 951
 952                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 953
 954                 /* Make sure the selected PLL is enabled to the transcoder */
 955                 KASSERT(((pch_dpll >> (4 * intel_crtc->pipe)) & 8) != 0,
 956                     ("transcoder %d PLL not enabled\n", intel_crtc->pipe));
 957         }
 958
 959         reg = intel_crtc->pch_pll->pll_reg;
 960         val = I915_READ(reg);
 961         cur_state = !!(val & DPLL_VCO_ENABLE);
 962         if (cur_state != state)
 963                 printf("PCH PLL state assertion failure (expected %s, current %s)\n",
 964                     state_string(state), state_string(cur_state));
 965 }
 966 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 967 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 968
 969 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 970                           enum pipe pipe, bool state)
 971 {
 972         int reg;
 973         u32 val;
 974         bool cur_state;
 975
 976         if (IS_HASWELL(dev_priv->dev)) {
 977                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
 978                 reg = TRANS_DDI_FUNC_CTL(pipe);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 981         } else {
 982                 reg = FDI_TX_CTL(pipe);
 983                 val = I915_READ(reg);
 984                 cur_state = !!(val & FDI_TX_ENABLE);
 985         }
 986         if (cur_state != state)
 987                 printf("FDI TX state assertion failure (expected %s, current %s)\n",
 988                     state_string(state), state_string(cur_state));
 989 }
 990 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 991 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 992
 993 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 994                           enum pipe pipe, bool state)
 995 {
 996         int reg;
 997         u32 val;
 998         bool cur_state;
 999
1000         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1001                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1002                         return;
1003         } else {
1004                 reg = FDI_RX_CTL(pipe);
1005                 val = I915_READ(reg);
1006                 cur_state = !!(val & FDI_RX_ENABLE);
1007         }
1008         if (cur_state != state)
1009                 printf("FDI RX state assertion failure (expected %s, current %s)\n",
1010                     state_string(state), state_string(cur_state));
1011 }
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016                                       enum pipe pipe)
1017 {
1018         int reg;
1019         u32 val;
1020
1021         /* ILK FDI PLL is always enabled */
1022         if (dev_priv->info->gen == 5)
1023                 return;
1024
1025         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026         if (IS_HASWELL(dev_priv->dev))
1027                 return;
1028
1029         reg = FDI_TX_CTL(pipe);
1030         val = I915_READ(reg);
1031         if (!(val & FDI_TX_PLL_ENABLE))
1032                 printf("FDI TX PLL assertion failure, should be active but is disabled\n");
1033 }
1034
1035 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1036                                       enum pipe pipe)
1037 {
1038         int reg;
1039         u32 val;
1040
1041         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1042                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1043                 return;
1044         }
1045         reg = FDI_RX_CTL(pipe);
1046         val = I915_READ(reg);
1047         if (!(val & FDI_RX_PLL_ENABLE))
1048                 printf("FDI RX PLL assertion failure, should be active but is disabled\n");
1049 }
1050
1051 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1052                                   enum pipe pipe)
1053 {
1054         int pp_reg, lvds_reg;
1055         u32 val;
1056         enum pipe panel_pipe = PIPE_A;
1057         bool locked = true;
1058
1059         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1060                 pp_reg = PCH_PP_CONTROL;
1061                 lvds_reg = PCH_LVDS;
1062         } else {
1063                 pp_reg = PP_CONTROL;
1064                 lvds_reg = LVDS;
1065         }
1066
1067         val = I915_READ(pp_reg);
1068         if (!(val & PANEL_POWER_ON) ||
1069             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1070                 locked = false;
1071
1072         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1073                 panel_pipe = PIPE_B;
1074
1075         if (panel_pipe == pipe && locked)
1076                 printf("panel assertion failure, pipe %c regs locked\n",
1077              pipe_name(pipe));
1078 }
1079
1080 void assert_pipe(struct drm_i915_private *dev_priv,
1081                  enum pipe pipe, bool state)
1082 {
1083         int reg;
1084         u32 val;
1085         bool cur_state;
1086
1087         /* if we need the pipe A quirk it must be always on */
1088         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1089                 state = true;
1090
1091         reg = PIPECONF(pipe);
1092         val = I915_READ(reg);
1093         cur_state = !!(val & PIPECONF_ENABLE);
1094         if (cur_state != state)
1095                 printf("pipe %c assertion failure (expected %s, current %s)\n",
1096                     pipe_name(pipe), state_string(state), state_string(cur_state));
1097 }
1098
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100                          enum plane plane, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105
1106         reg = DSPCNTR(plane);
1107         val = I915_READ(reg);
1108         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109         if (cur_state != state)
1110                 printf("plane %c assertion failure, (expected %s, current %s)\n",
1111                        plane_name(plane), state_string(state), state_string(cur_state));
1112 }
1113
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118                                    enum pipe pipe)
1119 {
1120         int reg, i;
1121         u32 val;
1122         int cur_pipe;
1123
1124         /* Planes are fixed to pipes on ILK+ */
1125         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1126                 reg = DSPCNTR(pipe);
1127                 val = I915_READ(reg);
1128                 if ((val & DISPLAY_PLANE_ENABLE) != 0)
1129                         printf("plane %c assertion failure, should be disabled but not\n",
1130                                plane_name(pipe));
1131                 return;
1132         }
1133
1134         /* Need to check both planes against the pipe */
1135         for (i = 0; i < 2; i++) {
1136                 reg = DSPCNTR(i);
1137                 val = I915_READ(reg);
1138                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1139                         DISPPLANE_SEL_PIPE_SHIFT;
1140                 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1141                         printf("plane %c assertion failure, should be off on pipe %c but is still active\n",
1142                      plane_name(i), pipe_name(pipe));
1143         }
1144 }
1145
1146 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1147 {
1148         u32 val;
1149         bool enabled;
1150
1151         if (HAS_PCH_LPT(dev_priv->dev)) {
1152                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1153                 return;
1154         }
1155
1156         val = I915_READ(PCH_DREF_CONTROL);
1157         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1158                             DREF_SUPERSPREAD_SOURCE_MASK));
1159         if (!enabled)
1160                 printf("PCH refclk assertion failure, should be active but is disabled\n");
1161 }
1162
1163 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1164                                        enum pipe pipe)
1165 {
1166         int reg;
1167         u32 val;
1168         bool enabled;
1169
1170         reg = TRANSCONF(pipe);
1171         val = I915_READ(reg);
1172         enabled = !!(val & TRANS_ENABLE);
1173         if (enabled)
1174                 printf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1179                             enum pipe pipe, u32 port_sel, u32 val)
1180 {
1181         if ((val & DP_PORT_EN) == 0)
1182                 return false;
1183
1184         if (HAS_PCH_CPT(dev_priv->dev)) {
1185                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1186                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1187                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1188                         return false;
1189         } else {
1190                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1191                         return false;
1192         }
1193         return true;
1194 }
1195
1196 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1197                               enum pipe pipe, u32 val)
1198 {
1199         if ((val & PORT_ENABLE) == 0)
1200                 return false;
1201
1202         if (HAS_PCH_CPT(dev_priv->dev)) {
1203                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1204                         return false;
1205         } else {
1206                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1207                         return false;
1208         }
1209         return true;
1210 }
1211
1212 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1213                               enum pipe pipe, u32 val)
1214 {
1215         if ((val & LVDS_PORT_EN) == 0)
1216                 return false;
1217
1218         if (HAS_PCH_CPT(dev_priv->dev)) {
1219                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1220                         return false;
1221         } else {
1222                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1223                         return false;
1224         }
1225         return true;
1226 }
1227
1228 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1229                               enum pipe pipe, u32 val)
1230 {
1231         if ((val & ADPA_DAC_ENABLE) == 0)
1232                 return false;
1233         if (HAS_PCH_CPT(dev_priv->dev)) {
1234                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1235                         return false;
1236         } else {
1237                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1238                         return false;
1239         }
1240         return true;
1241 }
1242
1243 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1244                                    enum pipe pipe, int reg, u32 port_sel)
1245 {
1246         u32 val = I915_READ(reg);
1247         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1248                 printf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1249              reg, pipe_name(pipe));
1250 }
1251
1252 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1253                                      enum pipe pipe, int reg)
1254 {
1255         u32 val = I915_READ(reg);
1256         if (hdmi_pipe_enabled(dev_priv, val, pipe))
1257                 printf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1258              reg, pipe_name(pipe));
1259 }
1260
1261 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1262                                       enum pipe pipe)
1263 {
1264         int reg;
1265         u32 val;
1266
1267         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1268         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1269         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1270
1271         reg = PCH_ADPA;
1272         val = I915_READ(reg);
1273         if (adpa_pipe_enabled(dev_priv, val, pipe))
1274                 printf("PCH VGA enabled on transcoder %c, should be disabled\n",
1275              pipe_name(pipe));
1276
1277         reg = PCH_LVDS;
1278         val = I915_READ(reg);
1279         if (lvds_pipe_enabled(dev_priv, val, pipe))
1280                 printf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1281              pipe_name(pipe));
1282
1283         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1284         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1285         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1286 }
1287
1288 /**
1289  * intel_enable_pll - enable a PLL
1290  * @dev_priv: i915 private structure
1291  * @pipe: pipe PLL to enable
1292  *
1293  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1294  * make sure the PLL reg is writable first though, since the panel write
1295  * protect mechanism may be enabled.
1296  *
1297  * Note!  This is for pre-ILK only.
1298  */
1299 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1300 {
1301         int reg;
1302         u32 val;
1303
1304         /* No really, not for ILK+ */
1305         KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1306
1307         /* PLL is protected by panel, make sure we can write it */
1308         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1309                 assert_panel_unlocked(dev_priv, pipe);
1310
1311         reg = DPLL(pipe);
1312         val = I915_READ(reg);
1313         val |= DPLL_VCO_ENABLE;
1314
1315         /* We do this three times for luck */
1316         I915_WRITE(reg, val);
1317         POSTING_READ(reg);
1318         DELAY(150); /* wait for warmup */
1319         I915_WRITE(reg, val);
1320         POSTING_READ(reg);
1321         DELAY(150); /* wait for warmup */
1322         I915_WRITE(reg, val);
1323         POSTING_READ(reg);
1324         DELAY(150); /* wait for warmup */
1325 }
1326
1327 /**
1328  * intel_disable_pll - disable a PLL
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe PLL to disable
1331  *
1332  * Disable the PLL for @pipe, making sure the pipe is off first.
1333  *
1334  * Note!  This is for pre-ILK only.
1335  */
1336 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1337 {
1338         int reg;
1339         u32 val;
1340
1341         /* Don't disable pipe A or pipe A PLLs if needed */
1342         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1343                 return;
1344
1345         /* Make sure the pipe isn't still relying on us */
1346         assert_pipe_disabled(dev_priv, pipe);
1347
1348         reg = DPLL(pipe);
1349         val = I915_READ(reg);
1350         val &= ~DPLL_VCO_ENABLE;
1351         I915_WRITE(reg, val);
1352         POSTING_READ(reg);
1353 }
1354
1355 /* SBI access */
1356 static void
1357 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1358 {
1359
1360         mtx_lock(&dev_priv->dpio_lock);
1361         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, 100)) {
1362                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1363                 goto out_unlock;
1364         }
1365
1366         I915_WRITE(SBI_ADDR, (reg << 16));
1367         I915_WRITE(SBI_DATA, value);
1368         I915_WRITE(SBI_CTL_STAT,
1369                         SBI_BUSY |
1370                         SBI_CTL_OP_CRWR);
1371
1372         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1373                                 100)) {
1374                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1375                 goto out_unlock;
1376         }
1377
1378 out_unlock:
1379         mtx_unlock(&dev_priv->dpio_lock);
1380 }
1381
1382 static u32
1383 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1384 {
1385         u32 value;
1386
1387         value = 0;
1388         mtx_lock(&dev_priv->dpio_lock);
1389         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, 100)) {
1390                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1391                 goto out_unlock;
1392         }
1393
1394         I915_WRITE(SBI_ADDR, (reg << 16));
1395         I915_WRITE(SBI_CTL_STAT,
1396                         SBI_BUSY |
1397                         SBI_CTL_OP_CRRD);
1398
1399         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1400                                 100)) {
1401                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1402                 goto out_unlock;
1403         }
1404
1405         value = I915_READ(SBI_DATA);
1406
1407 out_unlock:
1408         mtx_unlock(&dev_priv->dpio_lock);
1409         return value;
1410 }
1411
1412 /**
1413  * intel_enable_pch_pll - enable PCH PLL
1414  * @dev_priv: i915 private structure
1415  * @pipe: pipe PLL to enable
1416  *
1417  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1418  * drives the transcoder clock.
1419  */
1420 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1421 {
1422         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1423         struct intel_pch_pll *pll;
1424         int reg;
1425         u32 val;
1426
1427         /* PCH PLLs only available on ILK, SNB and IVB */
1428         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1429         pll = intel_crtc->pch_pll;
1430         if (pll == NULL)
1431                 return;
1432
1433         if (pll->refcount == 0) {
1434                 DRM_DEBUG_KMS("pll->refcount == 0\n");
1435                 return;
1436         }
1437
1438         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1439                       pll->pll_reg, pll->active, pll->on,
1440                       intel_crtc->base.base.id);
1441
1442         /* PCH refclock must be enabled first */
1443         assert_pch_refclk_enabled(dev_priv);
1444
1445         if (pll->active++ && pll->on) {
1446                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1447                 return;
1448         }
1449
1450         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1451
1452         reg = pll->pll_reg;
1453         val = I915_READ(reg);
1454         val |= DPLL_VCO_ENABLE;
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         DELAY(200);
1458
1459         pll->on = true;
1460 }
1461
1462 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1463 {
1464         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1465         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1466         int reg;
1467         u32 val;
1468
1469         /* PCH only available on ILK+ */
1470         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1471         if (pll == NULL)
1472                 return;
1473
1474         if (pll->refcount == 0) {
1475                 DRM_DEBUG_KMS("pll->refcount == 0\n");
1476                 return;
1477         }
1478
1479         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1480                       pll->pll_reg, pll->active, pll->on,
1481                       intel_crtc->base.base.id);
1482
1483         if (pll->active == 0) {
1484                 DRM_DEBUG_KMS("pll->active == 0\n");
1485                 assert_pch_pll_disabled(dev_priv, intel_crtc);
1486                 return;
1487         }
1488
1489         if (--pll->active) {
1490                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1491                 return;
1492         }
1493
1494         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1495
1496         /* Make sure transcoder isn't still depending on us */
1497         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1498
1499         reg = pll->pll_reg;
1500         val = I915_READ(reg);
1501         val &= ~DPLL_VCO_ENABLE;
1502         I915_WRITE(reg, val);
1503         POSTING_READ(reg);
1504         DELAY(200);
1505
1506         pll->on = false;
1507 }
1508
1509 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1510                                     enum pipe pipe)
1511 {
1512         int reg;
1513         u32 val, pipeconf_val;
1514         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1515
1516         /* PCH only available on ILK+ */
1517         KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1518
1519         /* Make sure PCH DPLL is enabled */
1520         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1521
1522         /* FDI must be feeding us bits for PCH ports */
1523         assert_fdi_tx_enabled(dev_priv, pipe);
1524         assert_fdi_rx_enabled(dev_priv, pipe);
1525
1526         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1527                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1528                 return;
1529         }
1530         reg = TRANSCONF(pipe);
1531         val = I915_READ(reg);
1532         pipeconf_val = I915_READ(PIPECONF(pipe));
1533         if (HAS_PCH_IBX(dev_priv->dev)) {
1534                 /*
1535                  * make the BPC in transcoder be consistent with
1536                  * that in pipeconf reg.
1537                  */
1538                 val &= ~PIPE_BPC_MASK;
1539                 val |= pipeconf_val & PIPE_BPC_MASK;
1540         }
1541
1542         val &= ~TRANS_INTERLACE_MASK;
1543         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1544                 if (HAS_PCH_IBX(dev_priv->dev) &&
1545                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1546                         val |= TRANS_LEGACY_INTERLACED_ILK;
1547                 else
1548                         val |= TRANS_INTERLACED;
1549         else
1550                 val |= TRANS_PROGRESSIVE;
1551
1552         I915_WRITE(reg, val | TRANS_ENABLE);
1553         if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1554             100, 1, "915trc"))
1555                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1556 }
1557
1558 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1559                                      enum pipe pipe)
1560 {
1561         int reg;
1562         u32 val;
1563
1564         /* FDI relies on the transcoder */
1565         assert_fdi_tx_disabled(dev_priv, pipe);
1566         assert_fdi_rx_disabled(dev_priv, pipe);
1567
1568         /* Ports must be off as well */
1569         assert_pch_ports_disabled(dev_priv, pipe);
1570
1571         reg = TRANSCONF(pipe);
1572         val = I915_READ(reg);
1573         val &= ~TRANS_ENABLE;
1574         I915_WRITE(reg, val);
1575         /* wait for PCH transcoder off, transcoder state */
1576         if (_intel_wait_for(dev_priv->dev,
1577             (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1578             1, "915trd"))
1579                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1580 }
1581
1582 /**
1583  * intel_enable_pipe - enable a pipe, asserting requirements
1584  * @dev_priv: i915 private structure
1585  * @pipe: pipe to enable
1586  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1587  *
1588  * Enable @pipe, making sure that various hardware specific requirements
1589  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1590  *
1591  * @pipe should be %PIPE_A or %PIPE_B.
1592  *
1593  * Will wait until the pipe is actually running (i.e. first vblank) before
1594  * returning.
1595  */
1596 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1597                               bool pch_port)
1598 {
1599         int reg;
1600         u32 val;
1601
1602         /*
1603          * A pipe without a PLL won't actually be able to drive bits from
1604          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1605          * need the check.
1606          */
1607         if (!HAS_PCH_SPLIT(dev_priv->dev))
1608                 assert_pll_enabled(dev_priv, pipe);
1609         else {
1610                 if (pch_port) {
1611                         /* if driving the PCH, we need FDI enabled */
1612                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1613                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1614                 }
1615                 /* FIXME: assert CPU port conditions for SNB+ */
1616         }
1617
1618         reg = PIPECONF(pipe);
1619         val = I915_READ(reg);
1620         if (val & PIPECONF_ENABLE)
1621                 return;
1622
1623         I915_WRITE(reg, val | PIPECONF_ENABLE);
1624         intel_wait_for_vblank(dev_priv->dev, pipe);
1625 }
1626
1627 /**
1628  * intel_disable_pipe - disable a pipe, asserting requirements
1629  * @dev_priv: i915 private structure
1630  * @pipe: pipe to disable
1631  *
1632  * Disable @pipe, making sure that various hardware specific requirements
1633  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1634  *
1635  * @pipe should be %PIPE_A or %PIPE_B.
1636  *
1637  * Will wait until the pipe has shut down before returning.
1638  */
1639 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1640                                enum pipe pipe)
1641 {
1642         int reg;
1643         u32 val;
1644
1645         /*
1646          * Make sure planes won't keep trying to pump pixels to us,
1647          * or we might hang the display.
1648          */
1649         assert_planes_disabled(dev_priv, pipe);
1650
1651         /* Don't disable pipe A or pipe A PLLs if needed */
1652         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1653                 return;
1654
1655         reg = PIPECONF(pipe);
1656         val = I915_READ(reg);
1657         if ((val & PIPECONF_ENABLE) == 0)
1658                 return;
1659
1660         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1661         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1662 }
1663
1664 /*
1665  * Plane regs are double buffered, going from enabled->disabled needs a
1666  * trigger in order to latch.  The display address reg provides this.
1667  */
1668 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1669                                       enum plane plane)
1670 {
1671         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1672         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1673 }
1674
1675 /**
1676  * intel_enable_plane - enable a display plane on a given pipe
1677  * @dev_priv: i915 private structure
1678  * @plane: plane to enable
1679  * @pipe: pipe being fed
1680  *
1681  * Enable @plane on @pipe, making sure that @pipe is running first.
1682  */
1683 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1684                                enum plane plane, enum pipe pipe)
1685 {
1686         int reg;
1687         u32 val;
1688
1689         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1690         assert_pipe_enabled(dev_priv, pipe);
1691
1692         reg = DSPCNTR(plane);
1693         val = I915_READ(reg);
1694         if (val & DISPLAY_PLANE_ENABLE)
1695                 return;
1696
1697         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1698         intel_flush_display_plane(dev_priv, plane);
1699         intel_wait_for_vblank(dev_priv->dev, pipe);
1700 }
1701
1702 /**
1703  * intel_disable_plane - disable a display plane
1704  * @dev_priv: i915 private structure
1705  * @plane: plane to disable
1706  * @pipe: pipe consuming the data
1707  *
1708  * Disable @plane; should be an independent operation.
1709  */
1710 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1711                                 enum plane plane, enum pipe pipe)
1712 {
1713         int reg;
1714         u32 val;
1715
1716         reg = DSPCNTR(plane);
1717         val = I915_READ(reg);
1718         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1719                 return;
1720
1721         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1722         intel_flush_display_plane(dev_priv, plane);
1723         intel_wait_for_vblank(dev_priv->dev, pipe);
1724 }
1725
1726 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1727                            enum pipe pipe, int reg, u32 port_sel)
1728 {
1729         u32 val = I915_READ(reg);
1730         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1731                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1732                 I915_WRITE(reg, val & ~DP_PORT_EN);
1733         }
1734 }
1735
1736 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1737                              enum pipe pipe, int reg)
1738 {
1739         u32 val = I915_READ(reg);
1740         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1741                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1742                               reg, pipe);
1743                 I915_WRITE(reg, val & ~PORT_ENABLE);
1744         }
1745 }
1746
1747 /* Disable any ports connected to this transcoder */
1748 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1749                                     enum pipe pipe)
1750 {
1751         u32 reg, val;
1752
1753         val = I915_READ(PCH_PP_CONTROL);
1754         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1755
1756         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1757         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1758         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1759
1760         reg = PCH_ADPA;
1761         val = I915_READ(reg);
1762         if (adpa_pipe_enabled(dev_priv, val, pipe))
1763                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1764
1765         reg = PCH_LVDS;
1766         val = I915_READ(reg);
1767         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1768                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1769                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1770                 POSTING_READ(reg);
1771                 DELAY(100);
1772         }
1773
1774         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1775         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1776         disable_pch_hdmi(dev_priv, pipe, HDMID);
1777 }
1778
1779 int
1780 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1781                            struct drm_i915_gem_object *obj,
1782                            struct intel_ring_buffer *pipelined)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785         u32 alignment;
1786         int ret;
1787
1788         alignment = 0; /* shut gcc */
1789         switch (obj->tiling_mode) {
1790         case I915_TILING_NONE:
1791                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792                         alignment = 128 * 1024;
1793                 else if (INTEL_INFO(dev)->gen >= 4)
1794                         alignment = 4 * 1024;
1795                 else
1796                         alignment = 64 * 1024;
1797                 break;
1798         case I915_TILING_X:
1799                 /* pin() will align the object as required by fence */
1800                 alignment = 0;
1801                 break;
1802         case I915_TILING_Y:
1803                 /* FIXME: Is this true? */
1804                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1805                 return -EINVAL;
1806         default:
1807                 KASSERT(0, ("Wrong tiling for fb obj"));
1808         }
1809
1810         dev_priv->mm.interruptible = false;
1811         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1812         if (ret)
1813                 goto err_interruptible;
1814
1815         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1816          * fence, whereas 965+ only requires a fence if using
1817          * framebuffer compression.  For simplicity, we always install
1818          * a fence as the cost is not that onerous.
1819          */
1820         ret = i915_gem_object_get_fence(obj);
1821         if (ret)
1822                 goto err_unpin;
1823
1824         i915_gem_object_pin_fence(obj);
1825
1826         dev_priv->mm.interruptible = true;
1827         return 0;
1828
1829 err_unpin:
1830         i915_gem_object_unpin_from_display_plane(obj);
1831 err_interruptible:
1832         dev_priv->mm.interruptible = true;
1833         return ret;
1834 }
1835
1836 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1837 {
1838         i915_gem_object_unpin_fence(obj);
1839         i915_gem_object_unpin_from_display_plane(obj);
1840 }
1841
1842 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1843                              int x, int y)
1844 {
1845         struct drm_device *dev = crtc->dev;
1846         struct drm_i915_private *dev_priv = dev->dev_private;
1847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1848         struct intel_framebuffer *intel_fb;
1849         struct drm_i915_gem_object *obj;
1850         int plane = intel_crtc->plane;
1851         unsigned long Start, Offset;
1852         u32 dspcntr;
1853         u32 reg;
1854
1855         switch (plane) {
1856         case 0:
1857         case 1:
1858                 break;
1859         default:
1860                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1861                 return -EINVAL;
1862         }
1863
1864         intel_fb = to_intel_framebuffer(fb);
1865         obj = intel_fb->obj;
1866
1867         reg = DSPCNTR(plane);
1868         dspcntr = I915_READ(reg);
1869         /* Mask out pixel format bits in case we change it */
1870         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1871         switch (fb->bits_per_pixel) {
1872         case 8:
1873                 dspcntr |= DISPPLANE_8BPP;
1874                 break;
1875         case 16:
1876                 if (fb->depth == 15)
1877                         dspcntr |= DISPPLANE_BGRX555;
1878                 else
1879                         dspcntr |= DISPPLANE_BGRX565;
1880                 break;
1881         case 24:
1882         case 32:
1883                 dspcntr |= DISPPLANE_BGRX888;
1884                 break;
1885         default:
1886                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1887                 return -EINVAL;
1888         }
1889         if (INTEL_INFO(dev)->gen >= 4) {
1890                 if (obj->tiling_mode != I915_TILING_NONE)
1891                         dspcntr |= DISPPLANE_TILED;
1892                 else
1893                         dspcntr &= ~DISPPLANE_TILED;
1894         }
1895
1896         I915_WRITE(reg, dspcntr);
1897
1898         Start = obj->gtt_offset;
1899         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1900
1901         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1902                       Start, Offset, x, y, fb->pitches[0]);
1903         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1904         if (INTEL_INFO(dev)->gen >= 4) {
1905                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1906                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1907                 I915_WRITE(DSPADDR(plane), Offset);
1908         } else
1909                 I915_WRITE(DSPADDR(plane), Start + Offset);
1910         POSTING_READ(reg);
1911
1912         return 0;
1913 }
1914
1915 static int ironlake_update_plane(struct drm_crtc *crtc,
1916                                  struct drm_framebuffer *fb, int x, int y)
1917 {
1918         struct drm_device *dev = crtc->dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         struct intel_framebuffer *intel_fb;
1922         struct drm_i915_gem_object *obj;
1923         int plane = intel_crtc->plane;
1924         unsigned long Start, Offset;
1925         u32 dspcntr;
1926         u32 reg;
1927
1928         switch (plane) {
1929         case 0:
1930         case 1:
1931         case 2:
1932                 break;
1933         default:
1934                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1935                 return -EINVAL;
1936         }
1937
1938         intel_fb = to_intel_framebuffer(fb);
1939         obj = intel_fb->obj;
1940
1941         reg = DSPCNTR(plane);
1942         dspcntr = I915_READ(reg);
1943         /* Mask out pixel format bits in case we change it */
1944         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1945         switch (fb->bits_per_pixel) {
1946         case 8:
1947                 dspcntr |= DISPPLANE_8BPP;
1948                 break;
1949         case 16:
1950                 if (fb->depth != 16) {
1951                         DRM_ERROR("bpp 16, depth %d\n", fb->depth);
1952                         return -EINVAL;
1953                 }
1954
1955                 dspcntr |= DISPPLANE_BGRX565;
1956                 break;
1957         case 24:
1958         case 32:
1959                 if (fb->depth == 24)
1960                         dspcntr |= DISPPLANE_BGRX888;
1961                 else if (fb->depth == 30)
1962                         dspcntr |= DISPPLANE_BGRX101010;
1963                 else {
1964                         DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
1965                             fb->depth);
1966                         return -EINVAL;
1967                 }
1968                 break;
1969         default:
1970                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1971                 return -EINVAL;
1972         }
1973
1974         if (obj->tiling_mode != I915_TILING_NONE)
1975                 dspcntr |= DISPPLANE_TILED;
1976         else
1977                 dspcntr &= ~DISPPLANE_TILED;
1978
1979         /* must disable */
1980         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1981
1982         I915_WRITE(reg, dspcntr);
1983
1984         Start = obj->gtt_offset;
1985         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1986
1987         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1988                       Start, Offset, x, y, fb->pitches[0]);
1989         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1990         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1991         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1992         I915_WRITE(DSPADDR(plane), Offset);
1993         POSTING_READ(reg);
1994
1995         return 0;
1996 }
1997
1998 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1999 static int
2000 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2001                            int x, int y, enum mode_set_atomic state)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005
2006         if (dev_priv->display.disable_fbc)
2007                 dev_priv->display.disable_fbc(dev);
2008         intel_increase_pllclock(crtc);
2009
2010         return dev_priv->display.update_plane(crtc, fb, x, y);
2011 }
2012
2013 static int
2014 intel_finish_fb(struct drm_framebuffer *old_fb)
2015 {
2016         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2017         struct drm_device *dev = obj->base.dev;
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         bool was_interruptible = dev_priv->mm.interruptible;
2020         int ret;
2021
2022         mtx_lock(&dev->event_lock);
2023         while (!atomic_load_acq_int(&dev_priv->mm.wedged) &&
2024             atomic_load_acq_int(&obj->pending_flip) != 0) {
2025                 msleep(&obj->pending_flip, &dev->event_lock,
2026                     0, "915flp", 0);
2027         }
2028         mtx_unlock(&dev->event_lock);
2029
2030         /* Big Hammer, we also need to ensure that any pending
2031          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2032          * current scanout is retired before unpinning the old
2033          * framebuffer.
2034          *
2035          * This should only fail upon a hung GPU, in which case we
2036          * can safely continue.
2037          */
2038         dev_priv->mm.interruptible = false;
2039         ret = i915_gem_object_finish_gpu(obj);
2040         dev_priv->mm.interruptible = was_interruptible;
2041
2042         return ret;
2043 }
2044
2045 static int
2046 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2047                     struct drm_framebuffer *old_fb)
2048 {
2049         struct drm_device *dev = crtc->dev;
2050         struct drm_i915_private *dev_priv = dev->dev_private;
2051         struct drm_i915_master_private *master_priv;
2052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053         int ret;
2054
2055         /* no fb bound */
2056         if (!crtc->fb) {
2057                 DRM_ERROR("No FB bound\n");
2058                 return 0;
2059         }
2060
2061         if(intel_crtc->plane > dev_priv->num_pipe) {
2062                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2063                                 intel_crtc->plane,
2064                                 dev_priv->num_pipe);
2065                 return -EINVAL;
2066         }
2067
2068         DRM_LOCK(dev);
2069         ret = intel_pin_and_fence_fb_obj(dev,
2070                                          to_intel_framebuffer(crtc->fb)->obj,
2071                                          NULL);
2072         if (ret != 0) {
2073                 DRM_UNLOCK(dev);
2074                 DRM_ERROR("pin & fence failed\n");
2075                 return ret;
2076         }
2077
2078         if (old_fb)
2079                 intel_finish_fb(old_fb);
2080
2081         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2082         if (ret) {
2083                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2084                 DRM_UNLOCK(dev);
2085                 DRM_ERROR("failed to update base address\n");
2086                 return ret;
2087         }
2088
2089         if (old_fb) {
2090                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2091                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2092         }
2093
2094         intel_update_fbc(dev);
2095         DRM_UNLOCK(dev);
2096
2097         if (!dev->primary->master)
2098                 return 0;
2099
2100         master_priv = dev->primary->master->driver_priv;
2101         if (!master_priv->sarea_priv)
2102                 return 0;
2103
2104         if (intel_crtc->pipe) {
2105                 master_priv->sarea_priv->pipeB_x = x;
2106                 master_priv->sarea_priv->pipeB_y = y;
2107         } else {
2108                 master_priv->sarea_priv->pipeA_x = x;
2109                 master_priv->sarea_priv->pipeA_y = y;
2110         }
2111
2112         return 0;
2113 }
2114
2115 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2116 {
2117         struct drm_device *dev = crtc->dev;
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119         u32 dpa_ctl;
2120
2121         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2122         dpa_ctl = I915_READ(DP_A);
2123         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2124
2125         if (clock < 200000) {
2126                 u32 temp;
2127                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2128                 /* workaround for 160Mhz:
2129                    1) program 0x4600c bits 15:0 = 0x8124
2130                    2) program 0x46010 bit 0 = 1
2131                    3) program 0x46034 bit 24 = 1
2132                    4) program 0x64000 bit 14 = 1
2133                    */
2134                 temp = I915_READ(0x4600c);
2135                 temp &= 0xffff0000;
2136                 I915_WRITE(0x4600c, temp | 0x8124);
2137
2138                 temp = I915_READ(0x46010);
2139                 I915_WRITE(0x46010, temp | 1);
2140
2141                 temp = I915_READ(0x46034);
2142                 I915_WRITE(0x46034, temp | (1 << 24));
2143         } else {
2144                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2145         }
2146         I915_WRITE(DP_A, dpa_ctl);
2147
2148         POSTING_READ(DP_A);
2149         DELAY(500);
2150 }
2151
2152 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2153 {
2154         struct drm_device *dev = crtc->dev;
2155         struct drm_i915_private *dev_priv = dev->dev_private;
2156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2157         int pipe = intel_crtc->pipe;
2158         u32 reg, temp;
2159
2160         /* enable normal train */
2161         reg = FDI_TX_CTL(pipe);
2162         temp = I915_READ(reg);
2163         if (IS_IVYBRIDGE(dev)) {
2164                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2165                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2166         } else {
2167                 temp &= ~FDI_LINK_TRAIN_NONE;
2168                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2169         }
2170         I915_WRITE(reg, temp);
2171
2172         reg = FDI_RX_CTL(pipe);
2173         temp = I915_READ(reg);
2174         if (HAS_PCH_CPT(dev)) {
2175                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2176                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2177         } else {
2178                 temp &= ~FDI_LINK_TRAIN_NONE;
2179                 temp |= FDI_LINK_TRAIN_NONE;
2180         }
2181         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2182
2183         /* wait one idle pattern time */
2184         POSTING_READ(reg);
2185         DELAY(1000);
2186
2187         /* IVB wants error correction enabled */
2188         if (IS_IVYBRIDGE(dev))
2189                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2190                            FDI_FE_ERRC_ENABLE);
2191 }
2192
2193 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2194 {
2195         struct drm_i915_private *dev_priv = dev->dev_private;
2196         u32 flags = I915_READ(SOUTH_CHICKEN1);
2197
2198         flags |= FDI_PHASE_SYNC_OVR(pipe);
2199         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2200         flags |= FDI_PHASE_SYNC_EN(pipe);
2201         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2202         POSTING_READ(SOUTH_CHICKEN1);
2203 }
2204
2205 /* The FDI link training functions for ILK/Ibexpeak. */
2206 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2207 {
2208         struct drm_device *dev = crtc->dev;
2209         struct drm_i915_private *dev_priv = dev->dev_private;
2210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211         int pipe = intel_crtc->pipe;
2212         int plane = intel_crtc->plane;
2213         u32 reg, temp, tries;
2214
2215         /* FDI needs bits from pipe & plane first */
2216         assert_pipe_enabled(dev_priv, pipe);
2217         assert_plane_enabled(dev_priv, plane);
2218
2219         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2220            for train result */
2221         reg = FDI_RX_IMR(pipe);
2222         temp = I915_READ(reg);
2223         temp &= ~FDI_RX_SYMBOL_LOCK;
2224         temp &= ~FDI_RX_BIT_LOCK;
2225         I915_WRITE(reg, temp);
2226         I915_READ(reg);
2227         DELAY(150);
2228
2229         /* enable CPU FDI TX and PCH FDI RX */
2230         reg = FDI_TX_CTL(pipe);
2231         temp = I915_READ(reg);
2232         temp &= ~(7 << 19);
2233         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2234         temp &= ~FDI_LINK_TRAIN_NONE;
2235         temp |= FDI_LINK_TRAIN_PATTERN_1;
2236         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2237
2238         reg = FDI_RX_CTL(pipe);
2239         temp = I915_READ(reg);
2240         temp &= ~FDI_LINK_TRAIN_NONE;
2241         temp |= FDI_LINK_TRAIN_PATTERN_1;
2242         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2243
2244         POSTING_READ(reg);
2245         DELAY(150);
2246
2247         /* Ironlake workaround, enable clock pointer after FDI enable*/
2248         if (HAS_PCH_IBX(dev)) {
2249                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2250                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2251                            FDI_RX_PHASE_SYNC_POINTER_EN);
2252         }
2253
2254         reg = FDI_RX_IIR(pipe);
2255         for (tries = 0; tries < 5; tries++) {
2256                 temp = I915_READ(reg);
2257                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2258
2259                 if ((temp & FDI_RX_BIT_LOCK)) {
2260                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2261                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2262                         break;
2263                 }
2264         }
2265         if (tries == 5)
2266                 DRM_ERROR("FDI train 1 fail!\n");
2267
2268         /* Train 2 */
2269         reg = FDI_TX_CTL(pipe);
2270         temp = I915_READ(reg);
2271         temp &= ~FDI_LINK_TRAIN_NONE;
2272         temp |= FDI_LINK_TRAIN_PATTERN_2;
2273         I915_WRITE(reg, temp);
2274
2275         reg = FDI_RX_CTL(pipe);
2276         temp = I915_READ(reg);
2277         temp &= ~FDI_LINK_TRAIN_NONE;
2278         temp |= FDI_LINK_TRAIN_PATTERN_2;
2279         I915_WRITE(reg, temp);
2280
2281         POSTING_READ(reg);
2282         DELAY(150);
2283
2284         reg = FDI_RX_IIR(pipe);
2285         for (tries = 0; tries < 5; tries++) {
2286                 temp = I915_READ(reg);
2287                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2288
2289                 if (temp & FDI_RX_SYMBOL_LOCK) {
2290                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2291                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2292                         break;
2293                 }
2294         }
2295         if (tries == 5)
2296                 DRM_ERROR("FDI train 2 fail!\n");
2297
2298         DRM_DEBUG_KMS("FDI train done\n");
2299
2300 }
2301
2302 static const int snb_b_fdi_train_param[] = {
2303         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2304         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2305         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2306         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2307 };
2308
2309 /* The FDI link training functions for SNB/Cougarpoint. */
2310 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2311 {
2312         struct drm_device *dev = crtc->dev;
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315         int pipe = intel_crtc->pipe;
2316         u32 reg, temp, i, retry;
2317
2318         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2319            for train result */
2320         reg = FDI_RX_IMR(pipe);
2321         temp = I915_READ(reg);
2322         temp &= ~FDI_RX_SYMBOL_LOCK;
2323         temp &= ~FDI_RX_BIT_LOCK;
2324         I915_WRITE(reg, temp);
2325
2326         POSTING_READ(reg);
2327         DELAY(150);
2328
2329         /* enable CPU FDI TX and PCH FDI RX */
2330         reg = FDI_TX_CTL(pipe);
2331         temp = I915_READ(reg);
2332         temp &= ~(7 << 19);
2333         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2334         temp &= ~FDI_LINK_TRAIN_NONE;
2335         temp |= FDI_LINK_TRAIN_PATTERN_1;
2336         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337         /* SNB-B */
2338         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2339         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2340
2341         reg = FDI_RX_CTL(pipe);
2342         temp = I915_READ(reg);
2343         if (HAS_PCH_CPT(dev)) {
2344                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2345                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2346         } else {
2347                 temp &= ~FDI_LINK_TRAIN_NONE;
2348                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2349         }
2350         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352         POSTING_READ(reg);
2353         DELAY(150);
2354
2355         if (HAS_PCH_CPT(dev))
2356                 cpt_phase_pointer_enable(dev, pipe);
2357
2358         for (i = 0; i < 4; i++) {
2359                 reg = FDI_TX_CTL(pipe);
2360                 temp = I915_READ(reg);
2361                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2362                 temp |= snb_b_fdi_train_param[i];
2363                 I915_WRITE(reg, temp);
2364
2365                 POSTING_READ(reg);
2366                 DELAY(500);
2367
2368                 for (retry = 0; retry < 5; retry++) {
2369                         reg = FDI_RX_IIR(pipe);
2370                         temp = I915_READ(reg);
2371                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2372
2373                         if (temp & FDI_RX_BIT_LOCK) {
2374                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2375                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2376                                 break;
2377                         }
2378                         DELAY(50);
2379                 }
2380                 if (retry < 5)
2381                         break;
2382         }
2383         if (i == 4)
2384                 DRM_ERROR("FDI train 1 fail!\n");
2385
2386         /* Train 2 */
2387         reg = FDI_TX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_2;
2391         if (IS_GEN6(dev)) {
2392                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2393                 /* SNB-B */
2394                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2395         }
2396         I915_WRITE(reg, temp);
2397
2398         reg = FDI_RX_CTL(pipe);
2399         temp = I915_READ(reg);
2400         if (HAS_PCH_CPT(dev)) {
2401                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2402                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2403         } else {
2404                 temp &= ~FDI_LINK_TRAIN_NONE;
2405                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2406         }
2407         I915_WRITE(reg, temp);
2408
2409         POSTING_READ(reg);
2410         DELAY(150);
2411
2412         for (i = 0; i < 4; i++) {
2413                 reg = FDI_TX_CTL(pipe);
2414                 temp = I915_READ(reg);
2415                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2416                 temp |= snb_b_fdi_train_param[i];
2417                 I915_WRITE(reg, temp);
2418
2419                 POSTING_READ(reg);
2420                 DELAY(500);
2421
2422                 for (retry = 0; retry < 5; retry++) {
2423                         reg = FDI_RX_IIR(pipe);
2424                         temp = I915_READ(reg);
2425                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2426
2427                         if (temp & FDI_RX_SYMBOL_LOCK) {
2428                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2429                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2430                                 break;
2431                         }
2432                         DELAY(50);
2433                 }
2434                 if (retry < 5)
2435                         break;
2436         }
2437         if (i == 4)
2438                 DRM_ERROR("FDI train 2 fail!\n");
2439
2440         DRM_DEBUG_KMS("FDI train done.\n");
2441 }
2442
2443 /* Manual link training for Ivy Bridge A0 parts */
2444 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2445 {
2446         struct drm_device *dev = crtc->dev;
2447         struct drm_i915_private *dev_priv = dev->dev_private;
2448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2449         int pipe = intel_crtc->pipe;
2450         u32 reg, temp, i;
2451
2452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2453            for train result */
2454         reg = FDI_RX_IMR(pipe);
2455         temp = I915_READ(reg);
2456         temp &= ~FDI_RX_SYMBOL_LOCK;
2457         temp &= ~FDI_RX_BIT_LOCK;
2458         I915_WRITE(reg, temp);
2459
2460         POSTING_READ(reg);
2461         DELAY(150);
2462
2463         /* enable CPU FDI TX and PCH FDI RX */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~(7 << 19);
2467         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2468         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2469         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2470         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2471         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472         temp |= FDI_COMPOSITE_SYNC;
2473         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2474
2475         reg = FDI_RX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         temp &= ~FDI_LINK_TRAIN_AUTO;
2478         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2480         temp |= FDI_COMPOSITE_SYNC;
2481         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2482
2483         POSTING_READ(reg);
2484         DELAY(150);
2485
2486         for (i = 0; i < 4; i++) {
2487                 reg = FDI_TX_CTL(pipe);
2488                 temp = I915_READ(reg);
2489                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2490                 temp |= snb_b_fdi_train_param[i];
2491                 I915_WRITE(reg, temp);
2492
2493                 POSTING_READ(reg);
2494                 DELAY(500);
2495
2496                 reg = FDI_RX_IIR(pipe);
2497                 temp = I915_READ(reg);
2498                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500                 if (temp & FDI_RX_BIT_LOCK ||
2501                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2502                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2503                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2504                         break;
2505                 }
2506         }
2507         if (i == 4)
2508                 DRM_ERROR("FDI train 1 fail!\n");
2509
2510         /* Train 2 */
2511         reg = FDI_TX_CTL(pipe);
2512         temp = I915_READ(reg);
2513         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2514         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2515         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2517         I915_WRITE(reg, temp);
2518
2519         reg = FDI_RX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2522         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2523         I915_WRITE(reg, temp);
2524
2525         POSTING_READ(reg);
2526         DELAY(150);
2527
2528         for (i = 0; i < 4; i++ ) {
2529                 reg = FDI_TX_CTL(pipe);
2530                 temp = I915_READ(reg);
2531                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2532                 temp |= snb_b_fdi_train_param[i];
2533                 I915_WRITE(reg, temp);
2534
2535                 POSTING_READ(reg);
2536                 DELAY(500);
2537
2538                 reg = FDI_RX_IIR(pipe);
2539                 temp = I915_READ(reg);
2540                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541
2542                 if (temp & FDI_RX_SYMBOL_LOCK) {
2543                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2544                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2545                         break;
2546                 }
2547         }
2548         if (i == 4)
2549                 DRM_ERROR("FDI train 2 fail!\n");
2550
2551         DRM_DEBUG_KMS("FDI train done.\n");
2552 }
2553
2554 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         struct drm_i915_private *dev_priv = dev->dev_private;
2558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559         int pipe = intel_crtc->pipe;
2560         u32 reg, temp;
2561
2562         /* Write the TU size bits so error detection works */
2563         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2564                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2565
2566         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2567         reg = FDI_RX_CTL(pipe);
2568         temp = I915_READ(reg);
2569         temp &= ~((0x7 << 19) | (0x7 << 16));
2570         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2571         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2572         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2573
2574         POSTING_READ(reg);
2575         DELAY(200);
2576
2577         /* Switch from Rawclk to PCDclk */
2578         temp = I915_READ(reg);
2579         I915_WRITE(reg, temp | FDI_PCDCLK);
2580
2581         POSTING_READ(reg);
2582         DELAY(200);
2583
2584         /* On Haswell, the PLL configuration for ports and pipes is handled
2585          * separately, as part of DDI setup */
2586         if (!IS_HASWELL(dev)) {
2587                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2588                 reg = FDI_TX_CTL(pipe);
2589                 temp = I915_READ(reg);
2590                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2591                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2592
2593                         POSTING_READ(reg);
2594                         DELAY(100);
2595                 }
2596         }
2597 }
2598
2599 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2600 {
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         u32 flags = I915_READ(SOUTH_CHICKEN1);
2603
2604         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2605         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2606         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2607         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2608         POSTING_READ(SOUTH_CHICKEN1);
2609 }
2610
2611 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2612 {
2613         struct drm_device *dev = crtc->dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616         int pipe = intel_crtc->pipe;
2617         u32 reg, temp;
2618
2619         /* disable CPU FDI tx and PCH FDI rx */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2623         POSTING_READ(reg);
2624
2625         reg = FDI_RX_CTL(pipe);
2626         temp = I915_READ(reg);
2627         temp &= ~(0x7 << 16);
2628         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2629         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2630
2631         POSTING_READ(reg);
2632         DELAY(100);
2633
2634         /* Ironlake workaround, disable clock pointer after downing FDI */
2635         if (HAS_PCH_IBX(dev)) {
2636                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2637                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2638                            I915_READ(FDI_RX_CHICKEN(pipe) &
2639                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2640         } else if (HAS_PCH_CPT(dev)) {
2641                 cpt_phase_pointer_disable(dev, pipe);
2642         }
2643
2644         /* still set train pattern 1 */
2645         reg = FDI_TX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         temp &= ~FDI_LINK_TRAIN_NONE;
2648         temp |= FDI_LINK_TRAIN_PATTERN_1;
2649         I915_WRITE(reg, temp);
2650
2651         reg = FDI_RX_CTL(pipe);
2652         temp = I915_READ(reg);
2653         if (HAS_PCH_CPT(dev)) {
2654                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2655                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2656         } else {
2657                 temp &= ~FDI_LINK_TRAIN_NONE;
2658                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2659         }
2660         /* BPC in FDI rx is consistent with that in PIPECONF */
2661         temp &= ~(0x07 << 16);
2662         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2663         I915_WRITE(reg, temp);
2664
2665         POSTING_READ(reg);
2666         DELAY(100);
2667 }
2668
2669 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2670 {
2671         struct drm_device *dev = crtc->dev;
2672
2673         if (crtc->fb == NULL)
2674                 return;
2675
2676         DRM_LOCK(dev);
2677         intel_finish_fb(crtc->fb);
2678         DRM_UNLOCK(dev);
2679 }
2680
2681 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2682 {
2683         struct drm_device *dev = crtc->dev;
2684         struct drm_mode_config *mode_config = &dev->mode_config;
2685         struct intel_encoder *encoder;
2686
2687         /*
2688          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2689          * must be driven by its own crtc; no sharing is possible.
2690          */
2691         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2692                 if (encoder->base.crtc != crtc)
2693                         continue;
2694
2695                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2696                  * CPU handles all others */
2697                 if (IS_HASWELL(dev)) {
2698                         /* It is still unclear how this will work on PPT, so throw up a warning */
2699                         if (!HAS_PCH_LPT(dev))
2700                                 DRM_DEBUG_KMS("Haswell: PPT\n");
2701
2702                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2703                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2704                                 return true;
2705                         } else {
2706                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2707                                                 encoder->type);
2708                                 return false;
2709                         }
2710                 }
2711
2712                 switch (encoder->type) {
2713                 case INTEL_OUTPUT_EDP:
2714                         if (!intel_encoder_is_pch_edp(&encoder->base))
2715                                 return false;
2716                         continue;
2717                 }
2718         }
2719
2720         return true;
2721 }
2722
2723 /* Program iCLKIP clock to the desired frequency */
2724 static void lpt_program_iclkip(struct drm_crtc *crtc)
2725 {
2726         struct drm_device *dev = crtc->dev;
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2729         u32 temp;
2730
2731         /* It is necessary to ungate the pixclk gate prior to programming
2732          * the divisors, and gate it back when it is done.
2733          */
2734         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2735
2736         /* Disable SSCCTL */
2737         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2738                         intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2739                                 SBI_SSCCTL_DISABLE);
2740
2741         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2742         if (crtc->mode.clock == 20000) {
2743                 auxdiv = 1;
2744                 divsel = 0x41;
2745                 phaseinc = 0x20;
2746         } else {
2747                 /* The iCLK virtual clock root frequency is in MHz,
2748                  * but the crtc->mode.clock in in KHz. To get the divisors,
2749                  * it is necessary to divide one by another, so we
2750                  * convert the virtual clock precision to KHz here for higher
2751                  * precision.
2752                  */
2753                 u32 iclk_virtual_root_freq = 172800 * 1000;
2754                 u32 iclk_pi_range = 64;
2755                 u32 desired_divisor, msb_divisor_value, pi_value;
2756
2757                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2758                 msb_divisor_value = desired_divisor / iclk_pi_range;
2759                 pi_value = desired_divisor % iclk_pi_range;
2760
2761                 auxdiv = 0;
2762                 divsel = msb_divisor_value - 2;
2763                 phaseinc = pi_value;
2764         }
2765
2766         /* This should not happen with any sane values */
2767         if ((SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2768              ~SBI_SSCDIVINTPHASE_DIVSEL_MASK))
2769                 DRM_DEBUG_KMS("DIVSEL_MASK");
2770         if ((SBI_SSCDIVINTPHASE_DIR(phasedir) &
2771              ~SBI_SSCDIVINTPHASE_INCVAL_MASK))
2772                 DRM_DEBUG_KMS("INCVAL_MASK");
2773
2774         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2775                         crtc->mode.clock,
2776                         auxdiv,
2777                         divsel,
2778                         phasedir,
2779                         phaseinc);
2780
2781         /* Program SSCDIVINTPHASE6 */
2782         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2783         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2784         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2785         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2786         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2787         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2788         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2789
2790         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp);
2791
2792         /* Program SSCAUXDIV */
2793         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2794         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2795         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2796         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp);
2797
2798         /* Enable modulator and associated divider */
2799         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2800         temp &= ~SBI_SSCCTL_DISABLE;
2801         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp);
2802
2803         /* Wait for initialization time */
2804         DELAY(24);
2805
2806         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2807 }
2808
2809 /*
2810  * Enable PCH resources required for PCH ports:
2811  *   - PCH PLLs
2812  *   - FDI training & RX/TX
2813  *   - update transcoder timings
2814  *   - DP transcoding bits
2815  *   - transcoder
2816  */
2817 static void ironlake_pch_enable(struct drm_crtc *crtc)
2818 {
2819         struct drm_device *dev = crtc->dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822         int pipe = intel_crtc->pipe;
2823         u32 reg, temp;
2824
2825         assert_transcoder_disabled(dev_priv, pipe);
2826
2827         /* For PCH output, training FDI link */
2828         dev_priv->display.fdi_link_train(crtc);
2829
2830         intel_enable_pch_pll(intel_crtc);
2831
2832         if (HAS_PCH_LPT(dev)) {
2833                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2834                 lpt_program_iclkip(crtc);
2835         } else if (HAS_PCH_CPT(dev)) {
2836                 u32 sel;
2837
2838                 temp = I915_READ(PCH_DPLL_SEL);
2839                 switch (pipe) {
2840                 default:
2841                 case 0:
2842                         temp |= TRANSA_DPLL_ENABLE;
2843                         sel = TRANSA_DPLLB_SEL;
2844                         break;
2845                 case 1:
2846                         temp |= TRANSB_DPLL_ENABLE;
2847                         sel = TRANSB_DPLLB_SEL;
2848                         break;
2849                 case 2:
2850                         temp |= TRANSC_DPLL_ENABLE;
2851                         sel = TRANSC_DPLLB_SEL;
2852                         break;
2853                 }
2854                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2855                         temp |= sel;
2856                 else
2857                         temp &= ~sel;
2858                 I915_WRITE(PCH_DPLL_SEL, temp);
2859         }
2860
2861         /* set transcoder timing, panel must allow it */
2862         assert_panel_unlocked(dev_priv, pipe);
2863         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2864         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2865         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2866
2867         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2868         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2869         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2870         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2871
2872         if (!IS_HASWELL(dev))
2873                 intel_fdi_normal_train(crtc);
2874
2875         /* For PCH DP, enable TRANS_DP_CTL */
2876         if (HAS_PCH_CPT(dev) &&
2877             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2878              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2879                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2880                 reg = TRANS_DP_CTL(pipe);
2881                 temp = I915_READ(reg);
2882                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2883                           TRANS_DP_SYNC_MASK |
2884                           TRANS_DP_BPC_MASK);
2885                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2886                          TRANS_DP_ENH_FRAMING);
2887                 temp |= bpc << 9; /* same format but at 11:9 */
2888
2889                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2890                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2891                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2892                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2893
2894                 switch (intel_trans_dp_port_sel(crtc)) {
2895                 case PCH_DP_B:
2896                         temp |= TRANS_DP_PORT_SEL_B;
2897                         break;
2898                 case PCH_DP_C:
2899                         temp |= TRANS_DP_PORT_SEL_C;
2900                         break;
2901                 case PCH_DP_D:
2902                         temp |= TRANS_DP_PORT_SEL_D;
2903                         break;
2904                 default:
2905                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2906                         temp |= TRANS_DP_PORT_SEL_B;
2907                         break;
2908                 }
2909
2910                 I915_WRITE(reg, temp);
2911         }
2912
2913         intel_enable_transcoder(dev_priv, pipe);
2914 }
2915
2916 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2917 {
2918         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2919
2920         if (pll == NULL)
2921                 return;
2922
2923         if (pll->refcount == 0) {
2924                 printf("bad PCH PLL refcount\n");
2925                 return;
2926         }
2927
2928         --pll->refcount;
2929         intel_crtc->pch_pll = NULL;
2930 }
2931
2932 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2933 {
2934         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2935         struct intel_pch_pll *pll;
2936         int i;
2937
2938         pll = intel_crtc->pch_pll;
2939         if (pll) {
2940                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2941                               intel_crtc->base.base.id, pll->pll_reg);
2942                 goto prepare;
2943         }
2944
2945         if (HAS_PCH_IBX(dev_priv->dev)) {
2946                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2947                 i = intel_crtc->pipe;
2948                 pll = &dev_priv->pch_plls[i];
2949
2950                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2951                               intel_crtc->base.base.id, pll->pll_reg);
2952
2953                 goto found;
2954         }
2955
2956         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2957                 pll = &dev_priv->pch_plls[i];
2958
2959                 /* Only want to check enabled timings first */
2960                 if (pll->refcount == 0)
2961                         continue;
2962
2963                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2964                     fp == I915_READ(pll->fp0_reg)) {
2965                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2966                                       intel_crtc->base.base.id,
2967                                       pll->pll_reg, pll->refcount, pll->active);
2968
2969                         goto found;
2970                 }
2971         }
2972
2973         /* Ok no matching timings, maybe there's a free one? */
2974         for (i = 0; i < dev_priv->num_pch_pll; i++) { /* XXXKIB: HACK */
2975                 pll = &dev_priv->pch_plls[i];
2976                 if (pll->refcount == 0) {
2977                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2978                                       intel_crtc->base.base.id, pll->pll_reg);
2979                         goto found;
2980                 }
2981         }
2982
2983         return NULL;
2984
2985 found:
2986         intel_crtc->pch_pll = pll;
2987         pll->refcount++;
2988         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2989 prepare: /* separate function? */
2990         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2991
2992         /* Wait for the clocks to stabilize before rewriting the regs */
2993         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2994         POSTING_READ(pll->pll_reg);
2995         DELAY(150);
2996
2997         I915_WRITE(pll->fp0_reg, fp);
2998         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2999         pll->on = false;
3000         return pll;
3001 }
3002
3003 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3004 {
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3007         u32 temp;
3008
3009         temp = I915_READ(dslreg);
3010         DELAY(500);
3011         if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1, "915cp1")) {
3012                 /* Without this, mode sets may fail silently on FDI */
3013                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3014                 DELAY(250);
3015                 I915_WRITE(tc2reg, 0);
3016                 if (_intel_wait_for(dev, I915_READ(dslreg) != temp, 5, 1,
3017                     "915cp2"))
3018                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3019         }
3020 }
3021
3022 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         int plane = intel_crtc->plane;
3029         u32 temp;
3030         bool is_pch_port;
3031
3032         if (intel_crtc->active)
3033                 return;
3034
3035         intel_crtc->active = true;
3036         intel_update_watermarks(dev);
3037
3038         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3039                 temp = I915_READ(PCH_LVDS);
3040                 if ((temp & LVDS_PORT_EN) == 0)
3041                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3042         }
3043
3044         is_pch_port = intel_crtc_driving_pch(crtc);
3045
3046         if (is_pch_port) {
3047                 ironlake_fdi_pll_enable(crtc);
3048         } else {
3049                 ironlake_fdi_disable(crtc);
3050         }
3051
3052         /* Enable panel fitting for LVDS */
3053         if (dev_priv->pch_pf_size &&
3054             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3055                 /* Force use of hard-coded filter coefficients
3056                  * as some pre-programmed values are broken,
3057                  * e.g. x201.
3058                  */
3059                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3060                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3061                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3062         }
3063
3064         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3065         intel_enable_plane(dev_priv, plane, pipe);
3066
3067         if (is_pch_port)
3068                 ironlake_pch_enable(crtc);
3069
3070         intel_crtc_load_lut(crtc);
3071
3072         DRM_LOCK(dev);
3073         intel_update_fbc(dev);
3074         DRM_UNLOCK(dev);
3075
3076         intel_crtc_update_cursor(crtc, true);
3077 }
3078
3079 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3080 {
3081         struct drm_device *dev = crtc->dev;
3082         struct drm_i915_private *dev_priv = dev->dev_private;
3083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084         int pipe = intel_crtc->pipe;
3085         int plane = intel_crtc->plane;
3086         u32 reg, temp;
3087
3088         if (!intel_crtc->active)
3089                 return;
3090
3091         intel_crtc_wait_for_pending_flips(crtc);
3092         drm_vblank_off(dev, pipe);
3093         intel_crtc_update_cursor(crtc, false);
3094
3095         intel_disable_plane(dev_priv, plane, pipe);
3096
3097         if (dev_priv->cfb_plane == plane)
3098                 intel_disable_fbc(dev);
3099
3100         intel_disable_pipe(dev_priv, pipe);
3101
3102         /* Disable PF */
3103         I915_WRITE(PF_CTL(pipe), 0);
3104         I915_WRITE(PF_WIN_SZ(pipe), 0);
3105
3106         ironlake_fdi_disable(crtc);
3107
3108         /* This is a horrible layering violation; we should be doing this in
3109          * the connector/encoder ->prepare instead, but we don't always have
3110          * enough information there about the config to know whether it will
3111          * actually be necessary or just cause undesired flicker.
3112          */
3113         intel_disable_pch_ports(dev_priv, pipe);
3114
3115         intel_disable_transcoder(dev_priv, pipe);
3116
3117         if (HAS_PCH_CPT(dev)) {
3118                 /* disable TRANS_DP_CTL */
3119                 reg = TRANS_DP_CTL(pipe);
3120                 temp = I915_READ(reg);
3121                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3122                 temp |= TRANS_DP_PORT_SEL_NONE;
3123                 I915_WRITE(reg, temp);
3124
3125                 /* disable DPLL_SEL */
3126                 temp = I915_READ(PCH_DPLL_SEL);
3127                 switch (pipe) {
3128                 case 0:
3129                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3130                         break;
3131                 case 1:
3132                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3133                         break;
3134                 case 2:
3135                         /* C shares PLL A or B */
3136                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3137                         break;
3138                 default:
3139                         KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
3140                 }
3141                 I915_WRITE(PCH_DPLL_SEL, temp);
3142         }
3143
3144         /* disable PCH DPLL */
3145         intel_disable_pch_pll(intel_crtc);
3146
3147         /* Switch from PCDclk to Rawclk */
3148         reg = FDI_RX_CTL(pipe);
3149         temp = I915_READ(reg);
3150         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3151
3152         /* Disable CPU FDI TX PLL */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3156
3157         POSTING_READ(reg);
3158         DELAY(100);
3159
3160         reg = FDI_RX_CTL(pipe);
3161         temp = I915_READ(reg);
3162         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3163
3164         /* Wait for the clocks to turn off. */
3165         POSTING_READ(reg);
3166         DELAY(100);
3167
3168         intel_crtc->active = false;
3169         intel_update_watermarks(dev);
3170
3171         DRM_LOCK(dev);
3172         intel_update_fbc(dev);
3173         DRM_UNLOCK(dev);
3174 }
3175
3176 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3177 {
3178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179         int pipe = intel_crtc->pipe;
3180         int plane = intel_crtc->plane;
3181
3182         /* XXX: When our outputs are all unaware of DPMS modes other than off
3183          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3184          */
3185         switch (mode) {
3186         case DRM_MODE_DPMS_ON:
3187         case DRM_MODE_DPMS_STANDBY:
3188         case DRM_MODE_DPMS_SUSPEND:
3189                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3190                 ironlake_crtc_enable(crtc);
3191                 break;
3192
3193         case DRM_MODE_DPMS_OFF:
3194                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3195                 ironlake_crtc_disable(crtc);
3196                 break;
3197         }
3198 }
3199
3200 static void ironlake_crtc_off(struct drm_crtc *crtc)
3201 {
3202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203         intel_put_pch_pll(intel_crtc);
3204 }
3205
3206 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3207 {
3208         if (!enable && intel_crtc->overlay) {
3209                 struct drm_device *dev = intel_crtc->base.dev;
3210                 struct drm_i915_private *dev_priv = dev->dev_private;
3211
3212                 DRM_LOCK(dev);
3213                 dev_priv->mm.interruptible = false;
3214                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3215                 dev_priv->mm.interruptible = true;
3216                 DRM_UNLOCK(dev);
3217         }
3218
3219         /* Let userspace switch the overlay on again. In most cases userspace
3220          * has to recompute where to put it anyway.
3221          */
3222 }
3223
3224 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3225 {
3226         struct drm_device *dev = crtc->dev;
3227         struct drm_i915_private *dev_priv = dev->dev_private;
3228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3229         int pipe = intel_crtc->pipe;
3230         int plane = intel_crtc->plane;
3231
3232         if (intel_crtc->active)
3233                 return;
3234
3235         intel_crtc->active = true;
3236         intel_update_watermarks(dev);
3237
3238         intel_enable_pll(dev_priv, pipe);
3239         intel_enable_pipe(dev_priv, pipe, false);
3240         intel_enable_plane(dev_priv, plane, pipe);
3241
3242         intel_crtc_load_lut(crtc);
3243         intel_update_fbc(dev);
3244
3245         /* Give the overlay scaler a chance to enable if it's on this pipe */
3246         intel_crtc_dpms_overlay(intel_crtc, true);
3247         intel_crtc_update_cursor(crtc, true);
3248 }
3249
3250 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3251 {
3252         struct drm_device *dev = crtc->dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255         int pipe = intel_crtc->pipe;
3256         int plane = intel_crtc->plane;
3257
3258         if (!intel_crtc->active)
3259                 return;
3260
3261         /* Give the overlay scaler a chance to disable if it's on this pipe */
3262         intel_crtc_wait_for_pending_flips(crtc);
3263         drm_vblank_off(dev, pipe);
3264         intel_crtc_dpms_overlay(intel_crtc, false);
3265         intel_crtc_update_cursor(crtc, false);
3266
3267         if (dev_priv->cfb_plane == plane)
3268                 intel_disable_fbc(dev);
3269
3270         intel_disable_plane(dev_priv, plane, pipe);
3271         intel_disable_pipe(dev_priv, pipe);
3272         intel_disable_pll(dev_priv, pipe);
3273
3274         intel_crtc->active = false;
3275         intel_update_fbc(dev);
3276         intel_update_watermarks(dev);
3277 }
3278
3279 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3280 {
3281         /* XXX: When our outputs are all unaware of DPMS modes other than off
3282          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3283          */
3284         switch (mode) {
3285         case DRM_MODE_DPMS_ON:
3286         case DRM_MODE_DPMS_STANDBY:
3287         case DRM_MODE_DPMS_SUSPEND:
3288                 i9xx_crtc_enable(crtc);
3289                 break;
3290         case DRM_MODE_DPMS_OFF:
3291                 i9xx_crtc_disable(crtc);
3292                 break;
3293         }
3294 }
3295
3296 static void i9xx_crtc_off(struct drm_crtc *crtc)
3297 {
3298 }
3299
3300 /**
3301  * Sets the power management mode of the pipe and plane.
3302  */
3303 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3304 {
3305         struct drm_device *dev = crtc->dev;
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         struct drm_i915_master_private *master_priv;
3308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309         int pipe = intel_crtc->pipe;
3310         bool enabled;
3311
3312         if (intel_crtc->dpms_mode == mode)
3313                 return;
3314
3315         intel_crtc->dpms_mode = mode;
3316
3317         dev_priv->display.dpms(crtc, mode);
3318
3319         if (!dev->primary->master)
3320                 return;
3321
3322         master_priv = dev->primary->master->driver_priv;
3323         if (!master_priv->sarea_priv)
3324                 return;
3325
3326         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3327
3328         switch (pipe) {
3329         case 0:
3330                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3331                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3332                 break;
3333         case 1:
3334                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3335                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3336                 break;
3337         default:
3338                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3339                 break;
3340         }
3341 }
3342
3343 static void intel_crtc_disable(struct drm_crtc *crtc)
3344 {
3345         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3346         struct drm_device *dev = crtc->dev;
3347         struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3350         dev_priv->display.off(crtc);
3351
3352         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3353         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3354
3355         if (crtc->fb) {
3356                 DRM_LOCK(dev);
3357                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3358                 DRM_UNLOCK(dev);
3359         }
3360 }
3361
3362 /* Prepare for a mode set.
3363  *
3364  * Note we could be a lot smarter here.  We need to figure out which outputs
3365  * will be enabled, which disabled (in short, how the config will changes)
3366  * and perform the minimum necessary steps to accomplish that, e.g. updating
3367  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3368  * panel fitting is in the proper state, etc.
3369  */
3370 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3371 {
3372         i9xx_crtc_disable(crtc);
3373 }
3374
3375 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3376 {
3377         i9xx_crtc_enable(crtc);
3378 }
3379
3380 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3381 {
3382         ironlake_crtc_disable(crtc);
3383 }
3384
3385 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3386 {
3387         ironlake_crtc_enable(crtc);
3388 }
3389
3390 void intel_encoder_prepare(struct drm_encoder *encoder)
3391 {
3392         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3393         /* lvds has its own version of prepare see intel_lvds_prepare */
3394         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3395 }
3396
3397 void intel_encoder_commit(struct drm_encoder *encoder)
3398 {
3399         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3400         struct drm_device *dev = encoder->dev;
3401         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3402
3403         /* lvds has its own version of commit see intel_lvds_commit */
3404         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3405
3406         if (HAS_PCH_CPT(dev))
3407                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3408 }
3409
3410 void intel_encoder_destroy(struct drm_encoder *encoder)
3411 {
3412         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3413
3414         drm_encoder_cleanup(encoder);
3415         free(intel_encoder, DRM_MEM_KMS);
3416 }
3417
3418 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3419                                   const struct drm_display_mode *mode,
3420                                   struct drm_display_mode *adjusted_mode)
3421 {
3422         struct drm_device *dev = crtc->dev;
3423
3424         if (HAS_PCH_SPLIT(dev)) {
3425                 /* FDI link clock is fixed at 2.7G */
3426                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3427                         return false;
3428         }
3429
3430         /* All interlaced capable intel hw wants timings in frames. Note though
3431          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3432          * timings, so we need to be careful not to clobber these.*/
3433         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3434                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3435
3436         return true;
3437 }
3438
3439 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3440 {
3441         return 400000; /* FIXME */
3442 }
3443
3444 static int i945_get_display_clock_speed(struct drm_device *dev)
3445 {
3446         return 400000;
3447 }
3448
3449 static int i915_get_display_clock_speed(struct drm_device *dev)
3450 {
3451         return 333000;
3452 }
3453
3454 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3455 {
3456         return 200000;
3457 }
3458
3459 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3460 {
3461         u16 gcfgc = 0;
3462
3463         gcfgc = pci_read_config(dev->dev, GCFGC, 2);
3464
3465         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3466                 return 133000;
3467         else {
3468                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3469                 case GC_DISPLAY_CLOCK_333_MHZ:
3470                         return 333000;
3471                 default:
3472                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3473                         return 190000;
3474                 }
3475         }
3476 }
3477
3478 static int i865_get_display_clock_speed(struct drm_device *dev)
3479 {
3480         return 266000;
3481 }
3482
3483 static int i855_get_display_clock_speed(struct drm_device *dev)
3484 {
3485         u16 hpllcc = 0;
3486         /* Assume that the hardware is in the high speed state.  This
3487          * should be the default.
3488          */
3489         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3490         case GC_CLOCK_133_200:
3491         case GC_CLOCK_100_200:
3492                 return 200000;
3493         case GC_CLOCK_166_250:
3494                 return 250000;
3495         case GC_CLOCK_100_133:
3496                 return 133000;
3497         }
3498
3499         /* Shouldn't happen */
3500         return 0;
3501 }
3502
3503 static int i830_get_display_clock_speed(struct drm_device *dev)
3504 {
3505         return 133000;
3506 }
3507
3508 struct fdi_m_n {
3509         u32        tu;
3510         u32        gmch_m;
3511         u32        gmch_n;
3512         u32        link_m;
3513         u32        link_n;
3514 };
3515
3516 static void
3517 fdi_reduce_ratio(u32 *num, u32 *den)
3518 {
3519         while (*num > 0xffffff || *den > 0xffffff) {
3520                 *num >>= 1;
3521                 *den >>= 1;
3522         }
3523 }
3524
3525 static void
3526 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3527                      int link_clock, struct fdi_m_n *m_n)
3528 {
3529         m_n->tu = 64; /* default size */
3530
3531         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3532         m_n->gmch_m = bits_per_pixel * pixel_clock;
3533         m_n->gmch_n = link_clock * nlanes * 8;
3534         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3535
3536         m_n->link_m = pixel_clock;
3537         m_n->link_n = link_clock;
3538         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3539 }
3540
3541 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3542 {
3543         if (i915_panel_use_ssc >= 0)
3544                 return i915_panel_use_ssc != 0;
3545         return dev_priv->lvds_use_ssc
3546                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3547 }
3548
3549 /**
3550  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3551  * @crtc: CRTC structure
3552  * @mode: requested mode
3553  *
3554  * A pipe may be connected to one or more outputs.  Based on the depth of the
3555  * attached framebuffer, choose a good color depth to use on the pipe.
3556  *
3557  * If possible, match the pipe depth to the fb depth.  In some cases, this
3558  * isn't ideal, because the connected output supports a lesser or restricted
3559  * set of depths.  Resolve that here:
3560  *    LVDS typically supports only 6bpc, so clamp down in that case
3561  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3562  *    Displays may support a restricted set as well, check EDID and clamp as
3563  *      appropriate.
3564  *    DP may want to dither down to 6bpc to fit larger modes
3565  *
3566  * RETURNS:
3567  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3568  * true if they don't match).
3569  */
3570 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3571                                          unsigned int *pipe_bpp,
3572                                          struct drm_display_mode *mode)
3573 {
3574         struct drm_device *dev = crtc->dev;
3575         struct drm_i915_private *dev_priv = dev->dev_private;
3576         struct drm_encoder *encoder;
3577         struct drm_connector *connector;
3578         unsigned int display_bpc = UINT_MAX, bpc;
3579
3580         /* Walk the encoders & connectors on this crtc, get min bpc */
3581         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3582                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3583
3584                 if (encoder->crtc != crtc)
3585                         continue;
3586
3587                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3588                         unsigned int lvds_bpc;
3589
3590                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3591                             LVDS_A3_POWER_UP)
3592                                 lvds_bpc = 8;
3593                         else
3594                                 lvds_bpc = 6;
3595
3596                         if (lvds_bpc < display_bpc) {
3597                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3598                                 display_bpc = lvds_bpc;
3599                         }
3600                         continue;
3601                 }
3602
3603                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3604                         /* Use VBT settings if we have an eDP panel */
3605                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3606
3607                         if (edp_bpc < display_bpc) {
3608                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3609                                 display_bpc = edp_bpc;
3610                         }
3611                         continue;
3612                 }
3613
3614                 /* Not one of the known troublemakers, check the EDID */
3615                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3616                                     head) {
3617                         if (connector->encoder != encoder)
3618                                 continue;
3619
3620                         /* Don't use an invalid EDID bpc value */
3621                         if (connector->display_info.bpc &&
3622                             connector->display_info.bpc < display_bpc) {
3623                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3624                                 display_bpc = connector->display_info.bpc;
3625                         }
3626                 }
3627
3628                 /*
3629                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3630                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3631                  */
3632                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3633                         if (display_bpc > 8 && display_bpc < 12) {
3634                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3635                                 display_bpc = 12;
3636                         } else {
3637                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3638                                 display_bpc = 8;
3639                         }
3640                 }
3641         }
3642
3643         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3644                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3645                 display_bpc = 6;
3646         }
3647
3648         /*
3649          * We could just drive the pipe at the highest bpc all the time and
3650          * enable dithering as needed, but that costs bandwidth.  So choose
3651          * the minimum value that expresses the full color range of the fb but
3652          * also stays within the max display bpc discovered above.
3653          */
3654
3655         switch (crtc->fb->depth) {
3656         case 8:
3657                 bpc = 8; /* since we go through a colormap */
3658                 break;
3659         case 15:
3660         case 16:
3661                 bpc = 6; /* min is 18bpp */
3662                 break;
3663         case 24:
3664                 bpc = 8;
3665                 break;
3666         case 30:
3667                 bpc = 10;
3668                 break;
3669         case 48:
3670                 bpc = 12;
3671                 break;
3672         default:
3673                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3674                 bpc = min((unsigned int)8, display_bpc);
3675                 break;
3676         }
3677
3678         display_bpc = min(display_bpc, bpc);
3679
3680         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3681                       bpc, display_bpc);
3682
3683         *pipe_bpp = display_bpc * 3;
3684
3685         return display_bpc != bpc;
3686 }
3687
3688 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3689 {
3690         struct drm_device *dev = crtc->dev;
3691         struct drm_i915_private *dev_priv = dev->dev_private;
3692         int refclk;
3693
3694         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3695             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3696                 refclk = dev_priv->lvds_ssc_freq * 1000;
3697                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3698                               refclk / 1000);
3699         } else if (!IS_GEN2(dev)) {
3700                 refclk = 96000;
3701         } else {
3702                 refclk = 48000;
3703         }
3704
3705         return refclk;
3706 }
3707
3708 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3709                                       intel_clock_t *clock)
3710 {
3711         /* SDVO TV has fixed PLL values depend on its clock range,
3712            this mirrors vbios setting. */
3713         if (adjusted_mode->clock >= 100000
3714             && adjusted_mode->clock < 140500) {
3715                 clock->p1 = 2;
3716                 clock->p2 = 10;
3717                 clock->n = 3;
3718                 clock->m1 = 16;
3719                 clock->m2 = 8;
3720         } else if (adjusted_mode->clock >= 140500
3721                    && adjusted_mode->clock <= 200000) {
3722                 clock->p1 = 1;
3723                 clock->p2 = 10;
3724                 clock->n = 6;
3725                 clock->m1 = 12;
3726                 clock->m2 = 8;
3727         }
3728 }
3729
3730 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3731                                      intel_clock_t *clock,
3732                                      intel_clock_t *reduced_clock)
3733 {
3734         struct drm_device *dev = crtc->dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737         int pipe = intel_crtc->pipe;
3738         u32 fp, fp2 = 0;
3739
3740         if (IS_PINEVIEW(dev)) {
3741                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3742                 if (reduced_clock)
3743                         fp2 = (1 << reduced_clock->n) << 16 |
3744                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3745         } else {
3746                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3747                 if (reduced_clock)
3748                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3749                                 reduced_clock->m2;
3750         }
3751
3752         I915_WRITE(FP0(pipe), fp);
3753
3754         intel_crtc->lowfreq_avail = false;
3755         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3756             reduced_clock && i915_powersave) {
3757                 I915_WRITE(FP1(pipe), fp2);
3758                 intel_crtc->lowfreq_avail = true;
3759         } else {
3760                 I915_WRITE(FP1(pipe), fp);
3761         }
3762 }
3763
3764 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3765                               struct drm_display_mode *adjusted_mode)
3766 {
3767         struct drm_device *dev = crtc->dev;
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770         int pipe = intel_crtc->pipe;
3771         u32 temp;
3772
3773         temp = I915_READ(LVDS);
3774         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3775         if (pipe == 1) {
3776                 temp |= LVDS_PIPEB_SELECT;
3777         } else {
3778                 temp &= ~LVDS_PIPEB_SELECT;
3779         }
3780         /* set the corresponsding LVDS_BORDER bit */
3781         temp |= dev_priv->lvds_border_bits;
3782         /* Set the B0-B3 data pairs corresponding to whether we're going to
3783          * set the DPLLs for dual-channel mode or not.
3784          */
3785         if (clock->p2 == 7)
3786                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3787         else
3788                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3789
3790         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3791          * appropriately here, but we need to look more thoroughly into how
3792          * panels behave in the two modes.
3793          */
3794         /* set the dithering flag on LVDS as needed */
3795         if (INTEL_INFO(dev)->gen >= 4) {
3796                 if (dev_priv->lvds_dither)
3797                         temp |= LVDS_ENABLE_DITHER;
3798                 else
3799                         temp &= ~LVDS_ENABLE_DITHER;
3800         }
3801         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3802         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3803                 temp |= LVDS_HSYNC_POLARITY;
3804         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3805                 temp |= LVDS_VSYNC_POLARITY;
3806         I915_WRITE(LVDS, temp);
3807 }
3808
3809 static void i9xx_update_pll(struct drm_crtc *crtc,
3810                             struct drm_display_mode *mode,
3811                             struct drm_display_mode *adjusted_mode,
3812                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3813                             int num_connectors)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818         int pipe = intel_crtc->pipe;
3819         u32 dpll;
3820         bool is_sdvo;
3821
3822         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3823                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3824
3825         dpll = DPLL_VGA_MODE_DIS;
3826
3827         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3828                 dpll |= DPLLB_MODE_LVDS;
3829         else
3830                 dpll |= DPLLB_MODE_DAC_SERIAL;
3831         if (is_sdvo) {
3832                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3833                 if (pixel_multiplier > 1) {
3834                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3835                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3836                 }
3837                 dpll |= DPLL_DVO_HIGH_SPEED;
3838         }
3839         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3840                 dpll |= DPLL_DVO_HIGH_SPEED;
3841
3842         /* compute bitmask from p1 value */
3843         if (IS_PINEVIEW(dev))
3844                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3845         else {
3846                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3847                 if (IS_G4X(dev) && reduced_clock)
3848                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3849         }
3850         switch (clock->p2) {
3851         case 5:
3852                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3853                 break;
3854         case 7:
3855                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3856                 break;
3857         case 10:
3858                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3859                 break;
3860         case 14:
3861                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3862                 break;
3863         }
3864         if (INTEL_INFO(dev)->gen >= 4)
3865                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3866
3867         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3868                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3869         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3870                 /* XXX: just matching BIOS for now */
3871                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3872                 dpll |= 3;
3873         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3874                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3875                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3876         else
3877                 dpll |= PLL_REF_INPUT_DREFCLK;
3878
3879         dpll |= DPLL_VCO_ENABLE;
3880         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3881         POSTING_READ(DPLL(pipe));
3882         DELAY(150);
3883
3884         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3885          * This is an exception to the general rule that mode_set doesn't turn
3886          * things on.
3887          */
3888         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3889                 intel_update_lvds(crtc, clock, adjusted_mode);
3890
3891         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3892                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3893
3894         I915_WRITE(DPLL(pipe), dpll);
3895
3896         /* Wait for the clocks to stabilize. */
3897         POSTING_READ(DPLL(pipe));
3898         DELAY(150);
3899
3900         if (INTEL_INFO(dev)->gen >= 4) {
3901                 u32 temp = 0;
3902                 if (is_sdvo) {
3903                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3904                         if (temp > 1)
3905                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3906                         else
3907                                 temp = 0;
3908                 }
3909                 I915_WRITE(DPLL_MD(pipe), temp);
3910         } else {
3911                 /* The pixel multiplier can only be updated once the
3912                  * DPLL is enabled and the clocks are stable.
3913                  *
3914                  * So write it again.
3915                  */
3916                 I915_WRITE(DPLL(pipe), dpll);
3917         }
3918 }
3919
3920 static void i8xx_update_pll(struct drm_crtc *crtc,
3921                             struct drm_display_mode *adjusted_mode,
3922                             intel_clock_t *clock,
3923                             int num_connectors)
3924 {
3925         struct drm_device *dev = crtc->dev;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928         int pipe = intel_crtc->pipe;
3929         u32 dpll;
3930
3931         dpll = DPLL_VGA_MODE_DIS;
3932
3933         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3934                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3935         } else {
3936                 if (clock->p1 == 2)
3937                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3938                 else
3939                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3940                 if (clock->p2 == 4)
3941                         dpll |= PLL_P2_DIVIDE_BY_4;
3942         }
3943
3944         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3945                 /* XXX: just matching BIOS for now */
3946                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3947                 dpll |= 3;
3948         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3949                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3950                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3951         else
3952                 dpll |= PLL_REF_INPUT_DREFCLK;
3953
3954         dpll |= DPLL_VCO_ENABLE;
3955         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3956         POSTING_READ(DPLL(pipe));
3957         DELAY(150);
3958
3959         I915_WRITE(DPLL(pipe), dpll);
3960
3961         /* Wait for the clocks to stabilize. */
3962         POSTING_READ(DPLL(pipe));
3963         DELAY(150);
3964
3965         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3966          * This is an exception to the general rule that mode_set doesn't turn
3967          * things on.
3968          */
3969         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3970                 intel_update_lvds(crtc, clock, adjusted_mode);
3971
3972         /* The pixel multiplier can only be updated once the
3973          * DPLL is enabled and the clocks are stable.
3974          *
3975          * So write it again.
3976          */
3977         I915_WRITE(DPLL(pipe), dpll);
3978 }
3979
3980 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3981                               struct drm_display_mode *mode,
3982                               struct drm_display_mode *adjusted_mode,
3983                               int x, int y,
3984                               struct drm_framebuffer *old_fb)
3985 {
3986         struct drm_device *dev = crtc->dev;
3987         struct drm_i915_private *dev_priv = dev->dev_private;
3988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3989         int pipe = intel_crtc->pipe;
3990         int plane = intel_crtc->plane;
3991         int refclk, num_connectors = 0;
3992         intel_clock_t clock, reduced_clock;
3993         u32 dspcntr, pipeconf, vsyncshift;
3994         bool ok, has_reduced_clock = false, is_sdvo = false;
3995         bool is_lvds = false, is_tv = false, is_dp = false;
3996         struct drm_mode_config *mode_config = &dev->mode_config;
3997         struct intel_encoder *encoder;
3998         const intel_limit_t *limit;
3999         int ret;
4000
4001         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4002                 if (encoder->base.crtc != crtc)
4003                         continue;
4004
4005                 switch (encoder->type) {
4006                 case INTEL_OUTPUT_LVDS:
4007                         is_lvds = true;
4008                         break;
4009                 case INTEL_OUTPUT_SDVO:
4010                 case INTEL_OUTPUT_HDMI:
4011                         is_sdvo = true;
4012                         if (encoder->needs_tv_clock)
4013                                 is_tv = true;
4014                         break;
4015                 case INTEL_OUTPUT_TVOUT:
4016                         is_tv = true;
4017                         break;
4018                 case INTEL_OUTPUT_DISPLAYPORT:
4019                         is_dp = true;
4020                         break;
4021                 }
4022
4023                 num_connectors++;
4024         }
4025
4026         refclk = i9xx_get_refclk(crtc, num_connectors);
4027
4028         /*
4029          * Returns a set of divisors for the desired target clock with the given
4030          * refclk, or false.  The returned values represent the clock equation:
4031          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4032          */
4033         limit = intel_limit(crtc, refclk);
4034         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4035                              &clock);
4036         if (!ok) {
4037                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4038                 return -EINVAL;
4039         }
4040
4041         /* Ensure that the cursor is valid for the new mode before changing... */
4042         intel_crtc_update_cursor(crtc, true);
4043
4044         if (is_lvds && dev_priv->lvds_downclock_avail) {
4045                 /*
4046                  * Ensure we match the reduced clock's P to the target clock.
4047                  * If the clocks don't match, we can't switch the display clock
4048                  * by using the FP0/FP1. In such case we will disable the LVDS
4049                  * downclock feature.
4050                 */
4051                 has_reduced_clock = limit->find_pll(limit, crtc,
4052                                                     dev_priv->lvds_downclock,
4053                                                     refclk,
4054                                                     &clock,
4055                                                     &reduced_clock);
4056         }
4057
4058         if (is_sdvo && is_tv)
4059                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4060
4061         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4062                                  &reduced_clock : NULL);
4063
4064         if (IS_GEN2(dev))
4065                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4066         else
4067                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4068                                 has_reduced_clock ? &reduced_clock : NULL,
4069                                 num_connectors);
4070
4071         /* setup pipeconf */
4072         pipeconf = I915_READ(PIPECONF(pipe));
4073
4074         /* Set up the display plane register */
4075         dspcntr = DISPPLANE_GAMMA_ENABLE;
4076
4077         if (pipe == 0)
4078                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4079         else
4080                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4081
4082         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4083                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4084                  * core speed.
4085                  *
4086                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4087                  * pipe == 0 check?
4088                  */
4089                 if (mode->clock >
4090                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4091                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4092                 else
4093                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4094         }
4095
4096         /* default to 8bpc */
4097         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4098         if (is_dp) {
4099                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4100                         pipeconf |= PIPECONF_BPP_6 |
4101                                     PIPECONF_DITHER_EN |
4102                                     PIPECONF_DITHER_TYPE_SP;
4103                 }
4104         }
4105
4106         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4107         drm_mode_debug_printmodeline(mode);
4108
4109         if (HAS_PIPE_CXSR(dev)) {
4110                 if (intel_crtc->lowfreq_avail) {
4111                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4112                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4113                 } else {
4114                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4115                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4116                 }
4117         }
4118
4119         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4120         if (!IS_GEN2(dev) &&
4121             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4122                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4123                 /* the chip adds 2 halflines automatically */
4124                 adjusted_mode->crtc_vtotal -= 1;
4125                 adjusted_mode->crtc_vblank_end -= 1;
4126                 vsyncshift = adjusted_mode->crtc_hsync_start
4127                              - adjusted_mode->crtc_htotal/2;
4128         } else {
4129                 pipeconf |= PIPECONF_PROGRESSIVE;
4130                 vsyncshift = 0;
4131         }
4132
4133         if (!IS_GEN3(dev))
4134                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4135
4136         I915_WRITE(HTOTAL(pipe),
4137                    (adjusted_mode->crtc_hdisplay - 1) |
4138                    ((adjusted_mode->crtc_htotal - 1) << 16));
4139         I915_WRITE(HBLANK(pipe),
4140                    (adjusted_mode->crtc_hblank_start - 1) |
4141                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4142         I915_WRITE(HSYNC(pipe),
4143                    (adjusted_mode->crtc_hsync_start - 1) |
4144                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4145
4146         I915_WRITE(VTOTAL(pipe),
4147                    (adjusted_mode->crtc_vdisplay - 1) |
4148                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4149         I915_WRITE(VBLANK(pipe),
4150                    (adjusted_mode->crtc_vblank_start - 1) |
4151                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4152         I915_WRITE(VSYNC(pipe),
4153                    (adjusted_mode->crtc_vsync_start - 1) |
4154                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4155
4156         /* pipesrc and dspsize control the size that is scaled from,
4157          * which should always be the user's requested size.
4158          */
4159         I915_WRITE(DSPSIZE(plane),
4160                    ((mode->vdisplay - 1) << 16) |
4161                    (mode->hdisplay - 1));
4162         I915_WRITE(DSPPOS(plane), 0);
4163         I915_WRITE(PIPESRC(pipe),
4164                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4165
4166         I915_WRITE(PIPECONF(pipe), pipeconf);
4167         POSTING_READ(PIPECONF(pipe));
4168         intel_enable_pipe(dev_priv, pipe, false);
4169
4170         intel_wait_for_vblank(dev, pipe);
4171
4172         I915_WRITE(DSPCNTR(plane), dspcntr);
4173         POSTING_READ(DSPCNTR(plane));
4174
4175         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4176
4177         intel_update_watermarks(dev);
4178
4179         return ret;
4180 }
4181
4182 /*
4183  * Initialize reference clocks when the driver loads
4184  */
4185 void ironlake_init_pch_refclk(struct drm_device *dev)
4186 {
4187         struct drm_i915_private *dev_priv = dev->dev_private;
4188         struct drm_mode_config *mode_config = &dev->mode_config;
4189         struct intel_encoder *encoder;
4190         u32 temp;
4191         bool has_lvds = false;
4192         bool has_cpu_edp = false;
4193         bool has_pch_edp = false;
4194         bool has_panel = false;
4195         bool has_ck505 = false;
4196         bool can_ssc = false;
4197
4198         /* We need to take the global config into account */
4199         list_for_each_entry(encoder, &mode_config->encoder_list,
4200                             base.head) {
4201                 switch (encoder->type) {
4202                 case INTEL_OUTPUT_LVDS:
4203                         has_panel = true;
4204                         has_lvds = true;
4205                         break;
4206                 case INTEL_OUTPUT_EDP:
4207                         has_panel = true;
4208                         if (intel_encoder_is_pch_edp(&encoder->base))
4209                                 has_pch_edp = true;
4210                         else
4211                                 has_cpu_edp = true;
4212                         break;
4213                 }
4214         }
4215
4216         if (HAS_PCH_IBX(dev)) {
4217                 has_ck505 = dev_priv->display_clock_mode;
4218                 can_ssc = has_ck505;
4219         } else {
4220                 has_ck505 = false;
4221                 can_ssc = true;
4222         }
4223
4224         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4225                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4226                       has_ck505);
4227
4228         /* Ironlake: try to setup display ref clock before DPLL
4229          * enabling. This is only under driver's control after
4230          * PCH B stepping, previous chipset stepping should be
4231          * ignoring this setting.
4232          */
4233         temp = I915_READ(PCH_DREF_CONTROL);
4234         /* Always enable nonspread source */
4235         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4236
4237         if (has_ck505)
4238                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4239         else
4240                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4241
4242         if (has_panel) {
4243                 temp &= ~DREF_SSC_SOURCE_MASK;
4244                 temp |= DREF_SSC_SOURCE_ENABLE;
4245
4246                 /* SSC must be turned on before enabling the CPU output  */
4247                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4248                         DRM_DEBUG_KMS("Using SSC on panel\n");
4249                         temp |= DREF_SSC1_ENABLE;
4250                 } else
4251                         temp &= ~DREF_SSC1_ENABLE;
4252
4253                 /* Get SSC going before enabling the outputs */
4254                 I915_WRITE(PCH_DREF_CONTROL, temp);
4255                 POSTING_READ(PCH_DREF_CONTROL);
4256                 DELAY(200);
4257
4258                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4259
4260                 /* Enable CPU source on CPU attached eDP */
4261                 if (has_cpu_edp) {
4262                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4263                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4264                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4265                         }
4266                         else
4267                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4268                 } else
4269                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4270
4271                 I915_WRITE(PCH_DREF_CONTROL, temp);
4272                 POSTING_READ(PCH_DREF_CONTROL);
4273                 DELAY(200);
4274         } else {
4275                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4276
4277                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4278
4279                 /* Turn off CPU output */
4280                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4281
4282                 I915_WRITE(PCH_DREF_CONTROL, temp);
4283                 POSTING_READ(PCH_DREF_CONTROL);
4284                 DELAY(200);
4285
4286                 /* Turn off the SSC source */
4287                 temp &= ~DREF_SSC_SOURCE_MASK;
4288                 temp |= DREF_SSC_SOURCE_DISABLE;
4289
4290                 /* Turn off SSC1 */
4291                 temp &= ~ DREF_SSC1_ENABLE;
4292
4293                 I915_WRITE(PCH_DREF_CONTROL, temp);
4294                 POSTING_READ(PCH_DREF_CONTROL);
4295                 DELAY(200);
4296         }
4297 }
4298
4299 static int ironlake_get_refclk(struct drm_crtc *crtc)
4300 {
4301         struct drm_device *dev = crtc->dev;
4302         struct drm_i915_private *dev_priv = dev->dev_private;
4303         struct intel_encoder *encoder;
4304         struct drm_mode_config *mode_config = &dev->mode_config;
4305         struct intel_encoder *edp_encoder = NULL;
4306         int num_connectors = 0;
4307         bool is_lvds = false;
4308
4309         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4310                 if (encoder->base.crtc != crtc)
4311                         continue;
4312
4313                 switch (encoder->type) {
4314                 case INTEL_OUTPUT_LVDS:
4315                         is_lvds = true;
4316                         break;
4317                 case INTEL_OUTPUT_EDP:
4318                         edp_encoder = encoder;
4319                         break;
4320                 }
4321                 num_connectors++;
4322         }
4323
4324         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4325                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4326                               dev_priv->lvds_ssc_freq);
4327                 return dev_priv->lvds_ssc_freq * 1000;
4328         }
4329
4330         return 120000;
4331 }
4332
4333 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4334                                   struct drm_display_mode *mode,
4335                                   struct drm_display_mode *adjusted_mode,
4336                                   int x, int y,
4337                                   struct drm_framebuffer *old_fb)
4338 {
4339         struct drm_device *dev = crtc->dev;
4340         struct drm_i915_private *dev_priv = dev->dev_private;
4341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4342         int pipe = intel_crtc->pipe;
4343         int plane = intel_crtc->plane;
4344         int refclk, num_connectors = 0;
4345         intel_clock_t clock, reduced_clock;
4346         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4347         bool ok, has_reduced_clock = false, is_sdvo = false;
4348         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4349         struct drm_mode_config *mode_config = &dev->mode_config;
4350         struct intel_encoder *encoder, *edp_encoder = NULL;
4351         const intel_limit_t *limit;
4352         int ret;
4353         struct fdi_m_n m_n = {0};
4354         u32 temp;
4355         int target_clock, pixel_multiplier, lane, link_bw, factor;
4356         unsigned int pipe_bpp;
4357         bool dither;
4358         bool is_cpu_edp = false, is_pch_edp = false;
4359
4360         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4361                 if (encoder->base.crtc != crtc)
4362                         continue;
4363
4364                 switch (encoder->type) {
4365                 case INTEL_OUTPUT_LVDS:
4366                         is_lvds = true;
4367                         break;
4368                 case INTEL_OUTPUT_SDVO:
4369                 case INTEL_OUTPUT_HDMI:
4370                         is_sdvo = true;
4371                         if (encoder->needs_tv_clock)
4372                                 is_tv = true;
4373                         break;
4374                 case INTEL_OUTPUT_TVOUT:
4375                         is_tv = true;
4376                         break;
4377                 case INTEL_OUTPUT_ANALOG:
4378                         is_crt = true;
4379                         break;
4380                 case INTEL_OUTPUT_DISPLAYPORT:
4381                         is_dp = true;
4382                         break;
4383                 case INTEL_OUTPUT_EDP:
4384                         is_dp = true;
4385                         if (intel_encoder_is_pch_edp(&encoder->base))
4386                                 is_pch_edp = true;
4387                         else
4388                                 is_cpu_edp = true;
4389                         edp_encoder = encoder;
4390                         break;
4391                 }
4392
4393                 num_connectors++;
4394         }
4395
4396         refclk = ironlake_get_refclk(crtc);
4397
4398         /*
4399          * Returns a set of divisors for the desired target clock with the given
4400          * refclk, or false.  The returned values represent the clock equation:
4401          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4402          */
4403         limit = intel_limit(crtc, refclk);
4404         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4405                              &clock);
4406         if (!ok) {
4407                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4408                 return -EINVAL;
4409         }
4410
4411         /* Ensure that the cursor is valid for the new mode before changing... */
4412         intel_crtc_update_cursor(crtc, true);
4413
4414         if (is_lvds && dev_priv->lvds_downclock_avail) {
4415                 /*
4416                  * Ensure we match the reduced clock's P to the target clock.
4417                  * If the clocks don't match, we can't switch the display clock
4418                  * by using the FP0/FP1. In such case we will disable the LVDS
4419                  * downclock feature.
4420                 */
4421                 has_reduced_clock = limit->find_pll(limit, crtc,
4422                                                     dev_priv->lvds_downclock,
4423                                                     refclk,
4424                                                     &clock,
4425                                                     &reduced_clock);
4426         }
4427         /* SDVO TV has fixed PLL values depend on its clock range,
4428            this mirrors vbios setting. */
4429         if (is_sdvo && is_tv) {
4430                 if (adjusted_mode->clock >= 100000
4431                     && adjusted_mode->clock < 140500) {
4432                         clock.p1 = 2;
4433                         clock.p2 = 10;
4434                         clock.n = 3;
4435                         clock.m1 = 16;
4436                         clock.m2 = 8;
4437                 } else if (adjusted_mode->clock >= 140500
4438                            && adjusted_mode->clock <= 200000) {
4439                         clock.p1 = 1;
4440                         clock.p2 = 10;
4441                         clock.n = 6;
4442                         clock.m1 = 12;
4443                         clock.m2 = 8;
4444                 }
4445         }
4446
4447         /* FDI link */
4448         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4449         lane = 0;
4450         /* CPU eDP doesn't require FDI link, so just set DP M/N
4451            according to current link config */
4452         if (is_cpu_edp) {
4453                 target_clock = mode->clock;
4454                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4455         } else {
4456                 /* [e]DP over FDI requires target mode clock
4457                    instead of link clock */
4458                 if (is_dp)
4459                         target_clock = mode->clock;
4460                 else
4461                         target_clock = adjusted_mode->clock;
4462
4463                 /* FDI is a binary signal running at ~2.7GHz, encoding
4464                  * each output octet as 10 bits. The actual frequency
4465                  * is stored as a divider into a 100MHz clock, and the
4466                  * mode pixel clock is stored in units of 1KHz.
4467                  * Hence the bw of each lane in terms of the mode signal
4468                  * is:
4469                  */
4470                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4471         }
4472
4473         /* determine panel color depth */
4474         temp = I915_READ(PIPECONF(pipe));
4475         temp &= ~PIPE_BPC_MASK;
4476         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4477         switch (pipe_bpp) {
4478         case 18:
4479                 temp |= PIPE_6BPC;
4480                 break;
4481         case 24:
4482                 temp |= PIPE_8BPC;
4483                 break;
4484         case 30:
4485                 temp |= PIPE_10BPC;
4486                 break;
4487         case 36:
4488                 temp |= PIPE_12BPC;
4489                 break;
4490         default:
4491                 printf("intel_choose_pipe_bpp returned invalid value %d\n",
4492                         pipe_bpp);
4493                 temp |= PIPE_8BPC;
4494                 pipe_bpp = 24;
4495                 break;
4496         }
4497
4498         intel_crtc->bpp = pipe_bpp;
4499         I915_WRITE(PIPECONF(pipe), temp);
4500
4501         if (!lane) {
4502                 /*
4503                  * Account for spread spectrum to avoid
4504                  * oversubscribing the link. Max center spread
4505                  * is 2.5%; use 5% for safety's sake.
4506                  */
4507                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4508                 lane = bps / (link_bw * 8) + 1;
4509         }
4510
4511         intel_crtc->fdi_lanes = lane;
4512
4513         if (pixel_multiplier > 1)
4514                 link_bw *= pixel_multiplier;
4515         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4516                              &m_n);
4517
4518         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4519         if (has_reduced_clock)
4520                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4521                         reduced_clock.m2;
4522
4523         /* Enable autotuning of the PLL clock (if permissible) */
4524         factor = 21;
4525         if (is_lvds) {
4526                 if ((intel_panel_use_ssc(dev_priv) &&
4527                      dev_priv->lvds_ssc_freq == 100) ||
4528                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4529                         factor = 25;
4530         } else if (is_sdvo && is_tv)
4531                 factor = 20;
4532
4533         if (clock.m < factor * clock.n)
4534                 fp |= FP_CB_TUNE;
4535
4536         dpll = 0;
4537
4538         if (is_lvds)
4539                 dpll |= DPLLB_MODE_LVDS;
4540         else
4541                 dpll |= DPLLB_MODE_DAC_SERIAL;
4542         if (is_sdvo) {
4543                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4544                 if (pixel_multiplier > 1) {
4545                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4546                 }
4547                 dpll |= DPLL_DVO_HIGH_SPEED;
4548         }
4549         if (is_dp && !is_cpu_edp)
4550                 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552         /* compute bitmask from p1 value */
4553         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4554         /* also FPA1 */
4555         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4556
4557         switch (clock.p2) {
4558         case 5:
4559                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4560                 break;
4561         case 7:
4562                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4563                 break;
4564         case 10:
4565                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4566                 break;
4567         case 14:
4568                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4569                 break;
4570         }
4571
4572         if (is_sdvo && is_tv)
4573                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4574         else if (is_tv)
4575                 /* XXX: just matching BIOS for now */
4576                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4577                 dpll |= 3;
4578         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4579                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4580         else
4581                 dpll |= PLL_REF_INPUT_DREFCLK;
4582
4583         /* setup pipeconf */
4584         pipeconf = I915_READ(PIPECONF(pipe));
4585
4586         /* Set up the display plane register */
4587         dspcntr = DISPPLANE_GAMMA_ENABLE;
4588         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4589         drm_mode_debug_printmodeline(mode);
4590
4591         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4592          * pre-Haswell/LPT generation */
4593         if (HAS_PCH_LPT(dev)) {
4594                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4595                                 pipe);
4596         } else if (!is_cpu_edp) {
4597                 struct intel_pch_pll *pll;
4598
4599                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4600                 if (pll == NULL) {
4601                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4602                                          pipe);
4603                         return -EINVAL;
4604                 }
4605         } else
4606                 intel_put_pch_pll(intel_crtc);
4607
4608         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4609          * This is an exception to the general rule that mode_set doesn't turn
4610          * things on.
4611          */
4612         if (is_lvds) {
4613                 temp = I915_READ(PCH_LVDS);
4614                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4615                 if (HAS_PCH_CPT(dev)) {
4616                         temp &= ~PORT_TRANS_SEL_MASK;
4617                         temp |= PORT_TRANS_SEL_CPT(pipe);
4618                 } else {
4619                         if (pipe == 1)
4620                                 temp |= LVDS_PIPEB_SELECT;
4621                         else
4622                                 temp &= ~LVDS_PIPEB_SELECT;
4623                 }
4624
4625                 /* set the corresponsding LVDS_BORDER bit */
4626                 temp |= dev_priv->lvds_border_bits;
4627                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4628                  * set the DPLLs for dual-channel mode or not.
4629                  */
4630                 if (clock.p2 == 7)
4631                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4632                 else
4633                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4634
4635                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4636                  * appropriately here, but we need to look more thoroughly into how
4637                  * panels behave in the two modes.
4638                  */
4639                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4640                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4641                         temp |= LVDS_HSYNC_POLARITY;
4642                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4643                         temp |= LVDS_VSYNC_POLARITY;
4644                 I915_WRITE(PCH_LVDS, temp);
4645         }
4646
4647         pipeconf &= ~PIPECONF_DITHER_EN;
4648         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4649         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4650                 pipeconf |= PIPECONF_DITHER_EN;
4651                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4652         }
4653         if (is_dp && !is_cpu_edp) {
4654                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4655         } else {
4656                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4657                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4658                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4659                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4660                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4661         }
4662
4663         if (intel_crtc->pch_pll) {
4664                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4665
4666                 /* Wait for the clocks to stabilize. */
4667                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4668                 DELAY(150);
4669
4670                 /* The pixel multiplier can only be updated once the
4671                  * DPLL is enabled and the clocks are stable.
4672                  *
4673                  * So write it again.
4674                  */
4675                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4676         }
4677
4678         intel_crtc->lowfreq_avail = false;
4679         if (intel_crtc->pch_pll) {
4680                 if (is_lvds && has_reduced_clock && i915_powersave) {
4681                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4682                         intel_crtc->lowfreq_avail = true;
4683                         if (HAS_PIPE_CXSR(dev)) {
4684                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4685                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4686                         }
4687                 } else {
4688                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4689                         if (HAS_PIPE_CXSR(dev)) {
4690                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4691                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4692                         }
4693                 }
4694         }
4695
4696         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4697         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4698                 pipeconf |= PIPECONF_INTERLACED_ILK;
4699                 /* the chip adds 2 halflines automatically */
4700                 adjusted_mode->crtc_vtotal -= 1;
4701                 adjusted_mode->crtc_vblank_end -= 1;
4702                 I915_WRITE(VSYNCSHIFT(pipe),
4703                            adjusted_mode->crtc_hsync_start
4704                            - adjusted_mode->crtc_htotal/2);
4705         } else {
4706                 pipeconf |= PIPECONF_PROGRESSIVE;
4707                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4708         }
4709
4710         I915_WRITE(HTOTAL(pipe),
4711                    (adjusted_mode->crtc_hdisplay - 1) |
4712                    ((adjusted_mode->crtc_htotal - 1) << 16));
4713         I915_WRITE(HBLANK(pipe),
4714                    (adjusted_mode->crtc_hblank_start - 1) |
4715                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4716         I915_WRITE(HSYNC(pipe),
4717                    (adjusted_mode->crtc_hsync_start - 1) |
4718                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4719
4720         I915_WRITE(VTOTAL(pipe),
4721                    (adjusted_mode->crtc_vdisplay - 1) |
4722                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4723         I915_WRITE(VBLANK(pipe),
4724                    (adjusted_mode->crtc_vblank_start - 1) |
4725                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4726         I915_WRITE(VSYNC(pipe),
4727                    (adjusted_mode->crtc_vsync_start - 1) |
4728                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4729
4730         /* pipesrc controls the size that is scaled from, which should
4731          * always be the user's requested size.
4732          */
4733         I915_WRITE(PIPESRC(pipe),
4734                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4735
4736         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4737         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4738         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4739         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4740
4741         if (is_cpu_edp)
4742                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4743
4744         I915_WRITE(PIPECONF(pipe), pipeconf);
4745         POSTING_READ(PIPECONF(pipe));
4746
4747         intel_wait_for_vblank(dev, pipe);
4748
4749         I915_WRITE(DSPCNTR(plane), dspcntr);
4750         POSTING_READ(DSPCNTR(plane));
4751
4752         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4753
4754         intel_update_watermarks(dev);
4755
4756         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4757
4758         return ret;
4759 }
4760
4761 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4762                                struct drm_display_mode *mode,
4763                                struct drm_display_mode *adjusted_mode,
4764                                int x, int y,
4765                                struct drm_framebuffer *old_fb)
4766 {
4767         struct drm_device *dev = crtc->dev;
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770         int pipe = intel_crtc->pipe;
4771         int ret;
4772
4773         drm_vblank_pre_modeset(dev, pipe);
4774
4775         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4776                                               x, y, old_fb);
4777         drm_vblank_post_modeset(dev, pipe);
4778
4779         if (ret)
4780                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4781         else
4782                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4783
4784         return ret;
4785 }
4786
4787 static bool intel_eld_uptodate(struct drm_connector *connector,
4788                                int reg_eldv, uint32_t bits_eldv,
4789                                int reg_elda, uint32_t bits_elda,
4790                                int reg_edid)
4791 {
4792         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4793         uint8_t *eld = connector->eld;
4794         uint32_t i;
4795
4796         i = I915_READ(reg_eldv);
4797         i &= bits_eldv;
4798
4799         if (!eld[0])
4800                 return !i;
4801
4802         if (!i)
4803                 return false;
4804
4805         i = I915_READ(reg_elda);
4806         i &= ~bits_elda;
4807         I915_WRITE(reg_elda, i);
4808
4809         for (i = 0; i < eld[2]; i++)
4810                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4811                         return false;
4812
4813         return true;
4814 }
4815
4816 static void g4x_write_eld(struct drm_connector *connector,
4817                           struct drm_crtc *crtc)
4818 {
4819         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4820         uint8_t *eld = connector->eld;
4821         uint32_t eldv;
4822         uint32_t len;
4823         uint32_t i;
4824
4825         i = I915_READ(G4X_AUD_VID_DID);
4826
4827         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4828                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4829         else
4830                 eldv = G4X_ELDV_DEVCTG;
4831
4832         if (intel_eld_uptodate(connector,
4833                                G4X_AUD_CNTL_ST, eldv,
4834                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4835                                G4X_HDMIW_HDMIEDID))
4836                 return;
4837
4838         i = I915_READ(G4X_AUD_CNTL_ST);
4839         i &= ~(eldv | G4X_ELD_ADDR);
4840         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4841         I915_WRITE(G4X_AUD_CNTL_ST, i);
4842
4843         if (!eld[0])
4844                 return;
4845
4846         if (eld[2] < (uint8_t)len)
4847                 len = eld[2];
4848         DRM_DEBUG_KMS("ELD size %d\n", len);
4849         for (i = 0; i < len; i++)
4850                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4851
4852         i = I915_READ(G4X_AUD_CNTL_ST);
4853         i |= eldv;
4854         I915_WRITE(G4X_AUD_CNTL_ST, i);
4855 }
4856
4857 static void ironlake_write_eld(struct drm_connector *connector,
4858                                      struct drm_crtc *crtc)
4859 {
4860         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4861         uint8_t *eld = connector->eld;
4862         uint32_t eldv;
4863         uint32_t i;
4864         int len;
4865         int hdmiw_hdmiedid;
4866         int aud_config;
4867         int aud_cntl_st;
4868         int aud_cntrl_st2;
4869
4870         if (HAS_PCH_IBX(connector->dev)) {
4871                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4872                 aud_config = IBX_AUD_CONFIG_A;
4873                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4874                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4875         } else {
4876                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4877                 aud_config = CPT_AUD_CONFIG_A;
4878                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4879                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4880         }
4881
4882         i = to_intel_crtc(crtc)->pipe;
4883         hdmiw_hdmiedid += i * 0x100;
4884         aud_cntl_st += i * 0x100;
4885         aud_config += i * 0x100;
4886
4887         DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
4888
4889         i = I915_READ(aud_cntl_st);
4890         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4891         if (!i) {
4892                 DRM_DEBUG_KMS("Audio directed to unknown port\n");
4893                 /* operate blindly on all ports */
4894                 eldv = IBX_ELD_VALIDB;
4895                 eldv |= IBX_ELD_VALIDB << 4;
4896                 eldv |= IBX_ELD_VALIDB << 8;
4897         } else {
4898                 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
4899                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4900         }
4901
4902         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4903                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4904                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4905                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4906         } else
4907                 I915_WRITE(aud_config, 0);
4908
4909         if (intel_eld_uptodate(connector,
4910                                aud_cntrl_st2, eldv,
4911                                aud_cntl_st, IBX_ELD_ADDRESS,
4912                                hdmiw_hdmiedid))
4913                 return;
4914
4915         i = I915_READ(aud_cntrl_st2);
4916         i &= ~eldv;
4917         I915_WRITE(aud_cntrl_st2, i);
4918
4919         if (!eld[0])
4920                 return;
4921
4922         i = I915_READ(aud_cntl_st);
4923         i &= ~IBX_ELD_ADDRESS;
4924         I915_WRITE(aud_cntl_st, i);
4925
4926         /* 84 bytes of hw ELD buffer */
4927         len = 21;
4928         if (eld[2] < (uint8_t)len)
4929                 len = eld[2];
4930         DRM_DEBUG_KMS("ELD size %d\n", len);
4931         for (i = 0; i < len; i++)
4932                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4933
4934         i = I915_READ(aud_cntrl_st2);
4935         i |= eldv;
4936         I915_WRITE(aud_cntrl_st2, i);
4937 }
4938
4939 void intel_write_eld(struct drm_encoder *encoder,
4940                      struct drm_display_mode *mode)
4941 {
4942         struct drm_crtc *crtc = encoder->crtc;
4943         struct drm_connector *connector;
4944         struct drm_device *dev = encoder->dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946
4947         connector = drm_select_eld(encoder, mode);
4948         if (!connector)
4949                 return;
4950
4951         DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4952                          connector->base.id,
4953                          drm_get_connector_name(connector),
4954                          connector->encoder->base.id,
4955                          drm_get_encoder_name(connector->encoder));
4956
4957         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4958
4959         if (dev_priv->display.write_eld)
4960                 dev_priv->display.write_eld(connector, crtc);
4961 }
4962
4963 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4964 void intel_crtc_load_lut(struct drm_crtc *crtc)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969         int palreg = PALETTE(intel_crtc->pipe);
4970         int i;
4971
4972         /* The clocks have to be on to load the palette. */
4973         if (!crtc->enabled || !intel_crtc->active)
4974                 return;
4975
4976         /* use legacy palette for Ironlake */
4977         if (HAS_PCH_SPLIT(dev))
4978                 palreg = LGC_PALETTE(intel_crtc->pipe);
4979
4980         for (i = 0; i < 256; i++) {
4981                 I915_WRITE(palreg + 4 * i,
4982                            (intel_crtc->lut_r[i] << 16) |
4983                            (intel_crtc->lut_g[i] << 8) |
4984                            intel_crtc->lut_b[i]);
4985         }
4986 }
4987
4988 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4989 {
4990         struct drm_device *dev = crtc->dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993         bool visible = base != 0;
4994         u32 cntl;
4995
4996         if (intel_crtc->cursor_visible == visible)
4997                 return;
4998
4999         cntl = I915_READ(_CURACNTR);
5000         if (visible) {
5001                 /* On these chipsets we can only modify the base whilst
5002                  * the cursor is disabled.
5003                  */
5004                 I915_WRITE(_CURABASE, base);
5005
5006                 cntl &= ~(CURSOR_FORMAT_MASK);
5007                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5008                 cntl |= CURSOR_ENABLE |
5009                         CURSOR_GAMMA_ENABLE |
5010                         CURSOR_FORMAT_ARGB;
5011         } else
5012                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5013         I915_WRITE(_CURACNTR, cntl);
5014
5015         intel_crtc->cursor_visible = visible;
5016 }
5017
5018 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5019 {
5020         struct drm_device *dev = crtc->dev;
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023         int pipe = intel_crtc->pipe;
5024         bool visible = base != 0;
5025
5026         if (intel_crtc->cursor_visible != visible) {
5027                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5028                 if (base) {
5029                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5030                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5031                         cntl |= pipe << 28; /* Connect to correct pipe */
5032                 } else {
5033                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5034                         cntl |= CURSOR_MODE_DISABLE;
5035                 }
5036                 I915_WRITE(CURCNTR(pipe), cntl);
5037
5038                 intel_crtc->cursor_visible = visible;
5039         }
5040         /* and commit changes on next vblank */
5041         I915_WRITE(CURBASE(pipe), base);
5042 }
5043
5044 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5045 {
5046         struct drm_device *dev = crtc->dev;
5047         struct drm_i915_private *dev_priv = dev->dev_private;
5048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049         int pipe = intel_crtc->pipe;
5050         bool visible = base != 0;
5051
5052         if (intel_crtc->cursor_visible != visible) {
5053                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5054                 if (base) {
5055                         cntl &= ~CURSOR_MODE;
5056                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5057                 } else {
5058                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5059                         cntl |= CURSOR_MODE_DISABLE;
5060                 }
5061                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5062
5063                 intel_crtc->cursor_visible = visible;
5064         }
5065         /* and commit changes on next vblank */
5066         I915_WRITE(CURBASE_IVB(pipe), base);
5067 }
5068
5069 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5070 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5071                                      bool on)
5072 {
5073         struct drm_device *dev = crtc->dev;
5074         struct drm_i915_private *dev_priv = dev->dev_private;
5075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5076         int pipe = intel_crtc->pipe;
5077         int x = intel_crtc->cursor_x;
5078         int y = intel_crtc->cursor_y;
5079         u32 base, pos;
5080         bool visible;
5081
5082         pos = 0;
5083
5084         if (on && crtc->enabled && crtc->fb) {
5085                 base = intel_crtc->cursor_addr;
5086                 if (x > (int) crtc->fb->width)
5087                         base = 0;
5088
5089                 if (y > (int) crtc->fb->height)
5090                         base = 0;
5091         } else
5092                 base = 0;
5093
5094         if (x < 0) {
5095                 if (x + intel_crtc->cursor_width < 0)
5096                         base = 0;
5097
5098                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5099                 x = -x;
5100         }
5101         pos |= x << CURSOR_X_SHIFT;
5102
5103         if (y < 0) {
5104                 if (y + intel_crtc->cursor_height < 0)
5105                         base = 0;
5106
5107                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5108                 y = -y;
5109         }
5110         pos |= y << CURSOR_Y_SHIFT;
5111
5112         visible = base != 0;
5113         if (!visible && !intel_crtc->cursor_visible)
5114                 return;
5115
5116         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5117                 I915_WRITE(CURPOS_IVB(pipe), pos);
5118                 ivb_update_cursor(crtc, base);
5119         } else {
5120                 I915_WRITE(CURPOS(pipe), pos);
5121                 if (IS_845G(dev) || IS_I865G(dev))
5122                         i845_update_cursor(crtc, base);
5123                 else
5124                         i9xx_update_cursor(crtc, base);
5125         }
5126 }
5127
5128 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5129                                  struct drm_file *file,
5130                                  uint32_t handle,
5131                                  uint32_t width, uint32_t height)
5132 {
5133         struct drm_device *dev = crtc->dev;
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136         struct drm_i915_gem_object *obj;
5137         uint32_t addr;
5138         int ret;
5139
5140         DRM_DEBUG_KMS("\n");
5141
5142         /* if we want to turn off the cursor ignore width and height */
5143         if (!handle) {
5144                 DRM_DEBUG_KMS("cursor off\n");
5145                 addr = 0;
5146                 obj = NULL;
5147                 DRM_LOCK(dev);
5148                 goto finish;
5149         }
5150
5151         /* Currently we only support 64x64 cursors */
5152         if (width != 64 || height != 64) {
5153                 DRM_ERROR("we currently only support 64x64 cursors\n");
5154                 return -EINVAL;
5155         }
5156
5157         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5158         if (&obj->base == NULL)
5159                 return -ENOENT;
5160
5161         if (obj->base.size < width * height * 4) {
5162                 DRM_ERROR("buffer is to small\n");
5163                 ret = -ENOMEM;
5164                 goto fail;
5165         }
5166
5167         /* we only need to pin inside GTT if cursor is non-phy */
5168         DRM_LOCK(dev);
5169         if (!dev_priv->info->cursor_needs_physical) {
5170                 if (obj->tiling_mode) {
5171                         DRM_ERROR("cursor cannot be tiled\n");
5172                         ret = -EINVAL;
5173                         goto fail_locked;
5174                 }
5175
5176                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5177                 if (ret) {
5178                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5179                         goto fail_locked;
5180                 }
5181
5182                 ret = i915_gem_object_put_fence(obj);
5183                 if (ret) {
5184                         DRM_ERROR("failed to release fence for cursor\n");
5185                         goto fail_unpin;
5186                 }
5187
5188                 addr = obj->gtt_offset;
5189         } else {
5190                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5191                 ret = i915_gem_attach_phys_object(dev, obj,
5192                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5193                                                   align);
5194                 if (ret) {
5195                         DRM_ERROR("failed to attach phys object\n");
5196                         goto fail_locked;
5197                 }
5198                 addr = obj->phys_obj->handle->busaddr;
5199         }
5200
5201         if (IS_GEN2(dev))
5202                 I915_WRITE(CURSIZE, (height << 12) | width);
5203
5204  finish:
5205         if (intel_crtc->cursor_bo) {
5206                 if (dev_priv->info->cursor_needs_physical) {
5207                         if (intel_crtc->cursor_bo != obj)
5208                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5209                 } else
5210                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
5211                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5212         }
5213
5214         DRM_UNLOCK(dev);
5215
5216         intel_crtc->cursor_addr = addr;
5217         intel_crtc->cursor_bo = obj;
5218         intel_crtc->cursor_width = width;
5219         intel_crtc->cursor_height = height;
5220
5221         intel_crtc_update_cursor(crtc, true);
5222
5223         return 0;
5224 fail_unpin:
5225         i915_gem_object_unpin_from_display_plane(obj);
5226 fail_locked:
5227         DRM_UNLOCK(dev);
5228 fail:
5229         drm_gem_object_unreference_unlocked(&obj->base);
5230         return ret;
5231 }
5232
5233 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5234 {
5235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236
5237         intel_crtc->cursor_x = x;
5238         intel_crtc->cursor_y = y;
5239
5240         intel_crtc_update_cursor(crtc, true);
5241
5242         return 0;
5243 }
5244
5245 /** Sets the color ramps on behalf of RandR */
5246 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5247                                  u16 blue, int regno)
5248 {
5249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5250
5251         intel_crtc->lut_r[regno] = red >> 8;
5252         intel_crtc->lut_g[regno] = green >> 8;
5253         intel_crtc->lut_b[regno] = blue >> 8;
5254 }
5255
5256 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5257                              u16 *blue, int regno)
5258 {
5259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5260
5261         *red = intel_crtc->lut_r[regno] << 8;
5262         *green = intel_crtc->lut_g[regno] << 8;
5263         *blue = intel_crtc->lut_b[regno] << 8;
5264 }
5265
5266 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5267                                  u16 *blue, uint32_t start, uint32_t size)
5268 {
5269         int end = (start + size > 256) ? 256 : start + size, i;
5270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5271
5272         for (i = start; i < end; i++) {
5273                 intel_crtc->lut_r[i] = red[i] >> 8;
5274                 intel_crtc->lut_g[i] = green[i] >> 8;
5275                 intel_crtc->lut_b[i] = blue[i] >> 8;
5276         }
5277
5278         intel_crtc_load_lut(crtc);
5279 }
5280
5281 /**
5282  * Get a pipe with a simple mode set on it for doing load-based monitor
5283  * detection.
5284  *
5285  * It will be up to the load-detect code to adjust the pipe as appropriate for
5286  * its requirements.  The pipe will be connected to no other encoders.
5287  *
5288  * Currently this code will only succeed if there is a pipe with no encoders
5289  * configured for it.  In the future, it could choose to temporarily disable
5290  * some outputs to free up a pipe for its use.
5291  *
5292  * \return crtc, or NULL if no pipes are available.
5293  */
5294
5295 /* VESA 640x480x72Hz mode to set on the pipe */
5296 static struct drm_display_mode load_detect_mode = {
5297         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5298                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5299 };
5300
5301 static int
5302 intel_framebuffer_create(struct drm_device *dev,
5303                          struct drm_mode_fb_cmd2 *mode_cmd,
5304                          struct drm_i915_gem_object *obj,
5305                          struct drm_framebuffer **res)
5306 {
5307         struct intel_framebuffer *intel_fb;
5308         int ret;
5309
5310         intel_fb = malloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5311         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5312         if (ret) {
5313                 drm_gem_object_unreference_unlocked(&obj->base);
5314                 free(intel_fb, DRM_MEM_KMS);
5315                 return ret;
5316         }
5317
5318         *res = &intel_fb->base;
5319         return 0;
5320 }
5321
5322 static u32
5323 intel_framebuffer_pitch_for_width(int width, int bpp)
5324 {
5325         u32 pitch = howmany(width * bpp, 8);
5326         return roundup2(pitch, 64);
5327 }
5328
5329 static u32
5330 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5331 {
5332         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5333         return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
5334 }
5335
5336 static int
5337 intel_framebuffer_create_for_mode(struct drm_device *dev,
5338                                   struct drm_display_mode *mode,
5339                                   int depth, int bpp,
5340                                   struct drm_framebuffer **res)
5341 {
5342         struct drm_i915_gem_object *obj;
5343         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
5344
5345         obj = i915_gem_alloc_object(dev,
5346                                     intel_framebuffer_size_for_mode(mode, bpp));
5347         if (obj == NULL)
5348                 return -ENOMEM;
5349
5350         mode_cmd.width = mode->hdisplay;
5351         mode_cmd.height = mode->vdisplay;
5352         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5353                                                                 bpp);
5354         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5355
5356         return intel_framebuffer_create(dev, &mode_cmd, obj, res);
5357 }
5358
5359 static int
5360 mode_fits_in_fbdev(struct drm_device *dev,
5361                    struct drm_display_mode *mode,
5362                    struct drm_framebuffer **res)
5363 {
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365         struct drm_i915_gem_object *obj;
5366         struct drm_framebuffer *fb;
5367
5368         if (dev_priv->fbdev == NULL) {
5369                 *res = NULL;
5370                 return 0;
5371         }
5372
5373         obj = dev_priv->fbdev->ifb.obj;
5374         if (obj == NULL) {
5375                 *res = NULL;
5376                 return 0;
5377         }
5378
5379         fb = &dev_priv->fbdev->ifb.base;
5380         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5381             fb->bits_per_pixel)) {
5382                 *res = NULL;
5383                 return 0;
5384         }
5385
5386         if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
5387                 *res = NULL;
5388                 return 0;
5389         }
5390
5391         *res = fb;
5392         return 0;
5393 }
5394
5395 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5396                                 struct drm_connector *connector,
5397                                 struct drm_display_mode *mode,
5398                                 struct intel_load_detect_pipe *old)
5399 {
5400         struct intel_crtc *intel_crtc;
5401         struct drm_crtc *possible_crtc;
5402         struct drm_encoder *encoder = &intel_encoder->base;
5403         struct drm_crtc *crtc = NULL;
5404         struct drm_device *dev = encoder->dev;
5405         struct drm_framebuffer *old_fb;
5406         int i = -1;
5407         int ret;
5408
5409         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5410                       connector->base.id, drm_get_connector_name(connector),
5411                       encoder->base.id, drm_get_encoder_name(encoder));
5412
5413         /*
5414          * Algorithm gets a little messy:
5415          *
5416          *   - if the connector already has an assigned crtc, use it (but make
5417          *     sure it's on first)
5418          *
5419          *   - try to find the first unused crtc that can drive this connector,
5420          *     and use that if we find one
5421          */
5422
5423         /* See if we already have a CRTC for this connector */
5424         if (encoder->crtc) {
5425                 crtc = encoder->crtc;
5426
5427                 intel_crtc = to_intel_crtc(crtc);
5428                 old->dpms_mode = intel_crtc->dpms_mode;
5429                 old->load_detect_temp = false;
5430
5431                 /* Make sure the crtc and connector are running */
5432                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5433                         struct drm_encoder_helper_funcs *encoder_funcs;
5434                         struct drm_crtc_helper_funcs *crtc_funcs;
5435
5436                         crtc_funcs = crtc->helper_private;
5437                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5438
5439                         encoder_funcs = encoder->helper_private;
5440                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5441                 }
5442
5443                 return true;
5444         }
5445
5446         /* Find an unused one (if possible) */
5447         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5448                 i++;
5449                 if (!(encoder->possible_crtcs & (1 << i)))
5450                         continue;
5451                 if (!possible_crtc->enabled) {
5452                         crtc = possible_crtc;
5453                         break;
5454                 }
5455         }
5456
5457         /*
5458          * If we didn't find an unused CRTC, don't use any.
5459          */
5460         if (!crtc) {
5461                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5462                 return false;
5463         }
5464
5465         encoder->crtc = crtc;
5466         connector->encoder = encoder;
5467
5468         intel_crtc = to_intel_crtc(crtc);
5469         old->dpms_mode = intel_crtc->dpms_mode;
5470         old->load_detect_temp = true;
5471         old->release_fb = NULL;
5472
5473         if (!mode)
5474                 mode = &load_detect_mode;
5475
5476         old_fb = crtc->fb;
5477
5478         /* We need a framebuffer large enough to accommodate all accesses
5479          * that the plane may generate whilst we perform load detection.
5480          * We can not rely on the fbcon either being present (we get called
5481          * during its initialisation to detect all boot displays, or it may
5482          * not even exist) or that it is large enough to satisfy the
5483          * requested mode.
5484          */
5485         ret = mode_fits_in_fbdev(dev, mode, &crtc->fb);
5486         if (crtc->fb == NULL) {
5487                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5488                 ret = intel_framebuffer_create_for_mode(dev, mode, 24, 32,
5489                     &crtc->fb);
5490                 old->release_fb = crtc->fb;
5491         } else
5492                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5493         if (ret) {
5494                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5495                 crtc->fb = old_fb;
5496                 return false;
5497         }
5498
5499         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5500                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5501                 if (old->release_fb)
5502                         old->release_fb->funcs->destroy(old->release_fb);
5503                 crtc->fb = old_fb;
5504                 return false;
5505         }
5506
5507         /* let the connector get through one full cycle before testing */
5508         intel_wait_for_vblank(dev, intel_crtc->pipe);
5509         return true;
5510 }
5511
5512 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5513                                     struct drm_connector *connector,
5514                                     struct intel_load_detect_pipe *old)
5515 {
5516         struct drm_encoder *encoder = &intel_encoder->base;
5517         struct drm_device *dev = encoder->dev;
5518         struct drm_crtc *crtc = encoder->crtc;
5519         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5520         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5521
5522         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5523                       connector->base.id, drm_get_connector_name(connector),
5524                       encoder->base.id, drm_get_encoder_name(encoder));
5525
5526         if (old->load_detect_temp) {
5527                 connector->encoder = NULL;
5528                 drm_helper_disable_unused_functions(dev);
5529
5530                 if (old->release_fb)
5531                         old->release_fb->funcs->destroy(old->release_fb);
5532
5533                 return;
5534         }
5535
5536         /* Switch crtc and encoder back off if necessary */
5537         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5538                 encoder_funcs->dpms(encoder, old->dpms_mode);
5539                 crtc_funcs->dpms(crtc, old->dpms_mode);
5540         }
5541 }
5542
5543 /* Returns the clock of the currently programmed mode of the given pipe. */
5544 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5545 {
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5548         int pipe = intel_crtc->pipe;
5549         u32 dpll = I915_READ(DPLL(pipe));
5550         u32 fp;
5551         intel_clock_t clock;
5552
5553         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5554                 fp = I915_READ(FP0(pipe));
5555         else
5556                 fp = I915_READ(FP1(pipe));
5557
5558         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5559         if (IS_PINEVIEW(dev)) {
5560                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5561                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5562         } else {
5563                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5564                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5565         }
5566
5567         if (!IS_GEN2(dev)) {
5568                 if (IS_PINEVIEW(dev))
5569                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5570                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5571                 else
5572                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5573                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5574
5575                 switch (dpll & DPLL_MODE_MASK) {
5576                 case DPLLB_MODE_DAC_SERIAL:
5577                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5578                                 5 : 10;
5579                         break;
5580                 case DPLLB_MODE_LVDS:
5581                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5582                                 7 : 14;
5583                         break;
5584                 default:
5585                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5586                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5587                         return 0;
5588                 }
5589
5590                 /* XXX: Handle the 100Mhz refclk */
5591                 intel_clock(dev, 96000, &clock);
5592         } else {
5593                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5594
5595                 if (is_lvds) {
5596                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5597                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5598                         clock.p2 = 14;
5599
5600                         if ((dpll & PLL_REF_INPUT_MASK) ==
5601                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5602                                 /* XXX: might not be 66MHz */
5603                                 intel_clock(dev, 66000, &clock);
5604                         } else
5605                                 intel_clock(dev, 48000, &clock);
5606                 } else {
5607                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5608                                 clock.p1 = 2;
5609                         else {
5610                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5611                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5612                         }
5613                         if (dpll & PLL_P2_DIVIDE_BY_4)
5614                                 clock.p2 = 4;
5615                         else
5616                                 clock.p2 = 2;
5617
5618                         intel_clock(dev, 48000, &clock);
5619                 }
5620         }
5621
5622         /* XXX: It would be nice to validate the clocks, but we can't reuse
5623          * i830PllIsValid() because it relies on the xf86_config connector
5624          * configuration being accurate, which it isn't necessarily.
5625          */
5626
5627         return clock.dot;
5628 }
5629
5630 /** Returns the currently programmed mode of the given pipe. */
5631 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5632                                              struct drm_crtc *crtc)
5633 {
5634         struct drm_i915_private *dev_priv = dev->dev_private;
5635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636         int pipe = intel_crtc->pipe;
5637         struct drm_display_mode *mode;
5638         int htot = I915_READ(HTOTAL(pipe));
5639         int hsync = I915_READ(HSYNC(pipe));
5640         int vtot = I915_READ(VTOTAL(pipe));
5641         int vsync = I915_READ(VSYNC(pipe));
5642
5643         mode = malloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5644
5645         mode->clock = intel_crtc_clock_get(dev, crtc);
5646         mode->hdisplay = (htot & 0xffff) + 1;
5647         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5648         mode->hsync_start = (hsync & 0xffff) + 1;
5649         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5650         mode->vdisplay = (vtot & 0xffff) + 1;
5651         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5652         mode->vsync_start = (vsync & 0xffff) + 1;
5653         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5654
5655         drm_mode_set_name(mode);
5656
5657         return mode;
5658 }
5659
5660 #define GPU_IDLE_TIMEOUT (500 /* ms */ * 1000 / hz)
5661
5662 /* When this timer fires, we've been idle for awhile */
5663 static void intel_gpu_idle_timer(void *arg)
5664 {
5665         struct drm_device *dev = arg;
5666         drm_i915_private_t *dev_priv = dev->dev_private;
5667
5668         if (!list_empty(&dev_priv->mm.active_list)) {
5669                 /* Still processing requests, so just re-arm the timer. */
5670                 callout_schedule(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT);
5671                 return;
5672         }
5673
5674         dev_priv->busy = false;
5675         taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
5676 }
5677
5678 #define CRTC_IDLE_TIMEOUT (1000 /* ms */ * 1000 / hz)
5679
5680 static void intel_crtc_idle_timer(void *arg)
5681 {
5682         struct intel_crtc *intel_crtc = arg;
5683         struct drm_crtc *crtc = &intel_crtc->base;
5684         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5685         struct intel_framebuffer *intel_fb;
5686
5687         intel_fb = to_intel_framebuffer(crtc->fb);
5688         if (intel_fb && intel_fb->obj->active) {
5689                 /* The framebuffer is still being accessed by the GPU. */
5690                 callout_schedule(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT);
5691                 return;
5692         }
5693
5694         intel_crtc->busy = false;
5695         taskqueue_enqueue(dev_priv->tq, &dev_priv->idle_task);
5696 }
5697
5698 static void intel_increase_pllclock(struct drm_crtc *crtc)
5699 {
5700         struct drm_device *dev = crtc->dev;
5701         drm_i915_private_t *dev_priv = dev->dev_private;
5702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703         int pipe = intel_crtc->pipe;
5704         int dpll_reg = DPLL(pipe);
5705         int dpll;
5706
5707         if (HAS_PCH_SPLIT(dev))
5708                 return;
5709
5710         if (!dev_priv->lvds_downclock_avail)
5711                 return;
5712
5713         dpll = I915_READ(dpll_reg);
5714         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5715                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5716
5717                 assert_panel_unlocked(dev_priv, pipe);
5718
5719                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5720                 I915_WRITE(dpll_reg, dpll);
5721                 intel_wait_for_vblank(dev, pipe);
5722
5723                 dpll = I915_READ(dpll_reg);
5724                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5725                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5726         }
5727
5728         /* Schedule downclock */
5729         callout_reset(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT,
5730             intel_crtc_idle_timer, intel_crtc);
5731 }
5732
5733 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5734 {
5735         struct drm_device *dev = crtc->dev;
5736         drm_i915_private_t *dev_priv = dev->dev_private;
5737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5738
5739         if (HAS_PCH_SPLIT(dev))
5740                 return;
5741
5742         if (!dev_priv->lvds_downclock_avail)
5743                 return;
5744
5745         /*
5746          * Since this is called by a timer, we should never get here in
5747          * the manual case.
5748          */
5749         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5750                 int pipe = intel_crtc->pipe;
5751                 int dpll_reg = DPLL(pipe);
5752                 int dpll;
5753
5754                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5755
5756                 assert_panel_unlocked(dev_priv, pipe);
5757
5758                 dpll = I915_READ(dpll_reg);
5759                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5760                 I915_WRITE(dpll_reg, dpll);
5761                 intel_wait_for_vblank(dev, pipe);
5762                 dpll = I915_READ(dpll_reg);
5763                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5764                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5765         }
5766
5767 }
5768
5769 /**
5770  * intel_idle_update - adjust clocks for idleness
5771  * @work: work struct
5772  *
5773  * Either the GPU or display (or both) went idle.  Check the busy status
5774  * here and adjust the CRTC and GPU clocks as necessary.
5775  */
5776 static void intel_idle_update(void *arg, int pending)
5777 {
5778         drm_i915_private_t *dev_priv = arg;
5779         struct drm_device *dev = dev_priv->dev;
5780         struct drm_crtc *crtc;
5781         struct intel_crtc *intel_crtc;
5782
5783         if (!i915_powersave)
5784                 return;
5785
5786         DRM_LOCK(dev);
5787
5788         i915_update_gfx_val(dev_priv);
5789
5790         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5791                 /* Skip inactive CRTCs */
5792                 if (!crtc->fb)
5793                         continue;
5794
5795                 intel_crtc = to_intel_crtc(crtc);
5796                 if (!intel_crtc->busy)
5797                         intel_decrease_pllclock(crtc);
5798         }
5799
5800         DRM_UNLOCK(dev);
5801 }
5802
5803 /**
5804  * intel_mark_busy - mark the GPU and possibly the display busy
5805  * @dev: drm device
5806  * @obj: object we're operating on
5807  *
5808  * Callers can use this function to indicate that the GPU is busy processing
5809  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5810  * buffer), we'll also mark the display as busy, so we know to increase its
5811  * clock frequency.
5812  */
5813 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5814 {
5815         drm_i915_private_t *dev_priv = dev->dev_private;
5816         struct drm_crtc *crtc = NULL;
5817         struct intel_framebuffer *intel_fb;
5818         struct intel_crtc *intel_crtc;
5819
5820         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5821                 return;
5822
5823         if (!dev_priv->busy) {
5824                 intel_sanitize_pm(dev);
5825                 dev_priv->busy = true;
5826         } else
5827                 callout_reset(&dev_priv->idle_callout, GPU_IDLE_TIMEOUT,
5828                     intel_gpu_idle_timer, dev);
5829
5830         if (obj == NULL)
5831                 return;
5832
5833         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5834                 if (!crtc->fb)
5835                         continue;
5836
5837                 intel_crtc = to_intel_crtc(crtc);
5838                 intel_fb = to_intel_framebuffer(crtc->fb);
5839                 if (intel_fb->obj == obj) {
5840                         if (!intel_crtc->busy) {
5841                                 /* Non-busy -> busy, upclock */
5842                                 intel_increase_pllclock(crtc);
5843                                 intel_crtc->busy = true;
5844                         } else {
5845                                 /* Busy -> busy, put off timer */
5846                                 callout_reset(&intel_crtc->idle_callout,
5847                                     CRTC_IDLE_TIMEOUT, intel_crtc_idle_timer,
5848                                     intel_crtc);
5849                         }
5850                 }
5851         }
5852 }
5853
5854 static void intel_crtc_destroy(struct drm_crtc *crtc)
5855 {
5856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5857         struct drm_device *dev = crtc->dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859         struct intel_unpin_work *work;
5860
5861         mtx_lock(&dev->event_lock);
5862         work = intel_crtc->unpin_work;
5863         intel_crtc->unpin_work = NULL;
5864         mtx_unlock(&dev->event_lock);
5865
5866         if (work) {
5867                 taskqueue_cancel(dev_priv->tq, &work->task, NULL);
5868                 taskqueue_drain(dev_priv->tq, &work->task);
5869                 free(work, DRM_MEM_KMS);
5870         }
5871
5872         drm_crtc_cleanup(crtc);
5873
5874         free(intel_crtc, DRM_MEM_KMS);
5875 }
5876
5877 static void intel_unpin_work_fn(void *arg, int pending)
5878 {
5879         struct intel_unpin_work *work =
5880                 arg;
5881         struct drm_device *dev = work->dev;
5882
5883         DRM_LOCK(dev);
5884         intel_unpin_fb_obj(work->old_fb_obj);
5885         drm_gem_object_unreference(&work->pending_flip_obj->base);
5886         drm_gem_object_unreference(&work->old_fb_obj->base);
5887
5888         intel_update_fbc(dev);
5889         DRM_UNLOCK(dev);
5890         free(work, DRM_MEM_KMS);
5891 }
5892
5893 static void do_intel_finish_page_flip(struct drm_device *dev,
5894                                       struct drm_crtc *crtc)
5895 {
5896         drm_i915_private_t *dev_priv = dev->dev_private;
5897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898         struct intel_unpin_work *work;
5899         struct drm_i915_gem_object *obj;
5900         struct drm_pending_vblank_event *e;
5901         struct timeval tnow, tvbl;
5902
5903         /* Ignore early vblank irqs */
5904         if (intel_crtc == NULL)
5905                 return;
5906
5907         microtime(&tnow);
5908
5909         mtx_lock(&dev->event_lock);
5910         work = intel_crtc->unpin_work;
5911         if (work == NULL || !work->pending) {
5912                 mtx_unlock(&dev->event_lock);
5913                 return;
5914         }
5915
5916         intel_crtc->unpin_work = NULL;
5917
5918         if (work->event) {
5919                 e = work->event;
5920                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5921
5922                 /* Called before vblank count and timestamps have
5923                  * been updated for the vblank interval of flip
5924                  * completion? Need to increment vblank count and
5925                  * add one videorefresh duration to returned timestamp
5926                  * to account for this. We assume this happened if we
5927                  * get called over 0.9 frame durations after the last
5928                  * timestamped vblank.
5929                  *
5930                  * This calculation can not be used with vrefresh rates
5931                  * below 5Hz (10Hz to be on the safe side) without
5932                  * promoting to 64 integers.
5933                  */
5934                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5935                     9 * crtc->framedur_ns) {
5936                         e->event.sequence++;
5937                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5938                                              crtc->framedur_ns);
5939                 }
5940
5941                 e->event.tv_sec = tvbl.tv_sec;
5942                 e->event.tv_usec = tvbl.tv_usec;
5943
5944                 list_add_tail(&e->base.link,
5945                               &e->base.file_priv->event_list);
5946                 drm_event_wakeup(&e->base);
5947         }
5948
5949         drm_vblank_put(dev, intel_crtc->pipe);
5950
5951         obj = work->old_fb_obj;
5952
5953         atomic_clear_int(&obj->pending_flip, 1 << intel_crtc->plane);
5954         if (atomic_load_acq_int(&obj->pending_flip) == 0)
5955                 wakeup(&obj->pending_flip);
5956         mtx_unlock(&dev->event_lock);
5957
5958         taskqueue_enqueue(dev_priv->tq, &work->task);
5959
5960         CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
5961             work->pending_flip_obj);
5962 }
5963
5964 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5965 {
5966         drm_i915_private_t *dev_priv = dev->dev_private;
5967         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5968
5969         do_intel_finish_page_flip(dev, crtc);
5970 }
5971
5972 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5973 {
5974         drm_i915_private_t *dev_priv = dev->dev_private;
5975         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5976
5977         do_intel_finish_page_flip(dev, crtc);
5978 }
5979
5980 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5981 {
5982         drm_i915_private_t *dev_priv = dev->dev_private;
5983         struct intel_crtc *intel_crtc =
5984                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5985
5986         mtx_lock(&dev->event_lock);
5987         if (intel_crtc->unpin_work) {
5988                 if ((++intel_crtc->unpin_work->pending) > 1)
5989                         DRM_ERROR("Prepared flip multiple times\n");
5990         } else {
5991                 DRM_DEBUG("preparing flip with no unpin work?\n");
5992         }
5993         mtx_unlock(&dev->event_lock);
5994 }
5995
5996 static int intel_gen2_queue_flip(struct drm_device *dev,
5997                                  struct drm_crtc *crtc,
5998                                  struct drm_framebuffer *fb,
5999                                  struct drm_i915_gem_object *obj)
6000 {
6001         struct drm_i915_private *dev_priv = dev->dev_private;
6002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003         unsigned long offset;
6004         u32 flip_mask;
6005         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6006         int ret;
6007
6008         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6009         if (ret)
6010                 goto err;
6011
6012         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6013         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6014
6015         ret = intel_ring_begin(ring, 6);
6016         if (ret)
6017                 goto err_unpin;
6018
6019         /* Can't queue multiple flips, so wait for the previous
6020          * one to finish before executing the next.
6021          */
6022         if (intel_crtc->plane)
6023                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6024         else
6025                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6026         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6027         intel_ring_emit(ring, MI_NOOP);
6028         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6029                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6030         intel_ring_emit(ring, fb->pitches[0]);
6031         intel_ring_emit(ring, obj->gtt_offset + offset);
6032         intel_ring_emit(ring, 0); /* aux display base address, unused */
6033         intel_ring_advance(ring);
6034         return 0;
6035
6036 err_unpin:
6037         intel_unpin_fb_obj(obj);
6038 err:
6039         return ret;
6040 }
6041
6042 static int intel_gen3_queue_flip(struct drm_device *dev,
6043                                  struct drm_crtc *crtc,
6044                                  struct drm_framebuffer *fb,
6045                                  struct drm_i915_gem_object *obj)
6046 {
6047         struct drm_i915_private *dev_priv = dev->dev_private;
6048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6049         unsigned long offset;
6050         u32 flip_mask;
6051         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6052         int ret;
6053
6054         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6055         if (ret)
6056                 goto err;
6057
6058         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6059         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6060
6061         ret = intel_ring_begin(ring, 6);
6062         if (ret)
6063                 goto err_unpin;
6064
6065         if (intel_crtc->plane)
6066                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6067         else
6068                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6069         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6070         intel_ring_emit(ring, MI_NOOP);
6071         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6072                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6073         intel_ring_emit(ring, fb->pitches[0]);
6074         intel_ring_emit(ring, obj->gtt_offset + offset);
6075         intel_ring_emit(ring, MI_NOOP);
6076
6077         intel_ring_advance(ring);
6078         return 0;
6079
6080 err_unpin:
6081         intel_unpin_fb_obj(obj);
6082 err:
6083         return ret;
6084 }
6085
6086 static int intel_gen4_queue_flip(struct drm_device *dev,
6087                                  struct drm_crtc *crtc,
6088                                  struct drm_framebuffer *fb,
6089                                  struct drm_i915_gem_object *obj)
6090 {
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6093         uint32_t pf, pipesrc;
6094         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6095         int ret;
6096
6097         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6098         if (ret)
6099                 goto err;
6100
6101         ret = intel_ring_begin(ring, 4);
6102         if (ret)
6103                 goto err_unpin;
6104
6105         /* i965+ uses the linear or tiled offsets from the
6106          * Display Registers (which do not change across a page-flip)
6107          * so we need only reprogram the base address.
6108          */
6109         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6110                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6111         intel_ring_emit(ring, fb->pitches[0]);
6112         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6113
6114         /* XXX Enabling the panel-fitter across page-flip is so far
6115          * untested on non-native modes, so ignore it for now.
6116          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6117          */
6118         pf = 0;
6119         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6120         intel_ring_emit(ring, pf | pipesrc);
6121         intel_ring_advance(ring);
6122         return 0;
6123
6124 err_unpin:
6125         intel_unpin_fb_obj(obj);
6126 err:
6127         return ret;
6128 }
6129
6130 static int intel_gen6_queue_flip(struct drm_device *dev,
6131                                  struct drm_crtc *crtc,
6132                                  struct drm_framebuffer *fb,
6133                                  struct drm_i915_gem_object *obj)
6134 {
6135         struct drm_i915_private *dev_priv = dev->dev_private;
6136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137         struct intel_ring_buffer *ring = &dev_priv->rings[RCS];
6138         uint32_t pf, pipesrc;
6139         int ret;
6140
6141         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6142         if (ret)
6143                 goto err;
6144
6145         ret = intel_ring_begin(ring, 4);
6146         if (ret)
6147                 goto err_unpin;
6148
6149         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6150                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6151         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6152         intel_ring_emit(ring, obj->gtt_offset);
6153
6154         /* Contrary to the suggestions in the documentation,
6155          * "Enable Panel Fitter" does not seem to be required when page
6156          * flipping with a non-native mode, and worse causes a normal
6157          * modeset to fail.
6158          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6159          */
6160         pf = 0;
6161         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6162         intel_ring_emit(ring, pf | pipesrc);
6163         intel_ring_advance(ring);
6164         return 0;
6165
6166 err_unpin:
6167         intel_unpin_fb_obj(obj);
6168 err:
6169         return ret;
6170 }
6171
6172 /*
6173  * On gen7 we currently use the blit ring because (in early silicon at least)
6174  * the render ring doesn't give us interrpts for page flip completion, which
6175  * means clients will hang after the first flip is queued.  Fortunately the
6176  * blit ring generates interrupts properly, so use it instead.
6177  */
6178 static int intel_gen7_queue_flip(struct drm_device *dev,
6179                                  struct drm_crtc *crtc,
6180                                  struct drm_framebuffer *fb,
6181                                  struct drm_i915_gem_object *obj)
6182 {
6183         struct drm_i915_private *dev_priv = dev->dev_private;
6184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185         struct intel_ring_buffer *ring = &dev_priv->rings[BCS];
6186         int ret;
6187
6188         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6189         if (ret)
6190                 goto err;
6191
6192         ret = intel_ring_begin(ring, 4);
6193         if (ret)
6194                 goto err_unpin;
6195
6196         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6197         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6198         intel_ring_emit(ring, (obj->gtt_offset));
6199         intel_ring_emit(ring, (MI_NOOP));
6200         intel_ring_advance(ring);
6201         return 0;
6202
6203 err_unpin:
6204         intel_unpin_fb_obj(obj);
6205 err:
6206         return ret;
6207 }
6208
6209 static int intel_default_queue_flip(struct drm_device *dev,
6210                                     struct drm_crtc *crtc,
6211                                     struct drm_framebuffer *fb,
6212                                     struct drm_i915_gem_object *obj)
6213 {
6214         return -ENODEV;
6215 }
6216
6217 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6218                                 struct drm_framebuffer *fb,
6219                                 struct drm_pending_vblank_event *event)
6220 {
6221         struct drm_device *dev = crtc->dev;
6222         struct drm_i915_private *dev_priv = dev->dev_private;
6223         struct intel_framebuffer *intel_fb;
6224         struct drm_i915_gem_object *obj;
6225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226         struct intel_unpin_work *work;
6227         int ret;
6228
6229         work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
6230
6231         work->event = event;
6232         work->dev = crtc->dev;
6233         intel_fb = to_intel_framebuffer(crtc->fb);
6234         work->old_fb_obj = intel_fb->obj;
6235         TASK_INIT(&work->task, 0, intel_unpin_work_fn, work);
6236
6237         ret = drm_vblank_get(dev, intel_crtc->pipe);
6238         if (ret)
6239                 goto free_work;
6240
6241         /* We borrow the event spin lock for protecting unpin_work */
6242         mtx_lock(&dev->event_lock);
6243         if (intel_crtc->unpin_work) {
6244                 mtx_unlock(&dev->event_lock);
6245                 free(work, DRM_MEM_KMS);
6246                 drm_vblank_put(dev, intel_crtc->pipe);
6247
6248                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6249                 return -EBUSY;
6250         }
6251         intel_crtc->unpin_work = work;
6252         mtx_unlock(&dev->event_lock);
6253
6254         intel_fb = to_intel_framebuffer(fb);
6255         obj = intel_fb->obj;
6256
6257         DRM_LOCK(dev);
6258
6259         /* Reference the objects for the scheduled work. */
6260         drm_gem_object_reference(&work->old_fb_obj->base);
6261         drm_gem_object_reference(&obj->base);
6262
6263         crtc->fb = fb;
6264
6265         work->pending_flip_obj = obj;
6266
6267         work->enable_stall_check = true;
6268
6269         /* Block clients from rendering to the new back buffer until
6270          * the flip occurs and the object is no longer visible.
6271          */
6272         atomic_set_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6273
6274         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6275         if (ret)
6276                 goto cleanup_pending;
6277         intel_disable_fbc(dev);
6278         intel_mark_busy(dev, obj);
6279         DRM_UNLOCK(dev);
6280
6281         CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
6282
6283         return 0;
6284
6285 cleanup_pending:
6286         atomic_clear_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6287         drm_gem_object_unreference(&work->old_fb_obj->base);
6288         drm_gem_object_unreference(&obj->base);
6289         DRM_UNLOCK(dev);
6290
6291         mtx_lock(&dev->event_lock);
6292         intel_crtc->unpin_work = NULL;
6293         mtx_unlock(&dev->event_lock);
6294
6295         drm_vblank_put(dev, intel_crtc->pipe);
6296 free_work:
6297         free(work, DRM_MEM_KMS);
6298
6299         return ret;
6300 }
6301
6302 static void intel_sanitize_modesetting(struct drm_device *dev,
6303                                        int pipe, int plane)
6304 {
6305         struct drm_i915_private *dev_priv = dev->dev_private;
6306         u32 reg, val;
6307         int i;
6308
6309         /* Clear any frame start delays used for debugging left by the BIOS */
6310         for_each_pipe(i) {
6311                 reg = PIPECONF(i);
6312                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6313         }
6314
6315         if (HAS_PCH_SPLIT(dev))
6316                 return;
6317
6318         /* Who knows what state these registers were left in by the BIOS or
6319          * grub?
6320          *
6321          * If we leave the registers in a conflicting state (e.g. with the
6322          * display plane reading from the other pipe than the one we intend
6323          * to use) then when we attempt to teardown the active mode, we will
6324          * not disable the pipes and planes in the correct order -- leaving
6325          * a plane reading from a disabled pipe and possibly leading to
6326          * undefined behaviour.
6327          */
6328
6329         reg = DSPCNTR(plane);
6330         val = I915_READ(reg);
6331
6332         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6333                 return;
6334         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6335                 return;
6336
6337         /* This display plane is active and attached to the other CPU pipe. */
6338         pipe = !pipe;
6339
6340         /* Disable the plane and wait for it to stop reading from the pipe. */
6341         intel_disable_plane(dev_priv, plane, pipe);
6342         intel_disable_pipe(dev_priv, pipe);
6343 }
6344
6345 static void intel_crtc_reset(struct drm_crtc *crtc)
6346 {
6347         struct drm_device *dev = crtc->dev;
6348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349
6350         /* Reset flags back to the 'unknown' status so that they
6351          * will be correctly set on the initial modeset.
6352          */
6353         intel_crtc->dpms_mode = -1;
6354
6355         /* We need to fix up any BIOS configuration that conflicts with
6356          * our expectations.
6357          */
6358         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6359 }
6360
6361 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6362         .dpms = intel_crtc_dpms,
6363         .mode_fixup = intel_crtc_mode_fixup,
6364         .mode_set = intel_crtc_mode_set,
6365         .mode_set_base = intel_pipe_set_base,
6366         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6367         .load_lut = intel_crtc_load_lut,
6368         .disable = intel_crtc_disable,
6369 };
6370
6371 static const struct drm_crtc_funcs intel_crtc_funcs = {
6372         .reset = intel_crtc_reset,
6373         .cursor_set = intel_crtc_cursor_set,
6374         .cursor_move = intel_crtc_cursor_move,
6375         .gamma_set = intel_crtc_gamma_set,
6376         .set_config = drm_crtc_helper_set_config,
6377         .destroy = intel_crtc_destroy,
6378         .page_flip = intel_crtc_page_flip,
6379 };
6380
6381 static void intel_pch_pll_init(struct drm_device *dev)
6382 {
6383         drm_i915_private_t *dev_priv = dev->dev_private;
6384         int i;
6385
6386         if (dev_priv->num_pch_pll == 0) {
6387                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6388                 return;
6389         }
6390
6391         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6392                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6393                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6394                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6395         }
6396 }
6397
6398 static void intel_crtc_init(struct drm_device *dev, int pipe)
6399 {
6400         drm_i915_private_t *dev_priv = dev->dev_private;
6401         struct intel_crtc *intel_crtc;
6402         int i;
6403
6404         intel_crtc = malloc(sizeof(struct intel_crtc) +
6405             (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
6406             DRM_MEM_KMS, M_WAITOK | M_ZERO);
6407
6408         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6409
6410         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6411         for (i = 0; i < 256; i++) {
6412                 intel_crtc->lut_r[i] = i;
6413                 intel_crtc->lut_g[i] = i;
6414                 intel_crtc->lut_b[i] = i;
6415         }
6416
6417         /* Swap pipes & planes for FBC on pre-965 */
6418         intel_crtc->pipe = pipe;
6419         intel_crtc->plane = pipe;
6420         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6421                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6422                 intel_crtc->plane = !pipe;
6423         }
6424
6425         KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
6426             dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
6427             ("plane_to_crtc is already initialized"));
6428         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6429         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6430
6431         intel_crtc_reset(&intel_crtc->base);
6432         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6433         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6434
6435         if (HAS_PCH_SPLIT(dev)) {
6436                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6437                 intel_helper_funcs.commit = ironlake_crtc_commit;
6438         } else {
6439                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6440                 intel_helper_funcs.commit = i9xx_crtc_commit;
6441         }
6442
6443         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6444
6445         intel_crtc->busy = false;
6446
6447         callout_init(&intel_crtc->idle_callout, 1);
6448 }
6449
6450 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6451                                 struct drm_file *file)
6452 {
6453         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6454         struct drm_mode_object *drmmode_obj;
6455         struct intel_crtc *crtc;
6456
6457         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6458                 return -ENODEV;
6459
6460         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6461                         DRM_MODE_OBJECT_CRTC);
6462
6463         if (!drmmode_obj) {
6464                 DRM_ERROR("no such CRTC id\n");
6465                 return -EINVAL;
6466         }
6467
6468         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6469         pipe_from_crtc_id->pipe = crtc->pipe;
6470
6471         return 0;
6472 }
6473
6474 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6475 {
6476         struct intel_encoder *encoder;
6477         int index_mask = 0;
6478         int entry = 0;
6479
6480         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6481                 if (type_mask & encoder->clone_mask)
6482                         index_mask |= (1 << entry);
6483                 entry++;
6484         }
6485
6486         return index_mask;
6487 }
6488
6489 static bool has_edp_a(struct drm_device *dev)
6490 {
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492
6493         if (!IS_MOBILE(dev))
6494                 return false;
6495
6496         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6497                 return false;
6498
6499         if (IS_GEN5(dev) &&
6500             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6501                 return false;
6502
6503         return true;
6504 }
6505
6506 static void intel_setup_outputs(struct drm_device *dev)
6507 {
6508         struct drm_i915_private *dev_priv = dev->dev_private;
6509         struct intel_encoder *encoder;
6510         bool dpd_is_edp = false;
6511         bool has_lvds;
6512
6513         has_lvds = intel_lvds_init(dev);
6514         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6515                 /* disable the panel fitter on everything but LVDS */
6516                 I915_WRITE(PFIT_CONTROL, 0);
6517         }
6518
6519         if (HAS_PCH_SPLIT(dev)) {
6520                 dpd_is_edp = intel_dpd_is_edp(dev);
6521
6522                 if (has_edp_a(dev))
6523                         intel_dp_init(dev, DP_A);
6524
6525                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6526                         intel_dp_init(dev, PCH_DP_D);
6527         }
6528
6529         intel_crt_init(dev);
6530
6531         if (IS_HASWELL(dev)) {
6532                 int found;
6533
6534                 /* Haswell uses DDI functions to detect digital outputs */
6535                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6536                 /* DDI A only supports eDP */
6537                 if (found)
6538                         intel_ddi_init(dev, PORT_A);
6539
6540                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6541                  * register */
6542                 found = I915_READ(SFUSE_STRAP);
6543
6544                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6545                         intel_ddi_init(dev, PORT_B);
6546                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6547                         intel_ddi_init(dev, PORT_C);
6548                 if (found & SFUSE_STRAP_DDID_DETECTED)
6549                         intel_ddi_init(dev, PORT_D);
6550         } else if (HAS_PCH_SPLIT(dev)) {
6551                 int found;
6552
6553                 DRM_DEBUG_KMS(
6554 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
6555                     (I915_READ(HDMIB) & PORT_DETECTED) != 0,
6556                     (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
6557                     (I915_READ(HDMIC) & PORT_DETECTED) != 0,
6558                     (I915_READ(HDMID) & PORT_DETECTED) != 0,
6559                     (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
6560                     (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
6561                     (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
6562
6563                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6564                         /* PCH SDVOB multiplex with HDMIB */
6565                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6566                         if (!found)
6567                                 intel_hdmi_init(dev, HDMIB);
6568                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6569                                 intel_dp_init(dev, PCH_DP_B);
6570                 }
6571
6572                 if (I915_READ(HDMIC) & PORT_DETECTED)
6573                         intel_hdmi_init(dev, HDMIC);
6574
6575                 if (I915_READ(HDMID) & PORT_DETECTED)
6576                         intel_hdmi_init(dev, HDMID);
6577
6578                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6579                         intel_dp_init(dev, PCH_DP_C);
6580
6581                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6582                         intel_dp_init(dev, PCH_DP_D);
6583
6584         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6585                 bool found = false;
6586
6587                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6588                         DRM_DEBUG_KMS("probing SDVOB\n");
6589                         found = intel_sdvo_init(dev, SDVOB, true);
6590                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6591                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6592                                 intel_hdmi_init(dev, SDVOB);
6593                         }
6594
6595                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6596                                 DRM_DEBUG_KMS("probing DP_B\n");
6597                                 intel_dp_init(dev, DP_B);
6598                         }
6599                 }
6600
6601                 /* Before G4X SDVOC doesn't have its own detect register */
6602
6603                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6604                         DRM_DEBUG_KMS("probing SDVOC\n");
6605                         found = intel_sdvo_init(dev, SDVOC, false);
6606                 }
6607
6608                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6609
6610                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6611                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6612                                 intel_hdmi_init(dev, SDVOC);
6613                         }
6614                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6615                                 DRM_DEBUG_KMS("probing DP_C\n");
6616                                 intel_dp_init(dev, DP_C);
6617                         }
6618                 }
6619
6620                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6621                     (I915_READ(DP_D) & DP_DETECTED)) {
6622                         DRM_DEBUG_KMS("probing DP_D\n");
6623                         intel_dp_init(dev, DP_D);
6624                 }
6625         } else if (IS_GEN2(dev)) {
6626 #if 1
6627                 KIB_NOTYET();
6628 #else
6629                 intel_dvo_init(dev);
6630 #endif
6631         }
6632
6633         if (SUPPORTS_TV(dev))
6634                 intel_tv_init(dev);
6635
6636         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6637                 encoder->base.possible_crtcs = encoder->crtc_mask;
6638                 encoder->base.possible_clones =
6639                         intel_encoder_clones(dev, encoder->clone_mask);
6640         }
6641
6642         /* disable all the possible outputs/crtcs before entering KMS mode */
6643         drm_helper_disable_unused_functions(dev);
6644
6645         if (HAS_PCH_SPLIT(dev))
6646                 ironlake_init_pch_refclk(dev);
6647 }
6648
6649 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6650 {
6651         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6652
6653         drm_framebuffer_cleanup(fb);
6654         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6655
6656         free(intel_fb, DRM_MEM_KMS);
6657 }
6658
6659 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6660                                                 struct drm_file *file,
6661                                                 unsigned int *handle)
6662 {
6663         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6664         struct drm_i915_gem_object *obj = intel_fb->obj;
6665
6666         return drm_gem_handle_create(file, &obj->base, handle);
6667 }
6668
6669 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6670         .destroy = intel_user_framebuffer_destroy,
6671         .create_handle = intel_user_framebuffer_create_handle,
6672 };
6673
6674 int intel_framebuffer_init(struct drm_device *dev,
6675                            struct intel_framebuffer *intel_fb,
6676                            struct drm_mode_fb_cmd2 *mode_cmd,
6677                            struct drm_i915_gem_object *obj)
6678 {
6679         int ret;
6680
6681         if (obj->tiling_mode == I915_TILING_Y)
6682                 return -EINVAL;
6683
6684         if (mode_cmd->pitches[0] & 63)
6685                 return -EINVAL;
6686
6687         switch (mode_cmd->pixel_format) {
6688         case DRM_FORMAT_RGB332:
6689         case DRM_FORMAT_RGB565:
6690         case DRM_FORMAT_XRGB8888:
6691         case DRM_FORMAT_XBGR8888:
6692         case DRM_FORMAT_ARGB8888:
6693         case DRM_FORMAT_XRGB2101010:
6694         case DRM_FORMAT_ARGB2101010:
6695                 /* RGB formats are common across chipsets */
6696                 break;
6697         case DRM_FORMAT_YUYV:
6698         case DRM_FORMAT_UYVY:
6699         case DRM_FORMAT_YVYU:
6700         case DRM_FORMAT_VYUY:
6701                 break;
6702         default:
6703                 DRM_DEBUG("unsupported pixel format %u\n", mode_cmd->pixel_format);
6704                 return -EINVAL;
6705         }
6706
6707         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6708         if (ret) {
6709                 DRM_ERROR("framebuffer init failed %d\n", ret);
6710                 return ret;
6711         }
6712
6713         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6714         intel_fb->obj = obj;
6715         return 0;
6716 }
6717
6718 static int
6719 intel_user_framebuffer_create(struct drm_device *dev,
6720                               struct drm_file *filp,
6721                               struct drm_mode_fb_cmd2 *mode_cmd,
6722                               struct drm_framebuffer **res)
6723 {
6724         struct drm_i915_gem_object *obj;
6725
6726         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6727                                                 mode_cmd->handles[0]));
6728         if (&obj->base == NULL)
6729                 return -ENOENT;
6730
6731         return intel_framebuffer_create(dev, mode_cmd, obj, res);
6732 }
6733
6734 static const struct drm_mode_config_funcs intel_mode_funcs = {
6735         .fb_create = intel_user_framebuffer_create,
6736         .output_poll_changed = intel_fb_output_poll_changed,
6737 };
6738
6739 /* Set up chip specific display functions */
6740 static void intel_init_display(struct drm_device *dev)
6741 {
6742         struct drm_i915_private *dev_priv = dev->dev_private;
6743
6744         /* We always want a DPMS function */
6745         if (HAS_PCH_SPLIT(dev)) {
6746                 dev_priv->display.dpms = ironlake_crtc_dpms;
6747                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6748                 dev_priv->display.off = ironlake_crtc_off;
6749                 dev_priv->display.update_plane = ironlake_update_plane;
6750         } else {
6751                 dev_priv->display.dpms = i9xx_crtc_dpms;
6752                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6753                 dev_priv->display.off = i9xx_crtc_off;
6754                 dev_priv->display.update_plane = i9xx_update_plane;
6755         }
6756
6757         /* Returns the core display clock speed */
6758         if (IS_VALLEYVIEW(dev))
6759                 dev_priv->display.get_display_clock_speed =
6760                         valleyview_get_display_clock_speed;
6761         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6762                 dev_priv->display.get_display_clock_speed =
6763                         i945_get_display_clock_speed;
6764         else if (IS_I915G(dev))
6765                 dev_priv->display.get_display_clock_speed =
6766                         i915_get_display_clock_speed;
6767         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6768                 dev_priv->display.get_display_clock_speed =
6769                         i9xx_misc_get_display_clock_speed;
6770         else if (IS_I915GM(dev))
6771                 dev_priv->display.get_display_clock_speed =
6772                         i915gm_get_display_clock_speed;
6773         else if (IS_I865G(dev))
6774                 dev_priv->display.get_display_clock_speed =
6775                         i865_get_display_clock_speed;
6776         else if (IS_I85X(dev))
6777                 dev_priv->display.get_display_clock_speed =
6778                         i855_get_display_clock_speed;
6779         else /* 852, 830 */
6780                 dev_priv->display.get_display_clock_speed =
6781                         i830_get_display_clock_speed;
6782
6783         if (HAS_PCH_SPLIT(dev)) {
6784                 if (IS_GEN5(dev)) {
6785                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6786                         dev_priv->display.write_eld = ironlake_write_eld;
6787                 } else if (IS_GEN6(dev)) {
6788                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6789                         dev_priv->display.write_eld = ironlake_write_eld;
6790                 } else if (IS_IVYBRIDGE(dev)) {
6791                         /* FIXME: detect B0+ stepping and use auto training */
6792                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6793                         dev_priv->display.write_eld = ironlake_write_eld;
6794                 } else if (IS_HASWELL(dev)) {
6795                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6796                         dev_priv->display.write_eld = ironlake_write_eld;
6797                 } else
6798                         dev_priv->display.update_wm = NULL;
6799         } else if (IS_VALLEYVIEW(dev)) {
6800                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6801                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6802         } else if (IS_G4X(dev)) {
6803                 dev_priv->display.write_eld = g4x_write_eld;
6804         }
6805
6806         /* Default just returns -ENODEV to indicate unsupported */
6807         dev_priv->display.queue_flip = intel_default_queue_flip;
6808
6809         switch (INTEL_INFO(dev)->gen) {
6810         case 2:
6811                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6812                 break;
6813
6814         case 3:
6815                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6816                 break;
6817
6818         case 4:
6819         case 5:
6820                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6821                 break;
6822
6823         case 6:
6824                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6825                 break;
6826         case 7:
6827                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6828                 break;
6829         }
6830 }
6831
6832 /*
6833  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6834  * resume, or other times.  This quirk makes sure that's the case for
6835  * affected systems.
6836  */
6837 static void quirk_pipea_force(struct drm_device *dev)
6838 {
6839         struct drm_i915_private *dev_priv = dev->dev_private;
6840
6841         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6842         DRM_INFO("applying pipe a force quirk\n");
6843 }
6844
6845 /*
6846  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6847  */
6848 static void quirk_ssc_force_disable(struct drm_device *dev)
6849 {
6850         struct drm_i915_private *dev_priv = dev->dev_private;
6851         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6852         DRM_INFO("applying lvds SSC disable quirk\n");
6853 }
6854
6855 /*
6856  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6857  * brightness value
6858  */
6859 static void quirk_invert_brightness(struct drm_device *dev)
6860 {
6861         struct drm_i915_private *dev_priv = dev->dev_private;
6862         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6863         DRM_INFO("applying inverted panel brightness quirk\n");
6864 }
6865
6866 struct intel_quirk {
6867         int device;
6868         int subsystem_vendor;
6869         int subsystem_device;
6870         void (*hook)(struct drm_device *dev);
6871 };
6872
6873 #define PCI_ANY_ID      (~0u)
6874
6875 static struct intel_quirk intel_quirks[] = {
6876         /* HP Mini needs pipe A force quirk (LP: #322104) */
6877         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6878
6879         /* Thinkpad R31 needs pipe A force quirk */
6880         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6881         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6882         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6883
6884         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6885         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6886         /* ThinkPad X40 needs pipe A force quirk */
6887
6888         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6889         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6890
6891         /* 855 & before need to leave pipe A & dpll A up */
6892         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6893         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6894
6895         /* Lenovo U160 cannot use SSC on LVDS */
6896         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6897
6898         /* Sony Vaio Y cannot use SSC on LVDS */
6899         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6900
6901         /* Acer Aspire 5734Z must invert backlight brightness */
6902         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6903 };
6904
6905 static void intel_init_quirks(struct drm_device *dev)
6906 {
6907         struct intel_quirk *q;
6908         device_t d;
6909         int i;
6910
6911         d = dev->dev;
6912         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6913                 q = &intel_quirks[i];
6914                 if (pci_get_device(d) == q->device &&
6915                     (pci_get_subvendor(d) == q->subsystem_vendor ||
6916                      q->subsystem_vendor == PCI_ANY_ID) &&
6917                     (pci_get_subdevice(d) == q->subsystem_device ||
6918                      q->subsystem_device == PCI_ANY_ID))
6919                         q->hook(dev);
6920         }
6921 }
6922
6923 /* Disable the VGA plane that we never use */
6924 static void i915_disable_vga(struct drm_device *dev)
6925 {
6926         struct drm_i915_private *dev_priv = dev->dev_private;
6927         u8 sr1;
6928         u32 vga_reg;
6929
6930         if (HAS_PCH_SPLIT(dev))
6931                 vga_reg = CPU_VGACNTRL;
6932         else
6933                 vga_reg = VGACNTRL;
6934
6935 #if 0
6936         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6937 #endif
6938         outb(VGA_SR_INDEX, SR01);
6939         sr1 = inb(VGA_SR_DATA);
6940         outb(VGA_SR_DATA, sr1 | 1<<5);
6941 #if 0
6942         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6943 #endif
6944         DELAY(300);
6945
6946         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6947         POSTING_READ(vga_reg);
6948 }
6949
6950 static void ivb_pch_pwm_override(struct drm_device *dev)
6951 {
6952         struct drm_i915_private *dev_priv = dev->dev_private;
6953
6954         /*
6955          * IVB has CPU eDP backlight regs too, set things up to let the
6956          * PCH regs control the backlight
6957          */
6958         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6959         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6960         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE);
6961 }
6962
6963 void intel_modeset_init_hw(struct drm_device *dev)
6964 {
6965         struct drm_i915_private *dev_priv = dev->dev_private;
6966
6967         intel_init_clock_gating(dev);
6968
6969         if (IS_IRONLAKE_M(dev)) {
6970                 ironlake_enable_drps(dev);
6971                 ironlake_enable_rc6(dev);
6972                 intel_init_emon(dev);
6973         }
6974
6975         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6976                 gen6_enable_rps(dev_priv);
6977                 gen6_update_ring_freq(dev_priv);
6978         }
6979
6980         if (IS_IVYBRIDGE(dev))
6981                 ivb_pch_pwm_override(dev);
6982 }
6983
6984 void intel_modeset_init(struct drm_device *dev)
6985 {
6986         struct drm_i915_private *dev_priv = dev->dev_private;
6987         int i, ret;
6988
6989         drm_mode_config_init(dev);
6990
6991         dev->mode_config.min_width = 0;
6992         dev->mode_config.min_height = 0;
6993
6994         dev->mode_config.preferred_depth = 24;
6995         dev->mode_config.prefer_shadow = 1;
6996
6997         dev->mode_config.funcs = &intel_mode_funcs;
6998
6999         intel_init_quirks(dev);
7000
7001         intel_init_pm(dev);
7002
7003         intel_prepare_ddi(dev);
7004
7005         intel_init_display(dev);
7006
7007         if (IS_GEN2(dev)) {
7008                 dev->mode_config.max_width = 2048;
7009                 dev->mode_config.max_height = 2048;
7010         } else if (IS_GEN3(dev)) {
7011                 dev->mode_config.max_width = 4096;
7012                 dev->mode_config.max_height = 4096;
7013         } else {
7014                 dev->mode_config.max_width = 8192;
7015                 dev->mode_config.max_height = 8192;
7016         }
7017         dev->mode_config.fb_base = dev->agp->base;
7018
7019         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7020                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7021
7022         for (i = 0; i < dev_priv->num_pipe; i++) {
7023                 intel_crtc_init(dev, i);
7024                 ret = intel_plane_init(dev, i);
7025                 if (ret)
7026                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7027         }
7028
7029         intel_pch_pll_init(dev);
7030
7031         /* Just disable it once at startup */
7032         i915_disable_vga(dev);
7033         intel_setup_outputs(dev);
7034
7035         TASK_INIT(&dev_priv->idle_task, 0, intel_idle_update, dev_priv);
7036         callout_init(&dev_priv->idle_callout, 1);
7037 }
7038
7039 void intel_modeset_gem_init(struct drm_device *dev)
7040 {
7041         intel_modeset_init_hw(dev);
7042
7043         intel_setup_overlay(dev);
7044 }
7045
7046 void intel_modeset_cleanup(struct drm_device *dev)
7047 {
7048         struct drm_i915_private *dev_priv = dev->dev_private;
7049         struct drm_crtc *crtc;
7050         struct intel_crtc *intel_crtc;
7051
7052         drm_kms_helper_poll_fini(dev);
7053         DRM_LOCK(dev);
7054
7055 #if 0
7056         intel_unregister_dsm_handler();
7057 #endif
7058
7059
7060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7061                 /* Skip inactive CRTCs */
7062                 if (!crtc->fb)
7063                         continue;
7064
7065                 intel_crtc = to_intel_crtc(crtc);
7066                 intel_increase_pllclock(crtc);
7067         }
7068
7069         intel_disable_fbc(dev);
7070
7071         if (IS_IRONLAKE_M(dev))
7072                 ironlake_disable_drps(dev);
7073         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7074                 gen6_disable_rps(dev);
7075
7076         if (IS_IRONLAKE_M(dev))
7077                 ironlake_disable_rc6(dev);
7078
7079         if (IS_VALLEYVIEW(dev))
7080                 vlv_init_dpio(dev);
7081
7082         DRM_UNLOCK(dev);
7083
7084         /* Disable the irq before mode object teardown, for the irq might
7085          * enqueue unpin/hotplug work. */
7086         drm_irq_uninstall(dev);
7087         if (taskqueue_cancel(dev_priv->tq, &dev_priv->hotplug_task, NULL))
7088                 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
7089         if (taskqueue_cancel(dev_priv->tq, &dev_priv->rps_task, NULL))
7090                 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
7091
7092         /* Shut off idle work before the crtcs get freed. */
7093         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7094                 intel_crtc = to_intel_crtc(crtc);
7095                 callout_drain(&intel_crtc->idle_callout);
7096         }
7097         callout_drain(&dev_priv->idle_callout);
7098         if (taskqueue_cancel(dev_priv->tq, &dev_priv->idle_task, NULL))
7099                 taskqueue_drain(dev_priv->tq, &dev_priv->idle_task);
7100
7101         drm_mode_config_cleanup(dev);
7102 }
7103
7104 /*
7105  * Return which encoder is currently attached for connector.
7106  */
7107 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7108 {
7109         return &intel_attached_encoder(connector)->base;
7110 }
7111
7112 void intel_connector_attach_encoder(struct intel_connector *connector,
7113                                     struct intel_encoder *encoder)
7114 {
7115         connector->encoder = encoder;
7116         drm_mode_connector_attach_encoder(&connector->base,
7117                                           &encoder->base);
7118 }
7119
7120 /*
7121  * set vga decode state - true == enable VGA decode
7122  */
7123 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7124 {
7125         device_t bridge_dev;
7126         u16 gmch_ctrl;
7127
7128         bridge_dev = intel_gtt_get_bridge_device();
7129         gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
7130         if (state)
7131                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7132         else
7133                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7134         pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
7135         return (0);
7136 }
7137
7138 struct intel_display_error_state {
7139         struct intel_cursor_error_state {
7140                 u32 control;
7141                 u32 position;
7142                 u32 base;
7143                 u32 size;
7144         } cursor[2];
7145
7146         struct intel_pipe_error_state {
7147                 u32 conf;
7148                 u32 source;
7149
7150                 u32 htotal;
7151                 u32 hblank;
7152                 u32 hsync;
7153                 u32 vtotal;
7154                 u32 vblank;
7155                 u32 vsync;
7156         } pipe[2];
7157
7158         struct intel_plane_error_state {
7159                 u32 control;
7160                 u32 stride;
7161                 u32 size;
7162                 u32 pos;
7163                 u32 addr;
7164                 u32 surface;
7165                 u32 tile_offset;
7166         } plane[2];
7167 };
7168
7169 struct intel_display_error_state *
7170 intel_display_capture_error_state(struct drm_device *dev)
7171 {
7172         drm_i915_private_t *dev_priv = dev->dev_private;
7173         struct intel_display_error_state *error;
7174         int i;
7175
7176         error = malloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
7177         if (error == NULL)
7178                 return NULL;
7179
7180         for (i = 0; i < 2; i++) {
7181                 error->cursor[i].control = I915_READ(CURCNTR(i));
7182                 error->cursor[i].position = I915_READ(CURPOS(i));
7183                 error->cursor[i].base = I915_READ(CURBASE(i));
7184
7185                 error->plane[i].control = I915_READ(DSPCNTR(i));
7186                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7187                 error->plane[i].size = I915_READ(DSPSIZE(i));
7188                 error->plane[i].pos = I915_READ(DSPPOS(i));
7189                 error->plane[i].addr = I915_READ(DSPADDR(i));
7190                 if (INTEL_INFO(dev)->gen >= 4) {
7191                         error->plane[i].surface = I915_READ(DSPSURF(i));
7192                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7193                 }
7194
7195                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7196                 error->pipe[i].source = I915_READ(PIPESRC(i));
7197                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7198                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7199                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7200                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7201                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7202                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7203         }
7204
7205         return error;
7206 }
7207
7208 void
7209 intel_display_print_error_state(struct sbuf *m,
7210                                 struct drm_device *dev,
7211                                 struct intel_display_error_state *error)
7212 {
7213         int i;
7214
7215         for (i = 0; i < 2; i++) {
7216                 sbuf_printf(m, "Pipe [%d]:\n", i);
7217                 sbuf_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7218                 sbuf_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7219                 sbuf_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7220                 sbuf_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7221                 sbuf_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7222                 sbuf_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7223                 sbuf_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7224                 sbuf_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7225
7226                 sbuf_printf(m, "Plane [%d]:\n", i);
7227                 sbuf_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7228                 sbuf_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7229                 sbuf_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7230                 sbuf_printf(m, "  POS: %08x\n", error->plane[i].pos);
7231                 sbuf_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7232                 if (INTEL_INFO(dev)->gen >= 4) {
7233                         sbuf_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7234                         sbuf_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7235                 }
7236
7237                 sbuf_printf(m, "Cursor [%d]:\n", i);
7238                 sbuf_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7239                 sbuf_printf(m, "  POS: %08x\n", error->cursor[i].position);
7240                 sbuf_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7241         }
7242 }