sys/dev/drm2/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <dev/drm2/drmP.h>
  32 #include <dev/drm2/drm.h>
  33 #include <dev/drm2/drm_crtc.h>
  34 #include <dev/drm2/drm_crtc_helper.h>
  35 #include <dev/drm2/i915/i915_drm.h>
  36 #include <dev/drm2/i915/i915_drv.h>
  37 #include <dev/drm2/i915/intel_drv.h>
  38 #include <dev/drm2/drm_dp_helper.h>
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 /* XXXKIB what is the right code for the FreeBSD ? */
  47 #define EREMOTEIO       ENXIO
  48
  49 struct intel_dp {
  50         struct intel_encoder base;
  51         uint32_t output_reg;
  52         uint32_t DP;
  53         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  54         bool has_audio;
  55         enum hdmi_force_audio force_audio;
  56         uint32_t color_range;
  57         int dpms_mode;
  58         uint8_t link_bw;
  59         uint8_t lane_count;
  60         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  61         device_t dp_iic_bus;
  62         device_t adapter;
  63         bool is_pch_edp;
  64         uint8_t train_set[4];
  65         int panel_power_up_delay;
  66         int panel_power_down_delay;
  67         int panel_power_cycle_delay;
  68         int backlight_on_delay;
  69         int backlight_off_delay;
  70         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  71         struct timeout_task panel_vdd_task;
  72         bool want_panel_vdd;
  73 };
  74
  75 /**
  76  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  77  * @intel_dp: DP struct
  78  *
  79  * If a CPU or PCH DP output is attached to an eDP panel, this function
  80  * will return true, and false otherwise.
  81  */
  82 static bool is_edp(struct intel_dp *intel_dp)
  83 {
  84         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  85 }
  86
  87 /**
  88  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  89  * @intel_dp: DP struct
  90  *
  91  * Returns true if the given DP struct corresponds to a PCH DP port attached
  92  * to an eDP panel, false otherwise.  Helpful for determining whether we
  93  * may need FDI resources for a given DP output or not.
  94  */
  95 static bool is_pch_edp(struct intel_dp *intel_dp)
  96 {
  97         return intel_dp->is_pch_edp;
  98 }
  99
 100 /**
 101  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 102  * @intel_dp: DP struct
 103  *
 104  * Returns true if the given DP struct corresponds to a CPU eDP port.
 105  */
 106 static bool is_cpu_edp(struct intel_dp *intel_dp)
 107 {
 108         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 109 }
 110
 111 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 112 {
 113         return container_of(encoder, struct intel_dp, base.base);
 114 }
 115
 116 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 117 {
 118         return container_of(intel_attached_encoder(connector),
 119                             struct intel_dp, base);
 120 }
 121
 122 /**
 123  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 124  * @encoder: DRM encoder
 125  *
 126  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 127  * by intel_display.c.
 128  */
 129 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 130 {
 131         struct intel_dp *intel_dp;
 132
 133         if (!encoder)
 134                 return false;
 135
 136         intel_dp = enc_to_intel_dp(encoder);
 137
 138         return is_pch_edp(intel_dp);
 139 }
 140
 141 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 142 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 143 static void intel_dp_link_down(struct intel_dp *intel_dp);
 144
 145 void
 146 intel_edp_link_config(struct intel_encoder *intel_encoder,
 147                        int *lane_num, int *link_bw)
 148 {
 149         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 150
 151         *lane_num = intel_dp->lane_count;
 152         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 153                 *link_bw = 162000;
 154         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 155                 *link_bw = 270000;
 156 }
 157
 158 static int
 159 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 160 {
 161         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 162         switch (max_lane_count) {
 163         case 1: case 2: case 4:
 164                 break;
 165         default:
 166                 max_lane_count = 4;
 167         }
 168         return max_lane_count;
 169 }
 170
 171 static int
 172 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 173 {
 174         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 175
 176         switch (max_link_bw) {
 177         case DP_LINK_BW_1_62:
 178         case DP_LINK_BW_2_7:
 179                 break;
 180         default:
 181                 max_link_bw = DP_LINK_BW_1_62;
 182                 break;
 183         }
 184         return max_link_bw;
 185 }
 186
 187 static int
 188 intel_dp_link_clock(uint8_t link_bw)
 189 {
 190         if (link_bw == DP_LINK_BW_2_7)
 191                 return 270000;
 192         else
 193                 return 162000;
 194 }
 195
 196 /*
 197  * The units on the numbers in the next two are... bizarre.  Examples will
 198  * make it clearer; this one parallels an example in the eDP spec.
 199  *
 200  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 201  *
 202  *     270000 * 1 * 8 / 10 == 216000
 203  *
 204  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 205  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 206  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 207  * 119000.  At 18bpp that's 2142000 kilobits per second.
 208  *
 209  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 210  * get the result in decakilobits instead of kilobits.
 211  */
 212
 213 static int
 214 intel_dp_link_required(int pixel_clock, int bpp)
 215 {
 216         return (pixel_clock * bpp + 9) / 10;
 217 }
 218
 219 static int
 220 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 221 {
 222         return (max_link_clock * max_lanes * 8) / 10;
 223 }
 224
 225 static bool
 226 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 227                           const struct drm_display_mode *mode,
 228                           struct drm_display_mode *adjusted_mode)
 229 {
 230         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 231         int max_lanes = intel_dp_max_lane_count(intel_dp);
 232         int max_rate, mode_rate;
 233
 234         mode_rate = intel_dp_link_required(mode->clock, 24);
 235         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 236
 237         if (mode_rate > max_rate) {
 238                 mode_rate = intel_dp_link_required(mode->clock, 18);
 239                 if (mode_rate > max_rate)
 240                         return false;
 241
 242                 if (adjusted_mode)
 243                         adjusted_mode->private_flags
 244                                 |= INTEL_MODE_DP_FORCE_6BPC;
 245
 246                 return true;
 247         }
 248
 249         return true;
 250 }
 251
 252 static int
 253 intel_dp_mode_valid(struct drm_connector *connector,
 254                     struct drm_display_mode *mode)
 255 {
 256         struct intel_dp *intel_dp = intel_attached_dp(connector);
 257
 258         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 259                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 260                         return MODE_PANEL;
 261
 262                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 263                         return MODE_PANEL;
 264         }
 265
 266         if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
 267                 return MODE_CLOCK_HIGH;
 268
 269         if (mode->clock < 10000)
 270                 return MODE_CLOCK_LOW;
 271
 272         return MODE_OK;
 273 }
 274
 275 static uint32_t
 276 pack_aux(uint8_t *src, int src_bytes)
 277 {
 278         int     i;
 279         uint32_t v = 0;
 280
 281         if (src_bytes > 4)
 282                 src_bytes = 4;
 283         for (i = 0; i < src_bytes; i++)
 284                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 285         return v;
 286 }
 287
 288 static void
 289 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 290 {
 291         int i;
 292         if (dst_bytes > 4)
 293                 dst_bytes = 4;
 294         for (i = 0; i < dst_bytes; i++)
 295                 dst[i] = src >> ((3-i) * 8);
 296 }
 297
 298 /* hrawclock is 1/4 the FSB frequency */
 299 static int
 300 intel_hrawclk(struct drm_device *dev)
 301 {
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         uint32_t clkcfg;
 304
 305         clkcfg = I915_READ(CLKCFG);
 306         switch (clkcfg & CLKCFG_FSB_MASK) {
 307         case CLKCFG_FSB_400:
 308                 return 100;
 309         case CLKCFG_FSB_533:
 310                 return 133;
 311         case CLKCFG_FSB_667:
 312                 return 166;
 313         case CLKCFG_FSB_800:
 314                 return 200;
 315         case CLKCFG_FSB_1067:
 316                 return 266;
 317         case CLKCFG_FSB_1333:
 318                 return 333;
 319         /* these two are just a guess; one of them might be right */
 320         case CLKCFG_FSB_1600:
 321         case CLKCFG_FSB_1600_ALT:
 322                 return 400;
 323         default:
 324                 return 133;
 325         }
 326 }
 327
 328 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 329 {
 330         struct drm_device *dev = intel_dp->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 334 }
 335
 336 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 337 {
 338         struct drm_device *dev = intel_dp->base.base.dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 342 }
 343
 344 static void
 345 intel_dp_check_edp(struct intel_dp *intel_dp)
 346 {
 347         struct drm_device *dev = intel_dp->base.base.dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349
 350         if (!is_edp(intel_dp))
 351                 return;
 352         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 353                 printf("eDP powered off while attempting aux channel communication.\n");
 354                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 355                               I915_READ(PCH_PP_STATUS),
 356                               I915_READ(PCH_PP_CONTROL));
 357         }
 358 }
 359
 360 static int
 361 intel_dp_aux_ch(struct intel_dp *intel_dp,
 362                 uint8_t *send, int send_bytes,
 363                 uint8_t *recv, int recv_size)
 364 {
 365         uint32_t output_reg = intel_dp->output_reg;
 366         struct drm_device *dev = intel_dp->base.base.dev;
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         uint32_t ch_ctl = output_reg + 0x10;
 369         uint32_t ch_data = ch_ctl + 4;
 370         int i;
 371         int recv_bytes;
 372         uint32_t status;
 373         uint32_t aux_clock_divider;
 374         int try, precharge = 5;
 375
 376         intel_dp_check_edp(intel_dp);
 377         /* The clock divider is based off the hrawclk,
 378          * and would like to run at 2MHz. So, take the
 379          * hrawclk value and divide by 2 and use that
 380          *
 381          * Note that PCH attached eDP panels should use a 125MHz input
 382          * clock divider.
 383          */
 384         if (is_cpu_edp(intel_dp)) {
 385                 if (IS_GEN6(dev) || IS_GEN7(dev))
 386                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 387                 else
 388                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 389         } else if (HAS_PCH_SPLIT(dev))
 390                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 391         else
 392                 aux_clock_divider = intel_hrawclk(dev) / 2;
 393
 394         /* Try to wait for any previous AUX channel activity */
 395         for (try = 0; try < 3; try++) {
 396                 status = I915_READ(ch_ctl);
 397                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 398                         break;
 399                 drm_msleep(1, "915ach");
 400         }
 401
 402         if (try == 3) {
 403                 printf("dp_aux_ch not started status 0x%08x\n",
 404                      I915_READ(ch_ctl));
 405                 return -EBUSY;
 406         }
 407
 408         /* Must try at least 3 times according to DP spec */
 409         for (try = 0; try < 5; try++) {
 410                 /* Load the send data into the aux channel data registers */
 411                 for (i = 0; i < send_bytes; i += 4)
 412                         I915_WRITE(ch_data + i,
 413                                    pack_aux(send + i, send_bytes - i));
 414
 415                 /* Send the command and wait for it to complete */
 416                 I915_WRITE(ch_ctl,
 417                            DP_AUX_CH_CTL_SEND_BUSY |
 418                            DP_AUX_CH_CTL_TIME_OUT_400us |
 419                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 420                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 421                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 422                            DP_AUX_CH_CTL_DONE |
 423                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 424                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 425                 for (;;) {
 426                         status = I915_READ(ch_ctl);
 427                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 428                                 break;
 429                         DELAY(100);
 430                 }
 431
 432                 /* Clear done status and any errors */
 433                 I915_WRITE(ch_ctl,
 434                            status |
 435                            DP_AUX_CH_CTL_DONE |
 436                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 437                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 438
 439                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 440                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 441                         continue;
 442                 if (status & DP_AUX_CH_CTL_DONE)
 443                         break;
 444         }
 445
 446         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 447                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 448                 return -EBUSY;
 449         }
 450
 451         /* Check for timeout or receive error.
 452          * Timeouts occur when the sink is not connected
 453          */
 454         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 455                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 456                 return -EIO;
 457         }
 458
 459         /* Timeouts occur when the device isn't connected, so they're
 460          * "normal" -- don't fill the kernel log with these */
 461         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 462                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 463                 return -ETIMEDOUT;
 464         }
 465
 466         /* Unload any bytes sent back from the other side */
 467         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 468                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 469         if (recv_bytes > recv_size)
 470                 recv_bytes = recv_size;
 471
 472         for (i = 0; i < recv_bytes; i += 4)
 473                 unpack_aux(I915_READ(ch_data + i),
 474                            recv + i, recv_bytes - i);
 475
 476         return recv_bytes;
 477 }
 478
 479 /* Write data to the aux channel in native mode */
 480 static int
 481 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 482                           uint16_t address, uint8_t *send, int send_bytes)
 483 {
 484         int ret;
 485         uint8_t msg[20];
 486         int msg_bytes;
 487         uint8_t ack;
 488
 489         intel_dp_check_edp(intel_dp);
 490         if (send_bytes > 16)
 491                 return -1;
 492         msg[0] = AUX_NATIVE_WRITE << 4;
 493         msg[1] = address >> 8;
 494         msg[2] = address & 0xff;
 495         msg[3] = send_bytes - 1;
 496         memcpy(&msg[4], send, send_bytes);
 497         msg_bytes = send_bytes + 4;
 498         for (;;) {
 499                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 500                 if (ret < 0)
 501                         return ret;
 502                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 503                         break;
 504                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 505                         DELAY(100);
 506                 else
 507                         return -EIO;
 508         }
 509         return send_bytes;
 510 }
 511
 512 /* Write a single byte to the aux channel in native mode */
 513 static int
 514 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 515                             uint16_t address, uint8_t byte)
 516 {
 517         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 518 }
 519
 520 /* read bytes from a native aux channel */
 521 static int
 522 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 523                          uint16_t address, uint8_t *recv, int recv_bytes)
 524 {
 525         uint8_t msg[4];
 526         int msg_bytes;
 527         uint8_t reply[20];
 528         int reply_bytes;
 529         uint8_t ack;
 530         int ret;
 531
 532         intel_dp_check_edp(intel_dp);
 533         msg[0] = AUX_NATIVE_READ << 4;
 534         msg[1] = address >> 8;
 535         msg[2] = address & 0xff;
 536         msg[3] = recv_bytes - 1;
 537
 538         msg_bytes = 4;
 539         reply_bytes = recv_bytes + 1;
 540
 541         for (;;) {
 542                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 543                                       reply, reply_bytes);
 544                 if (ret == 0)
 545                         return -EPROTO;
 546                 if (ret < 0)
 547                         return ret;
 548                 ack = reply[0];
 549                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 550                         memcpy(recv, reply + 1, ret - 1);
 551                         return ret - 1;
 552                 }
 553                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 554                         DELAY(100);
 555                 else
 556                         return -EIO;
 557         }
 558 }
 559
 560 static int
 561 intel_dp_i2c_aux_ch(device_t idev, int mode, uint8_t write_byte,
 562     uint8_t *read_byte)
 563 {
 564         struct iic_dp_aux_data *data;
 565         struct intel_dp *intel_dp;
 566         uint16_t address;
 567         uint8_t msg[5];
 568         uint8_t reply[2];
 569         unsigned retry;
 570         int msg_bytes;
 571         int reply_bytes;
 572         int ret;
 573
 574         data = device_get_softc(idev);
 575         intel_dp = data->priv;
 576         address = data->address;
 577
 578         intel_dp_check_edp(intel_dp);
 579         /* Set up the command byte */
 580         if (mode & MODE_I2C_READ)
 581                 msg[0] = AUX_I2C_READ << 4;
 582         else
 583                 msg[0] = AUX_I2C_WRITE << 4;
 584
 585         if (!(mode & MODE_I2C_STOP))
 586                 msg[0] |= AUX_I2C_MOT << 4;
 587
 588         msg[1] = address >> 8;
 589         msg[2] = address;
 590
 591         switch (mode) {
 592         case MODE_I2C_WRITE:
 593                 msg[3] = 0;
 594                 msg[4] = write_byte;
 595                 msg_bytes = 5;
 596                 reply_bytes = 1;
 597                 break;
 598         case MODE_I2C_READ:
 599                 msg[3] = 0;
 600                 msg_bytes = 4;
 601                 reply_bytes = 2;
 602                 break;
 603         default:
 604                 msg_bytes = 3;
 605                 reply_bytes = 1;
 606                 break;
 607         }
 608
 609         for (retry = 0; retry < 5; retry++) {
 610                 ret = intel_dp_aux_ch(intel_dp,
 611                                       msg, msg_bytes,
 612                                       reply, reply_bytes);
 613                 if (ret < 0) {
 614                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 615                         return (-ret);
 616                 }
 617
 618                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 619                 case AUX_NATIVE_REPLY_ACK:
 620                         /* I2C-over-AUX Reply field is only valid
 621                          * when paired with AUX ACK.
 622                          */
 623                         break;
 624                 case AUX_NATIVE_REPLY_NACK:
 625                         DRM_DEBUG_KMS("aux_ch native nack\n");
 626                         return (EREMOTEIO);
 627                 case AUX_NATIVE_REPLY_DEFER:
 628                         DELAY(100);
 629                         continue;
 630                 default:
 631                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 632                                   reply[0]);
 633                         return (EREMOTEIO);
 634                 }
 635
 636                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 637                 case AUX_I2C_REPLY_ACK:
 638                         if (mode == MODE_I2C_READ) {
 639                                 *read_byte = reply[1];
 640                         }
 641                         return (0/*reply_bytes - 1*/);
 642                 case AUX_I2C_REPLY_NACK:
 643                         DRM_DEBUG_KMS("aux_i2c nack\n");
 644                         return (EREMOTEIO);
 645                 case AUX_I2C_REPLY_DEFER:
 646                         DRM_DEBUG_KMS("aux_i2c defer\n");
 647                         DELAY(100);
 648                         break;
 649                 default:
 650                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 651                         return (EREMOTEIO);
 652                 }
 653         }
 654
 655         DRM_ERROR("too many retries, giving up\n");
 656         return (EREMOTEIO);
 657 }
 658
 659 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 660 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 661
 662 static int
 663 intel_dp_i2c_init(struct intel_dp *intel_dp,
 664                   struct intel_connector *intel_connector, const char *name)
 665 {
 666         int ret;
 667
 668         DRM_DEBUG_KMS("i2c_init %s\n", name);
 669
 670         ironlake_edp_panel_vdd_on(intel_dp);
 671         ret = iic_dp_aux_add_bus(intel_connector->base.dev->device, name,
 672             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
 673             &intel_dp->adapter);
 674         ironlake_edp_panel_vdd_off(intel_dp, false);
 675         return (ret);
 676 }
 677
 678 static bool
 679 intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
 680                     struct drm_display_mode *adjusted_mode)
 681 {
 682         struct drm_device *dev = encoder->dev;
 683         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 684         int lane_count, clock;
 685         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 686         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 687         int bpp;
 688         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 689
 690         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 691                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 692                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 693                                         mode, adjusted_mode);
 694         }
 695
 696         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode))
 697                 return false;
 698
 699         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 700
 701         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 702                 for (clock = 0; clock <= max_clock; clock++) {
 703                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 704
 705                         if (intel_dp_link_required(adjusted_mode->clock, bpp)
 706                                         <= link_avail) {
 707                                 intel_dp->link_bw = bws[clock];
 708                                 intel_dp->lane_count = lane_count;
 709                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 710                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 711                                                 "count %d clock %d\n",
 712                                        intel_dp->link_bw, intel_dp->lane_count,
 713                                        adjusted_mode->clock);
 714                                 return true;
 715                         }
 716                 }
 717         }
 718
 719         return false;
 720 }
 721
 722 struct intel_dp_m_n {
 723         uint32_t        tu;
 724         uint32_t        gmch_m;
 725         uint32_t        gmch_n;
 726         uint32_t        link_m;
 727         uint32_t        link_n;
 728 };
 729
 730 static void
 731 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 732 {
 733         while (*num > 0xffffff || *den > 0xffffff) {
 734                 *num >>= 1;
 735                 *den >>= 1;
 736         }
 737 }
 738
 739 static void
 740 intel_dp_compute_m_n(int bpp,
 741                      int nlanes,
 742                      int pixel_clock,
 743                      int link_clock,
 744                      struct intel_dp_m_n *m_n)
 745 {
 746         m_n->tu = 64;
 747         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 748         m_n->gmch_n = link_clock * nlanes;
 749         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 750         m_n->link_m = pixel_clock;
 751         m_n->link_n = link_clock;
 752         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 753 }
 754
 755 void
 756 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 757                  struct drm_display_mode *adjusted_mode)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct drm_encoder *encoder;
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 764         int lane_count = 4;
 765         struct intel_dp_m_n m_n;
 766         int pipe = intel_crtc->pipe;
 767
 768         /*
 769          * Find the lane count in the intel_encoder private
 770          */
 771         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 772                 struct intel_dp *intel_dp;
 773
 774                 if (encoder->crtc != crtc)
 775                         continue;
 776
 777                 intel_dp = enc_to_intel_dp(encoder);
 778                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 779                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 780                 {
 781                         lane_count = intel_dp->lane_count;
 782                         break;
 783                 }
 784         }
 785
 786         /*
 787          * Compute the GMCH and Link ratios. The '3' here is
 788          * the number of bytes_per_pixel post-LUT, which we always
 789          * set up for 8-bits of R/G/B, or 3 bytes total.
 790          */
 791         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 792                              mode->clock, adjusted_mode->clock, &m_n);
 793
 794         if (HAS_PCH_SPLIT(dev)) {
 795                 I915_WRITE(TRANSDATA_M1(pipe),
 796                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 797                            m_n.gmch_m);
 798                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 799                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 800                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 801         } else {
 802                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 803                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 804                            m_n.gmch_m);
 805                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 806                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 807                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 808         }
 809 }
 810
 811 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 812 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 813
 814 static void
 815 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 816                   struct drm_display_mode *adjusted_mode)
 817 {
 818         struct drm_device *dev = encoder->dev;
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 821         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 823
 824         /* Turn on the eDP PLL if needed */
 825         if (is_edp(intel_dp)) {
 826                 if (!is_pch_edp(intel_dp))
 827                         ironlake_edp_pll_on(encoder);
 828                 else
 829                         ironlake_edp_pll_off(encoder);
 830         }
 831
 832         /*
 833          * There are four kinds of DP registers:
 834          *
 835          *      IBX PCH
 836          *      SNB CPU
 837          *      IVB CPU
 838          *      CPT PCH
 839          *
 840          * IBX PCH and CPU are the same for almost everything,
 841          * except that the CPU DP PLL is configured in this
 842          * register
 843          *
 844          * CPT PCH is quite different, having many bits moved
 845          * to the TRANS_DP_CTL register instead. That
 846          * configuration happens (oddly) in ironlake_pch_enable
 847          */
 848
 849         /* Preserve the BIOS-computed detected bit. This is
 850          * supposed to be read-only.
 851          */
 852         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 853         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 854
 855         /* Handle DP bits in common between all three register formats */
 856
 857         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 858
 859         switch (intel_dp->lane_count) {
 860         case 1:
 861                 intel_dp->DP |= DP_PORT_WIDTH_1;
 862                 break;
 863         case 2:
 864                 intel_dp->DP |= DP_PORT_WIDTH_2;
 865                 break;
 866         case 4:
 867                 intel_dp->DP |= DP_PORT_WIDTH_4;
 868                 break;
 869         }
 870         if (intel_dp->has_audio) {
 871                 DRM_DEBUG_KMS("Enabling DP audio on pipe %c\n",
 872                                  pipe_name(intel_crtc->pipe));
 873                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 874                 intel_write_eld(encoder, adjusted_mode);
 875         }
 876         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 877         intel_dp->link_configuration[0] = intel_dp->link_bw;
 878         intel_dp->link_configuration[1] = intel_dp->lane_count;
 879         /*
 880          * Check for DPCD version > 1.1 and enhanced framing support
 881          */
 882         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 883             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 884                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 885         }
 886
 887         /* Split out the IBX/CPU vs CPT settings */
 888
 889         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 890                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 891                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 892                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 893                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 894                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 895
 896                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 897                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 898
 899                 intel_dp->DP |= intel_crtc->pipe << 29;
 900
 901                 /* don't miss out required setting for eDP */
 902                 intel_dp->DP |= DP_PLL_ENABLE;
 903                 if (adjusted_mode->clock < 200000)
 904                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 905                 else
 906                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 907         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 908                 intel_dp->DP |= intel_dp->color_range;
 909
 910                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 911                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 912                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 913                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 914                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 915
 916                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 917                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 918
 919                 if (intel_crtc->pipe == 1)
 920                         intel_dp->DP |= DP_PIPEB_SELECT;
 921
 922                 if (is_cpu_edp(intel_dp)) {
 923                         /* don't miss out required setting for eDP */
 924                         intel_dp->DP |= DP_PLL_ENABLE;
 925                         if (adjusted_mode->clock < 200000)
 926                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 927                         else
 928                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 929                 }
 930         } else {
 931                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 932         }
 933 }
 934
 935 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 936 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 937
 938 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 939 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 940
 941 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 942 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 943
 944 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 945                                        u32 mask,
 946                                        u32 value)
 947 {
 948         struct drm_device *dev = intel_dp->base.base.dev;
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950
 951         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 952                       mask, value,
 953                       I915_READ(PCH_PP_STATUS),
 954                       I915_READ(PCH_PP_CONTROL));
 955
 956         if (_intel_wait_for(dev,
 957             (I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10, "915iwp")) {
 958                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 959                           I915_READ(PCH_PP_STATUS),
 960                           I915_READ(PCH_PP_CONTROL));
 961         }
 962 }
 963
 964 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 965 {
 966         DRM_DEBUG_KMS("Wait for panel power on\n");
 967         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 968 }
 969
 970 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 971 {
 972         DRM_DEBUG_KMS("Wait for panel power off time\n");
 973         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 974 }
 975
 976 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 977 {
 978         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 979         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 980 }
 981
 982
 983 /* Read the current pp_control value, unlocking the register if it
 984  * is locked
 985  */
 986
 987 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 988 {
 989         u32     control = I915_READ(PCH_PP_CONTROL);
 990
 991         control &= ~PANEL_UNLOCK_MASK;
 992         control |= PANEL_UNLOCK_REGS;
 993         return control;
 994 }
 995
 996 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 997 {
 998         struct drm_device *dev = intel_dp->base.base.dev;
 999         struct drm_i915_private *dev_priv = dev->dev_private;
1000         u32 pp;
1001
1002         if (!is_edp(intel_dp))
1003                 return;
1004         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1005
1006         if (intel_dp->want_panel_vdd)
1007                 printf("eDP VDD already requested on\n");
1008
1009         intel_dp->want_panel_vdd = true;
1010
1011         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1012                 DRM_DEBUG_KMS("eDP VDD already on\n");
1013                 return;
1014         }
1015
1016         if (!ironlake_edp_have_panel_power(intel_dp))
1017                 ironlake_wait_panel_power_cycle(intel_dp);
1018
1019         pp = ironlake_get_pp_control(dev_priv);
1020         pp |= EDP_FORCE_VDD;
1021         I915_WRITE(PCH_PP_CONTROL, pp);
1022         POSTING_READ(PCH_PP_CONTROL);
1023         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1024                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1025
1026         /*
1027          * If the panel wasn't on, delay before accessing aux channel
1028          */
1029         if (!ironlake_edp_have_panel_power(intel_dp)) {
1030                 DRM_DEBUG_KMS("eDP was not running\n");
1031                 drm_msleep(intel_dp->panel_power_up_delay, "915edpon");
1032         }
1033 }
1034
1035 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1036 {
1037         struct drm_device *dev = intel_dp->base.base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         u32 pp;
1040
1041         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042                 pp = ironlake_get_pp_control(dev_priv);
1043                 pp &= ~EDP_FORCE_VDD;
1044                 I915_WRITE(PCH_PP_CONTROL, pp);
1045                 POSTING_READ(PCH_PP_CONTROL);
1046
1047                 /* Make sure sequencer is idle before allowing subsequent activity */
1048                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1050
1051                 drm_msleep(intel_dp->panel_power_down_delay, "915vddo");
1052         }
1053 }
1054
1055 static void ironlake_panel_vdd_work(void *arg, int pending __unused)
1056 {
1057         struct intel_dp *intel_dp = arg;
1058         struct drm_device *dev = intel_dp->base.base.dev;
1059
1060         sx_xlock(&dev->mode_config.mutex);
1061         ironlake_panel_vdd_off_sync(intel_dp);
1062         sx_xunlock(&dev->mode_config.mutex);
1063 }
1064
1065 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1066 {
1067         if (!is_edp(intel_dp))
1068                 return;
1069
1070         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1071         if (!intel_dp->want_panel_vdd)
1072                 printf("eDP VDD not forced on\n");
1073
1074         intel_dp->want_panel_vdd = false;
1075
1076         if (sync) {
1077                 ironlake_panel_vdd_off_sync(intel_dp);
1078         } else {
1079                 /*
1080                  * Queue the timer to fire a long
1081                  * time from now (relative to the power down delay)
1082                  * to keep the panel power up across a sequence of operations
1083                  */
1084                 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private;
1085                 taskqueue_enqueue_timeout(dev_priv->tq,
1086                     &intel_dp->panel_vdd_task,
1087                     msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1088         }
1089 }
1090
1091 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1092 {
1093         struct drm_device *dev = intel_dp->base.base.dev;
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         u32 pp;
1096
1097         if (!is_edp(intel_dp))
1098                 return;
1099
1100         DRM_DEBUG_KMS("Turn eDP power on\n");
1101
1102         if (ironlake_edp_have_panel_power(intel_dp)) {
1103                 DRM_DEBUG_KMS("eDP power already on\n");
1104                 return;
1105         }
1106
1107         ironlake_wait_panel_power_cycle(intel_dp);
1108
1109         pp = ironlake_get_pp_control(dev_priv);
1110         if (IS_GEN5(dev)) {
1111                 /* ILK workaround: disable reset around power sequence */
1112                 pp &= ~PANEL_POWER_RESET;
1113                 I915_WRITE(PCH_PP_CONTROL, pp);
1114                 POSTING_READ(PCH_PP_CONTROL);
1115         }
1116
1117         pp |= POWER_TARGET_ON;
1118         if (!IS_GEN5(dev))
1119                 pp |= PANEL_POWER_RESET;
1120
1121         I915_WRITE(PCH_PP_CONTROL, pp);
1122         POSTING_READ(PCH_PP_CONTROL);
1123
1124         ironlake_wait_panel_on(intel_dp);
1125
1126         if (IS_GEN5(dev)) {
1127                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1128                 I915_WRITE(PCH_PP_CONTROL, pp);
1129                 POSTING_READ(PCH_PP_CONTROL);
1130         }
1131 }
1132
1133 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1134 {
1135         struct drm_device *dev = intel_dp->base.base.dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         u32 pp;
1138
1139         if (!is_edp(intel_dp))
1140                 return;
1141
1142         DRM_DEBUG_KMS("Turn eDP power off\n");
1143
1144         if (intel_dp->want_panel_vdd)
1145                 printf("Cannot turn power off while VDD is on\n");
1146
1147         pp = ironlake_get_pp_control(dev_priv);
1148         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1149         I915_WRITE(PCH_PP_CONTROL, pp);
1150         POSTING_READ(PCH_PP_CONTROL);
1151
1152         ironlake_wait_panel_off(intel_dp);
1153 }
1154
1155 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1156 {
1157         struct drm_device *dev = intel_dp->base.base.dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         u32 pp;
1160
1161         if (!is_edp(intel_dp))
1162                 return;
1163
1164         DRM_DEBUG_KMS("\n");
1165         /*
1166          * If we enable the backlight right away following a panel power
1167          * on, we may see slight flicker as the panel syncs with the eDP
1168          * link.  So delay a bit to make sure the image is solid before
1169          * allowing it to appear.
1170          */
1171         drm_msleep(intel_dp->backlight_on_delay, "915ebo");
1172         pp = ironlake_get_pp_control(dev_priv);
1173         pp |= EDP_BLC_ENABLE;
1174         I915_WRITE(PCH_PP_CONTROL, pp);
1175         POSTING_READ(PCH_PP_CONTROL);
1176 }
1177
1178 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1179 {
1180         struct drm_device *dev = intel_dp->base.base.dev;
1181         struct drm_i915_private *dev_priv = dev->dev_private;
1182         u32 pp;
1183
1184         if (!is_edp(intel_dp))
1185                 return;
1186
1187         DRM_DEBUG_KMS("\n");
1188         pp = ironlake_get_pp_control(dev_priv);
1189         pp &= ~EDP_BLC_ENABLE;
1190         I915_WRITE(PCH_PP_CONTROL, pp);
1191         POSTING_READ(PCH_PP_CONTROL);
1192         drm_msleep(intel_dp->backlight_off_delay, "915bo1");
1193 }
1194
1195 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1196 {
1197         struct drm_device *dev = encoder->dev;
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpa_ctl;
1200
1201         DRM_DEBUG_KMS("\n");
1202         dpa_ctl = I915_READ(DP_A);
1203         dpa_ctl |= DP_PLL_ENABLE;
1204         I915_WRITE(DP_A, dpa_ctl);
1205         POSTING_READ(DP_A);
1206         DELAY(200);
1207 }
1208
1209 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1210 {
1211         struct drm_device *dev = encoder->dev;
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         u32 dpa_ctl;
1214
1215         dpa_ctl = I915_READ(DP_A);
1216         dpa_ctl &= ~DP_PLL_ENABLE;
1217         I915_WRITE(DP_A, dpa_ctl);
1218         POSTING_READ(DP_A);
1219         DELAY(200);
1220 }
1221
1222 /* If the sink supports it, try to set the power state appropriately */
1223 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1224 {
1225         int ret, i;
1226
1227         /* Should have a valid DPCD by this point */
1228         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1229                 return;
1230
1231         if (mode != DRM_MODE_DPMS_ON) {
1232                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1233                                                   DP_SET_POWER_D3);
1234                 if (ret != 1)
1235                         DRM_DEBUG("failed to write sink power state\n");
1236         } else {
1237                 /*
1238                  * When turning on, we need to retry for 1ms to give the sink
1239                  * time to wake up.
1240                  */
1241                 for (i = 0; i < 3; i++) {
1242                         ret = intel_dp_aux_native_write_1(intel_dp,
1243                                                           DP_SET_POWER,
1244                                                           DP_SET_POWER_D0);
1245                         if (ret == 1)
1246                                 break;
1247                         drm_msleep(1, "915dps");
1248                 }
1249         }
1250 }
1251
1252 static void intel_dp_prepare(struct drm_encoder *encoder)
1253 {
1254         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1255
1256         ironlake_edp_backlight_off(intel_dp);
1257         ironlake_edp_panel_off(intel_dp);
1258
1259         /* Wake up the sink first */
1260         ironlake_edp_panel_vdd_on(intel_dp);
1261         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1262         intel_dp_link_down(intel_dp);
1263         ironlake_edp_panel_vdd_off(intel_dp, false);
1264
1265         /* Make sure the panel is off before trying to
1266          * change the mode
1267          */
1268 }
1269
1270 static void intel_dp_commit(struct drm_encoder *encoder)
1271 {
1272         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1273         struct drm_device *dev = encoder->dev;
1274         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1275
1276         ironlake_edp_panel_vdd_on(intel_dp);
1277         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1278         intel_dp_start_link_train(intel_dp);
1279         ironlake_edp_panel_on(intel_dp);
1280         ironlake_edp_panel_vdd_off(intel_dp, true);
1281         intel_dp_complete_link_train(intel_dp);
1282         ironlake_edp_backlight_on(intel_dp);
1283
1284         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1285
1286         if (HAS_PCH_CPT(dev))
1287                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1288 }
1289
1290 static void
1291 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1292 {
1293         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1294         struct drm_device *dev = encoder->dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1297
1298         if (mode != DRM_MODE_DPMS_ON) {
1299                 ironlake_edp_backlight_off(intel_dp);
1300                 ironlake_edp_panel_off(intel_dp);
1301
1302                 ironlake_edp_panel_vdd_on(intel_dp);
1303                 intel_dp_sink_dpms(intel_dp, mode);
1304                 intel_dp_link_down(intel_dp);
1305                 ironlake_edp_panel_vdd_off(intel_dp, false);
1306
1307                 if (is_cpu_edp(intel_dp))
1308                         ironlake_edp_pll_off(encoder);
1309         } else {
1310                 if (is_cpu_edp(intel_dp))
1311                         ironlake_edp_pll_on(encoder);
1312
1313                 ironlake_edp_panel_vdd_on(intel_dp);
1314                 intel_dp_sink_dpms(intel_dp, mode);
1315                 if (!(dp_reg & DP_PORT_EN)) {
1316                         intel_dp_start_link_train(intel_dp);
1317                         ironlake_edp_panel_on(intel_dp);
1318                         ironlake_edp_panel_vdd_off(intel_dp, true);
1319                         intel_dp_complete_link_train(intel_dp);
1320                 } else
1321                         ironlake_edp_panel_vdd_off(intel_dp, false);
1322                 ironlake_edp_backlight_on(intel_dp);
1323         }
1324         intel_dp->dpms_mode = mode;
1325 }
1326 /*
1327  * Native read with retry for link status and receiver capability reads for
1328  * cases where the sink may still be asleep.
1329  */
1330 static bool
1331 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1332                                uint8_t *recv, int recv_bytes)
1333 {
1334         int ret, i;
1335
1336         /*
1337          * Sinks are *supposed* to come up within 1ms from an off state,
1338          * but we're also supposed to retry 3 times per the spec.
1339          */
1340         for (i = 0; i < 3; i++) {
1341                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1342                                                recv_bytes);
1343                 if (ret == recv_bytes)
1344                         return true;
1345                 drm_msleep(1, "915dpl");
1346         }
1347
1348         return false;
1349 }
1350
1351 /*
1352  * Fetch AUX CH registers 0x202 - 0x207 which contain
1353  * link status information
1354  */
1355 static bool
1356 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1357 {
1358         return intel_dp_aux_native_read_retry(intel_dp,
1359                                               DP_LANE0_1_STATUS,
1360                                               link_status,
1361                                               DP_LINK_STATUS_SIZE);
1362 }
1363
1364 static uint8_t
1365 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1366                      int r)
1367 {
1368         return link_status[r - DP_LANE0_1_STATUS];
1369 }
1370
1371 static uint8_t
1372 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1373                                  int lane)
1374 {
1375         int         s = ((lane & 1) ?
1376                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1377                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1378         uint8_t l = adjust_request[lane>>1];
1379
1380         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1381 }
1382
1383 static uint8_t
1384 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1385                                       int lane)
1386 {
1387         int         s = ((lane & 1) ?
1388                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1389                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1390         uint8_t l = adjust_request[lane>>1];
1391
1392         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1393 }
1394
1395
1396 #if 0
1397 static char     *voltage_names[] = {
1398         "0.4V", "0.6V", "0.8V", "1.2V"
1399 };
1400 static char     *pre_emph_names[] = {
1401         "0dB", "3.5dB", "6dB", "9.5dB"
1402 };
1403 static char     *link_train_names[] = {
1404         "pattern 1", "pattern 2", "idle", "off"
1405 };
1406 #endif
1407
1408 /*
1409  * These are source-specific values; current Intel hardware supports
1410  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1411  */
1412
1413 static uint8_t
1414 intel_dp_voltage_max(struct intel_dp *intel_dp)
1415 {
1416         struct drm_device *dev = intel_dp->base.base.dev;
1417
1418         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1419                 return DP_TRAIN_VOLTAGE_SWING_800;
1420         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1421                 return DP_TRAIN_VOLTAGE_SWING_1200;
1422         else
1423                 return DP_TRAIN_VOLTAGE_SWING_800;
1424 }
1425
1426 static uint8_t
1427 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1428 {
1429         struct drm_device *dev = intel_dp->base.base.dev;
1430
1431         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1432                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1433                 case DP_TRAIN_VOLTAGE_SWING_400:
1434                         return DP_TRAIN_PRE_EMPHASIS_6;
1435                 case DP_TRAIN_VOLTAGE_SWING_600:
1436                 case DP_TRAIN_VOLTAGE_SWING_800:
1437                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1438                 default:
1439                         return DP_TRAIN_PRE_EMPHASIS_0;
1440                 }
1441         } else {
1442                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1443                 case DP_TRAIN_VOLTAGE_SWING_400:
1444                         return DP_TRAIN_PRE_EMPHASIS_6;
1445                 case DP_TRAIN_VOLTAGE_SWING_600:
1446                         return DP_TRAIN_PRE_EMPHASIS_6;
1447                 case DP_TRAIN_VOLTAGE_SWING_800:
1448                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1449                 case DP_TRAIN_VOLTAGE_SWING_1200:
1450                 default:
1451                         return DP_TRAIN_PRE_EMPHASIS_0;
1452                 }
1453         }
1454 }
1455
1456 static void
1457 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1458 {
1459         uint8_t v = 0;
1460         uint8_t p = 0;
1461         int lane;
1462         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1463         uint8_t voltage_max;
1464         uint8_t preemph_max;
1465
1466         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1467                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1468                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1469
1470                 if (this_v > v)
1471                         v = this_v;
1472                 if (this_p > p)
1473                         p = this_p;
1474         }
1475
1476         voltage_max = intel_dp_voltage_max(intel_dp);
1477         if (v >= voltage_max)
1478                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1479
1480         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1481         if (p >= preemph_max)
1482                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1483
1484         for (lane = 0; lane < 4; lane++)
1485                 intel_dp->train_set[lane] = v | p;
1486 }
1487
1488 static uint32_t
1489 intel_dp_signal_levels(uint8_t train_set)
1490 {
1491         uint32_t        signal_levels = 0;
1492
1493         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1494         case DP_TRAIN_VOLTAGE_SWING_400:
1495         default:
1496                 signal_levels |= DP_VOLTAGE_0_4;
1497                 break;
1498         case DP_TRAIN_VOLTAGE_SWING_600:
1499                 signal_levels |= DP_VOLTAGE_0_6;
1500                 break;
1501         case DP_TRAIN_VOLTAGE_SWING_800:
1502                 signal_levels |= DP_VOLTAGE_0_8;
1503                 break;
1504         case DP_TRAIN_VOLTAGE_SWING_1200:
1505                 signal_levels |= DP_VOLTAGE_1_2;
1506                 break;
1507         }
1508         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1509         case DP_TRAIN_PRE_EMPHASIS_0:
1510         default:
1511                 signal_levels |= DP_PRE_EMPHASIS_0;
1512                 break;
1513         case DP_TRAIN_PRE_EMPHASIS_3_5:
1514                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1515                 break;
1516         case DP_TRAIN_PRE_EMPHASIS_6:
1517                 signal_levels |= DP_PRE_EMPHASIS_6;
1518                 break;
1519         case DP_TRAIN_PRE_EMPHASIS_9_5:
1520                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1521                 break;
1522         }
1523         return signal_levels;
1524 }
1525
1526 /* Gen6's DP voltage swing and pre-emphasis control */
1527 static uint32_t
1528 intel_gen6_edp_signal_levels(uint8_t train_set)
1529 {
1530         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1531                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1532         switch (signal_levels) {
1533         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1534         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1535                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1536         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1537                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1538         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1539         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1540                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1541         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1542         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1543                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1544         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1545         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1546                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1547         default:
1548                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1549                               "0x%x\n", signal_levels);
1550                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1551         }
1552 }
1553
1554 /* Gen7's DP voltage swing and pre-emphasis control */
1555 static uint32_t
1556 intel_gen7_edp_signal_levels(uint8_t train_set)
1557 {
1558         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1559                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1560         switch (signal_levels) {
1561         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1562                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1563         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1564                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1565         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1566                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1567
1568         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1569                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1570         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1571                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1572
1573         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1574                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1575         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1576                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1577
1578         default:
1579                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1580                               "0x%x\n", signal_levels);
1581                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1582         }
1583 }
1584
1585 static uint8_t
1586 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1587                       int lane)
1588 {
1589         int s = (lane & 1) * 4;
1590         uint8_t l = link_status[lane>>1];
1591
1592         return (l >> s) & 0xf;
1593 }
1594
1595 /* Check for clock recovery is done on all channels */
1596 static bool
1597 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1598 {
1599         int lane;
1600         uint8_t lane_status;
1601
1602         for (lane = 0; lane < lane_count; lane++) {
1603                 lane_status = intel_get_lane_status(link_status, lane);
1604                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1605                         return false;
1606         }
1607         return true;
1608 }
1609
1610 /* Check to see if channel eq is done on all channels */
1611 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1612                          DP_LANE_CHANNEL_EQ_DONE|\
1613                          DP_LANE_SYMBOL_LOCKED)
1614 static bool
1615 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1616 {
1617         uint8_t lane_align;
1618         uint8_t lane_status;
1619         int lane;
1620
1621         lane_align = intel_dp_link_status(link_status,
1622                                           DP_LANE_ALIGN_STATUS_UPDATED);
1623         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1624                 return false;
1625         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1626                 lane_status = intel_get_lane_status(link_status, lane);
1627                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1628                         return false;
1629         }
1630         return true;
1631 }
1632
1633 static bool
1634 intel_dp_set_link_train(struct intel_dp *intel_dp,
1635                         uint32_t dp_reg_value,
1636                         uint8_t dp_train_pat)
1637 {
1638         struct drm_device *dev = intel_dp->base.base.dev;
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640         int ret;
1641
1642         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1643         POSTING_READ(intel_dp->output_reg);
1644
1645         intel_dp_aux_native_write_1(intel_dp,
1646                                     DP_TRAINING_PATTERN_SET,
1647                                     dp_train_pat);
1648
1649         ret = intel_dp_aux_native_write(intel_dp,
1650                                         DP_TRAINING_LANE0_SET,
1651                                         intel_dp->train_set,
1652                                         intel_dp->lane_count);
1653         if (ret != intel_dp->lane_count)
1654                 return false;
1655
1656         return true;
1657 }
1658
1659 /* Enable corresponding port and start training pattern 1 */
1660 static void
1661 intel_dp_start_link_train(struct intel_dp *intel_dp)
1662 {
1663         struct drm_device *dev = intel_dp->base.base.dev;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1666         int i;
1667         uint8_t voltage;
1668         bool clock_recovery = false;
1669         int voltage_tries, loop_tries;
1670         u32 reg;
1671         uint32_t DP = intel_dp->DP;
1672
1673         /* Enable output, wait for it to become active */
1674         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1675         POSTING_READ(intel_dp->output_reg);
1676         intel_wait_for_vblank(dev, intel_crtc->pipe);
1677
1678         /* Write the link configuration data */
1679         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1680                                   intel_dp->link_configuration,
1681                                   DP_LINK_CONFIGURATION_SIZE);
1682
1683         DP |= DP_PORT_EN;
1684
1685         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1686                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1687         else
1688                 DP &= ~DP_LINK_TRAIN_MASK;
1689         memset(intel_dp->train_set, 0, 4);
1690         voltage = 0xff;
1691         voltage_tries = 0;
1692         loop_tries = 0;
1693         clock_recovery = false;
1694         for (;;) {
1695                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1696                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1697                 uint32_t    signal_levels;
1698
1699
1700                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1701                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1702                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1703                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1704                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1705                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1706                 } else {
1707                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1708                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1709                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1710                 }
1711
1712                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1713                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1714                 else
1715                         reg = DP | DP_LINK_TRAIN_PAT_1;
1716
1717                 if (!intel_dp_set_link_train(intel_dp, reg,
1718                                              DP_TRAINING_PATTERN_1))
1719                         break;
1720                 /* Set training pattern 1 */
1721
1722                 DELAY(100);
1723                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1724                         DRM_ERROR("failed to get link status\n");
1725                         break;
1726                 }
1727
1728                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1729                         DRM_DEBUG_KMS("clock recovery OK\n");
1730                         clock_recovery = true;
1731                         break;
1732                 }
1733
1734                 /* Check to see if we've tried the max voltage */
1735                 for (i = 0; i < intel_dp->lane_count; i++)
1736                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1737                                 break;
1738                 if (i == intel_dp->lane_count) {
1739                         ++loop_tries;
1740                         if (loop_tries == 5) {
1741                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1742                                 break;
1743                         }
1744                         memset(intel_dp->train_set, 0, 4);
1745                         voltage_tries = 0;
1746                         continue;
1747                 }
1748
1749                 /* Check to see if we've tried the same voltage 5 times */
1750                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1751                         ++voltage_tries;
1752                         if (voltage_tries == 5) {
1753                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1754                                 break;
1755                         }
1756                 } else
1757                         voltage_tries = 0;
1758                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1759
1760                 /* Compute new intel_dp->train_set as requested by target */
1761                 intel_get_adjust_train(intel_dp, link_status);
1762         }
1763
1764         intel_dp->DP = DP;
1765 }
1766
1767 static void
1768 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1769 {
1770         struct drm_device *dev = intel_dp->base.base.dev;
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         bool channel_eq = false;
1773         int tries, cr_tries;
1774         u32 reg;
1775         uint32_t DP = intel_dp->DP;
1776
1777         /* channel equalization */
1778         tries = 0;
1779         cr_tries = 0;
1780         channel_eq = false;
1781         for (;;) {
1782                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1783                 uint32_t    signal_levels;
1784                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1785
1786                 if (cr_tries > 5) {
1787                         DRM_ERROR("failed to train DP, aborting\n");
1788                         intel_dp_link_down(intel_dp);
1789                         break;
1790                 }
1791
1792                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1793                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1794                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1795                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1796                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1797                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1798                 } else {
1799                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1800                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1801                 }
1802
1803                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1804                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1805                 else
1806                         reg = DP | DP_LINK_TRAIN_PAT_2;
1807
1808                 /* channel eq pattern */
1809                 if (!intel_dp_set_link_train(intel_dp, reg,
1810                                              DP_TRAINING_PATTERN_2))
1811                         break;
1812
1813                 DELAY(400);
1814                 if (!intel_dp_get_link_status(intel_dp, link_status))
1815                         break;
1816
1817                 /* Make sure clock is still ok */
1818                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1819                         intel_dp_start_link_train(intel_dp);
1820                         cr_tries++;
1821                         continue;
1822                 }
1823
1824                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1825                         channel_eq = true;
1826                         break;
1827                 }
1828
1829                 /* Try 5 times, then try clock recovery if that fails */
1830                 if (tries > 5) {
1831                         intel_dp_link_down(intel_dp);
1832                         intel_dp_start_link_train(intel_dp);
1833                         tries = 0;
1834                         cr_tries++;
1835                         continue;
1836                 }
1837
1838                 /* Compute new intel_dp->train_set as requested by target */
1839                 intel_get_adjust_train(intel_dp, link_status);
1840                 ++tries;
1841         }
1842
1843         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1844                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1845         else
1846                 reg = DP | DP_LINK_TRAIN_OFF;
1847
1848         I915_WRITE(intel_dp->output_reg, reg);
1849         POSTING_READ(intel_dp->output_reg);
1850         intel_dp_aux_native_write_1(intel_dp,
1851                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1852 }
1853
1854 static void
1855 intel_dp_link_down(struct intel_dp *intel_dp)
1856 {
1857         struct drm_device *dev = intel_dp->base.base.dev;
1858         struct drm_i915_private *dev_priv = dev->dev_private;
1859         uint32_t DP = intel_dp->DP;
1860
1861         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1862                 return;
1863
1864         DRM_DEBUG_KMS("\n");
1865
1866         if (is_edp(intel_dp)) {
1867                 DP &= ~DP_PLL_ENABLE;
1868                 I915_WRITE(intel_dp->output_reg, DP);
1869                 POSTING_READ(intel_dp->output_reg);
1870                 DELAY(100);
1871         }
1872
1873         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1874                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1875                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1876         } else {
1877                 DP &= ~DP_LINK_TRAIN_MASK;
1878                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1879         }
1880         POSTING_READ(intel_dp->output_reg);
1881
1882         drm_msleep(17, "915dlo");
1883
1884         if (is_edp(intel_dp)) {
1885                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1886                         DP |= DP_LINK_TRAIN_OFF_CPT;
1887                 else
1888                         DP |= DP_LINK_TRAIN_OFF;
1889         }
1890
1891
1892         if (!HAS_PCH_CPT(dev) &&
1893             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1894                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1895
1896                 /* Hardware workaround: leaving our transcoder select
1897                  * set to transcoder B while it's off will prevent the
1898                  * corresponding HDMI output on transcoder A.
1899                  *
1900                  * Combine this with another hardware workaround:
1901                  * transcoder select bit can only be cleared while the
1902                  * port is enabled.
1903                  */
1904                 DP &= ~DP_PIPEB_SELECT;
1905                 I915_WRITE(intel_dp->output_reg, DP);
1906
1907                 /* Changes to enable or select take place the vblank
1908                  * after being written.
1909                  */
1910                 if (crtc == NULL) {
1911                         /* We can arrive here never having been attached
1912                          * to a CRTC, for instance, due to inheriting
1913                          * random state from the BIOS.
1914                          *
1915                          * If the pipe is not running, play safe and
1916                          * wait for the clocks to stabilise before
1917                          * continuing.
1918                          */
1919                         POSTING_READ(intel_dp->output_reg);
1920                         drm_msleep(50, "915dla");
1921                 } else
1922                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1923         }
1924
1925         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1926         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1927         POSTING_READ(intel_dp->output_reg);
1928         drm_msleep(intel_dp->panel_power_down_delay, "915ldo");
1929 }
1930
1931 static bool
1932 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1933 {
1934         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1935                                            sizeof(intel_dp->dpcd)) &&
1936             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1937                 return true;
1938         }
1939
1940         return false;
1941 }
1942
1943 static bool
1944 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1945 {
1946         int ret;
1947
1948         ret = intel_dp_aux_native_read_retry(intel_dp,
1949                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1950                                              sink_irq_vector, 1);
1951         if (!ret)
1952                 return false;
1953
1954         return true;
1955 }
1956
1957 static void
1958 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1959 {
1960         /* NAK by default */
1961         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1962 }
1963
1964 /*
1965  * According to DP spec
1966  * 5.1.2:
1967  *  1. Read DPCD
1968  *  2. Configure link according to Receiver Capabilities
1969  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1970  *  4. Check link status on receipt of hot-plug interrupt
1971  */
1972
1973 static void
1974 intel_dp_check_link_status(struct intel_dp *intel_dp)
1975 {
1976         u8 sink_irq_vector;
1977         u8 link_status[DP_LINK_STATUS_SIZE];
1978
1979         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1980                 return;
1981
1982         if (!intel_dp->base.base.crtc)
1983                 return;
1984
1985         /* Try to read receiver status if the link appears to be up */
1986         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1987                 intel_dp_link_down(intel_dp);
1988                 return;
1989         }
1990
1991         /* Now read the DPCD to see if it's actually running */
1992         if (!intel_dp_get_dpcd(intel_dp)) {
1993                 intel_dp_link_down(intel_dp);
1994                 return;
1995         }
1996
1997         /* Try to read the source of the interrupt */
1998         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1999             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2000                 /* Clear interrupt source */
2001                 intel_dp_aux_native_write_1(intel_dp,
2002                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2003                                             sink_irq_vector);
2004
2005                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2006                         intel_dp_handle_test_request(intel_dp);
2007                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2008                         DRM_DEBUG_KMS("CP or sink specific irq unhandled\n");
2009         }
2010
2011         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2012                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2013                               drm_get_encoder_name(&intel_dp->base.base));
2014                 intel_dp_start_link_train(intel_dp);
2015                 intel_dp_complete_link_train(intel_dp);
2016         }
2017 }
2018
2019 static enum drm_connector_status
2020 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2021 {
2022         if (intel_dp_get_dpcd(intel_dp))
2023                 return connector_status_connected;
2024         return connector_status_disconnected;
2025 }
2026
2027 static enum drm_connector_status
2028 ironlake_dp_detect(struct intel_dp *intel_dp)
2029 {
2030         enum drm_connector_status status;
2031
2032         /* Can't disconnect eDP, but you can close the lid... */
2033         if (is_edp(intel_dp)) {
2034                 status = intel_panel_detect(intel_dp->base.base.dev);
2035                 if (status == connector_status_unknown)
2036                         status = connector_status_connected;
2037                 return status;
2038         }
2039
2040         return intel_dp_detect_dpcd(intel_dp);
2041 }
2042
2043 static enum drm_connector_status
2044 g4x_dp_detect(struct intel_dp *intel_dp)
2045 {
2046         struct drm_device *dev = intel_dp->base.base.dev;
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         uint32_t temp, bit;
2049
2050         switch (intel_dp->output_reg) {
2051         case DP_B:
2052                 bit = DPB_HOTPLUG_INT_STATUS;
2053                 break;
2054         case DP_C:
2055                 bit = DPC_HOTPLUG_INT_STATUS;
2056                 break;
2057         case DP_D:
2058                 bit = DPD_HOTPLUG_INT_STATUS;
2059                 break;
2060         default:
2061                 return connector_status_unknown;
2062         }
2063
2064         temp = I915_READ(PORT_HOTPLUG_STAT);
2065
2066         if ((temp & bit) == 0)
2067                 return connector_status_disconnected;
2068
2069         return intel_dp_detect_dpcd(intel_dp);
2070 }
2071
2072 static struct edid *
2073 intel_dp_get_edid(struct drm_connector *connector, device_t adapter)
2074 {
2075         struct intel_dp *intel_dp = intel_attached_dp(connector);
2076         struct edid     *edid;
2077
2078         ironlake_edp_panel_vdd_on(intel_dp);
2079         edid = drm_get_edid(connector, adapter);
2080         ironlake_edp_panel_vdd_off(intel_dp, false);
2081         return edid;
2082 }
2083
2084 static int
2085 intel_dp_get_edid_modes(struct drm_connector *connector, device_t adapter)
2086 {
2087         struct intel_dp *intel_dp = intel_attached_dp(connector);
2088         int     ret;
2089
2090         ironlake_edp_panel_vdd_on(intel_dp);
2091         ret = intel_ddc_get_modes(connector, adapter);
2092         ironlake_edp_panel_vdd_off(intel_dp, false);
2093         return ret;
2094 }
2095
2096
2097 /**
2098  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2099  *
2100  * \return true if DP port is connected.
2101  * \return false if DP port is disconnected.
2102  */
2103 static enum drm_connector_status
2104 intel_dp_detect(struct drm_connector *connector, bool force)
2105 {
2106         struct intel_dp *intel_dp = intel_attached_dp(connector);
2107         struct drm_device *dev = intel_dp->base.base.dev;
2108         enum drm_connector_status status;
2109         struct edid *edid = NULL;
2110
2111         intel_dp->has_audio = false;
2112
2113         if (HAS_PCH_SPLIT(dev))
2114                 status = ironlake_dp_detect(intel_dp);
2115         else
2116                 status = g4x_dp_detect(intel_dp);
2117         if (status != connector_status_connected)
2118                 return status;
2119
2120         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2121                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2122         } else {
2123                 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2124                 if (edid) {
2125                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2126                         connector->display_info.raw_edid = NULL;
2127                         free(edid, DRM_MEM_KMS);
2128                 }
2129         }
2130
2131         return connector_status_connected;
2132 }
2133
2134 static int intel_dp_get_modes(struct drm_connector *connector)
2135 {
2136         struct intel_dp *intel_dp = intel_attached_dp(connector);
2137         struct drm_device *dev = intel_dp->base.base.dev;
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139         int ret;
2140
2141         /* We should parse the EDID data and find out if it has an audio sink
2142          */
2143
2144         ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2145         if (ret) {
2146                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2147                         struct drm_display_mode *newmode;
2148                         list_for_each_entry(newmode, &connector->probed_modes,
2149                                             head) {
2150                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2151                                         intel_dp->panel_fixed_mode =
2152                                                 drm_mode_duplicate(dev, newmode);
2153                                         break;
2154                                 }
2155                         }
2156                 }
2157                 return ret;
2158         }
2159
2160         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2161         if (is_edp(intel_dp)) {
2162                 /* initialize panel mode from VBT if available for eDP */
2163                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2164                         intel_dp->panel_fixed_mode =
2165                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2166                         if (intel_dp->panel_fixed_mode) {
2167                                 intel_dp->panel_fixed_mode->type |=
2168                                         DRM_MODE_TYPE_PREFERRED;
2169                         }
2170                 }
2171                 if (intel_dp->panel_fixed_mode) {
2172                         struct drm_display_mode *mode;
2173                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2174                         drm_mode_probed_add(connector, mode);
2175                         return 1;
2176                 }
2177         }
2178         return 0;
2179 }
2180
2181 static bool
2182 intel_dp_detect_audio(struct drm_connector *connector)
2183 {
2184         struct intel_dp *intel_dp = intel_attached_dp(connector);
2185         struct edid *edid;
2186         bool has_audio = false;
2187
2188         edid = intel_dp_get_edid(connector, intel_dp->adapter);
2189         if (edid) {
2190                 has_audio = drm_detect_monitor_audio(edid);
2191
2192                 connector->display_info.raw_edid = NULL;
2193                 free(edid, DRM_MEM_KMS);
2194         }
2195
2196         return has_audio;
2197 }
2198
2199 static int
2200 intel_dp_set_property(struct drm_connector *connector,
2201                       struct drm_property *property,
2202                       uint64_t val)
2203 {
2204         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2205         struct intel_dp *intel_dp = intel_attached_dp(connector);
2206         int ret;
2207
2208         ret = drm_connector_property_set_value(connector, property, val);
2209         if (ret)
2210                 return ret;
2211
2212         if (property == dev_priv->force_audio_property) {
2213                 int i = val;
2214                 bool has_audio;
2215
2216                 if (i == intel_dp->force_audio)
2217                         return 0;
2218
2219                 intel_dp->force_audio = i;
2220
2221                 if (i == HDMI_AUDIO_AUTO)
2222                         has_audio = intel_dp_detect_audio(connector);
2223                 else
2224                         has_audio = (i == HDMI_AUDIO_ON);
2225
2226                 if (has_audio == intel_dp->has_audio)
2227                         return 0;
2228
2229                 intel_dp->has_audio = has_audio;
2230                 goto done;
2231         }
2232
2233         if (property == dev_priv->broadcast_rgb_property) {
2234                 if (val == !!intel_dp->color_range)
2235                         return 0;
2236
2237                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2238                 goto done;
2239         }
2240
2241         return -EINVAL;
2242
2243 done:
2244         if (intel_dp->base.base.crtc) {
2245                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2246                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2247                                          crtc->x, crtc->y,
2248                                          crtc->fb);
2249         }
2250
2251         return 0;
2252 }
2253
2254 static void
2255 intel_dp_destroy(struct drm_connector *connector)
2256 {
2257         struct drm_device *dev = connector->dev;
2258
2259         if (intel_dpd_is_edp(dev))
2260                 intel_panel_destroy_backlight(dev);
2261
2262 #if 0
2263         drm_sysfs_connector_remove(connector);
2264 #endif
2265         drm_connector_cleanup(connector);
2266         free(connector, DRM_MEM_KMS);
2267 }
2268
2269 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2270 {
2271         struct drm_device *dev;
2272         struct intel_dp *intel_dp;
2273
2274         intel_dp = enc_to_intel_dp(encoder);
2275         dev = encoder->dev;
2276
2277         if (intel_dp->dp_iic_bus != NULL) {
2278                 if (intel_dp->adapter != NULL) {
2279                         device_delete_child(intel_dp->dp_iic_bus,
2280                             intel_dp->adapter);
2281                 }
2282                 device_delete_child(dev->device, intel_dp->dp_iic_bus);
2283         }
2284         drm_encoder_cleanup(encoder);
2285         if (is_edp(intel_dp)) {
2286                 struct drm_i915_private *dev_priv = intel_dp->base.base.dev->dev_private;
2287
2288                 taskqueue_cancel_timeout(dev_priv->tq,
2289                     &intel_dp->panel_vdd_task, NULL);
2290                 taskqueue_drain_timeout(dev_priv->tq,
2291                     &intel_dp->panel_vdd_task);
2292                 ironlake_panel_vdd_off_sync(intel_dp);
2293         }
2294         free(intel_dp, DRM_MEM_KMS);
2295 }
2296
2297 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2298         .dpms = intel_dp_dpms,
2299         .mode_fixup = intel_dp_mode_fixup,
2300         .prepare = intel_dp_prepare,
2301         .mode_set = intel_dp_mode_set,
2302         .commit = intel_dp_commit,
2303 };
2304
2305 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2306         .dpms = drm_helper_connector_dpms,
2307         .detect = intel_dp_detect,
2308         .fill_modes = drm_helper_probe_single_connector_modes,
2309         .set_property = intel_dp_set_property,
2310         .destroy = intel_dp_destroy,
2311 };
2312
2313 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2314         .get_modes = intel_dp_get_modes,
2315         .mode_valid = intel_dp_mode_valid,
2316         .best_encoder = intel_best_encoder,
2317 };
2318
2319 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2320         .destroy = intel_dp_encoder_destroy,
2321 };
2322
2323 static void
2324 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2325 {
2326         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2327
2328         intel_dp_check_link_status(intel_dp);
2329 }
2330
2331 /* Return which DP Port should be selected for Transcoder DP control */
2332 int
2333 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2334 {
2335         struct drm_device *dev = crtc->dev;
2336         struct drm_mode_config *mode_config = &dev->mode_config;
2337         struct drm_encoder *encoder;
2338
2339         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2340                 struct intel_dp *intel_dp;
2341
2342                 if (encoder->crtc != crtc)
2343                         continue;
2344
2345                 intel_dp = enc_to_intel_dp(encoder);
2346                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2347                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2348                         return intel_dp->output_reg;
2349         }
2350
2351         return -1;
2352 }
2353
2354 /* check the VBT to see whether the eDP is on DP-D port */
2355 bool intel_dpd_is_edp(struct drm_device *dev)
2356 {
2357         struct drm_i915_private *dev_priv = dev->dev_private;
2358         struct child_device_config *p_child;
2359         int i;
2360
2361         if (!dev_priv->child_dev_num)
2362                 return false;
2363
2364         for (i = 0; i < dev_priv->child_dev_num; i++) {
2365                 p_child = dev_priv->child_dev + i;
2366
2367                 if (p_child->dvo_port == PORT_IDPD &&
2368                     p_child->device_type == DEVICE_TYPE_eDP)
2369                         return true;
2370         }
2371         return false;
2372 }
2373
2374 static void
2375 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2376 {
2377         intel_attach_force_audio_property(connector);
2378         intel_attach_broadcast_rgb_property(connector);
2379 }
2380
2381 void
2382 intel_dp_init(struct drm_device *dev, int output_reg)
2383 {
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_connector *connector;
2386         struct intel_dp *intel_dp;
2387         struct intel_encoder *intel_encoder;
2388         struct intel_connector *intel_connector;
2389         const char *name = NULL;
2390         int type;
2391
2392         intel_dp = malloc(sizeof(struct intel_dp), DRM_MEM_KMS,
2393             M_WAITOK | M_ZERO);
2394
2395         intel_dp->output_reg = output_reg;
2396         intel_dp->dpms_mode = -1;
2397
2398         intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS,
2399             M_WAITOK | M_ZERO);
2400         intel_encoder = &intel_dp->base;
2401
2402         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2403                 if (intel_dpd_is_edp(dev))
2404                         intel_dp->is_pch_edp = true;
2405
2406         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2407                 type = DRM_MODE_CONNECTOR_eDP;
2408                 intel_encoder->type = INTEL_OUTPUT_EDP;
2409         } else {
2410                 type = DRM_MODE_CONNECTOR_DisplayPort;
2411                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2412         }
2413
2414         connector = &intel_connector->base;
2415         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2416         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2417
2418         connector->polled = DRM_CONNECTOR_POLL_HPD;
2419
2420         if (output_reg == DP_B || output_reg == PCH_DP_B)
2421                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2422         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2423                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2424         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2425                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2426
2427         if (is_edp(intel_dp)) {
2428                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2429                 TIMEOUT_TASK_INIT(dev_priv->tq, &intel_dp->panel_vdd_task, 0,
2430                     ironlake_panel_vdd_work, intel_dp);
2431         }
2432
2433         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2434         connector->interlace_allowed = true;
2435         connector->doublescan_allowed = 0;
2436
2437         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2438                          DRM_MODE_ENCODER_TMDS);
2439         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2440
2441         intel_connector_attach_encoder(intel_connector, intel_encoder);
2442 #if 0
2443         drm_sysfs_connector_add(connector);
2444 #endif
2445
2446         /* Set up the DDC bus. */
2447         switch (output_reg) {
2448                 case DP_A:
2449                         name = "DPDDC-A";
2450                         break;
2451                 case DP_B:
2452                 case PCH_DP_B:
2453                         dev_priv->hotplug_supported_mask |=
2454                                 HDMIB_HOTPLUG_INT_STATUS;
2455                         name = "DPDDC-B";
2456                         break;
2457                 case DP_C:
2458                 case PCH_DP_C:
2459                         dev_priv->hotplug_supported_mask |=
2460                                 HDMIC_HOTPLUG_INT_STATUS;
2461                         name = "DPDDC-C";
2462                         break;
2463                 case DP_D:
2464                 case PCH_DP_D:
2465                         dev_priv->hotplug_supported_mask |=
2466                                 HDMID_HOTPLUG_INT_STATUS;
2467                         name = "DPDDC-D";
2468                         break;
2469         }
2470
2471         /* Cache some DPCD data in the eDP case */
2472         if (is_edp(intel_dp)) {
2473                 bool ret;
2474                 struct edp_power_seq    cur, vbt;
2475                 u32 pp_on, pp_off, pp_div;
2476
2477                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2478                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2479                 pp_div = I915_READ(PCH_PP_DIVISOR);
2480
2481                 /* Pull timing values out of registers */
2482                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2483                         PANEL_POWER_UP_DELAY_SHIFT;
2484
2485                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2486                         PANEL_LIGHT_ON_DELAY_SHIFT;
2487
2488                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2489                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2490
2491                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2492                         PANEL_POWER_DOWN_DELAY_SHIFT;
2493
2494                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2495                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2496
2497                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2498                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2499
2500                 vbt = dev_priv->edp.pps;
2501
2502                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2503                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2504
2505 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2506
2507                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2508                 intel_dp->backlight_on_delay = get_delay(t8);
2509                 intel_dp->backlight_off_delay = get_delay(t9);
2510                 intel_dp->panel_power_down_delay = get_delay(t10);
2511                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2512
2513                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2514                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2515                               intel_dp->panel_power_cycle_delay);
2516
2517                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2518                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2519
2520                 ironlake_edp_panel_vdd_on(intel_dp);
2521                 ret = intel_dp_get_dpcd(intel_dp);
2522                 ironlake_edp_panel_vdd_off(intel_dp, false);
2523
2524                 if (ret) {
2525                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2526                                 dev_priv->no_aux_handshake =
2527                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2528                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2529                 } else {
2530                         /* if this fails, presume the device is a ghost */
2531                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2532                         intel_dp_encoder_destroy(&intel_dp->base.base);
2533                         intel_dp_destroy(&intel_connector->base);
2534                         return;
2535                 }
2536         }
2537
2538         intel_dp_i2c_init(intel_dp, intel_connector, name);
2539
2540         intel_encoder->hot_plug = intel_dp_hot_plug;
2541
2542         if (is_edp(intel_dp)) {
2543                 dev_priv->int_edp_connector = connector;
2544                 intel_panel_setup_backlight(dev);
2545         }
2546
2547         intel_dp_add_properties(intel_dp, connector);
2548
2549         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2550          * 0xd.  Failure to do so will result in spurious interrupts being
2551          * generated on the port when a cable is not attached.
2552          */
2553         if (IS_G4X(dev) && !IS_GM45(dev)) {
2554                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2555                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2556         }
2557 }