2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm_crtc.h>
34 #include <dev/drm2/drm_edid.h>
35 #include <dev/drm2/i915/intel_drv.h>
36 #include <dev/drm2/i915/i915_drm.h>
37 #include <dev/drm2/i915/i915_drv.h>
39 #define mmiowb() barrier()
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
73 uint8_t *data = (uint8_t *)frame;
80 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
83 frame->checksum = 0x100 - sum;
86 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
88 switch (frame->type) {
90 return VIDEO_DIP_SELECT_AVI;
92 return VIDEO_DIP_SELECT_SPD;
94 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
99 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
101 switch (frame->type) {
103 return VIDEO_DIP_ENABLE_AVI;
105 return VIDEO_DIP_ENABLE_SPD;
107 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
112 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
114 switch (frame->type) {
116 return VIDEO_DIP_ENABLE_AVI_HSW;
118 return VIDEO_DIP_ENABLE_SPD_HSW;
120 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
125 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
127 switch (frame->type) {
129 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
131 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
133 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
138 static void g4x_write_infoframe(struct drm_encoder *encoder,
139 struct dip_infoframe *frame)
141 uint32_t *data = (uint32_t *)frame;
142 struct drm_device *dev = encoder->dev;
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 u32 val = I915_READ(VIDEO_DIP_CTL);
145 unsigned i, len = DIP_HEADER_SIZE + frame->len;
147 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
149 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
150 val |= g4x_infoframe_index(frame);
152 val &= ~g4x_infoframe_enable(frame);
154 I915_WRITE(VIDEO_DIP_CTL, val);
157 for (i = 0; i < len; i += 4) {
158 I915_WRITE(VIDEO_DIP_DATA, *data);
161 /* Write every possible data byte to force correct ECC calculation. */
162 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
163 I915_WRITE(VIDEO_DIP_DATA, 0);
166 val |= g4x_infoframe_enable(frame);
167 val &= ~VIDEO_DIP_FREQ_MASK;
168 val |= VIDEO_DIP_FREQ_VSYNC;
170 I915_WRITE(VIDEO_DIP_CTL, val);
171 POSTING_READ(VIDEO_DIP_CTL);
174 static void ibx_write_infoframe(struct drm_encoder *encoder,
175 struct dip_infoframe *frame)
177 uint32_t *data = (uint32_t *)frame;
178 struct drm_device *dev = encoder->dev;
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
181 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
182 unsigned i, len = DIP_HEADER_SIZE + frame->len;
183 u32 val = I915_READ(reg);
185 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
187 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
188 val |= g4x_infoframe_index(frame);
190 val &= ~g4x_infoframe_enable(frame);
192 I915_WRITE(reg, val);
195 for (i = 0; i < len; i += 4) {
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
199 /* Write every possible data byte to force correct ECC calculation. */
200 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
201 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
204 val |= g4x_infoframe_enable(frame);
205 val &= ~VIDEO_DIP_FREQ_MASK;
206 val |= VIDEO_DIP_FREQ_VSYNC;
208 I915_WRITE(reg, val);
212 static void cpt_write_infoframe(struct drm_encoder *encoder,
213 struct dip_infoframe *frame)
215 uint32_t *data = (uint32_t *)frame;
216 struct drm_device *dev = encoder->dev;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
219 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
220 unsigned i, len = DIP_HEADER_SIZE + frame->len;
221 u32 val = I915_READ(reg);
223 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
226 val |= g4x_infoframe_index(frame);
228 /* The DIP control register spec says that we need to update the AVI
229 * infoframe without clearing its enable bit */
230 if (frame->type != DIP_TYPE_AVI)
231 val &= ~g4x_infoframe_enable(frame);
233 I915_WRITE(reg, val);
236 for (i = 0; i < len; i += 4) {
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
240 /* Write every possible data byte to force correct ECC calculation. */
241 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
242 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
245 val |= g4x_infoframe_enable(frame);
246 val &= ~VIDEO_DIP_FREQ_MASK;
247 val |= VIDEO_DIP_FREQ_VSYNC;
249 I915_WRITE(reg, val);
253 static void vlv_write_infoframe(struct drm_encoder *encoder,
254 struct dip_infoframe *frame)
256 uint32_t *data = (uint32_t *)frame;
257 struct drm_device *dev = encoder->dev;
258 struct drm_i915_private *dev_priv = dev->dev_private;
259 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
260 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
261 unsigned i, len = DIP_HEADER_SIZE + frame->len;
262 u32 val = I915_READ(reg);
264 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
266 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
267 val |= g4x_infoframe_index(frame);
269 val &= ~g4x_infoframe_enable(frame);
271 I915_WRITE(reg, val);
274 for (i = 0; i < len; i += 4) {
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
278 /* Write every possible data byte to force correct ECC calculation. */
279 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
280 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
283 val |= g4x_infoframe_enable(frame);
284 val &= ~VIDEO_DIP_FREQ_MASK;
285 val |= VIDEO_DIP_FREQ_VSYNC;
287 I915_WRITE(reg, val);
291 static void hsw_write_infoframe(struct drm_encoder *encoder,
292 struct dip_infoframe *frame)
294 uint32_t *data = (uint32_t *)frame;
295 struct drm_device *dev = encoder->dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
298 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
299 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
300 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
301 u32 val = I915_READ(ctl_reg);
306 val &= ~hsw_infoframe_enable(frame);
307 I915_WRITE(ctl_reg, val);
310 for (i = 0; i < len; i += 4) {
311 I915_WRITE(data_reg + i, *data);
314 /* Write every possible data byte to force correct ECC calculation. */
315 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
316 I915_WRITE(data_reg + i, 0);
319 val |= hsw_infoframe_enable(frame);
320 I915_WRITE(ctl_reg, val);
321 POSTING_READ(ctl_reg);
324 static void intel_set_infoframe(struct drm_encoder *encoder,
325 struct dip_infoframe *frame)
327 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
329 intel_dip_infoframe_csum(frame);
330 intel_hdmi->write_infoframe(encoder, frame);
333 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
334 struct drm_display_mode *adjusted_mode)
336 struct dip_infoframe avi_if = {
337 .type = DIP_TYPE_AVI,
338 .ver = DIP_VERSION_AVI,
342 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
343 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
345 avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
347 intel_set_infoframe(encoder, &avi_if);
350 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
352 struct dip_infoframe spd_if;
354 memset(&spd_if, 0, sizeof(spd_if));
355 spd_if.type = DIP_TYPE_SPD;
356 spd_if.ver = DIP_VERSION_SPD;
357 spd_if.len = DIP_LEN_SPD;
358 strcpy(spd_if.body.spd.vn, "Intel");
359 strcpy(spd_if.body.spd.pd, "Integrated gfx");
360 spd_if.body.spd.sdi = DIP_SPD_PC;
362 intel_set_infoframe(encoder, &spd_if);
365 static void g4x_set_infoframes(struct drm_encoder *encoder,
366 struct drm_display_mode *adjusted_mode)
368 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
369 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
370 u32 reg = VIDEO_DIP_CTL;
371 u32 val = I915_READ(reg);
374 assert_hdmi_port_disabled(intel_hdmi);
376 /* If the registers were not initialized yet, they might be zeroes,
377 * which means we're selecting the AVI DIP and we're setting its
378 * frequency to once. This seems to really confuse the HW and make
379 * things stop working (the register spec says the AVI always needs to
380 * be sent every VSync). So here we avoid writing to the register more
381 * than we need and also explicitly select the AVI DIP and explicitly
382 * set its frequency to every VSync. Avoiding to write it twice seems to
383 * be enough to solve the problem, but being defensive shouldn't hurt us
385 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
387 if (!intel_hdmi->has_hdmi_sink) {
388 if (!(val & VIDEO_DIP_ENABLE))
390 val &= ~VIDEO_DIP_ENABLE;
391 I915_WRITE(reg, val);
396 switch (intel_hdmi->sdvox_reg) {
398 port = VIDEO_DIP_PORT_B;
401 port = VIDEO_DIP_PORT_C;
408 if (port != (val & VIDEO_DIP_PORT_MASK)) {
409 if (val & VIDEO_DIP_ENABLE) {
410 val &= ~VIDEO_DIP_ENABLE;
411 I915_WRITE(reg, val);
414 val &= ~VIDEO_DIP_PORT_MASK;
418 val |= VIDEO_DIP_ENABLE;
419 val &= ~VIDEO_DIP_ENABLE_VENDOR;
421 I915_WRITE(reg, val);
424 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
425 intel_hdmi_set_spd_infoframe(encoder);
428 static void ibx_set_infoframes(struct drm_encoder *encoder,
429 struct drm_display_mode *adjusted_mode)
431 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
432 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
433 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
434 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
435 u32 val = I915_READ(reg);
438 assert_hdmi_port_disabled(intel_hdmi);
440 /* See the big comment in g4x_set_infoframes() */
441 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
443 if (!intel_hdmi->has_hdmi_sink) {
444 if (!(val & VIDEO_DIP_ENABLE))
446 val &= ~VIDEO_DIP_ENABLE;
447 I915_WRITE(reg, val);
452 switch (intel_hdmi->sdvox_reg) {
454 port = VIDEO_DIP_PORT_B;
457 port = VIDEO_DIP_PORT_C;
460 port = VIDEO_DIP_PORT_D;
467 if (port != (val & VIDEO_DIP_PORT_MASK)) {
468 if (val & VIDEO_DIP_ENABLE) {
469 val &= ~VIDEO_DIP_ENABLE;
470 I915_WRITE(reg, val);
473 val &= ~VIDEO_DIP_PORT_MASK;
477 val |= VIDEO_DIP_ENABLE;
478 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
479 VIDEO_DIP_ENABLE_GCP);
481 I915_WRITE(reg, val);
484 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
485 intel_hdmi_set_spd_infoframe(encoder);
488 static void cpt_set_infoframes(struct drm_encoder *encoder,
489 struct drm_display_mode *adjusted_mode)
491 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
492 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
493 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
494 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
495 u32 val = I915_READ(reg);
497 assert_hdmi_port_disabled(intel_hdmi);
499 /* See the big comment in g4x_set_infoframes() */
500 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
502 if (!intel_hdmi->has_hdmi_sink) {
503 if (!(val & VIDEO_DIP_ENABLE))
505 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
506 I915_WRITE(reg, val);
511 /* Set both together, unset both together: see the spec. */
512 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
513 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
514 VIDEO_DIP_ENABLE_GCP);
516 I915_WRITE(reg, val);
519 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
520 intel_hdmi_set_spd_infoframe(encoder);
523 static void vlv_set_infoframes(struct drm_encoder *encoder,
524 struct drm_display_mode *adjusted_mode)
526 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
527 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
528 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
529 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
530 u32 val = I915_READ(reg);
532 assert_hdmi_port_disabled(intel_hdmi);
534 /* See the big comment in g4x_set_infoframes() */
535 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
537 if (!intel_hdmi->has_hdmi_sink) {
538 if (!(val & VIDEO_DIP_ENABLE))
540 val &= ~VIDEO_DIP_ENABLE;
541 I915_WRITE(reg, val);
546 val |= VIDEO_DIP_ENABLE;
547 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
548 VIDEO_DIP_ENABLE_GCP);
550 I915_WRITE(reg, val);
553 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
554 intel_hdmi_set_spd_infoframe(encoder);
557 static void hsw_set_infoframes(struct drm_encoder *encoder,
558 struct drm_display_mode *adjusted_mode)
560 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
561 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
562 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
563 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
564 u32 val = I915_READ(reg);
566 assert_hdmi_port_disabled(intel_hdmi);
568 if (!intel_hdmi->has_hdmi_sink) {
574 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
575 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
577 I915_WRITE(reg, val);
580 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
581 intel_hdmi_set_spd_infoframe(encoder);
584 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
585 struct drm_display_mode *mode,
586 struct drm_display_mode *adjusted_mode)
588 struct drm_device *dev = encoder->dev;
589 struct drm_i915_private *dev_priv = dev->dev_private;
590 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
591 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
594 sdvox = SDVO_ENCODING_HDMI;
595 if (!HAS_PCH_SPLIT(dev))
596 sdvox |= intel_hdmi->color_range;
597 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
598 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
599 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
600 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
602 if (intel_crtc->bpp > 24)
603 sdvox |= COLOR_FORMAT_12bpc;
605 sdvox |= COLOR_FORMAT_8bpc;
607 /* Required on CPT */
608 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
609 sdvox |= HDMI_MODE_SELECT;
611 if (intel_hdmi->has_audio) {
612 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
613 pipe_name(intel_crtc->pipe));
614 sdvox |= SDVO_AUDIO_ENABLE;
615 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
616 intel_write_eld(encoder, adjusted_mode);
619 if (HAS_PCH_CPT(dev))
620 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
621 else if (intel_crtc->pipe == PIPE_B)
622 sdvox |= SDVO_PIPE_B_SELECT;
624 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
625 POSTING_READ(intel_hdmi->sdvox_reg);
627 intel_hdmi->set_infoframes(encoder, adjusted_mode);
630 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
633 struct drm_device *dev = encoder->base.dev;
634 struct drm_i915_private *dev_priv = dev->dev_private;
635 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
638 tmp = I915_READ(intel_hdmi->sdvox_reg);
640 if (!(tmp & SDVO_ENABLE))
643 if (HAS_PCH_CPT(dev))
644 *pipe = PORT_TO_PIPE_CPT(tmp);
646 *pipe = PORT_TO_PIPE(tmp);
651 static void intel_enable_hdmi(struct intel_encoder *encoder)
653 struct drm_device *dev = encoder->base.dev;
654 struct drm_i915_private *dev_priv = dev->dev_private;
655 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
657 u32 enable_bits = SDVO_ENABLE;
659 if (intel_hdmi->has_audio)
660 enable_bits |= SDVO_AUDIO_ENABLE;
662 temp = I915_READ(intel_hdmi->sdvox_reg);
664 /* HW workaround for IBX, we need to move the port to transcoder A
665 * before disabling it. */
666 if (HAS_PCH_IBX(dev)) {
667 struct drm_crtc *crtc = encoder->base.crtc;
668 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
670 /* Restore the transcoder select bit. */
672 enable_bits |= SDVO_PIPE_B_SELECT;
675 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
676 * we do this anyway which shows more stable in testing.
678 if (HAS_PCH_SPLIT(dev)) {
679 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
680 POSTING_READ(intel_hdmi->sdvox_reg);
685 I915_WRITE(intel_hdmi->sdvox_reg, temp);
686 POSTING_READ(intel_hdmi->sdvox_reg);
688 /* HW workaround, need to write this twice for issue that may result
689 * in first write getting masked.
691 if (HAS_PCH_SPLIT(dev)) {
692 I915_WRITE(intel_hdmi->sdvox_reg, temp);
693 POSTING_READ(intel_hdmi->sdvox_reg);
697 static void intel_disable_hdmi(struct intel_encoder *encoder)
699 struct drm_device *dev = encoder->base.dev;
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
703 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
705 temp = I915_READ(intel_hdmi->sdvox_reg);
707 /* HW workaround for IBX, we need to move the port to transcoder A
708 * before disabling it. */
709 if (HAS_PCH_IBX(dev)) {
710 struct drm_crtc *crtc = encoder->base.crtc;
711 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
713 if (temp & SDVO_PIPE_B_SELECT) {
714 temp &= ~SDVO_PIPE_B_SELECT;
715 I915_WRITE(intel_hdmi->sdvox_reg, temp);
716 POSTING_READ(intel_hdmi->sdvox_reg);
718 /* Again we need to write this twice. */
719 I915_WRITE(intel_hdmi->sdvox_reg, temp);
720 POSTING_READ(intel_hdmi->sdvox_reg);
722 /* Transcoder selection bits only update
723 * effectively on vblank. */
725 intel_wait_for_vblank(dev, pipe);
731 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
732 * we do this anyway which shows more stable in testing.
734 if (HAS_PCH_SPLIT(dev)) {
735 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
736 POSTING_READ(intel_hdmi->sdvox_reg);
739 temp &= ~enable_bits;
741 I915_WRITE(intel_hdmi->sdvox_reg, temp);
742 POSTING_READ(intel_hdmi->sdvox_reg);
744 /* HW workaround, need to write this twice for issue that may result
745 * in first write getting masked.
747 if (HAS_PCH_SPLIT(dev)) {
748 I915_WRITE(intel_hdmi->sdvox_reg, temp);
749 POSTING_READ(intel_hdmi->sdvox_reg);
753 static int intel_hdmi_mode_valid(struct drm_connector *connector,
754 struct drm_display_mode *mode)
756 if (mode->clock > 165000)
757 return MODE_CLOCK_HIGH;
758 if (mode->clock < 20000)
759 return MODE_CLOCK_LOW;
761 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
762 return MODE_NO_DBLESCAN;
767 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
768 const struct drm_display_mode *mode,
769 struct drm_display_mode *adjusted_mode)
774 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
776 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
777 struct drm_i915_private *dev_priv = dev->dev_private;
780 switch (intel_hdmi->sdvox_reg) {
782 bit = HDMIB_HOTPLUG_LIVE_STATUS;
785 bit = HDMIC_HOTPLUG_LIVE_STATUS;
792 return I915_READ(PORT_HOTPLUG_STAT) & bit;
795 static enum drm_connector_status
796 intel_hdmi_detect(struct drm_connector *connector, bool force)
798 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
799 struct intel_digital_port *intel_dig_port =
800 hdmi_to_dig_port(intel_hdmi);
801 struct intel_encoder *intel_encoder = &intel_dig_port->base;
802 struct drm_i915_private *dev_priv = connector->dev->dev_private;
804 enum drm_connector_status status = connector_status_disconnected;
806 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
809 intel_hdmi->has_hdmi_sink = false;
810 intel_hdmi->has_audio = false;
811 edid = drm_get_edid(connector,
812 intel_gmbus_get_adapter(dev_priv,
813 intel_hdmi->ddc_bus));
816 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
817 status = connector_status_connected;
818 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
819 intel_hdmi->has_hdmi_sink =
820 drm_detect_hdmi_monitor(edid);
821 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
823 free(edid, DRM_MEM_KMS);
826 if (status == connector_status_connected) {
827 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
828 intel_hdmi->has_audio =
829 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
830 intel_encoder->type = INTEL_OUTPUT_HDMI;
836 static int intel_hdmi_get_modes(struct drm_connector *connector)
838 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
839 struct drm_i915_private *dev_priv = connector->dev->dev_private;
841 /* We should parse the EDID data and find out if it's an HDMI sink so
842 * we can send audio to it.
845 return intel_ddc_get_modes(connector,
846 intel_gmbus_get_adapter(dev_priv,
847 intel_hdmi->ddc_bus));
851 intel_hdmi_detect_audio(struct drm_connector *connector)
853 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
854 struct drm_i915_private *dev_priv = connector->dev->dev_private;
856 bool has_audio = false;
858 edid = drm_get_edid(connector,
859 intel_gmbus_get_adapter(dev_priv,
860 intel_hdmi->ddc_bus));
862 if (edid->input & DRM_EDID_INPUT_DIGITAL)
863 has_audio = drm_detect_monitor_audio(edid);
864 free(edid, DRM_MEM_KMS);
871 intel_hdmi_set_property(struct drm_connector *connector,
872 struct drm_property *property,
875 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
876 struct intel_digital_port *intel_dig_port =
877 hdmi_to_dig_port(intel_hdmi);
878 struct drm_i915_private *dev_priv = connector->dev->dev_private;
881 ret = drm_object_property_set_value(&connector->base, property, val);
885 if (property == dev_priv->force_audio_property) {
886 enum hdmi_force_audio i = val;
889 if (i == intel_hdmi->force_audio)
892 intel_hdmi->force_audio = i;
894 if (i == HDMI_AUDIO_AUTO)
895 has_audio = intel_hdmi_detect_audio(connector);
897 has_audio = (i == HDMI_AUDIO_ON);
899 if (i == HDMI_AUDIO_OFF_DVI)
900 intel_hdmi->has_hdmi_sink = 0;
902 intel_hdmi->has_audio = has_audio;
906 if (property == dev_priv->broadcast_rgb_property) {
907 if (val == !!intel_hdmi->color_range)
910 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
917 if (intel_dig_port->base.base.crtc) {
918 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
919 intel_set_mode(crtc, &crtc->mode,
920 crtc->x, crtc->y, crtc->fb);
926 static void intel_hdmi_destroy(struct drm_connector *connector)
928 drm_connector_cleanup(connector);
929 free(connector, DRM_MEM_KMS);
932 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
933 .mode_fixup = intel_hdmi_mode_fixup,
934 .mode_set = intel_hdmi_mode_set,
935 .disable = intel_encoder_noop,
938 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
939 .dpms = intel_connector_dpms,
940 .detect = intel_hdmi_detect,
941 .fill_modes = drm_helper_probe_single_connector_modes,
942 .set_property = intel_hdmi_set_property,
943 .destroy = intel_hdmi_destroy,
946 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
947 .get_modes = intel_hdmi_get_modes,
948 .mode_valid = intel_hdmi_mode_valid,
949 .best_encoder = intel_best_encoder,
952 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
953 .destroy = intel_encoder_destroy,
957 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
959 intel_attach_force_audio_property(connector);
960 intel_attach_broadcast_rgb_property(connector);
963 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
964 struct intel_connector *intel_connector)
966 struct drm_connector *connector = &intel_connector->base;
967 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
968 struct intel_encoder *intel_encoder = &intel_dig_port->base;
969 struct drm_device *dev = intel_encoder->base.dev;
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 enum port port = intel_dig_port->port;
973 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
974 DRM_MODE_CONNECTOR_HDMIA);
975 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
977 connector->polled = DRM_CONNECTOR_POLL_HPD;
978 connector->interlace_allowed = 1;
979 connector->doublescan_allowed = 0;
983 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
984 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
987 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
988 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
991 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
992 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
995 /* Internal port only for eDP. */
1000 if (!HAS_PCH_SPLIT(dev)) {
1001 intel_hdmi->write_infoframe = g4x_write_infoframe;
1002 intel_hdmi->set_infoframes = g4x_set_infoframes;
1003 } else if (IS_VALLEYVIEW(dev)) {
1004 intel_hdmi->write_infoframe = vlv_write_infoframe;
1005 intel_hdmi->set_infoframes = vlv_set_infoframes;
1006 } else if (IS_HASWELL(dev)) {
1007 intel_hdmi->write_infoframe = hsw_write_infoframe;
1008 intel_hdmi->set_infoframes = hsw_set_infoframes;
1009 } else if (HAS_PCH_IBX(dev)) {
1010 intel_hdmi->write_infoframe = ibx_write_infoframe;
1011 intel_hdmi->set_infoframes = ibx_set_infoframes;
1013 intel_hdmi->write_infoframe = cpt_write_infoframe;
1014 intel_hdmi->set_infoframes = cpt_set_infoframes;
1017 if (IS_HASWELL(dev))
1018 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1020 intel_connector->get_hw_state = intel_connector_get_hw_state;
1022 intel_hdmi_add_properties(intel_hdmi, connector);
1024 intel_connector_attach_encoder(intel_connector, intel_encoder);
1026 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1027 * 0xd. Failure to do so will result in spurious interrupts being
1028 * generated on the port when a cable is not attached.
1030 if (IS_G4X(dev) && !IS_GM45(dev)) {
1031 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1032 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1036 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
1038 struct intel_digital_port *intel_dig_port;
1039 struct intel_encoder *intel_encoder;
1040 struct drm_encoder *encoder;
1041 struct intel_connector *intel_connector;
1043 intel_dig_port = malloc(sizeof(struct intel_digital_port), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1044 if (!intel_dig_port)
1047 intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1048 if (!intel_connector) {
1049 free(intel_dig_port, DRM_MEM_KMS);
1053 intel_encoder = &intel_dig_port->base;
1054 encoder = &intel_encoder->base;
1056 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1057 DRM_MODE_ENCODER_TMDS);
1058 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1060 intel_encoder->enable = intel_enable_hdmi;
1061 intel_encoder->disable = intel_disable_hdmi;
1062 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1064 intel_encoder->type = INTEL_OUTPUT_HDMI;
1065 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1066 intel_encoder->cloneable = false;
1068 intel_dig_port->port = port;
1069 intel_dig_port->hdmi.sdvox_reg = sdvox_reg;
1070 intel_dig_port->dp.output_reg = 0;
1072 intel_hdmi_init_connector(intel_dig_port, intel_connector);