2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/i915/intel_drv.h>
34 #include <dev/drm2/i915/i915_drm.h>
35 #include <dev/drm2/i915/i915_drv.h>
36 #include <dev/iicbus/iic.h>
37 #include <dev/iicbus/iiconf.h>
38 #include <dev/iicbus/iicbus.h>
39 #include "iicbus_if.h"
47 static const struct gmbus_port gmbus_ports[] = {
56 /* Intel GPIO access functions */
58 #define I2C_RISEFALL_TIME 10
61 * FIXME Linux<->FreeBSD: dvo_ns2501.C wants the struct intel_gmbus
62 * below but it just has the device_t at hand. It still uses
63 * device_get_softc(), thus expects struct intel_gmbus to remain the
66 struct intel_iic_softc {
67 struct intel_gmbus *bus;
72 static inline struct intel_gmbus *
73 to_intel_gmbus(device_t i2c)
75 struct intel_iic_softc *sc;
77 sc = device_get_softc(i2c);
81 bool intel_gmbus_is_forced_bit(device_t adapter)
83 struct intel_iic_softc *sc = device_get_softc(adapter);
84 struct intel_gmbus *bus = sc->bus;
86 return bus->force_bit;
90 intel_i2c_reset(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
97 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
99 struct intel_iic_softc *sc;
100 struct drm_device *dev;
102 sc = device_get_softc(idev);
103 dev = sc->bus->dev_priv->dev;
105 intel_i2c_reset(dev);
109 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
113 /* When using bit bashing for I2C, this bit needs to be set to 1 */
114 if (!IS_PINEVIEW(dev_priv->dev))
117 val = I915_READ(DSPCLK_GATE_D);
119 val |= DPCUNIT_CLOCK_GATE_DISABLE;
121 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
122 I915_WRITE(DSPCLK_GATE_D, val);
125 static u32 get_reserved(struct intel_gmbus *bus)
127 struct drm_i915_private *dev_priv = bus->dev_priv;
128 struct drm_device *dev = dev_priv->dev;
131 /* On most chips, these bits must be preserved in software. */
132 if (!IS_I830(dev) && !IS_845G(dev))
133 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
134 (GPIO_DATA_PULLUP_DISABLE |
135 GPIO_CLOCK_PULLUP_DISABLE);
140 static int get_clock(device_t adapter)
142 struct intel_iic_softc *sc = device_get_softc(adapter);
143 struct intel_gmbus *bus = sc->bus;
144 struct drm_i915_private *dev_priv = bus->dev_priv;
145 u32 reserved = get_reserved(bus);
146 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
147 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
148 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
151 static int get_data(device_t adapter)
153 struct intel_iic_softc *sc = device_get_softc(adapter);
154 struct intel_gmbus *bus = sc->bus;
155 struct drm_i915_private *dev_priv = bus->dev_priv;
156 u32 reserved = get_reserved(bus);
157 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
158 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
159 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
162 static void set_clock(device_t adapter, int state_high)
164 struct intel_iic_softc *sc = device_get_softc(adapter);
165 struct intel_gmbus *bus = sc->bus;
166 struct drm_i915_private *dev_priv = bus->dev_priv;
167 u32 reserved = get_reserved(bus);
171 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
173 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
176 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
177 POSTING_READ(bus->gpio_reg);
180 static void set_data(device_t adapter, int state_high)
182 struct intel_iic_softc *sc = device_get_softc(adapter);
183 struct intel_gmbus *bus = sc->bus;
184 struct drm_i915_private *dev_priv = bus->dev_priv;
185 u32 reserved = get_reserved(bus);
189 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
191 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
194 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
195 POSTING_READ(bus->gpio_reg);
199 intel_gpio_pre_xfer(device_t adapter)
201 struct intel_iic_softc *sc = device_get_softc(adapter);
202 struct intel_gmbus *bus = sc->bus;
203 struct drm_i915_private *dev_priv = bus->dev_priv;
205 intel_i2c_reset(dev_priv->dev);
206 intel_i2c_quirk_set(dev_priv, true);
207 IICBB_SETSDA(adapter, 1);
208 IICBB_SETSCL(adapter, 1);
209 udelay(I2C_RISEFALL_TIME);
214 intel_gpio_post_xfer(device_t adapter)
216 struct intel_iic_softc *sc = device_get_softc(adapter);
217 struct intel_gmbus *bus = sc->bus;
218 struct drm_i915_private *dev_priv = bus->dev_priv;
220 IICBB_SETSDA(adapter, 1);
221 IICBB_SETSCL(adapter, 1);
222 intel_i2c_quirk_set(dev_priv, false);
226 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
228 struct drm_i915_private *dev_priv = bus->dev_priv;
230 /* -1 to map pin pair to gmbus index */
231 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
235 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg,
238 int reg_offset = dev_priv->gpio_mmio_base;
242 I915_WRITE(GMBUS1 + reg_offset,
245 (len << GMBUS_BYTE_COUNT_SHIFT) |
246 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
247 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
253 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
254 (GMBUS_SATOER | GMBUS_HW_RDY),
258 if (gmbus2 & GMBUS_SATOER)
261 val = I915_READ(GMBUS3 + reg_offset);
265 } while (--len && ++loop < 4);
272 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg)
274 int reg_offset = dev_priv->gpio_mmio_base;
280 while (len && loop < 4) {
281 val |= *buf++ << (8 * loop++);
285 I915_WRITE(GMBUS3 + reg_offset, val);
286 I915_WRITE(GMBUS1 + reg_offset,
288 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
289 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
290 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
297 val |= *buf++ << (8 * loop);
298 } while (--len && ++loop < 4);
300 I915_WRITE(GMBUS3 + reg_offset, val);
302 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
303 (GMBUS_SATOER | GMBUS_HW_RDY),
307 if (gmbus2 & GMBUS_SATOER)
314 * The gmbus controller can combine a 1 or 2 byte write with a read that
315 * immediately follows it by using an "INDEX" cycle.
318 gmbus_is_index_read(struct iic_msg *msgs, int i, int num)
320 return (i + 1 < num &&
321 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
322 (msgs[i + 1].flags & I2C_M_RD));
326 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs)
328 int reg_offset = dev_priv->gpio_mmio_base;
329 u32 gmbus1_index = 0;
333 if (msgs[0].len == 2)
334 gmbus5 = GMBUS_2BYTE_INDEX_EN |
335 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
336 if (msgs[0].len == 1)
337 gmbus1_index = GMBUS_CYCLE_INDEX |
338 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
340 /* GMBUS5 holds 16-bit index */
342 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
344 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
346 /* Clear GMBUS5 after each index transfer */
348 I915_WRITE(GMBUS5 + reg_offset, 0);
354 gmbus_xfer(device_t adapter,
355 struct iic_msg *msgs,
358 struct intel_iic_softc *sc = device_get_softc(adapter);
359 struct intel_gmbus *bus = sc->bus;
360 struct drm_i915_private *dev_priv = bus->dev_priv;
364 sx_xlock(&dev_priv->gmbus_mutex);
366 if (bus->force_bit) {
367 ret = -IICBUS_TRANSFER(bus->bbbus, msgs, num);
371 reg_offset = dev_priv->gpio_mmio_base;
373 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
375 for (i = 0; i < num; i++) {
378 if (gmbus_is_index_read(msgs, i, num)) {
379 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
380 i += 1; /* set i to the index of the read xfer */
381 } else if (msgs[i].flags & I2C_M_RD) {
382 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
384 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
387 if (ret == -ETIMEDOUT)
392 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
393 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
397 if (gmbus2 & GMBUS_SATOER)
401 /* Generate a STOP condition on the bus. Note that gmbus can't generata
402 * a STOP on the very first cycle. To simplify the code we
403 * unconditionally generate the STOP condition with an additional gmbus
405 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
407 /* Mark the GMBUS interface as disabled after waiting for idle.
408 * We will re-enable it at the start of the next xfer,
409 * till then let it sleep.
411 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
413 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
414 device_get_desc(adapter));
417 I915_WRITE(GMBUS0 + reg_offset, 0);
422 * Wait for bus to IDLE before clearing NAK.
423 * If we clear the NAK while bus is still active, then it will stay
424 * active and the next transaction may fail.
426 * If no ACK is received during the address phase of a transaction, the
427 * adapter must report -ENXIO. It is not clear what to return if no ACK
428 * is received at other times. But we have to be careful to not return
429 * spurious -ENXIO because that will prevent i2c and drm edid functions
430 * from retrying. So return -ENXIO only when gmbus properly quiescents -
431 * timing out seems to happen when there _is_ a ddc chip present, but
432 * it's slow responding and only answers on the 2nd retry.
435 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
437 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
438 device_get_desc(adapter));
442 /* Toggle the Software Clear Interrupt bit. This has the effect
443 * of resetting the GMBUS controller and so clearing the
444 * BUS_ERROR raised by the slave's NAK.
446 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
447 I915_WRITE(GMBUS1 + reg_offset, 0);
448 I915_WRITE(GMBUS0 + reg_offset, 0);
450 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
451 device_get_desc(adapter), msgs[i].slave >> 1,
452 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
457 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
458 device_get_desc(adapter), bus->reg0 & 0xff);
459 I915_WRITE(GMBUS0 + reg_offset, 0);
461 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
463 ret = -IICBUS_TRANSFER(bus->bbbus, msgs, num);
466 sx_xunlock(&dev_priv->gmbus_mutex);
471 intel_gmbus_probe(device_t dev)
474 return (BUS_PROBE_SPECIFIC);
478 intel_gmbus_attach(device_t idev)
480 struct intel_iic_softc *sc;
481 struct drm_device *dev;
482 struct drm_i915_private *dev_priv;
485 sc = device_get_softc(idev);
486 pin = device_get_unit(idev);
487 port = pin + 1; /* +1 to map gmbus index to pin pair */
489 snprintf(sc->name, sizeof(sc->name), "i915 gmbus %s",
490 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
492 device_set_desc(idev, sc->name);
494 dev = device_get_softc(device_get_parent(idev));
495 dev_priv = dev->dev_private;
496 sc->bus = &dev_priv->gmbus[pin];
498 /* add bus interface device */
499 sc->iic_dev = device_add_child(idev, "iicbus", -1);
500 if (sc->iic_dev == NULL)
502 device_quiet(sc->iic_dev);
503 bus_generic_attach(idev);
509 intel_gmbus_detach(device_t idev)
512 bus_generic_detach(idev);
513 device_delete_children(idev);
518 static device_method_t intel_gmbus_methods[] = {
519 DEVMETHOD(device_probe, intel_gmbus_probe),
520 DEVMETHOD(device_attach, intel_gmbus_attach),
521 DEVMETHOD(device_detach, intel_gmbus_detach),
522 DEVMETHOD(iicbus_reset, intel_iicbus_reset),
523 DEVMETHOD(iicbus_transfer, gmbus_xfer),
526 static driver_t intel_gmbus_driver = {
529 sizeof(struct intel_iic_softc)
531 static devclass_t intel_gmbus_devclass;
532 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
533 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
534 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
537 intel_iicbb_probe(device_t dev)
540 return (BUS_PROBE_DEFAULT);
544 intel_iicbb_attach(device_t idev)
546 struct intel_iic_softc *sc;
547 struct drm_device *dev;
548 struct drm_i915_private *dev_priv;
551 sc = device_get_softc(idev);
552 pin = device_get_unit(idev);
555 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s",
556 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
558 device_set_desc(idev, sc->name);
560 dev = device_get_softc(device_get_parent(idev));
561 dev_priv = dev->dev_private;
562 sc->bus = &dev_priv->gmbus[pin];
564 /* add generic bit-banging code */
565 sc->iic_dev = device_add_child(idev, "iicbb", -1);
566 if (sc->iic_dev == NULL)
568 device_quiet(sc->iic_dev);
569 bus_generic_attach(idev);
570 iicbus_set_nostop(idev, true);
576 intel_iicbb_detach(device_t idev)
579 bus_generic_detach(idev);
580 device_delete_children(idev);
585 static device_method_t intel_iicbb_methods[] = {
586 DEVMETHOD(device_probe, intel_iicbb_probe),
587 DEVMETHOD(device_attach, intel_iicbb_attach),
588 DEVMETHOD(device_detach, intel_iicbb_detach),
590 DEVMETHOD(bus_add_child, bus_generic_add_child),
591 DEVMETHOD(bus_print_child, bus_generic_print_child),
593 DEVMETHOD(iicbb_callback, iicbus_null_callback),
594 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
595 DEVMETHOD(iicbb_setsda, set_data),
596 DEVMETHOD(iicbb_setscl, set_clock),
597 DEVMETHOD(iicbb_getsda, get_data),
598 DEVMETHOD(iicbb_getscl, get_clock),
599 DEVMETHOD(iicbb_pre_xfer, intel_gpio_pre_xfer),
600 DEVMETHOD(iicbb_post_xfer, intel_gpio_post_xfer),
603 static driver_t intel_iicbb_driver = {
606 sizeof(struct intel_iic_softc)
608 static devclass_t intel_iicbb_devclass;
609 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
610 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
611 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
614 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
617 int intel_setup_gmbus(struct drm_device *dev)
619 struct drm_i915_private *dev_priv = dev->dev_private;
623 if (HAS_PCH_SPLIT(dev))
624 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
626 dev_priv->gpio_mmio_base = 0;
628 sx_init(&dev_priv->gmbus_mutex, "gmbus");
631 * The Giant there is recursed, most likely. Normally, the
632 * intel_setup_gmbus() is called from the attach method of the
636 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
637 struct intel_gmbus *bus = &dev_priv->gmbus[i];
638 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
640 bus->dev_priv = dev_priv;
642 /* By default use a conservative clock rate */
643 bus->reg0 = port | GMBUS_RATE_100KHZ;
645 /* gmbus seems to be broken on i830 */
649 intel_gpio_setup(bus, port);
654 * Initialized bbbus_bridge before gmbus_bridge, since
655 * gmbus may decide to force quirk transfer in the
658 bus->bbbus_bridge = device_add_child(dev->dev,
660 if (bus->bbbus_bridge == NULL) {
661 DRM_ERROR("bbbus bridge %d creation failed\n", i);
665 device_quiet(bus->bbbus_bridge);
666 ret = -device_probe_and_attach(bus->bbbus_bridge);
668 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
674 iic_dev = device_find_child(bus->bbbus_bridge,
676 if (iic_dev == NULL) {
677 DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
680 iic_dev = device_find_child(iic_dev, "iicbus", -1);
681 if (iic_dev == NULL) {
683 "bbbus bridge doesn't have iicbus grandchild\n");
687 bus->bbbus = iic_dev;
690 bus->gmbus_bridge = device_add_child(dev->dev,
692 if (bus->gmbus_bridge == NULL) {
693 DRM_ERROR("gmbus bridge %d creation failed\n", i);
697 device_quiet(bus->gmbus_bridge);
698 ret = -device_probe_and_attach(bus->gmbus_bridge);
700 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
707 iic_dev = device_find_child(bus->gmbus_bridge,
709 if (iic_dev == NULL) {
710 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
714 bus->gmbus = iic_dev;
718 intel_i2c_reset(dev_priv->dev);
724 struct intel_gmbus *bus = &dev_priv->gmbus[i];
725 if (bus->gmbus_bridge != NULL)
726 device_delete_child(dev->dev, bus->gmbus_bridge);
727 if (bus->bbbus_bridge != NULL)
728 device_delete_child(dev->dev, bus->bbbus_bridge);
731 sx_destroy(&dev_priv->gmbus_mutex);
735 device_t intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
738 WARN_ON(!intel_gmbus_is_port_valid(port));
739 /* -1 to map pin pair to gmbus index */
740 return (intel_gmbus_is_port_valid(port)) ?
741 dev_priv->gmbus[port - 1].gmbus : NULL;
744 void intel_gmbus_set_speed(device_t adapter, int speed)
746 struct intel_gmbus *bus = to_intel_gmbus(adapter);
748 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
751 void intel_gmbus_force_bit(device_t adapter, bool force_bit)
753 struct intel_gmbus *bus = to_intel_gmbus(adapter);
755 bus->force_bit += force_bit ? 1 : -1;
756 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
757 force_bit ? "en" : "dis", device_get_desc(adapter),
761 void intel_teardown_gmbus(struct drm_device *dev)
763 struct drm_i915_private *dev_priv = dev->dev_private;
767 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
768 struct intel_gmbus *bus = &dev_priv->gmbus[i];
771 ret = device_delete_child(dev->dev, bus->gmbus_bridge);
774 KASSERT(ret == 0, ("unable to detach iic gmbus %s: %d",
775 device_get_desc(bus->gmbus_bridge), ret));
778 ret = device_delete_child(dev->dev, bus->bbbus_bridge);
781 KASSERT(ret == 0, ("unable to detach iic bbbus %s: %d",
782 device_get_desc(bus->bbbus_bridge), ret));
785 sx_destroy(&dev_priv->gmbus_mutex);