2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/i915/i915_drv.h>
33 #include <dev/drm2/i915/intel_drv.h>
35 #include <machine/clock.h>
37 #define FORCEWAKE_ACK_TIMEOUT_MS 2
39 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
40 * framebuffer contents in-memory, aiming at reducing the required bandwidth
41 * during in-memory transfers and, therefore, reduce the power packet.
43 * The benefits of FBC are mostly visible with solid backgrounds and
44 * variation-less patterns.
46 * FBC-related functionality can be enabled by the means of the
47 * i915.i915_enable_fbc parameter
50 static bool intel_crtc_active(struct drm_crtc *crtc)
52 /* Be paranoid as we can arrive here with only partial
53 * state retrieved from the hardware during setup.
55 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
58 static void i8xx_disable_fbc(struct drm_device *dev)
60 struct drm_i915_private *dev_priv = dev->dev_private;
63 /* Disable compression */
64 fbc_ctl = I915_READ(FBC_CONTROL);
65 if ((fbc_ctl & FBC_CTL_EN) == 0)
68 fbc_ctl &= ~FBC_CTL_EN;
69 I915_WRITE(FBC_CONTROL, fbc_ctl);
71 /* Wait for compressing bit to clear */
72 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
73 DRM_DEBUG_KMS("FBC idle timed out\n");
77 DRM_DEBUG_KMS("disabled FBC\n");
80 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
82 struct drm_device *dev = crtc->dev;
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 struct drm_framebuffer *fb = crtc->fb;
85 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
86 struct drm_i915_gem_object *obj = intel_fb->obj;
87 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
90 u32 fbc_ctl, fbc_ctl2;
92 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
93 if (fb->pitches[0] < cfb_pitch)
94 cfb_pitch = fb->pitches[0];
96 /* FBC_CTL wants 64B units */
97 cfb_pitch = (cfb_pitch / 64) - 1;
98 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
101 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
102 I915_WRITE(FBC_TAG + (i * 4), 0);
105 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
107 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
108 I915_WRITE(FBC_FENCE_OFF, crtc->y);
111 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
113 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
114 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
115 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
116 fbc_ctl |= obj->fence_reg;
117 I915_WRITE(FBC_CONTROL, fbc_ctl);
119 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
120 cfb_pitch, crtc->y, intel_crtc->plane);
123 static bool i8xx_fbc_enabled(struct drm_device *dev)
125 struct drm_i915_private *dev_priv = dev->dev_private;
127 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
130 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
132 struct drm_device *dev = crtc->dev;
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 struct drm_framebuffer *fb = crtc->fb;
135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
136 struct drm_i915_gem_object *obj = intel_fb->obj;
137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
138 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
139 unsigned long stall_watermark = 200;
142 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
143 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
144 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
146 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
147 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
148 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
149 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
154 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
157 static void g4x_disable_fbc(struct drm_device *dev)
159 struct drm_i915_private *dev_priv = dev->dev_private;
162 /* Disable compression */
163 dpfc_ctl = I915_READ(DPFC_CONTROL);
164 if (dpfc_ctl & DPFC_CTL_EN) {
165 dpfc_ctl &= ~DPFC_CTL_EN;
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
168 DRM_DEBUG_KMS("disabled FBC\n");
172 static bool g4x_fbc_enabled(struct drm_device *dev)
174 struct drm_i915_private *dev_priv = dev->dev_private;
176 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
179 static void sandybridge_blit_fbc_update(struct drm_device *dev)
181 struct drm_i915_private *dev_priv = dev->dev_private;
184 /* Make sure blitter notifies FBC of writes */
185 gen6_gt_force_wake_get(dev_priv);
186 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
188 GEN6_BLITTER_LOCK_SHIFT;
189 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
190 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
193 GEN6_BLITTER_LOCK_SHIFT);
194 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
195 POSTING_READ(GEN6_BLITTER_ECOSKPD);
196 gen6_gt_force_wake_put(dev_priv);
199 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
201 struct drm_device *dev = crtc->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 struct drm_framebuffer *fb = crtc->fb;
204 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
205 struct drm_i915_gem_object *obj = intel_fb->obj;
206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
207 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
208 unsigned long stall_watermark = 200;
211 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
212 dpfc_ctl &= DPFC_RESERVED;
213 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
214 /* Set persistent mode for front-buffer rendering, ala X. */
215 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
216 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
217 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
219 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
220 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
221 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
222 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
223 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
225 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
228 I915_WRITE(SNB_DPFC_CTL_SA,
229 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
230 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
231 sandybridge_blit_fbc_update(dev);
234 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
237 static void ironlake_disable_fbc(struct drm_device *dev)
239 struct drm_i915_private *dev_priv = dev->dev_private;
242 /* Disable compression */
243 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
244 if (dpfc_ctl & DPFC_CTL_EN) {
245 dpfc_ctl &= ~DPFC_CTL_EN;
246 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
248 DRM_DEBUG_KMS("disabled FBC\n");
252 static bool ironlake_fbc_enabled(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
259 bool intel_fbc_enabled(struct drm_device *dev)
261 struct drm_i915_private *dev_priv = dev->dev_private;
263 if (!dev_priv->display.fbc_enabled)
266 return dev_priv->display.fbc_enabled(dev);
269 static void intel_fbc_work_fn(void *arg, int pending)
271 struct intel_fbc_work *work = arg;
272 struct drm_device *dev = work->crtc->dev;
273 struct drm_i915_private *dev_priv = dev->dev_private;
276 if (work == dev_priv->fbc_work) {
277 /* Double check that we haven't switched fb without cancelling
280 if (work->crtc->fb == work->fb) {
281 dev_priv->display.enable_fbc(work->crtc,
284 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
285 dev_priv->cfb_fb = work->crtc->fb->base.id;
286 dev_priv->cfb_y = work->crtc->y;
289 dev_priv->fbc_work = NULL;
293 free(work, DRM_MEM_KMS);
296 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
298 if (dev_priv->fbc_work == NULL)
301 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
303 /* Synchronisation is provided by struct_mutex and checking of
304 * dev_priv->fbc_work, so we can perform the cancellation
305 * entirely asynchronously.
307 if (taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->fbc_work->work,
309 /* tasklet was killed before being run, clean up */
310 free(dev_priv->fbc_work, DRM_MEM_KMS);
312 /* Mark the work as no longer wanted so that if it does
313 * wake-up (because the work was already running and waiting
314 * for our mutex), it will discover that is no longer
317 dev_priv->fbc_work = NULL;
320 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
322 struct intel_fbc_work *work;
323 struct drm_device *dev = crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
326 if (!dev_priv->display.enable_fbc)
329 intel_cancel_fbc_work(dev_priv);
331 work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
333 dev_priv->display.enable_fbc(crtc, interval);
339 work->interval = interval;
340 TIMEOUT_TASK_INIT(dev_priv->wq, &work->work, 0, intel_fbc_work_fn,
343 dev_priv->fbc_work = work;
345 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
347 /* Delay the actual enabling to let pageflipping cease and the
348 * display to settle before starting the compression. Note that
349 * this delay also serves a second purpose: it allows for a
350 * vblank to pass after disabling the FBC before we attempt
351 * to modify the control registers.
353 * A more complicated solution would involve tracking vblanks
354 * following the termination of the page-flipping sequence
355 * and indeed performing the enable as a co-routine and not
356 * waiting synchronously upon the vblank.
358 taskqueue_enqueue_timeout(dev_priv->wq, &work->work,
359 msecs_to_jiffies(50));
362 void intel_disable_fbc(struct drm_device *dev)
364 struct drm_i915_private *dev_priv = dev->dev_private;
366 intel_cancel_fbc_work(dev_priv);
368 if (!dev_priv->display.disable_fbc)
371 dev_priv->display.disable_fbc(dev);
372 dev_priv->cfb_plane = -1;
376 * intel_update_fbc - enable/disable FBC as needed
377 * @dev: the drm_device
379 * Set up the framebuffer compression hardware at mode set time. We
380 * enable it if possible:
381 * - plane A only (on pre-965)
382 * - no pixel mulitply/line duplication
383 * - no alpha buffer discard
385 * - framebuffer <= 2048 in width, 1536 in height
387 * We can't assume that any compression will take place (worst case),
388 * so the compressed buffer has to be the same size as the uncompressed
389 * one. It also must reside (along with the line length buffer) in
392 * We need to enable/disable FBC on a global basis.
394 void intel_update_fbc(struct drm_device *dev)
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 struct drm_crtc *crtc = NULL, *tmp_crtc;
398 struct intel_crtc *intel_crtc;
399 struct drm_framebuffer *fb;
400 struct intel_framebuffer *intel_fb;
401 struct drm_i915_gem_object *obj;
407 if (!I915_HAS_FBC(dev))
411 * If FBC is already on, we just have to verify that we can
412 * keep it that way...
413 * Need to disable if:
414 * - more than one pipe is active
415 * - changing FBC params (stride, fence, mode)
416 * - new fb is too large to fit in compressed buffer
417 * - going to an unsupported config (interlace, pixel multiply, etc.)
419 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
420 if (intel_crtc_active(tmp_crtc) &&
421 !to_intel_crtc(tmp_crtc)->primary_disabled) {
423 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
424 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
431 if (!crtc || crtc->fb == NULL) {
432 DRM_DEBUG_KMS("no output, disabling\n");
433 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
437 intel_crtc = to_intel_crtc(crtc);
439 intel_fb = to_intel_framebuffer(fb);
442 enable_fbc = i915_enable_fbc;
443 if (enable_fbc < 0) {
444 DRM_DEBUG_KMS("fbc set to per-chip default\n");
446 if (INTEL_INFO(dev)->gen <= 6)
450 DRM_DEBUG_KMS("fbc disabled per module param\n");
451 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
454 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
455 DRM_DEBUG_KMS("framebuffer too large, disabling "
457 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
460 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
461 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
462 DRM_DEBUG_KMS("mode incompatible with compression, "
464 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
467 if ((crtc->mode.hdisplay > 2048) ||
468 (crtc->mode.vdisplay > 1536)) {
469 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
470 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
473 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
474 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
475 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
479 /* The use of a CPU fence is mandatory in order to detect writes
480 * by the CPU to the scanout and trigger updates to the FBC.
482 if (obj->tiling_mode != I915_TILING_X ||
483 obj->fence_reg == I915_FENCE_REG_NONE) {
484 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
485 dev_priv->no_fbc_reason = FBC_NOT_TILED;
489 /* If the kernel debugger is active, always disable compression */
493 /* If the scanout has not changed, don't modify the FBC settings.
494 * Note that we make the fundamental assumption that the fb->obj
495 * cannot be unpinned (and have its GTT offset and fence revoked)
496 * without first being decoupled from the scanout and FBC disabled.
498 if (dev_priv->cfb_plane == intel_crtc->plane &&
499 dev_priv->cfb_fb == fb->base.id &&
500 dev_priv->cfb_y == crtc->y)
503 if (intel_fbc_enabled(dev)) {
504 /* We update FBC along two paths, after changing fb/crtc
505 * configuration (modeswitching) and after page-flipping
506 * finishes. For the latter, we know that not only did
507 * we disable the FBC at the start of the page-flip
508 * sequence, but also more than one vblank has passed.
510 * For the former case of modeswitching, it is possible
511 * to switch between two FBC valid configurations
512 * instantaneously so we do need to disable the FBC
513 * before we can modify its control registers. We also
514 * have to wait for the next vblank for that to take
515 * effect. However, since we delay enabling FBC we can
516 * assume that a vblank has passed since disabling and
517 * that we can safely alter the registers in the deferred
520 * In the scenario that we go from a valid to invalid
521 * and then back to valid FBC configuration we have
522 * no strict enforcement that a vblank occurred since
523 * disabling the FBC. However, along all current pipe
524 * disabling paths we do need to wait for a vblank at
525 * some point. And we wait before enabling FBC anyway.
527 DRM_DEBUG_KMS("disabling active FBC for update\n");
528 intel_disable_fbc(dev);
531 intel_enable_fbc(crtc, 500);
535 /* Multiple disables should be harmless */
536 if (intel_fbc_enabled(dev)) {
537 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
538 intel_disable_fbc(dev);
542 static void i915_pineview_get_mem_freq(struct drm_device *dev)
544 drm_i915_private_t *dev_priv = dev->dev_private;
547 tmp = I915_READ(CLKCFG);
549 switch (tmp & CLKCFG_FSB_MASK) {
551 dev_priv->fsb_freq = 533; /* 133*4 */
554 dev_priv->fsb_freq = 800; /* 200*4 */
557 dev_priv->fsb_freq = 667; /* 167*4 */
560 dev_priv->fsb_freq = 400; /* 100*4 */
564 switch (tmp & CLKCFG_MEM_MASK) {
566 dev_priv->mem_freq = 533;
569 dev_priv->mem_freq = 667;
572 dev_priv->mem_freq = 800;
576 /* detect pineview DDR3 setting */
577 tmp = I915_READ(CSHRDDR3CTL);
578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
581 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
583 drm_i915_private_t *dev_priv = dev->dev_private;
586 ddrpll = I915_READ16(DDRMPLL1);
587 csipll = I915_READ16(CSIPLL0);
589 switch (ddrpll & 0xff) {
591 dev_priv->mem_freq = 800;
594 dev_priv->mem_freq = 1066;
597 dev_priv->mem_freq = 1333;
600 dev_priv->mem_freq = 1600;
603 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
605 dev_priv->mem_freq = 0;
609 dev_priv->ips.r_t = dev_priv->mem_freq;
611 switch (csipll & 0x3ff) {
613 dev_priv->fsb_freq = 3200;
616 dev_priv->fsb_freq = 3733;
619 dev_priv->fsb_freq = 4266;
622 dev_priv->fsb_freq = 4800;
625 dev_priv->fsb_freq = 5333;
628 dev_priv->fsb_freq = 5866;
631 dev_priv->fsb_freq = 6400;
634 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
636 dev_priv->fsb_freq = 0;
640 if (dev_priv->fsb_freq == 3200) {
641 dev_priv->ips.c_m = 0;
642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
643 dev_priv->ips.c_m = 1;
645 dev_priv->ips.c_m = 2;
649 static const struct cxsr_latency cxsr_latency_table[] = {
650 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
651 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
652 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
653 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
654 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
656 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
657 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
658 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
659 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
660 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
662 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
663 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
664 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
665 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
666 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
668 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
669 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
670 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
671 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
672 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
674 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
675 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
676 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
677 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
678 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
680 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
681 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
682 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
683 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
684 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
687 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
692 const struct cxsr_latency *latency;
695 if (fsb == 0 || mem == 0)
698 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
699 latency = &cxsr_latency_table[i];
700 if (is_desktop == latency->is_desktop &&
701 is_ddr3 == latency->is_ddr3 &&
702 fsb == latency->fsb_freq && mem == latency->mem_freq)
706 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
711 static void pineview_disable_cxsr(struct drm_device *dev)
713 struct drm_i915_private *dev_priv = dev->dev_private;
715 /* deactivate cxsr */
716 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
720 * Latency for FIFO fetches is dependent on several factors:
721 * - memory configuration (speed, channels)
723 * - current MCH state
724 * It can be fairly high in some situations, so here we assume a fairly
725 * pessimal value. It's a tradeoff between extra memory fetches (if we
726 * set this value too high, the FIFO will fetch frequently to stay full)
727 * and power consumption (set it too low to save power and we might see
728 * FIFO underruns and display "flicker").
730 * A value of 5us seems to be a good balance; safe for very low end
731 * platforms but not overly aggressive on lower latency configs.
733 static const int latency_ns = 5000;
735 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
737 struct drm_i915_private *dev_priv = dev->dev_private;
738 uint32_t dsparb = I915_READ(DSPARB);
741 size = dsparb & 0x7f;
743 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
745 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
746 plane ? "B" : "A", size);
751 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 uint32_t dsparb = I915_READ(DSPARB);
757 size = dsparb & 0x1ff;
759 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
760 size >>= 1; /* Convert to cachelines */
762 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
763 plane ? "B" : "A", size);
768 static int i845_get_fifo_size(struct drm_device *dev, int plane)
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 uint32_t dsparb = I915_READ(DSPARB);
774 size = dsparb & 0x7f;
775 size >>= 2; /* Convert to cachelines */
777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
784 static int i830_get_fifo_size(struct drm_device *dev, int plane)
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 uint32_t dsparb = I915_READ(DSPARB);
790 size = dsparb & 0x7f;
791 size >>= 1; /* Convert to cachelines */
793 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
794 plane ? "B" : "A", size);
799 /* Pineview has different values for various configs */
800 static const struct intel_watermark_params pineview_display_wm = {
801 PINEVIEW_DISPLAY_FIFO,
805 PINEVIEW_FIFO_LINE_SIZE
807 static const struct intel_watermark_params pineview_display_hplloff_wm = {
808 PINEVIEW_DISPLAY_FIFO,
810 PINEVIEW_DFT_HPLLOFF_WM,
812 PINEVIEW_FIFO_LINE_SIZE
814 static const struct intel_watermark_params pineview_cursor_wm = {
815 PINEVIEW_CURSOR_FIFO,
816 PINEVIEW_CURSOR_MAX_WM,
817 PINEVIEW_CURSOR_DFT_WM,
818 PINEVIEW_CURSOR_GUARD_WM,
819 PINEVIEW_FIFO_LINE_SIZE,
821 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
822 PINEVIEW_CURSOR_FIFO,
823 PINEVIEW_CURSOR_MAX_WM,
824 PINEVIEW_CURSOR_DFT_WM,
825 PINEVIEW_CURSOR_GUARD_WM,
826 PINEVIEW_FIFO_LINE_SIZE
828 static const struct intel_watermark_params g4x_wm_info = {
835 static const struct intel_watermark_params g4x_cursor_wm_info = {
842 static const struct intel_watermark_params valleyview_wm_info = {
843 VALLEYVIEW_FIFO_SIZE,
849 static const struct intel_watermark_params valleyview_cursor_wm_info = {
851 VALLEYVIEW_CURSOR_MAX_WM,
856 static const struct intel_watermark_params i965_cursor_wm_info = {
863 static const struct intel_watermark_params i945_wm_info = {
870 static const struct intel_watermark_params i915_wm_info = {
877 static const struct intel_watermark_params i855_wm_info = {
884 static const struct intel_watermark_params i830_wm_info = {
892 static const struct intel_watermark_params ironlake_display_wm_info = {
899 static const struct intel_watermark_params ironlake_cursor_wm_info = {
906 static const struct intel_watermark_params ironlake_display_srwm_info = {
908 ILK_DISPLAY_MAX_SRWM,
909 ILK_DISPLAY_DFT_SRWM,
913 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
921 static const struct intel_watermark_params sandybridge_display_wm_info = {
928 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
935 static const struct intel_watermark_params sandybridge_display_srwm_info = {
937 SNB_DISPLAY_MAX_SRWM,
938 SNB_DISPLAY_DFT_SRWM,
942 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
952 * intel_calculate_wm - calculate watermark level
953 * @clock_in_khz: pixel clock
954 * @wm: chip FIFO params
955 * @pixel_size: display pixel size
956 * @latency_ns: memory latency for the platform
958 * Calculate the watermark level (the level at which the display plane will
959 * start fetching from memory again). Each chip has a different display
960 * FIFO size and allocation, so the caller needs to figure that out and pass
961 * in the correct intel_watermark_params structure.
963 * As the pixel clock runs, the FIFO will be drained at a rate that depends
964 * on the pixel size. When it reaches the watermark level, it'll start
965 * fetching FIFO line sized based chunks from memory until the FIFO fills
966 * past the watermark point. If the FIFO drains completely, a FIFO underrun
967 * will occur, and a display engine hang could result.
969 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
970 const struct intel_watermark_params *wm,
973 unsigned long latency_ns)
975 long entries_required, wm_size;
978 * Note: we need to make sure we don't overflow for various clock &
980 * clocks go from a few thousand to several hundred thousand.
981 * latency is usually a few thousand
983 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
987 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
989 wm_size = fifo_size - (entries_required + wm->guard_size);
991 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
993 /* Don't promote wm_size to unsigned... */
994 if (wm_size > (long)wm->max_wm)
995 wm_size = wm->max_wm;
997 wm_size = wm->default_wm;
1001 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1003 struct drm_crtc *crtc, *enabled = NULL;
1005 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1006 if (intel_crtc_active(crtc)) {
1016 static void pineview_update_wm(struct drm_device *dev)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 struct drm_crtc *crtc;
1020 const struct cxsr_latency *latency;
1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1025 dev_priv->fsb_freq, dev_priv->mem_freq);
1027 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1028 pineview_disable_cxsr(dev);
1032 crtc = single_enabled_crtc(dev);
1034 int clock = crtc->mode.clock;
1035 int pixel_size = crtc->fb->bits_per_pixel / 8;
1038 wm = intel_calculate_wm(clock, &pineview_display_wm,
1039 pineview_display_wm.fifo_size,
1040 pixel_size, latency->display_sr);
1041 reg = I915_READ(DSPFW1);
1042 reg &= ~DSPFW_SR_MASK;
1043 reg |= wm << DSPFW_SR_SHIFT;
1044 I915_WRITE(DSPFW1, reg);
1045 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1048 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1049 pineview_display_wm.fifo_size,
1050 pixel_size, latency->cursor_sr);
1051 reg = I915_READ(DSPFW3);
1052 reg &= ~DSPFW_CURSOR_SR_MASK;
1053 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1054 I915_WRITE(DSPFW3, reg);
1056 /* Display HPLL off SR */
1057 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1058 pineview_display_hplloff_wm.fifo_size,
1059 pixel_size, latency->display_hpll_disable);
1060 reg = I915_READ(DSPFW3);
1061 reg &= ~DSPFW_HPLL_SR_MASK;
1062 reg |= wm & DSPFW_HPLL_SR_MASK;
1063 I915_WRITE(DSPFW3, reg);
1065 /* cursor HPLL off SR */
1066 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1067 pineview_display_hplloff_wm.fifo_size,
1068 pixel_size, latency->cursor_hpll_disable);
1069 reg = I915_READ(DSPFW3);
1070 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1071 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1072 I915_WRITE(DSPFW3, reg);
1073 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1077 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1078 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1080 pineview_disable_cxsr(dev);
1081 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1085 static bool g4x_compute_wm0(struct drm_device *dev,
1087 const struct intel_watermark_params *display,
1088 int display_latency_ns,
1089 const struct intel_watermark_params *cursor,
1090 int cursor_latency_ns,
1094 struct drm_crtc *crtc;
1095 int htotal, hdisplay, clock, pixel_size;
1096 int line_time_us, line_count;
1097 int entries, tlb_miss;
1099 crtc = intel_get_crtc_for_plane(dev, plane);
1100 if (!intel_crtc_active(crtc)) {
1101 *cursor_wm = cursor->guard_size;
1102 *plane_wm = display->guard_size;
1106 htotal = crtc->mode.htotal;
1107 hdisplay = crtc->mode.hdisplay;
1108 clock = crtc->mode.clock;
1109 pixel_size = crtc->fb->bits_per_pixel / 8;
1111 /* Use the small buffer method to calculate plane watermark */
1112 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1115 entries += tlb_miss;
1116 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1117 *plane_wm = entries + display->guard_size;
1118 if (*plane_wm > (int)display->max_wm)
1119 *plane_wm = display->max_wm;
1121 /* Use the large buffer method to calculate cursor watermark */
1122 line_time_us = ((htotal * 1000) / clock);
1123 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1124 entries = line_count * 64 * pixel_size;
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1127 entries += tlb_miss;
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1129 *cursor_wm = entries + cursor->guard_size;
1130 if (*cursor_wm > (int)cursor->max_wm)
1131 *cursor_wm = (int)cursor->max_wm;
1137 * Check the wm result.
1139 * If any calculated watermark values is larger than the maximum value that
1140 * can be programmed into the associated watermark register, that watermark
1143 static bool g4x_check_srwm(struct drm_device *dev,
1144 int display_wm, int cursor_wm,
1145 const struct intel_watermark_params *display,
1146 const struct intel_watermark_params *cursor)
1148 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1149 display_wm, cursor_wm);
1151 if (display_wm > display->max_wm) {
1152 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1153 display_wm, display->max_wm);
1157 if (cursor_wm > cursor->max_wm) {
1158 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1159 cursor_wm, cursor->max_wm);
1163 if (!(display_wm || cursor_wm)) {
1164 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1171 static bool g4x_compute_srwm(struct drm_device *dev,
1174 const struct intel_watermark_params *display,
1175 const struct intel_watermark_params *cursor,
1176 int *display_wm, int *cursor_wm)
1178 struct drm_crtc *crtc;
1179 int hdisplay, htotal, pixel_size, clock;
1180 unsigned long line_time_us;
1181 int line_count, line_size;
1186 *display_wm = *cursor_wm = 0;
1190 crtc = intel_get_crtc_for_plane(dev, plane);
1191 hdisplay = crtc->mode.hdisplay;
1192 htotal = crtc->mode.htotal;
1193 clock = crtc->mode.clock;
1194 pixel_size = crtc->fb->bits_per_pixel / 8;
1196 line_time_us = (htotal * 1000) / clock;
1197 line_count = (latency_ns / line_time_us + 1000) / 1000;
1198 line_size = hdisplay * pixel_size;
1200 /* Use the minimum of the small and large buffer method for primary */
1201 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1202 large = line_count * line_size;
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1205 *display_wm = entries + display->guard_size;
1207 /* calculate the self-refresh watermark for display cursor */
1208 entries = line_count * pixel_size * 64;
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1210 *cursor_wm = entries + cursor->guard_size;
1212 return g4x_check_srwm(dev,
1213 *display_wm, *cursor_wm,
1217 static bool vlv_compute_drain_latency(struct drm_device *dev,
1219 int *plane_prec_mult,
1221 int *cursor_prec_mult,
1224 struct drm_crtc *crtc;
1225 int clock, pixel_size;
1228 crtc = intel_get_crtc_for_plane(dev, plane);
1229 if (!intel_crtc_active(crtc))
1232 clock = crtc->mode.clock; /* VESA DOT Clock */
1233 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1235 entries = (clock / 1000) * pixel_size;
1236 *plane_prec_mult = (entries > 256) ?
1237 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1238 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1241 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1242 *cursor_prec_mult = (entries > 256) ?
1243 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1244 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1250 * Update drain latency registers of memory arbiter
1252 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1253 * to be programmed. Each plane has a drain latency multiplier and a drain
1257 static void vlv_update_drain_latency(struct drm_device *dev)
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1261 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1262 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1265 /* For plane A, Cursor A */
1266 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1267 &cursor_prec_mult, &cursora_dl)) {
1268 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1269 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1270 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1273 I915_WRITE(VLV_DDL1, cursora_prec |
1274 (cursora_dl << DDL_CURSORA_SHIFT) |
1275 planea_prec | planea_dl);
1278 /* For plane B, Cursor B */
1279 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1280 &cursor_prec_mult, &cursorb_dl)) {
1281 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1283 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1284 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1286 I915_WRITE(VLV_DDL2, cursorb_prec |
1287 (cursorb_dl << DDL_CURSORB_SHIFT) |
1288 planeb_prec | planeb_dl);
1292 #define single_plane_enabled(mask) ((mask) != 0 && powerof2(mask))
1294 static void valleyview_update_wm(struct drm_device *dev)
1296 static const int sr_latency_ns = 12000;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1299 int plane_sr, cursor_sr;
1300 int ignore_plane_sr, ignore_cursor_sr;
1301 unsigned int enabled = 0;
1303 vlv_update_drain_latency(dev);
1305 if (g4x_compute_wm0(dev, 0,
1306 &valleyview_wm_info, latency_ns,
1307 &valleyview_cursor_wm_info, latency_ns,
1308 &planea_wm, &cursora_wm))
1311 if (g4x_compute_wm0(dev, 1,
1312 &valleyview_wm_info, latency_ns,
1313 &valleyview_cursor_wm_info, latency_ns,
1314 &planeb_wm, &cursorb_wm))
1317 if (single_plane_enabled(enabled) &&
1318 g4x_compute_srwm(dev, ffs(enabled) - 1,
1320 &valleyview_wm_info,
1321 &valleyview_cursor_wm_info,
1322 &plane_sr, &ignore_cursor_sr) &&
1323 g4x_compute_srwm(dev, ffs(enabled) - 1,
1325 &valleyview_wm_info,
1326 &valleyview_cursor_wm_info,
1327 &ignore_plane_sr, &cursor_sr)) {
1328 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1330 I915_WRITE(FW_BLC_SELF_VLV,
1331 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1332 plane_sr = cursor_sr = 0;
1335 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1336 planea_wm, cursora_wm,
1337 planeb_wm, cursorb_wm,
1338 plane_sr, cursor_sr);
1341 (plane_sr << DSPFW_SR_SHIFT) |
1342 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1343 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1346 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1347 (cursora_wm << DSPFW_CURSORA_SHIFT));
1349 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1350 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1353 static void g4x_update_wm(struct drm_device *dev)
1355 static const int sr_latency_ns = 12000;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1358 int plane_sr, cursor_sr;
1359 unsigned int enabled = 0;
1361 if (g4x_compute_wm0(dev, 0,
1362 &g4x_wm_info, latency_ns,
1363 &g4x_cursor_wm_info, latency_ns,
1364 &planea_wm, &cursora_wm))
1367 if (g4x_compute_wm0(dev, 1,
1368 &g4x_wm_info, latency_ns,
1369 &g4x_cursor_wm_info, latency_ns,
1370 &planeb_wm, &cursorb_wm))
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1377 &g4x_cursor_wm_info,
1378 &plane_sr, &cursor_sr)) {
1379 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1381 I915_WRITE(FW_BLC_SELF,
1382 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1383 plane_sr = cursor_sr = 0;
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1399 /* HPLL off in SR has some issues on G4x... disable it */
1401 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1402 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1405 static void i965_update_wm(struct drm_device *dev)
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 struct drm_crtc *crtc;
1412 /* Calc sr entries for one plane configs */
1413 crtc = single_enabled_crtc(dev);
1415 /* self-refresh has much higher latency */
1416 static const int sr_latency_ns = 12000;
1417 int clock = crtc->mode.clock;
1418 int htotal = crtc->mode.htotal;
1419 int hdisplay = crtc->mode.hdisplay;
1420 int pixel_size = crtc->fb->bits_per_pixel / 8;
1421 unsigned long line_time_us;
1424 line_time_us = ((htotal * 1000) / clock);
1426 /* Use ns/us then divide to preserve precision */
1427 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1428 pixel_size * hdisplay;
1429 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1430 srwm = I965_FIFO_SIZE - entries;
1434 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1437 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1439 entries = DIV_ROUND_UP(entries,
1440 i965_cursor_wm_info.cacheline_size);
1441 cursor_sr = i965_cursor_wm_info.fifo_size -
1442 (entries + i965_cursor_wm_info.guard_size);
1444 if (cursor_sr > i965_cursor_wm_info.max_wm)
1445 cursor_sr = i965_cursor_wm_info.max_wm;
1447 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1448 "cursor %d\n", srwm, cursor_sr);
1450 if (IS_CRESTLINE(dev))
1451 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1453 /* Turn off self refresh if both pipes are enabled */
1454 if (IS_CRESTLINE(dev))
1455 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1459 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1462 /* 965 has limitations... */
1463 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1464 (8 << 16) | (8 << 8) | (8 << 0));
1465 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1466 /* update cursor SR watermark */
1467 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1470 static void i9xx_update_wm(struct drm_device *dev)
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 const struct intel_watermark_params *wm_info;
1478 int planea_wm, planeb_wm;
1479 struct drm_crtc *crtc, *enabled = NULL;
1482 wm_info = &i945_wm_info;
1483 else if (!IS_GEN2(dev))
1484 wm_info = &i915_wm_info;
1486 wm_info = &i855_wm_info;
1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1489 crtc = intel_get_crtc_for_plane(dev, 0);
1490 if (intel_crtc_active(crtc)) {
1491 int cpp = crtc->fb->bits_per_pixel / 8;
1495 planea_wm = intel_calculate_wm(crtc->mode.clock,
1496 wm_info, fifo_size, cpp,
1500 planea_wm = fifo_size - wm_info->guard_size;
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1503 crtc = intel_get_crtc_for_plane(dev, 1);
1504 if (intel_crtc_active(crtc)) {
1505 int cpp = crtc->fb->bits_per_pixel / 8;
1509 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1510 wm_info, fifo_size, cpp,
1512 if (enabled == NULL)
1517 planeb_wm = fifo_size - wm_info->guard_size;
1519 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1522 * Overlay gets an aggressive default since video jitter is bad.
1526 /* Play safe and disable self-refresh before adjusting watermarks. */
1527 if (IS_I945G(dev) || IS_I945GM(dev))
1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1529 else if (IS_I915GM(dev))
1530 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1532 /* Calc sr entries for one plane configs */
1533 if (HAS_FW_BLC(dev) && enabled) {
1534 /* self-refresh has much higher latency */
1535 static const int sr_latency_ns = 6000;
1536 int clock = enabled->mode.clock;
1537 int htotal = enabled->mode.htotal;
1538 int hdisplay = enabled->mode.hdisplay;
1539 int pixel_size = enabled->fb->bits_per_pixel / 8;
1540 unsigned long line_time_us;
1543 line_time_us = (htotal * 1000) / clock;
1545 /* Use ns/us then divide to preserve precision */
1546 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1547 pixel_size * hdisplay;
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1549 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1550 srwm = wm_info->fifo_size - entries;
1554 if (IS_I945G(dev) || IS_I945GM(dev))
1555 I915_WRITE(FW_BLC_SELF,
1556 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1557 else if (IS_I915GM(dev))
1558 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1561 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1562 planea_wm, planeb_wm, cwm, srwm);
1564 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1565 fwater_hi = (cwm & 0x1f);
1567 /* Set request length to 8 cachelines per fetch */
1568 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1569 fwater_hi = fwater_hi | (1 << 8);
1571 I915_WRITE(FW_BLC, fwater_lo);
1572 I915_WRITE(FW_BLC2, fwater_hi);
1574 if (HAS_FW_BLC(dev)) {
1576 if (IS_I945G(dev) || IS_I945GM(dev))
1577 I915_WRITE(FW_BLC_SELF,
1578 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1579 else if (IS_I915GM(dev))
1580 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1581 DRM_DEBUG_KMS("memory self refresh enabled\n");
1583 DRM_DEBUG_KMS("memory self refresh disabled\n");
1587 static void i830_update_wm(struct drm_device *dev)
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct drm_crtc *crtc;
1594 crtc = single_enabled_crtc(dev);
1598 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1599 dev_priv->display.get_fifo_size(dev, 0),
1601 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1602 fwater_lo |= (3<<8) | planea_wm;
1604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1606 I915_WRITE(FW_BLC, fwater_lo);
1609 #define ILK_LP0_PLANE_LATENCY 700
1610 #define ILK_LP0_CURSOR_LATENCY 1300
1613 * Check the wm result.
1615 * If any calculated watermark values is larger than the maximum value that
1616 * can be programmed into the associated watermark register, that watermark
1619 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1620 int fbc_wm, int display_wm, int cursor_wm,
1621 const struct intel_watermark_params *display,
1622 const struct intel_watermark_params *cursor)
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1626 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1627 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1629 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1630 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1631 fbc_wm, SNB_FBC_MAX_SRWM, level);
1633 /* fbc has it's own way to disable FBC WM */
1634 I915_WRITE(DISP_ARB_CTL,
1635 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1639 if (display_wm > display->max_wm) {
1640 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1641 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1645 if (cursor_wm > cursor->max_wm) {
1646 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1647 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1651 if (!(fbc_wm || display_wm || cursor_wm)) {
1652 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1660 * Compute watermark values of WM[1-3],
1662 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1664 const struct intel_watermark_params *display,
1665 const struct intel_watermark_params *cursor,
1666 int *fbc_wm, int *display_wm, int *cursor_wm)
1668 struct drm_crtc *crtc;
1669 unsigned long line_time_us;
1670 int hdisplay, htotal, pixel_size, clock;
1671 int line_count, line_size;
1676 *fbc_wm = *display_wm = *cursor_wm = 0;
1680 crtc = intel_get_crtc_for_plane(dev, plane);
1681 hdisplay = crtc->mode.hdisplay;
1682 htotal = crtc->mode.htotal;
1683 clock = crtc->mode.clock;
1684 pixel_size = crtc->fb->bits_per_pixel / 8;
1686 line_time_us = (htotal * 1000) / clock;
1687 line_count = (latency_ns / line_time_us + 1000) / 1000;
1688 line_size = hdisplay * pixel_size;
1690 /* Use the minimum of the small and large buffer method for primary */
1691 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1692 large = line_count * line_size;
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1695 *display_wm = entries + display->guard_size;
1699 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1701 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1703 /* calculate the self-refresh watermark for display cursor */
1704 entries = line_count * pixel_size * 64;
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1706 *cursor_wm = entries + cursor->guard_size;
1708 return ironlake_check_srwm(dev, level,
1709 *fbc_wm, *display_wm, *cursor_wm,
1713 static void ironlake_update_wm(struct drm_device *dev)
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 int fbc_wm, plane_wm, cursor_wm;
1717 unsigned int enabled;
1720 if (g4x_compute_wm0(dev, 0,
1721 &ironlake_display_wm_info,
1722 ILK_LP0_PLANE_LATENCY,
1723 &ironlake_cursor_wm_info,
1724 ILK_LP0_CURSOR_LATENCY,
1725 &plane_wm, &cursor_wm)) {
1726 I915_WRITE(WM0_PIPEA_ILK,
1727 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1728 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1729 " plane %d, " "cursor: %d\n",
1730 plane_wm, cursor_wm);
1734 if (g4x_compute_wm0(dev, 1,
1735 &ironlake_display_wm_info,
1736 ILK_LP0_PLANE_LATENCY,
1737 &ironlake_cursor_wm_info,
1738 ILK_LP0_CURSOR_LATENCY,
1739 &plane_wm, &cursor_wm)) {
1740 I915_WRITE(WM0_PIPEB_ILK,
1741 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1742 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1743 " plane %d, cursor: %d\n",
1744 plane_wm, cursor_wm);
1749 * Calculate and update the self-refresh watermark only when one
1750 * display plane is used.
1752 I915_WRITE(WM3_LP_ILK, 0);
1753 I915_WRITE(WM2_LP_ILK, 0);
1754 I915_WRITE(WM1_LP_ILK, 0);
1756 if (!single_plane_enabled(enabled))
1758 enabled = ffs(enabled) - 1;
1761 if (!ironlake_compute_srwm(dev, 1, enabled,
1762 ILK_READ_WM1_LATENCY() * 500,
1763 &ironlake_display_srwm_info,
1764 &ironlake_cursor_srwm_info,
1765 &fbc_wm, &plane_wm, &cursor_wm))
1768 I915_WRITE(WM1_LP_ILK,
1770 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1771 (fbc_wm << WM1_LP_FBC_SHIFT) |
1772 (plane_wm << WM1_LP_SR_SHIFT) |
1776 if (!ironlake_compute_srwm(dev, 2, enabled,
1777 ILK_READ_WM2_LATENCY() * 500,
1778 &ironlake_display_srwm_info,
1779 &ironlake_cursor_srwm_info,
1780 &fbc_wm, &plane_wm, &cursor_wm))
1783 I915_WRITE(WM2_LP_ILK,
1785 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1786 (fbc_wm << WM1_LP_FBC_SHIFT) |
1787 (plane_wm << WM1_LP_SR_SHIFT) |
1791 * WM3 is unsupported on ILK, probably because we don't have latency
1792 * data for that power state
1796 static void sandybridge_update_wm(struct drm_device *dev)
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1801 int fbc_wm, plane_wm, cursor_wm;
1802 unsigned int enabled;
1805 if (g4x_compute_wm0(dev, 0,
1806 &sandybridge_display_wm_info, latency,
1807 &sandybridge_cursor_wm_info, latency,
1808 &plane_wm, &cursor_wm)) {
1809 val = I915_READ(WM0_PIPEA_ILK);
1810 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1811 I915_WRITE(WM0_PIPEA_ILK, val |
1812 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1813 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1814 " plane %d, " "cursor: %d\n",
1815 plane_wm, cursor_wm);
1819 if (g4x_compute_wm0(dev, 1,
1820 &sandybridge_display_wm_info, latency,
1821 &sandybridge_cursor_wm_info, latency,
1822 &plane_wm, &cursor_wm)) {
1823 val = I915_READ(WM0_PIPEB_ILK);
1824 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1825 I915_WRITE(WM0_PIPEB_ILK, val |
1826 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1827 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1828 " plane %d, cursor: %d\n",
1829 plane_wm, cursor_wm);
1834 * Calculate and update the self-refresh watermark only when one
1835 * display plane is used.
1837 * SNB support 3 levels of watermark.
1839 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1840 * and disabled in the descending order
1843 I915_WRITE(WM3_LP_ILK, 0);
1844 I915_WRITE(WM2_LP_ILK, 0);
1845 I915_WRITE(WM1_LP_ILK, 0);
1847 if (!single_plane_enabled(enabled) ||
1848 dev_priv->sprite_scaling_enabled)
1850 enabled = ffs(enabled) - 1;
1853 if (!ironlake_compute_srwm(dev, 1, enabled,
1854 SNB_READ_WM1_LATENCY() * 500,
1855 &sandybridge_display_srwm_info,
1856 &sandybridge_cursor_srwm_info,
1857 &fbc_wm, &plane_wm, &cursor_wm))
1860 I915_WRITE(WM1_LP_ILK,
1862 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1863 (fbc_wm << WM1_LP_FBC_SHIFT) |
1864 (plane_wm << WM1_LP_SR_SHIFT) |
1868 if (!ironlake_compute_srwm(dev, 2, enabled,
1869 SNB_READ_WM2_LATENCY() * 500,
1870 &sandybridge_display_srwm_info,
1871 &sandybridge_cursor_srwm_info,
1872 &fbc_wm, &plane_wm, &cursor_wm))
1875 I915_WRITE(WM2_LP_ILK,
1877 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1878 (fbc_wm << WM1_LP_FBC_SHIFT) |
1879 (plane_wm << WM1_LP_SR_SHIFT) |
1883 if (!ironlake_compute_srwm(dev, 3, enabled,
1884 SNB_READ_WM3_LATENCY() * 500,
1885 &sandybridge_display_srwm_info,
1886 &sandybridge_cursor_srwm_info,
1887 &fbc_wm, &plane_wm, &cursor_wm))
1890 I915_WRITE(WM3_LP_ILK,
1892 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1893 (fbc_wm << WM1_LP_FBC_SHIFT) |
1894 (plane_wm << WM1_LP_SR_SHIFT) |
1898 static void ivybridge_update_wm(struct drm_device *dev)
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1903 int fbc_wm, plane_wm, cursor_wm;
1904 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1905 unsigned int enabled;
1908 if (g4x_compute_wm0(dev, 0,
1909 &sandybridge_display_wm_info, latency,
1910 &sandybridge_cursor_wm_info, latency,
1911 &plane_wm, &cursor_wm)) {
1912 val = I915_READ(WM0_PIPEA_ILK);
1913 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1914 I915_WRITE(WM0_PIPEA_ILK, val |
1915 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1916 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1917 " plane %d, " "cursor: %d\n",
1918 plane_wm, cursor_wm);
1922 if (g4x_compute_wm0(dev, 1,
1923 &sandybridge_display_wm_info, latency,
1924 &sandybridge_cursor_wm_info, latency,
1925 &plane_wm, &cursor_wm)) {
1926 val = I915_READ(WM0_PIPEB_ILK);
1927 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1928 I915_WRITE(WM0_PIPEB_ILK, val |
1929 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1930 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1931 " plane %d, cursor: %d\n",
1932 plane_wm, cursor_wm);
1936 if (g4x_compute_wm0(dev, 2,
1937 &sandybridge_display_wm_info, latency,
1938 &sandybridge_cursor_wm_info, latency,
1939 &plane_wm, &cursor_wm)) {
1940 val = I915_READ(WM0_PIPEC_IVB);
1941 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1942 I915_WRITE(WM0_PIPEC_IVB, val |
1943 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1944 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1945 " plane %d, cursor: %d\n",
1946 plane_wm, cursor_wm);
1951 * Calculate and update the self-refresh watermark only when one
1952 * display plane is used.
1954 * SNB support 3 levels of watermark.
1956 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1957 * and disabled in the descending order
1960 I915_WRITE(WM3_LP_ILK, 0);
1961 I915_WRITE(WM2_LP_ILK, 0);
1962 I915_WRITE(WM1_LP_ILK, 0);
1964 if (!single_plane_enabled(enabled) ||
1965 dev_priv->sprite_scaling_enabled)
1967 enabled = ffs(enabled) - 1;
1970 if (!ironlake_compute_srwm(dev, 1, enabled,
1971 SNB_READ_WM1_LATENCY() * 500,
1972 &sandybridge_display_srwm_info,
1973 &sandybridge_cursor_srwm_info,
1974 &fbc_wm, &plane_wm, &cursor_wm))
1977 I915_WRITE(WM1_LP_ILK,
1979 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1980 (fbc_wm << WM1_LP_FBC_SHIFT) |
1981 (plane_wm << WM1_LP_SR_SHIFT) |
1985 if (!ironlake_compute_srwm(dev, 2, enabled,
1986 SNB_READ_WM2_LATENCY() * 500,
1987 &sandybridge_display_srwm_info,
1988 &sandybridge_cursor_srwm_info,
1989 &fbc_wm, &plane_wm, &cursor_wm))
1992 I915_WRITE(WM2_LP_ILK,
1994 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1995 (fbc_wm << WM1_LP_FBC_SHIFT) |
1996 (plane_wm << WM1_LP_SR_SHIFT) |
1999 /* WM3, note we have to correct the cursor latency */
2000 if (!ironlake_compute_srwm(dev, 3, enabled,
2001 SNB_READ_WM3_LATENCY() * 500,
2002 &sandybridge_display_srwm_info,
2003 &sandybridge_cursor_srwm_info,
2004 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2005 !ironlake_compute_srwm(dev, 3, enabled,
2006 2 * SNB_READ_WM3_LATENCY() * 500,
2007 &sandybridge_display_srwm_info,
2008 &sandybridge_cursor_srwm_info,
2009 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2012 I915_WRITE(WM3_LP_ILK,
2014 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2015 (fbc_wm << WM1_LP_FBC_SHIFT) |
2016 (plane_wm << WM1_LP_SR_SHIFT) |
2021 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2022 struct drm_display_mode *mode)
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2027 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2028 temp &= ~PIPE_WM_LINETIME_MASK;
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2033 temp |= PIPE_WM_LINETIME_TIME(
2034 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2036 /* IPS watermarks are only used by pipe A, and are ignored by
2037 * pipes B and C. They are calculated similarly to the common
2038 * linetime values, except that we are using CD clock frequency
2039 * in MHz instead of pixel rate for the division.
2041 * This is a placeholder for the IPS watermark calculation code.
2044 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2048 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2049 uint32_t sprite_width, int pixel_size,
2050 const struct intel_watermark_params *display,
2051 int display_latency_ns, int *sprite_wm)
2053 struct drm_crtc *crtc;
2055 int entries, tlb_miss;
2057 crtc = intel_get_crtc_for_plane(dev, plane);
2058 if (!intel_crtc_active(crtc)) {
2059 *sprite_wm = display->guard_size;
2063 clock = crtc->mode.clock;
2065 /* Use the small buffer method to calculate the sprite watermark */
2066 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2067 tlb_miss = display->fifo_size*display->cacheline_size -
2070 entries += tlb_miss;
2071 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2072 *sprite_wm = entries + display->guard_size;
2073 if (*sprite_wm > (int)display->max_wm)
2074 *sprite_wm = display->max_wm;
2080 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2081 uint32_t sprite_width, int pixel_size,
2082 const struct intel_watermark_params *display,
2083 int latency_ns, int *sprite_wm)
2085 struct drm_crtc *crtc;
2086 unsigned long line_time_us;
2088 int line_count, line_size;
2097 crtc = intel_get_crtc_for_plane(dev, plane);
2098 clock = crtc->mode.clock;
2104 line_time_us = (sprite_width * 1000) / clock;
2105 if (!line_time_us) {
2110 line_count = (latency_ns / line_time_us + 1000) / 1000;
2111 line_size = sprite_width * pixel_size;
2113 /* Use the minimum of the small and large buffer method for primary */
2114 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2115 large = line_count * line_size;
2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2118 *sprite_wm = entries + display->guard_size;
2120 return *sprite_wm > 0x3ff ? false : true;
2123 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2124 uint32_t sprite_width, int pixel_size)
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2134 reg = WM0_PIPEA_ILK;
2137 reg = WM0_PIPEB_ILK;
2140 reg = WM0_PIPEC_IVB;
2143 return; /* bad pipe */
2146 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2147 &sandybridge_display_wm_info,
2148 latency, &sprite_wm);
2150 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2155 val = I915_READ(reg);
2156 val &= ~WM0_PIPE_SPRITE_MASK;
2157 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2158 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2161 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2163 &sandybridge_display_srwm_info,
2164 SNB_READ_WM1_LATENCY() * 500,
2167 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2171 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2173 /* Only IVB has two more LP watermarks for sprite */
2174 if (!IS_IVYBRIDGE(dev))
2177 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2179 &sandybridge_display_srwm_info,
2180 SNB_READ_WM2_LATENCY() * 500,
2183 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2187 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2189 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2191 &sandybridge_display_srwm_info,
2192 SNB_READ_WM3_LATENCY() * 500,
2195 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2199 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2203 * intel_update_watermarks - update FIFO watermark values based on current modes
2205 * Calculate watermark values for the various WM regs based on current mode
2206 * and plane configuration.
2208 * There are several cases to deal with here:
2209 * - normal (i.e. non-self-refresh)
2210 * - self-refresh (SR) mode
2211 * - lines are large relative to FIFO size (buffer can hold up to 2)
2212 * - lines are small relative to FIFO size (buffer can hold more than 2
2213 * lines), so need to account for TLB latency
2215 * The normal calculation is:
2216 * watermark = dotclock * bytes per pixel * latency
2217 * where latency is platform & configuration dependent (we assume pessimal
2220 * The SR calculation is:
2221 * watermark = (trunc(latency/line time)+1) * surface width *
2224 * line time = htotal / dotclock
2225 * surface width = hdisplay for normal plane and 64 for cursor
2226 * and latency is assumed to be high, as above.
2228 * The final value programmed to the register should always be rounded up,
2229 * and include an extra 2 entries to account for clock crossings.
2231 * We don't use the sprite, so we can ignore that. And on Crestline we have
2232 * to set the non-SR watermarks to 8.
2234 void intel_update_watermarks(struct drm_device *dev)
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2238 if (dev_priv->display.update_wm)
2239 dev_priv->display.update_wm(dev);
2242 void intel_update_linetime_watermarks(struct drm_device *dev,
2243 int pipe, struct drm_display_mode *mode)
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2247 if (dev_priv->display.update_linetime_wm)
2248 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2251 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2252 uint32_t sprite_width, int pixel_size)
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2256 if (dev_priv->display.update_sprite_wm)
2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2261 static struct drm_i915_gem_object *
2262 intel_alloc_context_page(struct drm_device *dev)
2264 struct drm_i915_gem_object *ctx;
2267 DRM_LOCK_ASSERT(dev);
2269 ctx = i915_gem_alloc_object(dev, 4096);
2271 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2275 ret = i915_gem_object_pin(ctx, 4096, true, false);
2277 DRM_ERROR("failed to pin power context: %d\n", ret);
2281 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2283 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2290 i915_gem_object_unpin(ctx);
2292 drm_gem_object_unreference(&ctx->base);
2298 * Lock protecting IPS related data structures
2300 struct mtx mchdev_lock;
2301 MTX_SYSINIT(mchdev, &mchdev_lock, "mchdev", MTX_DEF);
2303 /* Global for IPS driver to get at the current i915 device. Protected by
2305 static struct drm_i915_private *i915_mch_dev;
2307 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2312 mtx_assert(&mchdev_lock, MA_OWNED);
2314 rgvswctl = I915_READ16(MEMSWCTL);
2315 if (rgvswctl & MEMCTL_CMD_STS) {
2316 DRM_DEBUG("gpu busy, RCS change rejected\n");
2317 return false; /* still busy with another command */
2320 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2321 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2322 I915_WRITE16(MEMSWCTL, rgvswctl);
2323 POSTING_READ16(MEMSWCTL);
2325 rgvswctl |= MEMCTL_CMD_STS;
2326 I915_WRITE16(MEMSWCTL, rgvswctl);
2331 static void ironlake_enable_drps(struct drm_device *dev)
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 u32 rgvmodectl = I915_READ(MEMMODECTL);
2335 u8 fmax, fmin, fstart, vstart;
2337 mtx_lock(&mchdev_lock);
2339 /* Enable temp reporting */
2340 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2341 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2343 /* 100ms RC evaluation intervals */
2344 I915_WRITE(RCUPEI, 100000);
2345 I915_WRITE(RCDNEI, 100000);
2347 /* Set max/min thresholds to 90ms and 80ms respectively */
2348 I915_WRITE(RCBMAXAVG, 90000);
2349 I915_WRITE(RCBMINAVG, 80000);
2351 I915_WRITE(MEMIHYST, 1);
2353 /* Set up min, max, and cur for interrupt handling */
2354 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2355 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2356 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2357 MEMMODE_FSTART_SHIFT;
2359 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2362 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2363 dev_priv->ips.fstart = fstart;
2365 dev_priv->ips.max_delay = fstart;
2366 dev_priv->ips.min_delay = fmin;
2367 dev_priv->ips.cur_delay = fstart;
2369 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2370 fmax, fmin, fstart);
2372 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2375 * Interrupts will be enabled in ironlake_irq_postinstall
2378 I915_WRITE(VIDSTART, vstart);
2379 POSTING_READ(VIDSTART);
2381 rgvmodectl |= MEMMODE_SWMODE_EN;
2382 I915_WRITE(MEMMODECTL, rgvmodectl);
2384 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2385 DRM_ERROR("stuck trying to change perf mode\n");
2388 ironlake_set_drps(dev, fstart);
2390 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2392 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2393 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2394 getrawmonotonic(&dev_priv->ips.last_time2);
2396 mtx_unlock(&mchdev_lock);
2399 static void ironlake_disable_drps(struct drm_device *dev)
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2404 mtx_lock(&mchdev_lock);
2406 rgvswctl = I915_READ16(MEMSWCTL);
2408 /* Ack interrupts, disable EFC interrupt */
2409 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2410 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2411 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2412 I915_WRITE(DEIIR, DE_PCU_EVENT);
2413 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2415 /* Go back to the starting frequency */
2416 ironlake_set_drps(dev, dev_priv->ips.fstart);
2418 rgvswctl |= MEMCTL_CMD_STS;
2419 I915_WRITE(MEMSWCTL, rgvswctl);
2422 mtx_unlock(&mchdev_lock);
2425 /* There's a funny hw issue where the hw returns all 0 when reading from
2426 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2427 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2428 * all limits and the gpu stuck at whatever frequency it is at atm).
2430 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2436 if (*val >= dev_priv->rps.max_delay)
2437 *val = dev_priv->rps.max_delay;
2438 limits |= dev_priv->rps.max_delay << 24;
2440 /* Only set the down limit when we've reached the lowest level to avoid
2441 * getting more interrupts, otherwise leave this clear. This prevents a
2442 * race in the hw when coming out of rc6: There's a tiny window where
2443 * the hw runs at the minimal clock before selecting the desired
2444 * frequency, if the down threshold expires in that window we will not
2445 * receive a down interrupt. */
2446 if (*val <= dev_priv->rps.min_delay) {
2447 *val = dev_priv->rps.min_delay;
2448 limits |= dev_priv->rps.min_delay << 16;
2454 void gen6_set_rps(struct drm_device *dev, u8 val)
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 u32 limits = gen6_rps_limits(dev_priv, &val);
2459 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2460 WARN_ON(val > dev_priv->rps.max_delay);
2461 WARN_ON(val < dev_priv->rps.min_delay);
2463 if (val == dev_priv->rps.cur_delay)
2466 I915_WRITE(GEN6_RPNSWREQ,
2467 GEN6_FREQUENCY(val) |
2469 GEN6_AGGRESSIVE_TURBO);
2471 /* Make sure we continue to get interrupts
2472 * until we hit the minimum or maximum frequencies.
2474 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2476 POSTING_READ(GEN6_RPNSWREQ);
2478 dev_priv->rps.cur_delay = val;
2481 static void gen6_disable_rps(struct drm_device *dev)
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2485 I915_WRITE(GEN6_RC_CONTROL, 0);
2486 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2487 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2488 I915_WRITE(GEN6_PMIER, 0);
2489 /* Complete PM interrupt masking here doesn't race with the rps work
2490 * item again unmasking PM interrupts because that is using a different
2491 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2492 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2494 mtx_lock(&dev_priv->rps.lock);
2495 dev_priv->rps.pm_iir = 0;
2496 mtx_unlock(&dev_priv->rps.lock);
2498 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2501 int intel_enable_rc6(const struct drm_device *dev)
2503 /* Respect the kernel parameter if it is set */
2504 if (i915_enable_rc6 >= 0)
2505 return i915_enable_rc6;
2507 /* Disable RC6 on Ironlake */
2508 if (INTEL_INFO(dev)->gen == 5)
2511 if (IS_HASWELL(dev)) {
2512 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2513 return INTEL_RC6_ENABLE;
2516 /* snb/ivb have more than one rc6 state. */
2517 if (INTEL_INFO(dev)->gen == 6) {
2518 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2519 return INTEL_RC6_ENABLE;
2522 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2523 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2526 static void gen6_enable_rps(struct drm_device *dev)
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 struct intel_ring_buffer *ring;
2532 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2537 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2539 /* Here begins a magic sequence of register writes to enable
2540 * auto-downclocking.
2542 * Perhaps there might be some value in exposing these to
2545 I915_WRITE(GEN6_RC_STATE, 0);
2547 /* Clear the DBG now so we don't confuse earlier errors */
2548 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2549 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2550 I915_WRITE(GTFIFODBG, gtfifodbg);
2553 gen6_gt_force_wake_get(dev_priv);
2555 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2556 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2558 /* In units of 100MHz */
2559 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2560 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2561 dev_priv->rps.cur_delay = 0;
2563 /* disable the counters and set deterministic thresholds */
2564 I915_WRITE(GEN6_RC_CONTROL, 0);
2566 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2567 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2568 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2569 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2570 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2572 for_each_ring(ring, dev_priv, i)
2573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2575 I915_WRITE(GEN6_RC_SLEEP, 0);
2576 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2577 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2578 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2579 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2581 /* Check if we are enabling RC6 */
2582 rc6_mode = intel_enable_rc6(dev_priv->dev);
2583 if (rc6_mode & INTEL_RC6_ENABLE)
2584 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2586 /* We don't use those on Haswell */
2587 if (!IS_HASWELL(dev)) {
2588 if (rc6_mode & INTEL_RC6p_ENABLE)
2589 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2591 if (rc6_mode & INTEL_RC6pp_ENABLE)
2592 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2595 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2596 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2597 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2598 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2600 I915_WRITE(GEN6_RC_CONTROL,
2602 GEN6_RC_CTL_EI_MODE(1) |
2603 GEN6_RC_CTL_HW_ENABLE);
2605 I915_WRITE(GEN6_RPNSWREQ,
2606 GEN6_FREQUENCY(10) |
2608 GEN6_AGGRESSIVE_TURBO);
2609 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2610 GEN6_FREQUENCY(12));
2612 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2613 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2614 dev_priv->rps.max_delay << 24 |
2615 dev_priv->rps.min_delay << 16);
2617 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2618 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2619 I915_WRITE(GEN6_RP_UP_EI, 66000);
2620 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2622 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2623 I915_WRITE(GEN6_RP_CONTROL,
2624 GEN6_RP_MEDIA_TURBO |
2625 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2626 GEN6_RP_MEDIA_IS_GFX |
2628 GEN6_RP_UP_BUSY_AVG |
2629 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2631 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2634 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2635 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2636 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2637 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2640 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2643 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2645 /* requires MSI enabled */
2646 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2647 mtx_lock(&dev_priv->rps.lock);
2648 WARN_ON(dev_priv->rps.pm_iir != 0);
2649 I915_WRITE(GEN6_PMIMR, 0);
2650 mtx_unlock(&dev_priv->rps.lock);
2651 /* enable all PM interrupts */
2652 I915_WRITE(GEN6_PMINTRMSK, 0);
2655 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2656 if (IS_GEN6(dev) && ret) {
2657 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2658 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2659 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2660 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2661 rc6vids &= 0xffff00;
2662 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2663 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2665 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2668 gen6_gt_force_wake_put(dev_priv);
2671 static void gen6_update_ring_freq(struct drm_device *dev)
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2676 unsigned int ia_freq, max_ia_freq;
2677 int scaling_factor = 180;
2679 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2682 max_ia_freq = cpufreq_quick_get_max(0);
2684 * Default to measured freq if none found, PCU will ensure we don't go
2688 max_ia_freq = tsc_khz;
2691 freq = atomic_load_acq_64(&tsc_freq);
2692 max_ia_freq = freq / 1000;
2693 #endif /* FREEBSD_WIP */
2695 /* Convert from kHz to MHz */
2696 max_ia_freq /= 1000;
2699 * For each potential GPU frequency, load a ring frequency we'd like
2700 * to use for memory access. We do this by specifying the IA frequency
2701 * the PCU should use as a reference to determine the ring frequency.
2703 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2705 int diff = dev_priv->rps.max_delay - gpu_freq;
2708 * For GPU frequencies less than 750MHz, just use the lowest
2711 if (gpu_freq < min_freq)
2714 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2715 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2716 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2718 sandybridge_pcode_write(dev_priv,
2719 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2720 ia_freq | gpu_freq);
2724 void ironlake_teardown_rc6(struct drm_device *dev)
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2728 if (dev_priv->ips.renderctx) {
2729 i915_gem_object_unpin(dev_priv->ips.renderctx);
2730 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2731 dev_priv->ips.renderctx = NULL;
2734 if (dev_priv->ips.pwrctx) {
2735 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2736 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2737 dev_priv->ips.pwrctx = NULL;
2741 static void ironlake_disable_rc6(struct drm_device *dev)
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2745 if (I915_READ(PWRCTXA)) {
2746 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2747 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2748 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2751 I915_WRITE(PWRCTXA, 0);
2752 POSTING_READ(PWRCTXA);
2754 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2755 POSTING_READ(RSTDBYCTL);
2759 static int ironlake_setup_rc6(struct drm_device *dev)
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2763 if (dev_priv->ips.renderctx == NULL)
2764 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2765 if (!dev_priv->ips.renderctx)
2768 if (dev_priv->ips.pwrctx == NULL)
2769 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2770 if (!dev_priv->ips.pwrctx) {
2771 ironlake_teardown_rc6(dev);
2778 static void ironlake_enable_rc6(struct drm_device *dev)
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2782 bool was_interruptible;
2785 /* rc6 disabled by default due to repeated reports of hanging during
2788 if (!intel_enable_rc6(dev))
2791 DRM_LOCK_ASSERT(dev);
2793 ret = ironlake_setup_rc6(dev);
2797 was_interruptible = dev_priv->mm.interruptible;
2798 dev_priv->mm.interruptible = false;
2801 * GPU can automatically power down the render unit if given a page
2804 ret = intel_ring_begin(ring, 6);
2806 ironlake_teardown_rc6(dev);
2807 dev_priv->mm.interruptible = was_interruptible;
2811 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2812 intel_ring_emit(ring, MI_SET_CONTEXT);
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2815 MI_SAVE_EXT_STATE_EN |
2816 MI_RESTORE_EXT_STATE_EN |
2817 MI_RESTORE_INHIBIT);
2818 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2819 intel_ring_emit(ring, MI_NOOP);
2820 intel_ring_emit(ring, MI_FLUSH);
2821 intel_ring_advance(ring);
2824 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2825 * does an implicit flush, combined with MI_FLUSH above, it should be
2826 * safe to assume that renderctx is valid
2828 ret = intel_ring_idle(ring);
2829 dev_priv->mm.interruptible = was_interruptible;
2831 DRM_ERROR("failed to enable ironlake power power savings\n");
2832 ironlake_teardown_rc6(dev);
2836 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2837 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2840 static unsigned long intel_pxfreq(u32 vidfreq)
2843 int div = (vidfreq & 0x3f0000) >> 16;
2844 int post = (vidfreq & 0x3000) >> 12;
2845 int pre = (vidfreq & 0x7);
2850 freq = ((div * 133333) / ((1<<post) * pre));
2855 static const struct cparams {
2861 { 1, 1333, 301, 28664 },
2862 { 1, 1066, 294, 24460 },
2863 { 1, 800, 294, 25192 },
2864 { 0, 1333, 276, 27605 },
2865 { 0, 1066, 276, 27605 },
2866 { 0, 800, 231, 23784 },
2869 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2871 u64 total_count, diff, ret;
2872 u32 count1, count2, count3, m = 0, c = 0;
2873 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2876 mtx_assert(&mchdev_lock, MA_OWNED);
2878 diff1 = now - dev_priv->ips.last_time1;
2880 /* Prevent division-by-zero if we are asking too fast.
2881 * Also, we don't get interesting results if we are polling
2882 * faster than once in 10ms, so just return the saved value
2886 return dev_priv->ips.chipset_power;
2888 count1 = I915_READ(DMIEC);
2889 count2 = I915_READ(DDREC);
2890 count3 = I915_READ(CSIEC);
2892 total_count = count1 + count2 + count3;
2894 /* FIXME: handle per-counter overflow */
2895 if (total_count < dev_priv->ips.last_count1) {
2896 diff = ~0UL - dev_priv->ips.last_count1;
2897 diff += total_count;
2899 diff = total_count - dev_priv->ips.last_count1;
2902 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2903 if (cparams[i].i == dev_priv->ips.c_m &&
2904 cparams[i].t == dev_priv->ips.r_t) {
2911 diff = div_u64(diff, diff1);
2912 ret = ((m * diff) + c);
2913 ret = div_u64(ret, 10);
2915 dev_priv->ips.last_count1 = total_count;
2916 dev_priv->ips.last_time1 = now;
2918 dev_priv->ips.chipset_power = ret;
2923 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2927 if (dev_priv->info->gen != 5)
2930 mtx_lock(&mchdev_lock);
2932 val = __i915_chipset_val(dev_priv);
2934 mtx_unlock(&mchdev_lock);
2939 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2941 unsigned long m, x, b;
2944 tsfs = I915_READ(TSFS);
2946 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2947 x = I915_READ8(I915_TR1);
2949 b = tsfs & TSFS_INTR_MASK;
2951 return ((m * x) / 127) - b;
2954 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2956 static const struct v_table {
2957 u16 vd; /* in .1 mil */
2958 u16 vm; /* in .1 mil */
3089 if (dev_priv->info->is_mobile)
3090 return v_table[pxvid].vm;
3092 return v_table[pxvid].vd;
3095 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3097 struct timespec now, diff1;
3099 unsigned long diffms;
3102 mtx_assert(&mchdev_lock, MA_OWNED);
3106 timespecsub(&diff1, &dev_priv->ips.last_time2);
3108 /* Don't divide by 0 */
3109 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3113 count = I915_READ(GFXEC);
3115 if (count < dev_priv->ips.last_count2) {
3116 diff = ~0UL - dev_priv->ips.last_count2;
3119 diff = count - dev_priv->ips.last_count2;
3122 dev_priv->ips.last_count2 = count;
3123 dev_priv->ips.last_time2 = now;
3125 /* More magic constants... */
3127 diff = div_u64(diff, diffms * 10);
3128 dev_priv->ips.gfx_power = diff;
3131 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3133 if (dev_priv->info->gen != 5)
3136 mtx_lock(&mchdev_lock);
3138 __i915_update_gfx_val(dev_priv);
3140 mtx_unlock(&mchdev_lock);
3143 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3145 unsigned long t, corr, state1, corr2, state2;
3148 mtx_assert(&mchdev_lock, MA_OWNED);
3150 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3151 pxvid = (pxvid >> 24) & 0x7f;
3152 ext_v = pvid_to_extvid(dev_priv, pxvid);
3156 t = i915_mch_val(dev_priv);
3158 /* Revel in the empirically derived constants */
3160 /* Correction factor in 1/100000 units */
3162 corr = ((t * 2349) + 135940);
3164 corr = ((t * 964) + 29317);
3166 corr = ((t * 301) + 1004);
3168 corr = corr * ((150142 * state1) / 10000 - 78642);
3170 corr2 = (corr * dev_priv->ips.corr);
3172 state2 = (corr2 * state1) / 10000;
3173 state2 /= 100; /* convert to mW */
3175 __i915_update_gfx_val(dev_priv);
3177 return dev_priv->ips.gfx_power + state2;
3180 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3184 if (dev_priv->info->gen != 5)
3187 mtx_lock(&mchdev_lock);
3189 val = __i915_gfx_val(dev_priv);
3191 mtx_unlock(&mchdev_lock);
3197 * i915_read_mch_val - return value for IPS use
3199 * Calculate and return a value for the IPS driver to use when deciding whether
3200 * we have thermal and power headroom to increase CPU or GPU power budget.
3202 unsigned long i915_read_mch_val(void)
3204 struct drm_i915_private *dev_priv;
3205 unsigned long chipset_val, graphics_val, ret = 0;
3207 mtx_lock(&mchdev_lock);
3210 dev_priv = i915_mch_dev;
3212 chipset_val = __i915_chipset_val(dev_priv);
3213 graphics_val = __i915_gfx_val(dev_priv);
3215 ret = chipset_val + graphics_val;
3218 mtx_unlock(&mchdev_lock);
3222 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3225 * i915_gpu_raise - raise GPU frequency limit
3227 * Raise the limit; IPS indicates we have thermal headroom.
3229 bool i915_gpu_raise(void)
3231 struct drm_i915_private *dev_priv;
3234 mtx_lock(&mchdev_lock);
3235 if (!i915_mch_dev) {
3239 dev_priv = i915_mch_dev;
3241 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3242 dev_priv->ips.max_delay--;
3245 mtx_unlock(&mchdev_lock);
3249 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3252 * i915_gpu_lower - lower GPU frequency limit
3254 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3255 * frequency maximum.
3257 bool i915_gpu_lower(void)
3259 struct drm_i915_private *dev_priv;
3262 mtx_lock(&mchdev_lock);
3263 if (!i915_mch_dev) {
3267 dev_priv = i915_mch_dev;
3269 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3270 dev_priv->ips.max_delay++;
3273 mtx_unlock(&mchdev_lock);
3277 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3280 * i915_gpu_busy - indicate GPU business to IPS
3282 * Tell the IPS driver whether or not the GPU is busy.
3284 bool i915_gpu_busy(void)
3286 struct drm_i915_private *dev_priv;
3287 struct intel_ring_buffer *ring;
3291 mtx_lock(&mchdev_lock);
3294 dev_priv = i915_mch_dev;
3296 for_each_ring(ring, dev_priv, i)
3297 ret |= !list_empty(&ring->request_list);
3300 mtx_unlock(&mchdev_lock);
3304 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3307 * i915_gpu_turbo_disable - disable graphics turbo
3309 * Disable graphics turbo by resetting the max frequency and setting the
3310 * current frequency to the default.
3312 bool i915_gpu_turbo_disable(void)
3314 struct drm_i915_private *dev_priv;
3317 mtx_lock(&mchdev_lock);
3318 if (!i915_mch_dev) {
3322 dev_priv = i915_mch_dev;
3324 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3326 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3330 mtx_unlock(&mchdev_lock);
3334 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3338 * Tells the intel_ips driver that the i915 driver is now loaded, if
3339 * IPS got loaded first.
3341 * This awkward dance is so that neither module has to depend on the
3342 * other in order for IPS to do the appropriate communication of
3343 * GPU turbo limits to i915.
3346 ips_ping_for_i915_load(void)
3350 link = symbol_get(ips_link_to_i915_driver);
3353 symbol_put(ips_link_to_i915_driver);
3356 #endif /* FREEBSD_WIP */
3358 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3360 /* We only register the i915 ips part with intel-ips once everything is
3361 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3362 mtx_lock(&mchdev_lock);
3363 i915_mch_dev = dev_priv;
3364 mtx_unlock(&mchdev_lock);
3367 ips_ping_for_i915_load();
3368 #endif /* FREEBSD_WIP */
3371 void intel_gpu_ips_teardown(void)
3373 mtx_lock(&mchdev_lock);
3374 i915_mch_dev = NULL;
3375 mtx_unlock(&mchdev_lock);
3377 static void intel_init_emon(struct drm_device *dev)
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3384 /* Disable to program */
3388 /* Program energy weights for various events */
3389 I915_WRITE(SDEW, 0x15040d00);
3390 I915_WRITE(CSIEW0, 0x007f0000);
3391 I915_WRITE(CSIEW1, 0x1e220004);
3392 I915_WRITE(CSIEW2, 0x04000004);
3394 for (i = 0; i < 5; i++)
3395 I915_WRITE(PEW + (i * 4), 0);
3396 for (i = 0; i < 3; i++)
3397 I915_WRITE(DEW + (i * 4), 0);
3399 /* Program P-state weights to account for frequency power adjustment */
3400 for (i = 0; i < 16; i++) {
3401 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3402 unsigned long freq = intel_pxfreq(pxvidfreq);
3403 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3408 val *= (freq / 1000);
3410 val /= (127*127*900);
3412 DRM_ERROR("bad pxval: %ld\n", val);
3415 /* Render standby states get 0 weight */
3419 for (i = 0; i < 4; i++) {
3420 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3421 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3422 I915_WRITE(PXW + (i * 4), val);
3425 /* Adjust magic regs to magic values (more experimental results) */
3426 I915_WRITE(OGW0, 0);
3427 I915_WRITE(OGW1, 0);
3428 I915_WRITE(EG0, 0x00007f00);
3429 I915_WRITE(EG1, 0x0000000e);
3430 I915_WRITE(EG2, 0x000e0000);
3431 I915_WRITE(EG3, 0x68000300);
3432 I915_WRITE(EG4, 0x42000000);
3433 I915_WRITE(EG5, 0x00140031);
3437 for (i = 0; i < 8; i++)
3438 I915_WRITE(PXWL + (i * 4), 0);
3440 /* Enable PMON + select events */
3441 I915_WRITE(ECR, 0x80000019);
3443 lcfuse = I915_READ(LCFUSE02);
3445 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3448 void intel_disable_gt_powersave(struct drm_device *dev)
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3452 if (IS_IRONLAKE_M(dev)) {
3453 ironlake_disable_drps(dev);
3454 ironlake_disable_rc6(dev);
3455 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3456 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work, NULL);
3457 sx_xlock(&dev_priv->rps.hw_lock);
3458 gen6_disable_rps(dev);
3459 sx_xunlock(&dev_priv->rps.hw_lock);
3463 static void intel_gen6_powersave_work(void *arg, int pending)
3465 struct drm_i915_private *dev_priv = arg;
3466 struct drm_device *dev = dev_priv->dev;
3468 sx_xlock(&dev_priv->rps.hw_lock);
3469 gen6_enable_rps(dev);
3470 gen6_update_ring_freq(dev);
3471 sx_xunlock(&dev_priv->rps.hw_lock);
3474 void intel_enable_gt_powersave(struct drm_device *dev)
3476 struct drm_i915_private *dev_priv = dev->dev_private;
3478 if (IS_IRONLAKE_M(dev)) {
3479 ironlake_enable_drps(dev);
3480 ironlake_enable_rc6(dev);
3481 intel_init_emon(dev);
3482 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3484 * PCU communication is slow and this doesn't need to be
3485 * done at any specific time, so do this out of our fast path
3486 * to make resume and init faster.
3488 taskqueue_enqueue_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work,
3489 round_jiffies_up_relative(HZ));
3493 static void ibx_init_clock_gating(struct drm_device *dev)
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3498 * On Ibex Peak and Cougar Point, we need to disable clock
3499 * gating for the panel power sequencer or it will fail to
3500 * start up when no ports are active.
3502 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3505 static void ironlake_init_clock_gating(struct drm_device *dev)
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3510 /* Required for FBC */
3511 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3512 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3513 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3515 I915_WRITE(PCH_3DCGDIS0,
3516 MARIUNIT_CLOCK_GATE_DISABLE |
3517 SVSMUNIT_CLOCK_GATE_DISABLE);
3518 I915_WRITE(PCH_3DCGDIS1,
3519 VFMUNIT_CLOCK_GATE_DISABLE);
3522 * According to the spec the following bits should be set in
3523 * order to enable memory self-refresh
3524 * The bit 22/21 of 0x42004
3525 * The bit 5 of 0x42020
3526 * The bit 15 of 0x45000
3528 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3529 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3530 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3531 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3532 I915_WRITE(DISP_ARB_CTL,
3533 (I915_READ(DISP_ARB_CTL) |
3535 I915_WRITE(WM3_LP_ILK, 0);
3536 I915_WRITE(WM2_LP_ILK, 0);
3537 I915_WRITE(WM1_LP_ILK, 0);
3540 * Based on the document from hardware guys the following bits
3541 * should be set unconditionally in order to enable FBC.
3542 * The bit 22 of 0x42000
3543 * The bit 22 of 0x42004
3544 * The bit 7,8,9 of 0x42020.
3546 if (IS_IRONLAKE_M(dev)) {
3547 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3548 I915_READ(ILK_DISPLAY_CHICKEN1) |
3550 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3551 I915_READ(ILK_DISPLAY_CHICKEN2) |
3555 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3557 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3558 I915_READ(ILK_DISPLAY_CHICKEN2) |
3559 ILK_ELPIN_409_SELECT);
3560 I915_WRITE(_3D_CHICKEN2,
3561 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3562 _3D_CHICKEN2_WM_READ_PIPELINED);
3564 /* WaDisableRenderCachePipelinedFlush */
3565 I915_WRITE(CACHE_MODE_0,
3566 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3568 ibx_init_clock_gating(dev);
3571 static void cpt_init_clock_gating(struct drm_device *dev)
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3578 * On Ibex Peak and Cougar Point, we need to disable clock
3579 * gating for the panel power sequencer or it will fail to
3580 * start up when no ports are active.
3582 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3583 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3584 DPLS_EDP_PPS_FIX_DIS);
3585 /* The below fixes the weird display corruption, a few pixels shifted
3586 * downward, on (only) LVDS of some HP laptops with IVY.
3588 for_each_pipe(pipe) {
3589 val = TRANS_CHICKEN2_TIMING_OVERRIDE;
3590 if (dev_priv->fdi_rx_polarity_inverted)
3591 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3592 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3594 /* WADP0ClockGatingDisable */
3595 for_each_pipe(pipe) {
3596 I915_WRITE(TRANS_CHICKEN1(pipe),
3597 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3601 static void gen6_init_clock_gating(struct drm_device *dev)
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3605 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3607 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3609 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3610 I915_READ(ILK_DISPLAY_CHICKEN2) |
3611 ILK_ELPIN_409_SELECT);
3613 /* WaDisableHiZPlanesWhenMSAAEnabled */
3614 I915_WRITE(_3D_CHICKEN,
3615 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3617 /* WaSetupGtModeTdRowDispatch */
3618 if (IS_SNB_GT1(dev))
3619 I915_WRITE(GEN6_GT_MODE,
3620 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3622 I915_WRITE(WM3_LP_ILK, 0);
3623 I915_WRITE(WM2_LP_ILK, 0);
3624 I915_WRITE(WM1_LP_ILK, 0);
3626 I915_WRITE(CACHE_MODE_0,
3627 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3629 I915_WRITE(GEN6_UCGCTL1,
3630 I915_READ(GEN6_UCGCTL1) |
3631 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3632 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3634 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3635 * gating disable must be set. Failure to set it results in
3636 * flickering pixels due to Z write ordering failures after
3637 * some amount of runtime in the Mesa "fire" demo, and Unigine
3638 * Sanctuary and Tropics, and apparently anything else with
3639 * alpha test or pixel discard.
3641 * According to the spec, bit 11 (RCCUNIT) must also be set,
3642 * but we didn't debug actual testcases to find it out.
3644 * Also apply WaDisableVDSUnitClockGating and
3645 * WaDisableRCPBUnitClockGating.
3647 I915_WRITE(GEN6_UCGCTL2,
3648 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3649 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3650 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3652 /* Bspec says we need to always set all mask bits. */
3653 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3654 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3657 * According to the spec the following bits should be
3658 * set in order to enable memory self-refresh and fbc:
3659 * The bit21 and bit22 of 0x42000
3660 * The bit21 and bit22 of 0x42004
3661 * The bit5 and bit7 of 0x42020
3662 * The bit14 of 0x70180
3663 * The bit14 of 0x71180
3665 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3666 I915_READ(ILK_DISPLAY_CHICKEN1) |
3667 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3668 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3669 I915_READ(ILK_DISPLAY_CHICKEN2) |
3670 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3671 I915_WRITE(ILK_DSPCLK_GATE_D,
3672 I915_READ(ILK_DSPCLK_GATE_D) |
3673 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3674 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3678 /* NOTE Linux<->FreeBSD: Disable GEN6_MBCTL write.
3680 * This arrived in Linux 3.6 in commit
3681 * b4ae3f22d238617ca11610b29fde16cf8c0bc6e0 and causes significantly
3682 * increased power consumption after kldloading i915kms.ko on FreeBSD
3683 * on (some) Sandy Bridge laptops. A Thinkpad X220 reported about 11W
3684 * after booting while idle at the vt(4) console and about double that
3685 * after loading the driver.
3687 * There were reports in Linux of increased consumption after a suspend
3688 * and resume cycle due to that change.
3690 * Linux bug reports:
3691 * https://bugs.freedesktop.org/show_bug.cgi?id=54089
3692 * https://bugzilla.kernel.org/show_bug.cgi?id=58971
3694 * This suspend and resume issue is reportedly fixed in Linux with
3695 * commits 7dcd2677ea912573d9ed4bcd629b0023b2d11505 and
3696 * 7dcd2677ea912573d9ed4bcd629b0023b2d11505 (Linux 3.11). However, I
3697 * found that those changes did not help on FreeBSD, where increased
3698 * power consumption is observed after loading i915kms.ko without
3699 * suspending and resuming.
3701 * This workaround should be removed after updating to a future Linux
3702 * i915 version and verifying normal power consumption on Sandy Bridge.
3705 /* WaMbcDriverBootEnable */
3706 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3707 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3708 #endif /* FREEBSD_WIP */
3710 for_each_pipe(pipe) {
3711 I915_WRITE(DSPCNTR(pipe),
3712 I915_READ(DSPCNTR(pipe)) |
3713 DISPPLANE_TRICKLE_FEED_DISABLE);
3714 intel_flush_display_plane(dev_priv, pipe);
3717 /* The default value should be 0x200 according to docs, but the two
3718 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3719 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3720 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3722 cpt_init_clock_gating(dev);
3725 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3727 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3729 reg &= ~GEN7_FF_SCHED_MASK;
3730 reg |= GEN7_FF_TS_SCHED_HW;
3731 reg |= GEN7_FF_VS_SCHED_HW;
3732 reg |= GEN7_FF_DS_SCHED_HW;
3734 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3737 static void lpt_init_clock_gating(struct drm_device *dev)
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3742 * TODO: this bit should only be enabled when really needed, then
3743 * disabled when not needed anymore in order to save power.
3745 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3746 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3747 I915_READ(SOUTH_DSPCLK_GATE_D) |
3748 PCH_LP_PARTITION_LEVEL_DISABLE);
3751 static void haswell_init_clock_gating(struct drm_device *dev)
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3756 I915_WRITE(WM3_LP_ILK, 0);
3757 I915_WRITE(WM2_LP_ILK, 0);
3758 I915_WRITE(WM1_LP_ILK, 0);
3760 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3761 * This implements the WaDisableRCZUnitClockGating workaround.
3763 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3765 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3766 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3767 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3769 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3770 I915_WRITE(GEN7_L3CNTLREG1,
3771 GEN7_WA_FOR_GEN7_L3_CONTROL);
3772 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3773 GEN7_WA_L3_CHICKEN_MODE);
3775 /* This is required by WaCatErrorRejectionIssue */
3776 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3777 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3778 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3780 for_each_pipe(pipe) {
3781 I915_WRITE(DSPCNTR(pipe),
3782 I915_READ(DSPCNTR(pipe)) |
3783 DISPPLANE_TRICKLE_FEED_DISABLE);
3784 intel_flush_display_plane(dev_priv, pipe);
3787 gen7_setup_fixed_func_scheduler(dev_priv);
3789 /* WaDisable4x2SubspanOptimization */
3790 I915_WRITE(CACHE_MODE_1,
3791 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3793 /* WaMbcDriverBootEnable */
3794 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3795 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3797 /* XXX: This is a workaround for early silicon revisions and should be
3802 WM_DBG_DISALLOW_MULTIPLE_LP |
3803 WM_DBG_DISALLOW_SPRITE |
3804 WM_DBG_DISALLOW_MAXFIFO);
3806 lpt_init_clock_gating(dev);
3809 static void ivybridge_init_clock_gating(struct drm_device *dev)
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3815 I915_WRITE(WM3_LP_ILK, 0);
3816 I915_WRITE(WM2_LP_ILK, 0);
3817 I915_WRITE(WM1_LP_ILK, 0);
3819 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3821 /* WaDisableEarlyCull */
3822 I915_WRITE(_3D_CHICKEN3,
3823 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3825 /* WaDisableBackToBackFlipFix */
3826 I915_WRITE(IVB_CHICKEN3,
3827 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3828 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3830 /* WaDisablePSDDualDispatchEnable */
3831 if (IS_IVB_GT1(dev))
3832 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3833 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3835 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3836 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3838 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3839 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3840 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3842 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3843 I915_WRITE(GEN7_L3CNTLREG1,
3844 GEN7_WA_FOR_GEN7_L3_CONTROL);
3845 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3846 GEN7_WA_L3_CHICKEN_MODE);
3847 if (IS_IVB_GT1(dev))
3848 I915_WRITE(GEN7_ROW_CHICKEN2,
3849 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3851 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3852 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3855 /* WaForceL3Serialization */
3856 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3857 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3859 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3860 * gating disable must be set. Failure to set it results in
3861 * flickering pixels due to Z write ordering failures after
3862 * some amount of runtime in the Mesa "fire" demo, and Unigine
3863 * Sanctuary and Tropics, and apparently anything else with
3864 * alpha test or pixel discard.
3866 * According to the spec, bit 11 (RCCUNIT) must also be set,
3867 * but we didn't debug actual testcases to find it out.
3869 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3870 * This implements the WaDisableRCZUnitClockGating workaround.
3872 I915_WRITE(GEN6_UCGCTL2,
3873 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3874 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3876 /* This is required by WaCatErrorRejectionIssue */
3877 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3878 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3879 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3881 for_each_pipe(pipe) {
3882 I915_WRITE(DSPCNTR(pipe),
3883 I915_READ(DSPCNTR(pipe)) |
3884 DISPPLANE_TRICKLE_FEED_DISABLE);
3885 intel_flush_display_plane(dev_priv, pipe);
3888 /* WaMbcDriverBootEnable */
3889 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3890 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3892 gen7_setup_fixed_func_scheduler(dev_priv);
3894 /* WaDisable4x2SubspanOptimization */
3895 I915_WRITE(CACHE_MODE_1,
3896 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3898 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3899 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3900 snpcr |= GEN6_MBC_SNPCR_MED;
3901 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3903 cpt_init_clock_gating(dev);
3906 static void valleyview_init_clock_gating(struct drm_device *dev)
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3911 I915_WRITE(WM3_LP_ILK, 0);
3912 I915_WRITE(WM2_LP_ILK, 0);
3913 I915_WRITE(WM1_LP_ILK, 0);
3915 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3917 /* WaDisableEarlyCull */
3918 I915_WRITE(_3D_CHICKEN3,
3919 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3921 /* WaDisableBackToBackFlipFix */
3922 I915_WRITE(IVB_CHICKEN3,
3923 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3924 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3926 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3927 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3929 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3930 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3931 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3933 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3934 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3935 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3937 /* WaForceL3Serialization */
3938 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3939 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3941 /* WaDisableDopClockGating */
3942 I915_WRITE(GEN7_ROW_CHICKEN2,
3943 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3945 /* WaForceL3Serialization */
3946 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3947 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3949 /* This is required by WaCatErrorRejectionIssue */
3950 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3951 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3952 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3954 /* WaMbcDriverBootEnable */
3955 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3956 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3959 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3960 * gating disable must be set. Failure to set it results in
3961 * flickering pixels due to Z write ordering failures after
3962 * some amount of runtime in the Mesa "fire" demo, and Unigine
3963 * Sanctuary and Tropics, and apparently anything else with
3964 * alpha test or pixel discard.
3966 * According to the spec, bit 11 (RCCUNIT) must also be set,
3967 * but we didn't debug actual testcases to find it out.
3969 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3970 * This implements the WaDisableRCZUnitClockGating workaround.
3972 * Also apply WaDisableVDSUnitClockGating and
3973 * WaDisableRCPBUnitClockGating.
3975 I915_WRITE(GEN6_UCGCTL2,
3976 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3977 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3978 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3979 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3980 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3982 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3984 for_each_pipe(pipe) {
3985 I915_WRITE(DSPCNTR(pipe),
3986 I915_READ(DSPCNTR(pipe)) |
3987 DISPPLANE_TRICKLE_FEED_DISABLE);
3988 intel_flush_display_plane(dev_priv, pipe);
3991 I915_WRITE(CACHE_MODE_1,
3992 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3995 * On ValleyView, the GUnit needs to signal the GT
3996 * when flip and other events complete. So enable
3997 * all the GUnit->GT interrupts here
3999 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
4000 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
4001 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
4002 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
4003 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
4004 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
4005 PLANEA_FLIPDONE_INT_EN);
4008 * WaDisableVLVClockGating_VBIIssue
4009 * Disable clock gating on th GCFG unit to prevent a delay
4010 * in the reporting of vblank events.
4012 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
4015 static void g4x_init_clock_gating(struct drm_device *dev)
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4018 uint32_t dspclk_gate;
4020 I915_WRITE(RENCLK_GATE_D1, 0);
4021 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4022 GS_UNIT_CLOCK_GATE_DISABLE |
4023 CL_UNIT_CLOCK_GATE_DISABLE);
4024 I915_WRITE(RAMCLK_GATE_D, 0);
4025 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4026 OVRUNIT_CLOCK_GATE_DISABLE |
4027 OVCUNIT_CLOCK_GATE_DISABLE;
4029 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4030 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4032 /* WaDisableRenderCachePipelinedFlush */
4033 I915_WRITE(CACHE_MODE_0,
4034 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4037 static void crestline_init_clock_gating(struct drm_device *dev)
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4041 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4042 I915_WRITE(RENCLK_GATE_D2, 0);
4043 I915_WRITE(DSPCLK_GATE_D, 0);
4044 I915_WRITE(RAMCLK_GATE_D, 0);
4045 I915_WRITE16(DEUC, 0);
4048 static void broadwater_init_clock_gating(struct drm_device *dev)
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4052 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4053 I965_RCC_CLOCK_GATE_DISABLE |
4054 I965_RCPB_CLOCK_GATE_DISABLE |
4055 I965_ISC_CLOCK_GATE_DISABLE |
4056 I965_FBC_CLOCK_GATE_DISABLE);
4057 I915_WRITE(RENCLK_GATE_D2, 0);
4060 static void gen3_init_clock_gating(struct drm_device *dev)
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 u32 dstate = I915_READ(D_STATE);
4065 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4066 DSTATE_DOT_CLOCK_GATING;
4067 I915_WRITE(D_STATE, dstate);
4069 if (IS_PINEVIEW(dev))
4070 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4072 /* IIR "flip pending" means done if this bit is set */
4073 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4076 static void i85x_init_clock_gating(struct drm_device *dev)
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4080 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4083 static void i830_init_clock_gating(struct drm_device *dev)
4085 struct drm_i915_private *dev_priv = dev->dev_private;
4087 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4090 void intel_init_clock_gating(struct drm_device *dev)
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4094 dev_priv->display.init_clock_gating(dev);
4097 /* Starting with Haswell, we have different power wells for
4098 * different parts of the GPU. This attempts to enable them all.
4100 void intel_init_power_wells(struct drm_device *dev)
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 unsigned long power_wells[] = {
4110 if (!IS_HASWELL(dev))
4115 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4116 int well = I915_READ(power_wells[i]);
4118 if ((well & HSW_PWR_WELL_STATE) == 0) {
4119 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4120 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4121 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4128 /* Set up chip specific power management-related functions */
4129 void intel_init_pm(struct drm_device *dev)
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4133 if (I915_HAS_FBC(dev)) {
4134 if (HAS_PCH_SPLIT(dev)) {
4135 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4136 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4137 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4138 } else if (IS_GM45(dev)) {
4139 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4140 dev_priv->display.enable_fbc = g4x_enable_fbc;
4141 dev_priv->display.disable_fbc = g4x_disable_fbc;
4142 } else if (IS_CRESTLINE(dev)) {
4143 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4144 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4145 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4147 /* 855GM needs testing */
4151 if (IS_PINEVIEW(dev))
4152 i915_pineview_get_mem_freq(dev);
4153 else if (IS_GEN5(dev))
4154 i915_ironlake_get_mem_freq(dev);
4156 /* For FIFO watermark updates */
4157 if (HAS_PCH_SPLIT(dev)) {
4159 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4160 dev_priv->display.update_wm = ironlake_update_wm;
4162 DRM_DEBUG_KMS("Failed to get proper latency. "
4164 dev_priv->display.update_wm = NULL;
4166 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4167 } else if (IS_GEN6(dev)) {
4168 if (SNB_READ_WM0_LATENCY()) {
4169 dev_priv->display.update_wm = sandybridge_update_wm;
4170 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4172 DRM_DEBUG_KMS("Failed to read display plane latency. "
4174 dev_priv->display.update_wm = NULL;
4176 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4177 } else if (IS_IVYBRIDGE(dev)) {
4178 /* FIXME: detect B0+ stepping and use auto training */
4179 if (SNB_READ_WM0_LATENCY()) {
4180 dev_priv->display.update_wm = ivybridge_update_wm;
4181 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4183 DRM_DEBUG_KMS("Failed to read display plane latency. "
4185 dev_priv->display.update_wm = NULL;
4187 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4188 } else if (IS_HASWELL(dev)) {
4189 if (SNB_READ_WM0_LATENCY()) {
4190 dev_priv->display.update_wm = sandybridge_update_wm;
4191 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4192 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4194 DRM_DEBUG_KMS("Failed to read display plane latency. "
4196 dev_priv->display.update_wm = NULL;
4198 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4200 dev_priv->display.update_wm = NULL;
4201 } else if (IS_VALLEYVIEW(dev)) {
4202 dev_priv->display.update_wm = valleyview_update_wm;
4203 dev_priv->display.init_clock_gating =
4204 valleyview_init_clock_gating;
4205 } else if (IS_PINEVIEW(dev)) {
4206 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4209 dev_priv->mem_freq)) {
4210 DRM_INFO("failed to find known CxSR latency "
4211 "(found ddr%s fsb freq %d, mem freq %d), "
4213 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4214 dev_priv->fsb_freq, dev_priv->mem_freq);
4215 /* Disable CxSR and never update its watermark again */
4216 pineview_disable_cxsr(dev);
4217 dev_priv->display.update_wm = NULL;
4219 dev_priv->display.update_wm = pineview_update_wm;
4220 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4221 } else if (IS_G4X(dev)) {
4222 dev_priv->display.update_wm = g4x_update_wm;
4223 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4224 } else if (IS_GEN4(dev)) {
4225 dev_priv->display.update_wm = i965_update_wm;
4226 if (IS_CRESTLINE(dev))
4227 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4228 else if (IS_BROADWATER(dev))
4229 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4230 } else if (IS_GEN3(dev)) {
4231 dev_priv->display.update_wm = i9xx_update_wm;
4232 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4233 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4234 } else if (IS_I865G(dev)) {
4235 dev_priv->display.update_wm = i830_update_wm;
4236 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4237 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4238 } else if (IS_I85X(dev)) {
4239 dev_priv->display.update_wm = i9xx_update_wm;
4240 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4241 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4243 dev_priv->display.update_wm = i830_update_wm;
4244 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4246 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4248 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4252 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4254 u32 gt_thread_status_mask;
4256 if (IS_HASWELL(dev_priv->dev))
4257 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4259 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4261 /* w/a for a sporadic read returning 0 by waiting for the GT
4262 * thread to wake up.
4264 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4265 DRM_ERROR("GT thread status wait timed out\n");
4268 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4270 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4271 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4274 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4278 if (IS_HASWELL(dev_priv->dev))
4279 forcewake_ack = FORCEWAKE_ACK_HSW;
4281 forcewake_ack = FORCEWAKE_ACK;
4283 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4284 FORCEWAKE_ACK_TIMEOUT_MS))
4285 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4287 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4288 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4290 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4291 FORCEWAKE_ACK_TIMEOUT_MS))
4292 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4294 __gen6_gt_wait_for_thread_c0(dev_priv);
4297 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4299 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4300 /* something from same cacheline, but !FORCEWAKE_MT */
4301 POSTING_READ(ECOBUS);
4304 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4308 if (IS_HASWELL(dev_priv->dev))
4309 forcewake_ack = FORCEWAKE_ACK_HSW;
4311 forcewake_ack = FORCEWAKE_MT_ACK;
4313 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4314 FORCEWAKE_ACK_TIMEOUT_MS))
4315 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4317 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4318 /* something from same cacheline, but !FORCEWAKE_MT */
4319 POSTING_READ(ECOBUS);
4321 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4322 FORCEWAKE_ACK_TIMEOUT_MS))
4323 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4325 __gen6_gt_wait_for_thread_c0(dev_priv);
4329 * Generally this is called implicitly by the register read function. However,
4330 * if some sequence requires the GT to not power down then this function should
4331 * be called at the beginning of the sequence followed by a call to
4332 * gen6_gt_force_wake_put() at the end of the sequence.
4334 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4337 mtx_lock(&dev_priv->gt_lock);
4338 if (dev_priv->forcewake_count++ == 0)
4339 dev_priv->gt.force_wake_get(dev_priv);
4340 mtx_unlock(&dev_priv->gt_lock);
4343 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4346 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4347 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4348 "MMIO read or write has been dropped %x\n", gtfifodbg))
4349 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4352 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4354 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4355 /* something from same cacheline, but !FORCEWAKE */
4356 POSTING_READ(ECOBUS);
4357 gen6_gt_check_fifodbg(dev_priv);
4360 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4362 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4363 /* something from same cacheline, but !FORCEWAKE_MT */
4364 POSTING_READ(ECOBUS);
4365 gen6_gt_check_fifodbg(dev_priv);
4369 * see gen6_gt_force_wake_get()
4371 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4374 mtx_lock(&dev_priv->gt_lock);
4375 if (--dev_priv->forcewake_count == 0)
4376 dev_priv->gt.force_wake_put(dev_priv);
4377 mtx_unlock(&dev_priv->gt_lock);
4380 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4384 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4386 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4387 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4389 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4391 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4393 dev_priv->gt_fifo_count = fifo;
4395 dev_priv->gt_fifo_count--;
4400 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4402 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4403 /* something from same cacheline, but !FORCEWAKE_VLV */
4404 POSTING_READ(FORCEWAKE_ACK_VLV);
4407 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4409 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4410 FORCEWAKE_ACK_TIMEOUT_MS))
4411 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4413 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4415 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4416 FORCEWAKE_ACK_TIMEOUT_MS))
4417 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4419 __gen6_gt_wait_for_thread_c0(dev_priv);
4422 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4424 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4425 /* something from same cacheline, but !FORCEWAKE_VLV */
4426 POSTING_READ(FORCEWAKE_ACK_VLV);
4427 gen6_gt_check_fifodbg(dev_priv);
4430 void intel_gt_reset(struct drm_device *dev)
4432 struct drm_i915_private *dev_priv = dev->dev_private;
4434 if (IS_VALLEYVIEW(dev)) {
4435 vlv_force_wake_reset(dev_priv);
4436 } else if (INTEL_INFO(dev)->gen >= 6) {
4437 __gen6_gt_force_wake_reset(dev_priv);
4438 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4439 __gen6_gt_force_wake_mt_reset(dev_priv);
4443 void intel_gt_init(struct drm_device *dev)
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4447 mtx_init(&dev_priv->gt_lock, "i915_gt_lock", NULL, MTX_DEF);
4449 intel_gt_reset(dev);
4451 if (IS_VALLEYVIEW(dev)) {
4452 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4453 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4454 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4455 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4456 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4457 } else if (IS_GEN6(dev)) {
4458 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4459 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4461 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->rps.delayed_resume_work, 0,
4462 intel_gen6_powersave_work, dev_priv);
4465 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4467 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
4469 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4470 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4474 I915_WRITE(GEN6_PCODE_DATA, *val);
4475 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4477 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4479 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4483 *val = I915_READ(GEN6_PCODE_DATA);
4484 I915_WRITE(GEN6_PCODE_DATA, 0);
4489 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4491 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
4493 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4494 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4498 I915_WRITE(GEN6_PCODE_DATA, val);
4499 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4501 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4503 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4507 I915_WRITE(GEN6_PCODE_DATA, 0);