2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
30 * @file SDVO command definitions and structures.
33 #define SDVO_OUTPUT_FIRST (0)
34 #define SDVO_OUTPUT_TMDS0 (1 << 0)
35 #define SDVO_OUTPUT_RGB0 (1 << 1)
36 #define SDVO_OUTPUT_CVBS0 (1 << 2)
37 #define SDVO_OUTPUT_SVID0 (1 << 3)
38 #define SDVO_OUTPUT_YPRPB0 (1 << 4)
39 #define SDVO_OUTPUT_SCART0 (1 << 5)
40 #define SDVO_OUTPUT_LVDS0 (1 << 6)
41 #define SDVO_OUTPUT_TMDS1 (1 << 8)
42 #define SDVO_OUTPUT_RGB1 (1 << 9)
43 #define SDVO_OUTPUT_CVBS1 (1 << 10)
44 #define SDVO_OUTPUT_SVID1 (1 << 11)
45 #define SDVO_OUTPUT_YPRPB1 (1 << 12)
46 #define SDVO_OUTPUT_SCART1 (1 << 13)
47 #define SDVO_OUTPUT_LVDS1 (1 << 14)
48 #define SDVO_OUTPUT_LAST (14)
50 struct intel_sdvo_caps {
54 u8 sdvo_version_major;
55 u8 sdvo_version_minor;
56 unsigned int sdvo_inputs_mask:2;
57 unsigned int smooth_scaling:1;
58 unsigned int sharp_scaling:1;
59 unsigned int up_scaling:1;
60 unsigned int down_scaling:1;
61 unsigned int stall_support:1;
64 } __attribute__((packed));
66 /* Note: SDVO detailed timing flags match EDID misc flags. */
67 #define DTD_FLAG_HSYNC_POSITIVE (1 << 1)
68 #define DTD_FLAG_VSYNC_POSITIVE (1 << 2)
69 #define DTD_FLAG_INTERLACE (1 << 7)
71 /** This matches the EDID DTD structure, more or less */
72 struct intel_sdvo_dtd {
74 u16 clock; /**< pixel clock, in 10kHz units */
75 u8 h_active; /**< lower 8 bits (pixels) */
76 u8 h_blank; /**< lower 8 bits (pixels) */
77 u8 h_high; /**< upper 4 bits each h_active, h_blank */
78 u8 v_active; /**< lower 8 bits (lines) */
79 u8 v_blank; /**< lower 8 bits (lines) */
80 u8 v_high; /**< upper 4 bits each v_active, v_blank */
84 u8 h_sync_off; /**< lower 8 bits, from hblank start */
85 u8 h_sync_width; /**< lower 8 bits (pixels) */
86 /** lower 4 bits each vsync offset, vsync width */
89 * 2 high bits of hsync offset, 2 high bits of hsync width,
90 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
92 u8 sync_off_width_high;
95 /** bits 6-7 of vsync offset at bits 6-7 */
99 } __attribute__((packed));
101 struct intel_sdvo_pixel_clock_range {
102 u16 min; /**< pixel clock, in 10kHz units */
103 u16 max; /**< pixel clock, in 10kHz units */
104 } __attribute__((packed));
106 struct intel_sdvo_preferred_input_timing_args {
113 } __attribute__((packed));
115 /* I2C registers for SDVO */
116 #define SDVO_I2C_ARG_0 0x07
117 #define SDVO_I2C_ARG_1 0x06
118 #define SDVO_I2C_ARG_2 0x05
119 #define SDVO_I2C_ARG_3 0x04
120 #define SDVO_I2C_ARG_4 0x03
121 #define SDVO_I2C_ARG_5 0x02
122 #define SDVO_I2C_ARG_6 0x01
123 #define SDVO_I2C_ARG_7 0x00
124 #define SDVO_I2C_OPCODE 0x08
125 #define SDVO_I2C_CMD_STATUS 0x09
126 #define SDVO_I2C_RETURN_0 0x0a
127 #define SDVO_I2C_RETURN_1 0x0b
128 #define SDVO_I2C_RETURN_2 0x0c
129 #define SDVO_I2C_RETURN_3 0x0d
130 #define SDVO_I2C_RETURN_4 0x0e
131 #define SDVO_I2C_RETURN_5 0x0f
132 #define SDVO_I2C_RETURN_6 0x10
133 #define SDVO_I2C_RETURN_7 0x11
134 #define SDVO_I2C_VENDOR_BEGIN 0x20
137 #define SDVO_CMD_STATUS_POWER_ON 0x0
138 #define SDVO_CMD_STATUS_SUCCESS 0x1
139 #define SDVO_CMD_STATUS_NOTSUPP 0x2
140 #define SDVO_CMD_STATUS_INVALID_ARG 0x3
141 #define SDVO_CMD_STATUS_PENDING 0x4
142 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
143 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
145 /* SDVO commands, argument/result registers */
147 #define SDVO_CMD_RESET 0x01
149 /** Returns a struct intel_sdvo_caps */
150 #define SDVO_CMD_GET_DEVICE_CAPS 0x02
152 #define SDVO_CMD_GET_FIRMWARE_REV 0x86
153 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
154 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
155 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
158 * Reports which inputs are trained (managed to sync).
160 * Devices must have trained within 2 vsyncs of a mode change.
162 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03
163 struct intel_sdvo_get_trained_inputs_response {
164 unsigned int input0_trained:1;
165 unsigned int input1_trained:1;
167 } __attribute__((packed));
169 /** Returns a struct intel_sdvo_output_flags of active outputs. */
170 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
173 * Sets the current set of active outputs.
175 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
176 * on multi-output devices.
178 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
181 * Returns the current mapping of SDVO inputs to outputs on the device.
183 * Returns two struct intel_sdvo_output_flags structures.
185 #define SDVO_CMD_GET_IN_OUT_MAP 0x06
186 struct intel_sdvo_in_out_map {
191 * Sets the current mapping of SDVO inputs to outputs on the device.
193 * Takes two struct i380_sdvo_output_flags structures.
195 #define SDVO_CMD_SET_IN_OUT_MAP 0x07
198 * Returns a struct intel_sdvo_output_flags of attached displays.
200 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
203 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
205 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
208 * Takes a struct intel_sdvo_output_flags.
210 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
213 * Returns a struct intel_sdvo_output_flags of displays with hot plug
214 * interrupts enabled.
216 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
218 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
219 struct intel_sdvo_get_interrupt_event_source_response {
220 u16 interrupt_status;
221 unsigned int ambient_light_interrupt:1;
222 unsigned int hdmi_audio_encrypt_change:1;
224 } __attribute__((packed));
227 * Selects which input is affected by future input commands.
229 * Commands affected include SET_INPUT_TIMINGS_PART[12],
230 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
231 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
233 #define SDVO_CMD_SET_TARGET_INPUT 0x10
234 struct intel_sdvo_set_target_input_args {
235 unsigned int target_1:1;
237 } __attribute__((packed));
240 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
241 * future output commands.
243 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
244 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
246 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11
248 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
249 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
250 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
251 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
252 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
253 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
254 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
255 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
257 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
258 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
259 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
260 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
261 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
262 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
263 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
264 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
266 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
267 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
268 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
269 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
270 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
271 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
272 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
273 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
274 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
275 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
276 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
277 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
278 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
279 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
280 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
281 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
282 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
283 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
286 * Generates a DTD based on the given width, height, and flags.
288 * This will be supported by any device supporting scaling or interlaced
291 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
292 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
293 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
294 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
295 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
296 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
297 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
298 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
299 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
300 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
302 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
303 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
305 /** Returns a struct intel_sdvo_pixel_clock_range */
306 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
307 /** Returns a struct intel_sdvo_pixel_clock_range */
308 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
310 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
311 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
313 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
314 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
315 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
316 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
317 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
318 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
319 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
321 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
322 /** 6 bytes of bit flags for TV formats shared by all TV format functions */
323 struct intel_sdvo_tv_format {
324 unsigned int ntsc_m:1;
325 unsigned int ntsc_j:1;
326 unsigned int ntsc_443:1;
327 unsigned int pal_b:1;
328 unsigned int pal_d:1;
329 unsigned int pal_g:1;
330 unsigned int pal_h:1;
331 unsigned int pal_i:1;
333 unsigned int pal_m:1;
334 unsigned int pal_n:1;
335 unsigned int pal_nc:1;
336 unsigned int pal_60:1;
337 unsigned int secam_b:1;
338 unsigned int secam_d:1;
339 unsigned int secam_g:1;
340 unsigned int secam_k:1;
342 unsigned int secam_k1:1;
343 unsigned int secam_l:1;
344 unsigned int secam_60:1;
345 unsigned int hdtv_std_smpte_240m_1080i_59:1;
346 unsigned int hdtv_std_smpte_240m_1080i_60:1;
347 unsigned int hdtv_std_smpte_260m_1080i_59:1;
348 unsigned int hdtv_std_smpte_260m_1080i_60:1;
349 unsigned int hdtv_std_smpte_274m_1080i_50:1;
351 unsigned int hdtv_std_smpte_274m_1080i_59:1;
352 unsigned int hdtv_std_smpte_274m_1080i_60:1;
353 unsigned int hdtv_std_smpte_274m_1080p_23:1;
354 unsigned int hdtv_std_smpte_274m_1080p_24:1;
355 unsigned int hdtv_std_smpte_274m_1080p_25:1;
356 unsigned int hdtv_std_smpte_274m_1080p_29:1;
357 unsigned int hdtv_std_smpte_274m_1080p_30:1;
358 unsigned int hdtv_std_smpte_274m_1080p_50:1;
360 unsigned int hdtv_std_smpte_274m_1080p_59:1;
361 unsigned int hdtv_std_smpte_274m_1080p_60:1;
362 unsigned int hdtv_std_smpte_295m_1080i_50:1;
363 unsigned int hdtv_std_smpte_295m_1080p_50:1;
364 unsigned int hdtv_std_smpte_296m_720p_59:1;
365 unsigned int hdtv_std_smpte_296m_720p_60:1;
366 unsigned int hdtv_std_smpte_296m_720p_50:1;
367 unsigned int hdtv_std_smpte_293m_480p_59:1;
369 unsigned int hdtv_std_smpte_170m_480i_59:1;
370 unsigned int hdtv_std_iturbt601_576i_50:1;
371 unsigned int hdtv_std_iturbt601_576p_50:1;
372 unsigned int hdtv_std_eia_7702a_480i_60:1;
373 unsigned int hdtv_std_eia_7702a_480p_60:1;
375 } __attribute__((packed));
377 #define SDVO_CMD_GET_TV_FORMAT 0x28
379 #define SDVO_CMD_SET_TV_FORMAT 0x29
381 /** Returns the resolutiosn that can be used with the given TV format */
382 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
383 struct intel_sdvo_sdtv_resolution_request {
384 unsigned int ntsc_m:1;
385 unsigned int ntsc_j:1;
386 unsigned int ntsc_443:1;
387 unsigned int pal_b:1;
388 unsigned int pal_d:1;
389 unsigned int pal_g:1;
390 unsigned int pal_h:1;
391 unsigned int pal_i:1;
393 unsigned int pal_m:1;
394 unsigned int pal_n:1;
395 unsigned int pal_nc:1;
396 unsigned int pal_60:1;
397 unsigned int secam_b:1;
398 unsigned int secam_d:1;
399 unsigned int secam_g:1;
400 unsigned int secam_k:1;
402 unsigned int secam_k1:1;
403 unsigned int secam_l:1;
404 unsigned int secam_60:1;
406 } __attribute__((packed));
408 struct intel_sdvo_sdtv_resolution_reply {
409 unsigned int res_320x200:1;
410 unsigned int res_320x240:1;
411 unsigned int res_400x300:1;
412 unsigned int res_640x350:1;
413 unsigned int res_640x400:1;
414 unsigned int res_640x480:1;
415 unsigned int res_704x480:1;
416 unsigned int res_704x576:1;
418 unsigned int res_720x350:1;
419 unsigned int res_720x400:1;
420 unsigned int res_720x480:1;
421 unsigned int res_720x540:1;
422 unsigned int res_720x576:1;
423 unsigned int res_768x576:1;
424 unsigned int res_800x600:1;
425 unsigned int res_832x624:1;
427 unsigned int res_920x766:1;
428 unsigned int res_1024x768:1;
429 unsigned int res_1280x1024:1;
431 } __attribute__((packed));
433 /* Get supported resolution with squire pixel aspect ratio that can be
434 scaled for the requested HDTV format */
435 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
437 struct intel_sdvo_hdtv_resolution_request {
438 unsigned int hdtv_std_smpte_240m_1080i_59:1;
439 unsigned int hdtv_std_smpte_240m_1080i_60:1;
440 unsigned int hdtv_std_smpte_260m_1080i_59:1;
441 unsigned int hdtv_std_smpte_260m_1080i_60:1;
442 unsigned int hdtv_std_smpte_274m_1080i_50:1;
443 unsigned int hdtv_std_smpte_274m_1080i_59:1;
444 unsigned int hdtv_std_smpte_274m_1080i_60:1;
445 unsigned int hdtv_std_smpte_274m_1080p_23:1;
447 unsigned int hdtv_std_smpte_274m_1080p_24:1;
448 unsigned int hdtv_std_smpte_274m_1080p_25:1;
449 unsigned int hdtv_std_smpte_274m_1080p_29:1;
450 unsigned int hdtv_std_smpte_274m_1080p_30:1;
451 unsigned int hdtv_std_smpte_274m_1080p_50:1;
452 unsigned int hdtv_std_smpte_274m_1080p_59:1;
453 unsigned int hdtv_std_smpte_274m_1080p_60:1;
454 unsigned int hdtv_std_smpte_295m_1080i_50:1;
456 unsigned int hdtv_std_smpte_295m_1080p_50:1;
457 unsigned int hdtv_std_smpte_296m_720p_59:1;
458 unsigned int hdtv_std_smpte_296m_720p_60:1;
459 unsigned int hdtv_std_smpte_296m_720p_50:1;
460 unsigned int hdtv_std_smpte_293m_480p_59:1;
461 unsigned int hdtv_std_smpte_170m_480i_59:1;
462 unsigned int hdtv_std_iturbt601_576i_50:1;
463 unsigned int hdtv_std_iturbt601_576p_50:1;
465 unsigned int hdtv_std_eia_7702a_480i_60:1;
466 unsigned int hdtv_std_eia_7702a_480p_60:1;
468 } __attribute__((packed));
470 struct intel_sdvo_hdtv_resolution_reply {
471 unsigned int res_640x480:1;
472 unsigned int res_800x600:1;
473 unsigned int res_1024x768:1;
474 unsigned int res_1280x960:1;
475 unsigned int res_1400x1050:1;
476 unsigned int res_1600x1200:1;
477 unsigned int res_1920x1440:1;
478 unsigned int res_2048x1536:1;
480 unsigned int res_2560x1920:1;
481 unsigned int res_3200x2400:1;
482 unsigned int res_3840x2880:1;
485 unsigned int res_848x480:1;
486 unsigned int res_1064x600:1;
487 unsigned int res_1280x720:1;
488 unsigned int res_1360x768:1;
489 unsigned int res_1704x960:1;
490 unsigned int res_1864x1050:1;
491 unsigned int res_1920x1080:1;
492 unsigned int res_2128x1200:1;
494 unsigned int res_2560x1400:1;
495 unsigned int res_2728x1536:1;
496 unsigned int res_3408x1920:1;
497 unsigned int res_4264x2400:1;
498 unsigned int res_5120x2880:1;
501 unsigned int res_768x480:1;
502 unsigned int res_960x600:1;
503 unsigned int res_1152x720:1;
504 unsigned int res_1124x768:1;
505 unsigned int res_1536x960:1;
506 unsigned int res_1680x1050:1;
507 unsigned int res_1728x1080:1;
508 unsigned int res_1920x1200:1;
510 unsigned int res_2304x1440:1;
511 unsigned int res_2456x1536:1;
512 unsigned int res_3072x1920:1;
513 unsigned int res_3840x2400:1;
514 unsigned int res_4608x2880:1;
517 unsigned int res_1280x1024:1;
520 unsigned int res_1280x768:1;
522 } __attribute__((packed));
524 /* Get supported power state returns info for encoder and monitor, rely on
525 last SetTargetInput and SetTargetOutput calls */
526 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
527 /* Get power state returns info for encoder and monitor, rely on last
528 SetTargetInput and SetTargetOutput calls */
529 #define SDVO_CMD_GET_POWER_STATE 0x2b
530 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
531 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
532 # define SDVO_ENCODER_STATE_ON (1 << 0)
533 # define SDVO_ENCODER_STATE_STANDBY (1 << 1)
534 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
535 # define SDVO_ENCODER_STATE_OFF (1 << 3)
536 # define SDVO_MONITOR_STATE_ON (1 << 4)
537 # define SDVO_MONITOR_STATE_STANDBY (1 << 5)
538 # define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
539 # define SDVO_MONITOR_STATE_OFF (1 << 7)
541 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
542 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
543 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
545 * The panel power sequencing parameters are in units of milliseconds.
546 * The high fields are bits 8:9 of the 10-bit values.
548 struct sdvo_panel_power_sequencing {
555 unsigned int t0_high:2;
556 unsigned int t1_high:2;
557 unsigned int t2_high:2;
558 unsigned int t3_high:2;
560 unsigned int t4_high:2;
562 } __attribute__((packed));
564 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
565 struct sdvo_max_backlight_reply {
568 } __attribute__((packed));
570 #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
571 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
573 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
574 struct sdvo_get_ambient_light_reply {
578 } __attribute__((packed));
579 #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
580 struct sdvo_set_ambient_light_reply {
583 unsigned int enable:1;
585 } __attribute__((packed));
587 /* Set display power state */
588 #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
589 # define SDVO_DISPLAY_STATE_ON (1 << 0)
590 # define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
591 # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
592 # define SDVO_DISPLAY_STATE_OFF (1 << 3)
594 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
595 struct intel_sdvo_enhancements_reply {
596 unsigned int flicker_filter:1;
597 unsigned int flicker_filter_adaptive:1;
598 unsigned int flicker_filter_2d:1;
599 unsigned int saturation:1;
601 unsigned int brightness:1;
602 unsigned int contrast:1;
603 unsigned int overscan_h:1;
605 unsigned int overscan_v:1;
608 unsigned int sharpness:1;
609 unsigned int dot_crawl:1;
610 unsigned int dither:1;
611 unsigned int tv_chroma_filter:1;
612 unsigned int tv_luma_filter:1;
613 } __attribute__((packed));
615 /* Picture enhancement limits below are dependent on the current TV format,
616 * and thus need to be queried and set after it.
618 #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
619 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
620 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
621 #define SDVO_CMD_GET_MAX_SATURATION 0x55
622 #define SDVO_CMD_GET_MAX_HUE 0x58
623 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
624 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e
625 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
626 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
627 #define SDVO_CMD_GET_MAX_HPOS 0x67
628 #define SDVO_CMD_GET_MAX_VPOS 0x6a
629 #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
630 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
631 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
632 struct intel_sdvo_enhancement_limits_reply {
635 } __attribute__((packed));
637 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
638 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
639 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
640 # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
641 # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
642 # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
643 # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
644 # define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
646 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e
647 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f
648 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
649 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
650 #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
651 #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
652 #define SDVO_CMD_GET_SATURATION 0x56
653 #define SDVO_CMD_SET_SATURATION 0x57
654 #define SDVO_CMD_GET_HUE 0x59
655 #define SDVO_CMD_SET_HUE 0x5a
656 #define SDVO_CMD_GET_BRIGHTNESS 0x5c
657 #define SDVO_CMD_SET_BRIGHTNESS 0x5d
658 #define SDVO_CMD_GET_CONTRAST 0x5f
659 #define SDVO_CMD_SET_CONTRAST 0x60
660 #define SDVO_CMD_GET_OVERSCAN_H 0x62
661 #define SDVO_CMD_SET_OVERSCAN_H 0x63
662 #define SDVO_CMD_GET_OVERSCAN_V 0x65
663 #define SDVO_CMD_SET_OVERSCAN_V 0x66
664 #define SDVO_CMD_GET_HPOS 0x68
665 #define SDVO_CMD_SET_HPOS 0x69
666 #define SDVO_CMD_GET_VPOS 0x6b
667 #define SDVO_CMD_SET_VPOS 0x6c
668 #define SDVO_CMD_GET_SHARPNESS 0x6e
669 #define SDVO_CMD_SET_SHARPNESS 0x6f
670 #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
671 #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
672 #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
673 #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
674 struct intel_sdvo_enhancements_arg {
676 } __attribute__((packed));
678 #define SDVO_CMD_GET_DOT_CRAWL 0x70
679 #define SDVO_CMD_SET_DOT_CRAWL 0x71
680 # define SDVO_DOT_CRAWL_ON (1 << 0)
681 # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
683 #define SDVO_CMD_GET_DITHER 0x72
684 #define SDVO_CMD_SET_DITHER 0x73
685 # define SDVO_DITHER_ON (1 << 0)
686 # define SDVO_DITHER_DEFAULT_ON (1 << 1)
688 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
689 # define SDVO_CONTROL_BUS_PROM (1 << 0)
690 # define SDVO_CONTROL_BUS_DDC1 (1 << 1)
691 # define SDVO_CONTROL_BUS_DDC2 (1 << 2)
692 # define SDVO_CONTROL_BUS_DDC3 (1 << 3)
695 #define SDVO_CMD_GET_SUPP_ENCODE 0x9d
696 #define SDVO_CMD_GET_ENCODE 0x9e
697 #define SDVO_CMD_SET_ENCODE 0x9f
698 #define SDVO_ENCODE_DVI 0x0
699 #define SDVO_ENCODE_HDMI 0x1
700 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b
701 #define SDVO_CMD_GET_PIXEL_REPLI 0x8c
702 #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
703 #define SDVO_CMD_SET_COLORIMETRY 0x8e
704 #define SDVO_COLORIMETRY_RGB256 0x0
705 #define SDVO_COLORIMETRY_RGB220 0x1
706 #define SDVO_COLORIMETRY_YCrCb422 0x3
707 #define SDVO_COLORIMETRY_YCrCb444 0x4
708 #define SDVO_CMD_GET_COLORIMETRY 0x8f
709 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
710 #define SDVO_CMD_SET_AUDIO_STAT 0x91
711 #define SDVO_CMD_GET_AUDIO_STAT 0x92
712 #define SDVO_CMD_SET_HBUF_INDEX 0x93
713 #define SDVO_HBUF_INDEX_ELD 0
714 #define SDVO_HBUF_INDEX_AVI_IF 1
715 #define SDVO_CMD_GET_HBUF_INDEX 0x94
716 #define SDVO_CMD_GET_HBUF_INFO 0x95
717 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
718 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
719 #define SDVO_CMD_SET_HBUF_DATA 0x98
720 #define SDVO_CMD_GET_HBUF_DATA 0x99
721 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a
722 #define SDVO_CMD_GET_HBUF_TXRATE 0x9b
723 #define SDVO_HBUF_TX_DISABLED (0 << 6)
724 #define SDVO_HBUF_TX_ONCE (2 << 6)
725 #define SDVO_HBUF_TX_VSYNC (3 << 6)
726 #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
727 #define SDVO_NEED_TO_STALL (1 << 7)
729 struct intel_sdvo_encode {
732 } __attribute__ ((packed));