2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <dev/drm2/drmP.h>
37 #include <dev/drm2/drm.h>
38 #include <dev/drm2/i915/i915_drm.h>
39 #include <dev/drm2/i915/i915_drv.h>
40 #include <dev/drm2/i915/intel_drv.h>
41 #include <dev/drm2/drm_fourcc.h>
44 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
45 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
46 unsigned int crtc_w, unsigned int crtc_h,
47 uint32_t x, uint32_t y,
48 uint32_t src_w, uint32_t src_h)
50 struct drm_device *dev = plane->dev;
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 struct intel_plane *intel_plane = to_intel_plane(plane);
53 int pipe = intel_plane->pipe;
54 u32 sprctl, sprscale = 0;
57 sprctl = I915_READ(SPRCTL(pipe));
59 /* Mask out pixel format bits in case we change it */
60 sprctl &= ~SPRITE_PIXFORMAT_MASK;
61 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
62 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
64 switch (fb->pixel_format) {
65 case DRM_FORMAT_XBGR8888:
66 sprctl |= SPRITE_FORMAT_RGBX888;
69 case DRM_FORMAT_XRGB8888:
70 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
74 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
78 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
82 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
86 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
90 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
91 sprctl |= DVS_FORMAT_RGBX888;
96 if (obj->tiling_mode != I915_TILING_NONE)
97 sprctl |= SPRITE_TILED;
100 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
101 sprctl |= SPRITE_ENABLE;
103 /* Sizes are 0 based */
109 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
112 * IVB workaround: must disable low power watermarks for at least
113 * one frame before enabling scaling. LP watermarks can be re-enabled
114 * when scaling is disabled.
116 if (crtc_w != src_w || crtc_h != src_h) {
117 if (!dev_priv->sprite_scaling_enabled) {
118 dev_priv->sprite_scaling_enabled = true;
119 intel_update_watermarks(dev);
120 intel_wait_for_vblank(dev, pipe);
122 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
124 if (dev_priv->sprite_scaling_enabled) {
125 dev_priv->sprite_scaling_enabled = false;
126 /* potentially re-enable LP watermarks */
127 intel_update_watermarks(dev);
131 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
132 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
133 if (obj->tiling_mode != I915_TILING_NONE) {
134 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
136 unsigned long offset;
138 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
139 I915_WRITE(SPRLINOFF(pipe), offset);
141 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
142 I915_WRITE(SPRSCALE(pipe), sprscale);
143 I915_WRITE(SPRCTL(pipe), sprctl);
144 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
145 POSTING_READ(SPRSURF(pipe));
149 ivb_disable_plane(struct drm_plane *plane)
151 struct drm_device *dev = plane->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct intel_plane *intel_plane = to_intel_plane(plane);
154 int pipe = intel_plane->pipe;
156 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
157 /* Can't leave the scaler enabled... */
158 I915_WRITE(SPRSCALE(pipe), 0);
159 /* Activate double buffered register update */
160 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
161 POSTING_READ(SPRSURF(pipe));
163 dev_priv->sprite_scaling_enabled = false;
164 intel_update_watermarks(dev);
168 ivb_update_colorkey(struct drm_plane *plane,
169 struct drm_intel_sprite_colorkey *key)
171 struct drm_device *dev = plane->dev;
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct intel_plane *intel_plane;
177 intel_plane = to_intel_plane(plane);
179 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
180 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
181 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
183 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
184 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
185 if (key->flags & I915_SET_COLORKEY_DESTINATION)
186 sprctl |= SPRITE_DEST_KEY;
187 else if (key->flags & I915_SET_COLORKEY_SOURCE)
188 sprctl |= SPRITE_SOURCE_KEY;
189 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
191 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
197 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
199 struct drm_device *dev = plane->dev;
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 struct intel_plane *intel_plane;
204 intel_plane = to_intel_plane(plane);
206 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
207 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
208 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
211 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
213 if (sprctl & SPRITE_DEST_KEY)
214 key->flags = I915_SET_COLORKEY_DESTINATION;
215 else if (sprctl & SPRITE_SOURCE_KEY)
216 key->flags = I915_SET_COLORKEY_SOURCE;
218 key->flags = I915_SET_COLORKEY_NONE;
222 ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
223 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
224 unsigned int crtc_w, unsigned int crtc_h,
225 uint32_t x, uint32_t y,
226 uint32_t src_w, uint32_t src_h)
228 struct drm_device *dev = plane->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 struct intel_plane *intel_plane = to_intel_plane(plane);
231 int pipe = intel_plane->pipe, pixel_size;
232 u32 dvscntr, dvsscale;
234 dvscntr = I915_READ(DVSCNTR(pipe));
236 /* Mask out pixel format bits in case we change it */
237 dvscntr &= ~DVS_PIXFORMAT_MASK;
238 dvscntr &= ~DVS_RGB_ORDER_XBGR;
239 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
241 switch (fb->pixel_format) {
242 case DRM_FORMAT_XBGR8888:
243 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
246 case DRM_FORMAT_XRGB8888:
247 dvscntr |= DVS_FORMAT_RGBX888;
250 case DRM_FORMAT_YUYV:
251 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
254 case DRM_FORMAT_YVYU:
255 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
258 case DRM_FORMAT_UYVY:
259 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
262 case DRM_FORMAT_VYUY:
263 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
267 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
268 dvscntr |= DVS_FORMAT_RGBX888;
273 if (obj->tiling_mode != I915_TILING_NONE)
274 dvscntr |= DVS_TILED;
277 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
278 dvscntr |= DVS_ENABLE;
280 /* Sizes are 0 based */
286 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
289 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
290 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
292 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
293 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
294 if (obj->tiling_mode != I915_TILING_NONE) {
295 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
297 unsigned long offset;
299 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
300 I915_WRITE(DVSLINOFF(pipe), offset);
302 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
303 I915_WRITE(DVSSCALE(pipe), dvsscale);
304 I915_WRITE(DVSCNTR(pipe), dvscntr);
305 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
306 POSTING_READ(DVSSURF(pipe));
310 ilk_disable_plane(struct drm_plane *plane)
312 struct drm_device *dev = plane->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_plane *intel_plane = to_intel_plane(plane);
315 int pipe = intel_plane->pipe;
317 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
318 /* Disable the scaler */
319 I915_WRITE(DVSSCALE(pipe), 0);
320 /* Flush double buffered register updates */
321 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
322 POSTING_READ(DVSSURF(pipe));
326 intel_enable_primary(struct drm_crtc *crtc)
328 struct drm_device *dev = crtc->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
331 int reg = DSPCNTR(intel_crtc->plane);
333 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
337 intel_disable_primary(struct drm_crtc *crtc)
339 struct drm_device *dev = crtc->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
342 int reg = DSPCNTR(intel_crtc->plane);
344 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
348 ilk_update_colorkey(struct drm_plane *plane,
349 struct drm_intel_sprite_colorkey *key)
351 struct drm_device *dev = plane->dev;
352 struct drm_i915_private *dev_priv = dev->dev_private;
353 struct intel_plane *intel_plane;
357 intel_plane = to_intel_plane(plane);
359 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
360 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
361 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
363 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
364 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
365 if (key->flags & I915_SET_COLORKEY_DESTINATION)
366 dvscntr |= DVS_DEST_KEY;
367 else if (key->flags & I915_SET_COLORKEY_SOURCE)
368 dvscntr |= DVS_SOURCE_KEY;
369 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
371 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
377 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
379 struct drm_device *dev = plane->dev;
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 struct intel_plane *intel_plane;
384 intel_plane = to_intel_plane(plane);
386 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
387 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
388 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
391 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
393 if (dvscntr & DVS_DEST_KEY)
394 key->flags = I915_SET_COLORKEY_DESTINATION;
395 else if (dvscntr & DVS_SOURCE_KEY)
396 key->flags = I915_SET_COLORKEY_SOURCE;
398 key->flags = I915_SET_COLORKEY_NONE;
402 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
403 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
404 unsigned int crtc_w, unsigned int crtc_h,
405 uint32_t src_x, uint32_t src_y,
406 uint32_t src_w, uint32_t src_h)
408 struct drm_device *dev = plane->dev;
409 struct drm_i915_private *dev_priv = dev->dev_private;
410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
411 struct intel_plane *intel_plane = to_intel_plane(plane);
412 struct intel_framebuffer *intel_fb;
413 struct drm_i915_gem_object *obj, *old_obj;
414 int pipe = intel_plane->pipe;
416 int x = src_x >> 16, y = src_y >> 16;
417 int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
418 bool disable_primary = false;
420 intel_fb = to_intel_framebuffer(fb);
423 old_obj = intel_plane->obj;
428 /* Pipe must be running... */
429 if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
432 if (crtc_x >= primary_w || crtc_y >= primary_h)
435 /* Don't modify another pipe's plane */
436 if (intel_plane->pipe != intel_crtc->pipe)
440 * Clamp the width & height into the visible area. Note we don't
441 * try to scale the source if part of the visible region is offscreen.
442 * The caller must handle that by adjusting source offset and size.
444 if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
448 if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
450 if ((crtc_x + crtc_w) > primary_w)
451 crtc_w = primary_w - crtc_x;
453 if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
457 if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
459 if (crtc_y + crtc_h > primary_h)
460 crtc_h = primary_h - crtc_y;
462 if (!crtc_w || !crtc_h) /* Again, nothing to display */
466 * We can take a larger source and scale it down, but
467 * only so much... 16x is the max on SNB.
469 if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
473 * If the sprite is completely covering the primary plane,
474 * we can disable the primary and save power.
476 if ((crtc_x == 0) && (crtc_y == 0) &&
477 (crtc_w == primary_w) && (crtc_h == primary_h))
478 disable_primary = true;
482 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
486 intel_plane->obj = obj;
489 * Be sure to re-enable the primary before the sprite is no longer
492 if (!disable_primary && intel_plane->primary_disabled) {
493 intel_enable_primary(crtc);
494 intel_plane->primary_disabled = false;
497 intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
498 crtc_w, crtc_h, x, y, src_w, src_h);
500 if (disable_primary) {
501 intel_disable_primary(crtc);
502 intel_plane->primary_disabled = true;
505 /* Unpin old obj after new one is active to avoid ugliness */
508 * It's fairly common to simply update the position of
509 * an existing object. In that case, we don't need to
510 * wait for vblank to avoid ugliness, we only need to
511 * do the pin & ref bookkeeping.
513 if (old_obj != obj) {
515 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
518 intel_unpin_fb_obj(old_obj);
528 intel_disable_plane(struct drm_plane *plane)
530 struct drm_device *dev = plane->dev;
531 struct intel_plane *intel_plane = to_intel_plane(plane);
534 if (intel_plane->primary_disabled) {
535 intel_enable_primary(plane->crtc);
536 intel_plane->primary_disabled = false;
539 intel_plane->disable_plane(plane);
541 if (!intel_plane->obj)
545 intel_unpin_fb_obj(intel_plane->obj);
546 intel_plane->obj = NULL;
553 static void intel_destroy_plane(struct drm_plane *plane)
555 struct intel_plane *intel_plane = to_intel_plane(plane);
556 intel_disable_plane(plane);
557 drm_plane_cleanup(plane);
558 free(intel_plane, DRM_MEM_KMS);
561 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
562 struct drm_file *file_priv)
564 struct drm_intel_sprite_colorkey *set = data;
565 struct drm_mode_object *obj;
566 struct drm_plane *plane;
567 struct intel_plane *intel_plane;
570 if (!drm_core_check_feature(dev, DRIVER_MODESET))
573 /* Make sure we don't try to enable both src & dest simultaneously */
574 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
577 sx_xlock(&dev->mode_config.mutex);
579 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
585 plane = obj_to_plane(obj);
586 intel_plane = to_intel_plane(plane);
587 ret = intel_plane->update_colorkey(plane, set);
590 sx_xunlock(&dev->mode_config.mutex);
594 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
595 struct drm_file *file_priv)
597 struct drm_intel_sprite_colorkey *get = data;
598 struct drm_mode_object *obj;
599 struct drm_plane *plane;
600 struct intel_plane *intel_plane;
603 if (!drm_core_check_feature(dev, DRIVER_MODESET))
606 sx_xlock(&dev->mode_config.mutex);
608 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
614 plane = obj_to_plane(obj);
615 intel_plane = to_intel_plane(plane);
616 intel_plane->get_colorkey(plane, get);
619 sx_xunlock(&dev->mode_config.mutex);
623 static const struct drm_plane_funcs intel_plane_funcs = {
624 .update_plane = intel_update_plane,
625 .disable_plane = intel_disable_plane,
626 .destroy = intel_destroy_plane,
629 static uint32_t ilk_plane_formats[] = {
637 static uint32_t snb_plane_formats[] = {
647 intel_plane_init(struct drm_device *dev, enum pipe pipe)
649 struct intel_plane *intel_plane;
650 unsigned long possible_crtcs;
651 const uint32_t *plane_formats;
652 int num_plane_formats;
655 if (INTEL_INFO(dev)->gen < 5)
658 intel_plane = malloc(sizeof(struct intel_plane), DRM_MEM_KMS,
661 switch (INTEL_INFO(dev)->gen) {
664 intel_plane->max_downscale = 16;
665 intel_plane->update_plane = ilk_update_plane;
666 intel_plane->disable_plane = ilk_disable_plane;
667 intel_plane->update_colorkey = ilk_update_colorkey;
668 intel_plane->get_colorkey = ilk_get_colorkey;
671 plane_formats = snb_plane_formats;
672 num_plane_formats = DRM_ARRAY_SIZE(snb_plane_formats);
674 plane_formats = ilk_plane_formats;
675 num_plane_formats = DRM_ARRAY_SIZE(ilk_plane_formats);
680 intel_plane->max_downscale = 2;
681 intel_plane->update_plane = ivb_update_plane;
682 intel_plane->disable_plane = ivb_disable_plane;
683 intel_plane->update_colorkey = ivb_update_colorkey;
684 intel_plane->get_colorkey = ivb_get_colorkey;
686 plane_formats = snb_plane_formats;
687 num_plane_formats = DRM_ARRAY_SIZE(snb_plane_formats);
694 intel_plane->pipe = pipe;
695 possible_crtcs = (1 << pipe);
696 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
698 plane_formats, num_plane_formats,
701 free(intel_plane, DRM_MEM_KMS);