2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <sys/cdefs.h>
24 __FBSDID("$FreeBSD$");
27 /****************************************************************************/
28 /*Portion I: Definitions shared between VBIOS and Driver */
29 /****************************************************************************/
35 #define ATOM_VERSION_MAJOR 0x00020000
36 #define ATOM_VERSION_MINOR 0x00000002
38 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
40 /* Endianness should be specified before inclusion,
41 * default to little endian
43 #ifndef ATOM_BIG_ENDIAN
44 #error Endian not specified
49 typedef unsigned long ULONG;
53 typedef unsigned char UCHAR;
57 typedef unsigned short USHORT;
63 #define ATOM_EXT_DAC 2
71 #define ATOM_CRTC_INVALID 0xFF
80 #define ATOM_EXT_PLL1 8
81 #define ATOM_EXT_PLL2 9
82 #define ATOM_EXT_CLOCK 10
83 #define ATOM_PPLL_INVALID 0xFF
85 #define ENCODER_REFCLK_SRC_P1PLL 0
86 #define ENCODER_REFCLK_SRC_P2PLL 1
87 #define ENCODER_REFCLK_SRC_DCPLL 2
88 #define ENCODER_REFCLK_SRC_EXTCLK 3
89 #define ENCODER_REFCLK_SRC_INVALID 0xFF
91 #define ATOM_SCALER1 0
92 #define ATOM_SCALER2 1
94 #define ATOM_SCALER_DISABLE 0
95 #define ATOM_SCALER_CENTER 1
96 #define ATOM_SCALER_EXPANSION 2
97 #define ATOM_SCALER_MULTI_EX 3
99 #define ATOM_DISABLE 0
100 #define ATOM_ENABLE 1
101 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
102 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
103 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
104 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
105 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
106 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
107 #define ATOM_INIT (ATOM_DISABLE+7)
108 #define ATOM_GET_STATUS (ATOM_DISABLE+8)
110 #define ATOM_BLANKING 1
111 #define ATOM_BLANKING_OFF 0
113 #define ATOM_CURSOR1 0
114 #define ATOM_CURSOR2 1
122 #define ATOM_TV_NTSC 1
123 #define ATOM_TV_NTSCJ 2
124 #define ATOM_TV_PAL 3
125 #define ATOM_TV_PALM 4
126 #define ATOM_TV_PALCN 5
127 #define ATOM_TV_PALN 6
128 #define ATOM_TV_PAL60 7
129 #define ATOM_TV_SECAM 8
130 #define ATOM_TV_CV 16
132 #define ATOM_DAC1_PS2 1
133 #define ATOM_DAC1_CV 2
134 #define ATOM_DAC1_NTSC 3
135 #define ATOM_DAC1_PAL 4
137 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2
138 #define ATOM_DAC2_CV ATOM_DAC1_CV
139 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
140 #define ATOM_DAC2_PAL ATOM_DAC1_PAL
143 #define ATOM_PM_STANDBY 1
144 #define ATOM_PM_SUSPEND 2
145 #define ATOM_PM_OFF 3
147 /* Bit0:{=0:single, =1:dual},
148 Bit1 {=0:666RGB, =1:888RGB},
150 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
152 #define ATOM_PANEL_MISC_DUAL 0x00000001
153 #define ATOM_PANEL_MISC_888RGB 0x00000002
154 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
155 #define ATOM_PANEL_MISC_FPDI 0x00000010
156 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
157 #define ATOM_PANEL_MISC_SPATIAL 0x00000020
158 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040
159 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080
162 #define MEMTYPE_DDR1 "DDR1"
163 #define MEMTYPE_DDR2 "DDR2"
164 #define MEMTYPE_DDR3 "DDR3"
165 #define MEMTYPE_DDR4 "DDR4"
167 #define ASIC_BUS_TYPE_PCI "PCI"
168 #define ASIC_BUS_TYPE_AGP "AGP"
169 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
171 /* Maximum size of that FireGL flag string */
173 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
174 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
176 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
177 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
179 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
180 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
182 #define HW_ASSISTED_I2C_STATUS_FAILURE 2
183 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
185 #pragma pack(1) /* BIOS data must use byte aligment */
187 /* Define offset to location of ROM header. */
189 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
190 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
192 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
193 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
194 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
195 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
197 /* Common header for all ROM Data tables.
198 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
199 And the pointer actually points to this header. */
201 typedef struct _ATOM_COMMON_TABLE_HEADER
203 USHORT usStructureSize;
204 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
205 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
206 /*Image can't be updated, while Driver needs to carry the new table! */
207 }ATOM_COMMON_TABLE_HEADER;
209 /****************************************************************************/
210 // Structure stores the ROM header.
211 /****************************************************************************/
212 typedef struct _ATOM_ROM_HEADER
214 ATOM_COMMON_TABLE_HEADER sHeader;
215 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
216 atombios should init it as "ATOM", don't change the position */
217 USHORT usBiosRuntimeSegmentAddress;
218 USHORT usProtectedModeInfoOffset;
219 USHORT usConfigFilenameOffset;
220 USHORT usCRC_BlockOffset;
221 USHORT usBIOS_BootupMessageOffset;
222 USHORT usInt10Offset;
223 USHORT usPciBusDevInitCode;
224 USHORT usIoBaseAddress;
225 USHORT usSubsystemVendorID;
226 USHORT usSubsystemID;
227 USHORT usPCI_InfoOffset;
228 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
229 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
230 UCHAR ucExtendedFunctionCode;
234 /*==============================Command Table Portion==================================== */
241 /****************************************************************************/
242 // Structures used in Command.mtb
243 /****************************************************************************/
244 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
245 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
246 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
247 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
248 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
249 USHORT DIGxEncoderControl; //Only used by Bios
250 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
251 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
252 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
253 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
254 USHORT GPIOPinControl; //Atomic Table, only used by Bios
255 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
256 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
257 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
258 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
259 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
260 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
261 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
262 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
263 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
264 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
265 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
266 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
267 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
268 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
269 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
270 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
271 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
272 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
273 USHORT GetConditionalGoldenSetting; //Only used by Bios
274 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
275 USHORT PatchMCSetting; //only used by BIOS
276 USHORT MC_SEQ_Control; //only used by BIOS
277 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
278 USHORT EnableScaler; //Atomic Table, used only by Bios
279 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
280 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
281 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
282 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
283 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
284 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
285 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
286 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
287 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
288 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
289 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
290 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
291 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
292 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
293 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
294 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
295 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
296 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
297 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
298 USHORT MemoryCleanUp; //Atomic Table, only used by Bios
299 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
300 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
301 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
302 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
303 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
304 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
305 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
306 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
307 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
308 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
309 USHORT MemoryTraining; //Atomic Table, used only by Bios
310 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
311 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
312 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
313 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
314 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
315 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
316 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
317 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
318 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
319 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
320 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
321 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
322 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
323 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
324 USHORT DPEncoderService; //Function Table,only used by Bios
325 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
326 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
328 // For backward compatible
329 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
330 #define DPTranslatorControl DIG2EncoderControl
331 #define UNIPHYTransmitterControl DIG1TransmitterControl
332 #define LVTMATransmitterControl DIG2TransmitterControl
333 #define SetCRTC_DPM_State GetConditionalGoldenSetting
334 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
335 #define HPDInterruptService ReadHWAssistedI2CStatus
336 #define EnableVGA_Access GetSCLKOverMCLKRatio
337 #define EnableYUV GetDispObjectInfo
338 #define DynamicClockGating EnableDispPowerGating
339 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam
341 #define TMDSAEncoderControl PatchMCSetting
342 #define LVDSEncoderControl MC_SEQ_Control
343 #define LCD1OutputControl HW_Misc_Operation
346 typedef struct _ATOM_MASTER_COMMAND_TABLE
348 ATOM_COMMON_TABLE_HEADER sHeader;
349 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
350 }ATOM_MASTER_COMMAND_TABLE;
352 /****************************************************************************/
353 // Structures used in every command table
354 /****************************************************************************/
355 typedef struct _ATOM_TABLE_ATTRIBUTE
358 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
359 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
362 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
363 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
364 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
366 }ATOM_TABLE_ATTRIBUTE;
368 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
370 ATOM_TABLE_ATTRIBUTE sbfAccess;
372 }ATOM_TABLE_ATTRIBUTE_ACCESS;
374 /****************************************************************************/
375 // Common header for all command tables.
376 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
377 // And the pointer actually points to this header.
378 /****************************************************************************/
379 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
381 ATOM_COMMON_TABLE_HEADER CommonHeader;
382 ATOM_TABLE_ATTRIBUTE TableAttribute;
383 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
385 /****************************************************************************/
386 // Structures used by ComputeMemoryEnginePLLTable
387 /****************************************************************************/
388 #define COMPUTE_MEMORY_PLL_PARAM 1
389 #define COMPUTE_ENGINE_PLL_PARAM 2
390 #define ADJUST_MC_SETTING_PARAM 3
392 /****************************************************************************/
393 // Structures used by AdjustMemoryControllerTable
394 /****************************************************************************/
395 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
398 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
399 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
400 ULONG ulClockFreq:24;
402 ULONG ulClockFreq:24;
403 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
404 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
406 }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
407 #define POINTER_RETURN_FLAG 0x80
409 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
411 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
412 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
413 UCHAR ucReserved; //may expand to return larger Fbdiv later
414 UCHAR ucFbDiv; //return value
415 UCHAR ucPostDiv; //return value
416 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
418 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
420 ULONG ulClock; //When return, [23:0] return real clock
421 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
422 USHORT usFbDiv; //return Feedback value to be written to register
423 UCHAR ucPostDiv; //return post div to be written to register
424 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
425 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
428 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
429 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
430 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
431 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
432 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
433 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
434 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
436 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
437 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
438 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
439 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
440 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
442 typedef struct _ATOM_COMPUTE_CLOCK_FREQ
445 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
446 ULONG ulClockFreq:24; // in unit of 10kHz
448 ULONG ulClockFreq:24; // in unit of 10kHz
449 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
451 }ATOM_COMPUTE_CLOCK_FREQ;
453 typedef struct _ATOM_S_MPLL_FB_DIVIDER
457 }ATOM_S_MPLL_FB_DIVIDER;
459 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
463 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
464 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
466 UCHAR ucRefDiv; //Output Parameter
467 UCHAR ucPostDiv; //Output Parameter
468 UCHAR ucCntlFlag; //Output Parameter
470 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
473 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
474 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
475 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
476 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
479 // V4 are only used for APU which PLL outside GPU
480 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
483 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
484 ULONG ulClock:24; //Input= target clock, output = actual clock
486 ULONG ulClock:24; //Input= target clock, output = actual clock
487 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
489 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
491 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
496 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
498 UCHAR ucRefDiv; //Output Parameter
499 UCHAR ucPostDiv; //Output Parameter
502 UCHAR ucCntlFlag; //Output Flags
503 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
506 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
509 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
511 // use for ComputeMemoryClockParamTable
512 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
517 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
519 UCHAR ucDllSpeed; //Output
520 UCHAR ucPostDiv; //Output
522 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
523 UCHAR ucPllCntlFlag; //Output:
526 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
528 // definition of ucInputFlag
529 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
530 // definition of ucPllCntlFlag
531 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
532 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
533 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
534 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
536 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
537 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
539 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
541 ATOM_COMPUTE_CLOCK_FREQ ulClock;
543 }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
545 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
547 ATOM_COMPUTE_CLOCK_FREQ ulClock;
550 }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
552 /****************************************************************************/
553 // Structures used by SetEngineClockTable
554 /****************************************************************************/
555 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
557 ULONG ulTargetEngineClock; //In 10Khz unit
558 }SET_ENGINE_CLOCK_PARAMETERS;
560 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
562 ULONG ulTargetEngineClock; //In 10Khz unit
563 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
564 }SET_ENGINE_CLOCK_PS_ALLOCATION;
566 /****************************************************************************/
567 // Structures used by SetMemoryClockTable
568 /****************************************************************************/
569 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
571 ULONG ulTargetMemoryClock; //In 10Khz unit
572 }SET_MEMORY_CLOCK_PARAMETERS;
574 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
576 ULONG ulTargetMemoryClock; //In 10Khz unit
577 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
578 }SET_MEMORY_CLOCK_PS_ALLOCATION;
580 /****************************************************************************/
581 // Structures used by ASIC_Init.ctb
582 /****************************************************************************/
583 typedef struct _ASIC_INIT_PARAMETERS
585 ULONG ulDefaultEngineClock; //In 10Khz unit
586 ULONG ulDefaultMemoryClock; //In 10Khz unit
587 }ASIC_INIT_PARAMETERS;
589 typedef struct _ASIC_INIT_PS_ALLOCATION
591 ASIC_INIT_PARAMETERS sASICInitClocks;
592 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
593 }ASIC_INIT_PS_ALLOCATION;
595 /****************************************************************************/
596 // Structure used by DynamicClockGatingTable.ctb
597 /****************************************************************************/
598 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
600 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
602 }DYNAMIC_CLOCK_GATING_PARAMETERS;
603 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
605 /****************************************************************************/
606 // Structure used by EnableDispPowerGatingTable.ctb
607 /****************************************************************************/
608 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
610 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
611 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
613 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
615 /****************************************************************************/
616 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
617 /****************************************************************************/
618 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
620 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
622 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
623 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
625 /****************************************************************************/
626 // Structures used by DAC_LoadDetectionTable.ctb
627 /****************************************************************************/
628 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
630 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
631 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
632 UCHAR ucMisc; //Valid only when table revision =1.3 and above
633 }DAC_LOAD_DETECTION_PARAMETERS;
635 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
636 #define DAC_LOAD_MISC_YPrPb 0x01
638 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
640 DAC_LOAD_DETECTION_PARAMETERS sDacload;
641 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
642 }DAC_LOAD_DETECTION_PS_ALLOCATION;
644 /****************************************************************************/
645 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
646 /****************************************************************************/
647 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
649 USHORT usPixelClock; // in 10KHz; for bios convenient
650 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
651 UCHAR ucAction; // 0: turn off encoder
652 // 1: setup and turn on encoder
653 // 7: ATOM_ENCODER_INIT Initialize DAC
654 }DAC_ENCODER_CONTROL_PARAMETERS;
656 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
658 /****************************************************************************/
659 // Structures used by DIG1EncoderControlTable
660 // DIG2EncoderControlTable
661 // ExternalEncoderControlTable
662 /****************************************************************************/
663 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
665 USHORT usPixelClock; // in 10KHz; for bios convenient
668 // =0: PHY linkA if bfLane<3
669 // =1: PHY linkB if bfLanes<3
670 // =0: PHY linkA+B if bfLanes=3
671 // [3] Transmitter Sel
672 // =0: UNIPHY or PCIEPHY
674 UCHAR ucAction; // =0: turn off encoder
675 // =1: turn on encoder
682 UCHAR ucLaneNum; // how many lanes to enable
684 }DIG_ENCODER_CONTROL_PARAMETERS;
685 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
686 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
689 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
690 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
691 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
692 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
693 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
694 #define ATOM_ENCODER_CONFIG_LINKA 0x00
695 #define ATOM_ENCODER_CONFIG_LINKB 0x04
696 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
697 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
698 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
699 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00
700 #define ATOM_ENCODER_CONFIG_LVTMA 0x08
701 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
702 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
703 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
705 // ATOM_ENABLE: Enable Encoder
706 // ATOM_DISABLE: Disable Encoder
709 #define ATOM_ENCODER_MODE_DP 0
710 #define ATOM_ENCODER_MODE_LVDS 1
711 #define ATOM_ENCODER_MODE_DVI 2
712 #define ATOM_ENCODER_MODE_HDMI 3
713 #define ATOM_ENCODER_MODE_SDVO 4
714 #define ATOM_ENCODER_MODE_DP_AUDIO 5
715 #define ATOM_ENCODER_MODE_TV 13
716 #define ATOM_ENCODER_MODE_CV 14
717 #define ATOM_ENCODER_MODE_CRT 15
718 #define ATOM_ENCODER_MODE_DVO 16
719 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
720 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
722 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
726 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
727 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
729 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
731 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
733 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
734 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
737 }ATOM_DIG_ENCODER_CONFIG_V2;
740 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
742 USHORT usPixelClock; // in 10KHz; for bios convenient
743 ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
751 UCHAR ucLaneNum; // how many lanes to enable
752 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
754 }DIG_ENCODER_CONTROL_PARAMETERS_V2;
757 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
758 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
759 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
760 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
761 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
762 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
763 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
764 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
765 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
766 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
771 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
773 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
774 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
775 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
776 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
777 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
778 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
779 #define ATOM_ENCODER_CMD_SETUP 0x0f
780 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
783 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
784 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
786 //ucTableFormatRevision=1
787 //ucTableContentRevision=3
788 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
789 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
793 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
795 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
797 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
799 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
802 }ATOM_DIG_ENCODER_CONFIG_V3;
804 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
805 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
806 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
807 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
808 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
809 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
810 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
811 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
812 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
813 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
815 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
817 USHORT usPixelClock; // in 10KHz; for bios convenient
818 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
828 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
831 // =0x11: internal DP1 for NutMeg/Travis DP translator
833 UCHAR ucLaneNum; // how many lanes to enable
834 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
836 }DIG_ENCODER_CONTROL_PARAMETERS_V3;
838 //ucTableFormatRevision=1
839 //ucTableContentRevision=4
841 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
842 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
846 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
848 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
850 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
852 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
855 }ATOM_DIG_ENCODER_CONFIG_V4;
857 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
859 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
860 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
861 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
862 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
863 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
864 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
865 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
866 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
867 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
868 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
869 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
871 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
873 USHORT usPixelClock; // in 10KHz; for bios convenient
875 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
887 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
890 // =0x11: internal DP1 for NutMeg/Travis DP translator
892 UCHAR ucLaneNum; // how many lanes to enable
893 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
894 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
895 }DIG_ENCODER_CONTROL_PARAMETERS_V4;
897 // define ucBitPerColor:
898 #define PANEL_BPC_UNDEFINE 0x00
899 #define PANEL_6BIT_PER_COLOR 0x01
900 #define PANEL_8BIT_PER_COLOR 0x02
901 #define PANEL_10BIT_PER_COLOR 0x03
902 #define PANEL_12BIT_PER_COLOR 0x04
903 #define PANEL_16BIT_PER_COLOR 0x05
906 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
907 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
908 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
910 /****************************************************************************/
911 // Structures used by UNIPHYTransmitterControlTable
912 // LVTMATransmitterControlTable
913 // DVOOutputControlTable
914 /****************************************************************************/
915 typedef struct _ATOM_DP_VS_MODE
921 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
925 USHORT usPixelClock; // in 10KHz; for bios convenient
926 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
927 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
930 // [0]=0: 4 lane Link,
931 // =1: 8 lane Link ( Dual Links TMDS )
932 // [1]=0: InCoherent mode
935 // =0: PHY linkA if bfLane<3
936 // =1: PHY linkB if bfLanes<3
937 // =0: PHY linkA+B if bfLanes=3
938 // [5:4]PCIE lane Sel
939 // =0: lane 0~3 or 0~7
941 // =2: lane 8~11 or 8~15
943 UCHAR ucAction; // =0: turn off encoder
944 // =1: turn on encoder
946 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
948 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
951 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
954 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
955 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
956 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
957 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
958 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
959 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
960 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
962 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
963 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
964 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
966 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
967 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
968 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
969 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
970 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
971 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
972 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
973 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
974 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
975 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
976 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
979 #define ATOM_TRANSMITTER_ACTION_DISABLE 0
980 #define ATOM_TRANSMITTER_ACTION_ENABLE 1
981 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
982 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
983 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
984 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
985 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
986 #define ATOM_TRANSMITTER_ACTION_INIT 7
987 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
988 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
989 #define ATOM_TRANSMITTER_ACTION_SETUP 10
990 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
991 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12
992 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
994 // Following are used for DigTransmitterControlTable ver1.2
995 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
998 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
999 // =1 Dig Transmitter 2 ( Uniphy CD )
1000 // =2 Dig Transmitter 3 ( Uniphy EF )
1002 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1003 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1004 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1005 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1007 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1008 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1010 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1011 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1012 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1013 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1014 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1015 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1017 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1018 // =1 Dig Transmitter 2 ( Uniphy CD )
1019 // =2 Dig Transmitter 3 ( Uniphy EF )
1021 }ATOM_DIG_TRANSMITTER_CONFIG_V2;
1025 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1028 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1031 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1032 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1033 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1036 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1037 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1038 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1041 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1044 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1045 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1046 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1047 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1049 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1053 USHORT usPixelClock; // in 10KHz; for bios convenient
1054 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1055 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1057 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1058 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1059 UCHAR ucReserved[4];
1060 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1062 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1065 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1066 // =1 Dig Transmitter 2 ( Uniphy CD )
1067 // =2 Dig Transmitter 3 ( Uniphy EF )
1068 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1069 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1070 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1071 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1072 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1073 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1075 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1076 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1077 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1078 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1079 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1080 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1081 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1082 // =1 Dig Transmitter 2 ( Uniphy CD )
1083 // =2 Dig Transmitter 3 ( Uniphy EF )
1085 }ATOM_DIG_TRANSMITTER_CONFIG_V3;
1088 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1092 USHORT usPixelClock; // in 10KHz; for bios convenient
1093 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1094 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1096 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1097 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1099 UCHAR ucReserved[3];
1100 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1104 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1107 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1110 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1111 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1112 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1115 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1116 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1117 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1120 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1121 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1122 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1123 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1126 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1127 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1128 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1129 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1132 /****************************************************************************/
1133 // Structures used by UNIPHYTransmitterControlTable V1.4
1134 // ASIC Families: NI
1135 // ucTableFormatRevision=1
1136 // ucTableContentRevision=4
1137 /****************************************************************************/
1138 typedef struct _ATOM_DP_VS_MODE_V4
1146 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1147 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1148 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1150 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1151 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1152 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1156 }ATOM_DP_VS_MODE_V4;
1158 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1161 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1162 // =1 Dig Transmitter 2 ( Uniphy CD )
1163 // =2 Dig Transmitter 3 ( Uniphy EF )
1164 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1165 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1166 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1167 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1168 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1169 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1171 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1172 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1173 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1174 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1175 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1176 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1177 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1178 // =1 Dig Transmitter 2 ( Uniphy CD )
1179 // =2 Dig Transmitter 3 ( Uniphy EF )
1181 }ATOM_DIG_TRANSMITTER_CONFIG_V4;
1183 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1187 USHORT usPixelClock; // in 10KHz; for bios convenient
1188 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1189 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1193 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1196 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1198 UCHAR ucReserved[3];
1199 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1203 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1205 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1207 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1208 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1209 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1211 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1212 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1213 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1215 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1216 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1217 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1218 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1219 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1221 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1222 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1223 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1224 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1227 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1232 UCHAR ucPhyClkSrcId:2;
1233 UCHAR ucCoherentMode:1;
1237 UCHAR ucCoherentMode:1;
1238 UCHAR ucPhyClkSrcId:2;
1242 }ATOM_DIG_TRANSMITTER_CONFIG_V5;
1244 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1246 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1247 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1248 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1249 UCHAR ucLaneNum; // indicate lane number 1-8
1250 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1251 UCHAR ucDigMode; // indicate DIG mode
1253 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1256 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1260 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1263 #define ATOM_PHY_ID_UNIPHYA 0
1264 #define ATOM_PHY_ID_UNIPHYB 1
1265 #define ATOM_PHY_ID_UNIPHYC 2
1266 #define ATOM_PHY_ID_UNIPHYD 3
1267 #define ATOM_PHY_ID_UNIPHYE 4
1268 #define ATOM_PHY_ID_UNIPHYF 5
1269 #define ATOM_PHY_ID_UNIPHYG 6
1272 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1273 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1274 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1275 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1276 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1277 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1278 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1281 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1282 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1283 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1284 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1285 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1286 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1289 #define DP_LANE_SET__0DB_0_4V 0x00
1290 #define DP_LANE_SET__0DB_0_6V 0x01
1291 #define DP_LANE_SET__0DB_0_8V 0x02
1292 #define DP_LANE_SET__0DB_1_2V 0x03
1293 #define DP_LANE_SET__3_5DB_0_4V 0x08
1294 #define DP_LANE_SET__3_5DB_0_6V 0x09
1295 #define DP_LANE_SET__3_5DB_0_8V 0x0a
1296 #define DP_LANE_SET__6DB_0_4V 0x10
1297 #define DP_LANE_SET__6DB_0_6V 0x11
1298 #define DP_LANE_SET__9_5DB_0_4V 0x18
1300 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1302 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1305 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1306 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1308 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1309 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1310 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1311 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1313 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1314 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1316 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1317 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1320 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1321 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1322 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1324 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1327 /****************************************************************************/
1328 // Structures used by ExternalEncoderControlTable V1.3
1329 // ASIC Families: Evergreen, Llano, NI
1330 // ucTableFormatRevision=1
1331 // ucTableContentRevision=3
1332 /****************************************************************************/
1334 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1337 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1338 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1340 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1342 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1343 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1344 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1346 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1349 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1350 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1351 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1352 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1353 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1354 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1355 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1356 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1359 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1360 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1361 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1362 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1363 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
1364 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1365 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1366 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1368 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1370 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1371 ULONG ulReserved[2];
1372 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1375 /****************************************************************************/
1376 // Structures used by DAC1OuputControlTable
1377 // DAC2OuputControlTable
1378 // LVTMAOutputControlTable (Before DEC30)
1379 // TMDSAOutputControlTable (Before DEC30)
1380 /****************************************************************************/
1381 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1383 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1384 // When the display is LCD, in addition to above:
1385 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1386 // ATOM_LCD_SELFTEST_STOP
1388 UCHAR aucPadding[3]; // padding to DWORD aligned
1389 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1391 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1394 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1395 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1397 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1398 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1400 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1401 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1403 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1404 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1406 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1407 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1409 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1410 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1412 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1413 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1415 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1416 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1417 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1419 /****************************************************************************/
1420 // Structures used by BlankCRTCTable
1421 /****************************************************************************/
1422 typedef struct _BLANK_CRTC_PARAMETERS
1424 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1425 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1426 USHORT usBlackColorRCr;
1427 USHORT usBlackColorGY;
1428 USHORT usBlackColorBCb;
1429 }BLANK_CRTC_PARAMETERS;
1430 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1432 /****************************************************************************/
1433 // Structures used by EnableCRTCTable
1434 // EnableCRTCMemReqTable
1435 // UpdateCRTC_DoubleBufferRegistersTable
1436 /****************************************************************************/
1437 typedef struct _ENABLE_CRTC_PARAMETERS
1439 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1440 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1442 }ENABLE_CRTC_PARAMETERS;
1443 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1445 /****************************************************************************/
1446 // Structures used by SetCRTC_OverScanTable
1447 /****************************************************************************/
1448 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1450 USHORT usOverscanRight; // right
1451 USHORT usOverscanLeft; // left
1452 USHORT usOverscanBottom; // bottom
1453 USHORT usOverscanTop; // top
1454 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1456 }SET_CRTC_OVERSCAN_PARAMETERS;
1457 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1459 /****************************************************************************/
1460 // Structures used by SetCRTC_ReplicationTable
1461 /****************************************************************************/
1462 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1464 UCHAR ucH_Replication; // horizontal replication
1465 UCHAR ucV_Replication; // vertical replication
1466 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1468 }SET_CRTC_REPLICATION_PARAMETERS;
1469 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1471 /****************************************************************************/
1472 // Structures used by SelectCRTC_SourceTable
1473 /****************************************************************************/
1474 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1476 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1477 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1479 }SELECT_CRTC_SOURCE_PARAMETERS;
1480 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1482 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1484 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1485 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1486 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1488 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
1491 //#define ASIC_INT_DAC1_ENCODER_ID 0x00
1492 //#define ASIC_INT_TV_ENCODER_ID 0x02
1493 //#define ASIC_INT_DIG1_ENCODER_ID 0x03
1494 //#define ASIC_INT_DAC2_ENCODER_ID 0x04
1495 //#define ASIC_EXT_TV_ENCODER_ID 0x06
1496 //#define ASIC_INT_DVO_ENCODER_ID 0x07
1497 //#define ASIC_INT_DIG2_ENCODER_ID 0x09
1498 //#define ASIC_EXT_DIG_ENCODER_ID 0x05
1501 //#define ATOM_ENCODER_MODE_DP 0
1502 //#define ATOM_ENCODER_MODE_LVDS 1
1503 //#define ATOM_ENCODER_MODE_DVI 2
1504 //#define ATOM_ENCODER_MODE_HDMI 3
1505 //#define ATOM_ENCODER_MODE_SDVO 4
1506 //#define ATOM_ENCODER_MODE_TV 13
1507 //#define ATOM_ENCODER_MODE_CV 14
1508 //#define ATOM_ENCODER_MODE_CRT 15
1510 /****************************************************************************/
1511 // Structures used by SetPixelClockTable
1512 // GetPixelClockTable
1513 /****************************************************************************/
1514 //Major revision=1., Minor revision=1
1515 typedef struct _PIXEL_CLOCK_PARAMETERS
1517 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1518 // 0 means disable PPLL
1519 USHORT usRefDiv; // Reference divider
1520 USHORT usFbDiv; // feedback divider
1521 UCHAR ucPostDiv; // post divider
1522 UCHAR ucFracFbDiv; // fractional feedback divider
1523 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1524 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1525 UCHAR ucCRTC; // Which CRTC uses this Ppll
1527 }PIXEL_CLOCK_PARAMETERS;
1529 //Major revision=1., Minor revision=2, add ucMiscIfno
1531 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1532 #define MISC_DEVICE_INDEX_MASK 0xF0
1533 #define MISC_DEVICE_INDEX_SHIFT 4
1535 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1537 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1538 // 0 means disable PPLL
1539 USHORT usRefDiv; // Reference divider
1540 USHORT usFbDiv; // feedback divider
1541 UCHAR ucPostDiv; // post divider
1542 UCHAR ucFracFbDiv; // fractional feedback divider
1543 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1544 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1545 UCHAR ucCRTC; // Which CRTC uses this Ppll
1546 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1547 }PIXEL_CLOCK_PARAMETERS_V2;
1549 //Major revision=1., Minor revision=3, structure/definition change
1551 //ATOM_ENCODER_MODE_DP
1552 //ATOM_ENOCDER_MODE_LVDS
1553 //ATOM_ENOCDER_MODE_DVI
1554 //ATOM_ENOCDER_MODE_HDMI
1555 //ATOM_ENOCDER_MODE_SDVO
1556 //ATOM_ENCODER_MODE_TV 13
1557 //ATOM_ENCODER_MODE_CV 14
1558 //ATOM_ENCODER_MODE_CRT 15
1561 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1562 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1563 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1564 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1565 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1566 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1567 //#define DVO_ENCODER_CONFIG_24BIT 0x08
1569 //ucMiscInfo: also changed, see below
1570 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1571 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1572 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1573 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1574 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1575 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1576 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1577 // V1.4 for RoadRunner
1578 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1579 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1582 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1584 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1585 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1586 USHORT usRefDiv; // Reference divider
1587 USHORT usFbDiv; // feedback divider
1588 UCHAR ucPostDiv; // post divider
1589 UCHAR ucFracFbDiv; // fractional feedback divider
1590 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1591 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1594 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1595 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1597 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1598 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1599 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1600 }PIXEL_CLOCK_PARAMETERS_V3;
1602 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1603 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1605 typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1607 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1608 // drive the pixel clock. not used for DCPLL case.
1611 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1613 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1614 // 0 means disable PPLL/DCPLL.
1615 USHORT usFbDiv; // feedback divider integer part.
1616 UCHAR ucPostDiv; // post divider.
1617 UCHAR ucRefDiv; // Reference divider
1618 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1619 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1620 // indicate which graphic encoder will be used.
1621 UCHAR ucEncoderMode; // Encoder mode:
1622 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1623 // bit[1]= when VGA timing is used.
1624 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1625 // bit[4]= RefClock source for PPLL.
1626 // =0: XTLAIN( default mode )
1627 // =1: other external clock source, which is pre-defined
1628 // by VBIOS depend on the feature required.
1629 // bit[7:5]: reserved.
1630 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1632 }PIXEL_CLOCK_PARAMETERS_V5;
1634 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1635 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1636 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1637 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1638 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1639 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1640 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1642 typedef struct _CRTC_PIXEL_CLOCK_FREQ
1645 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1646 // drive the pixel clock. not used for DCPLL case.
1647 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1648 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1650 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1651 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1652 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1653 // drive the pixel clock. not used for DCPLL case.
1655 }CRTC_PIXEL_CLOCK_FREQ;
1657 typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1660 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1661 ULONG ulDispEngClkFreq; // dispclk frequency
1663 USHORT usFbDiv; // feedback divider integer part.
1664 UCHAR ucPostDiv; // post divider.
1665 UCHAR ucRefDiv; // Reference divider
1666 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1667 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1668 // indicate which graphic encoder will be used.
1669 UCHAR ucEncoderMode; // Encoder mode:
1670 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1671 // bit[1]= when VGA timing is used.
1672 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1673 // bit[4]= RefClock source for PPLL.
1674 // =0: XTLAIN( default mode )
1675 // =1: other external clock source, which is pre-defined
1676 // by VBIOS depend on the feature required.
1677 // bit[7:5]: reserved.
1678 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1680 }PIXEL_CLOCK_PARAMETERS_V6;
1682 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1683 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1684 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1685 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1686 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1687 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1688 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1689 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1691 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1693 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1694 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1696 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1699 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1700 UCHAR ucReserved[2];
1701 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1703 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1705 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1706 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1708 /****************************************************************************/
1709 // Structures used by AdjustDisplayPllTable
1710 /****************************************************************************/
1711 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1713 USHORT usPixelClock;
1714 UCHAR ucTransmitterID;
1718 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1719 UCHAR ucConfig; //if none DVO, not defined yet
1721 UCHAR ucReserved[3];
1722 }ADJUST_DISPLAY_PLL_PARAMETERS;
1724 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
1725 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
1727 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1729 USHORT usPixelClock; // target pixel clock
1730 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1731 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1732 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1733 UCHAR ucExtTransmitterID; // external encoder id.
1734 UCHAR ucReserved[2];
1735 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1737 // usDispPllConfig v1.2 for RoadRunner
1738 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
1739 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
1740 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
1741 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
1742 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
1743 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
1744 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
1745 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
1746 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
1747 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
1750 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1752 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1753 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1754 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1755 UCHAR ucReserved[2];
1756 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1758 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1762 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
1763 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1765 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1767 /****************************************************************************/
1768 // Structures used by EnableYUVTable
1769 /****************************************************************************/
1770 typedef struct _ENABLE_YUV_PARAMETERS
1772 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1773 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1775 }ENABLE_YUV_PARAMETERS;
1776 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1778 /****************************************************************************/
1779 // Structures used by GetMemoryClockTable
1780 /****************************************************************************/
1781 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1783 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1784 } GET_MEMORY_CLOCK_PARAMETERS;
1785 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
1787 /****************************************************************************/
1788 // Structures used by GetEngineClockTable
1789 /****************************************************************************/
1790 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1792 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1793 } GET_ENGINE_CLOCK_PARAMETERS;
1794 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
1796 /****************************************************************************/
1797 // Following Structures and constant may be obsolete
1798 /****************************************************************************/
1799 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1800 //Read operaion successeful when the parameter space is non-zero, otherwise read operation failed
1801 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1803 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1804 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
1805 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
1806 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
1807 UCHAR ucSlaveAddr; //Read from which slave
1808 UCHAR ucLineNumber; //Read from which HW assisted line
1809 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1810 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1813 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
1814 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
1815 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
1816 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
1817 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
1819 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1821 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1822 USHORT usByteOffset; //Write to which byte
1823 //Upper portion of usByteOffset is Format of data
1828 //blockID+counterID+offsetID
1829 UCHAR ucData; //PS data1
1830 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1831 UCHAR ucSlaveAddr; //Write to which slave
1832 UCHAR ucLineNumber; //Write from which HW assisted line
1833 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1835 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1837 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1839 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1840 UCHAR ucSlaveAddr; //Write to which slave
1841 UCHAR ucLineNumber; //Write from which HW assisted line
1842 }SET_UP_HW_I2C_DATA_PARAMETERS;
1845 /**************************************************************************/
1846 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1849 /****************************************************************************/
1850 // Structures used by PowerConnectorDetectionTable
1851 /****************************************************************************/
1852 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
1854 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1855 UCHAR ucPwrBehaviorId;
1856 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1857 }POWER_CONNECTOR_DETECTION_PARAMETERS;
1859 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1861 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1863 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1864 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1865 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1867 /****************************LVDS SS Command Table Definitions**********************/
1869 /****************************************************************************/
1870 // Structures used by EnableSpreadSpectrumOnPPLLTable
1871 /****************************************************************************/
1872 typedef struct _ENABLE_LVDS_SS_PARAMETERS
1874 USHORT usSpreadSpectrumPercentage;
1875 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1876 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1877 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1879 }ENABLE_LVDS_SS_PARAMETERS;
1881 //ucTableFormatRevision=1,ucTableContentRevision=2
1882 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
1884 USHORT usSpreadSpectrumPercentage;
1885 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1886 UCHAR ucSpreadSpectrumStep; //
1887 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1888 UCHAR ucSpreadSpectrumDelay;
1889 UCHAR ucSpreadSpectrumRange;
1891 }ENABLE_LVDS_SS_PARAMETERS_V2;
1893 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1894 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1896 USHORT usSpreadSpectrumPercentage;
1897 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1898 UCHAR ucSpreadSpectrumStep; //
1899 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1900 UCHAR ucSpreadSpectrumDelay;
1901 UCHAR ucSpreadSpectrumRange;
1902 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1903 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1905 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1907 USHORT usSpreadSpectrumPercentage;
1908 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1909 // Bit[1]: 1-Ext. 0-Int.
1910 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1911 // Bits[7:4] reserved
1912 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1913 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1914 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1915 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1917 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
1918 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
1919 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
1920 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
1921 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
1922 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
1923 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
1924 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
1925 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
1926 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
1927 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1930 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
1932 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
1933 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1934 // Bit[1]: 1-Ext. 0-Int.
1935 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1936 // Bits[7:4] reserved
1937 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1938 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1939 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1940 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
1942 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
1943 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
1944 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
1945 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
1946 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
1947 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
1948 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
1949 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
1950 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
1951 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
1952 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
1953 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
1955 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
1957 /**************************************************************************/
1959 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
1961 PIXEL_CLOCK_PARAMETERS sPCLKInput;
1962 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
1963 }SET_PIXEL_CLOCK_PS_ALLOCATION;
1965 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
1967 /****************************************************************************/
1968 // Structures used by ###
1969 /****************************************************************************/
1970 typedef struct _MEMORY_TRAINING_PARAMETERS
1972 ULONG ulTargetMemoryClock; //In 10Khz unit
1973 }MEMORY_TRAINING_PARAMETERS;
1974 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
1977 /****************************LVDS and other encoder command table definitions **********************/
1980 /****************************************************************************/
1981 // Structures used by LVDSEncoderControlTable (Before DCE30)
1982 // LVTMAEncoderControlTable (Before DCE30)
1983 // TMDSAEncoderControlTable (Before DCE30)
1984 /****************************************************************************/
1985 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
1987 USHORT usPixelClock; // in 10KHz; for bios convenient
1988 UCHAR ucMisc; // bit0=0: Enable single link
1989 // =1: Enable dual link
1992 UCHAR ucAction; // 0: turn off encoder
1993 // 1: setup and turn on encoder
1994 }LVDS_ENCODER_CONTROL_PARAMETERS;
1996 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
1998 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
1999 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2001 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
2002 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2005 //ucTableFormatRevision=1,ucTableContentRevision=2
2006 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2008 USHORT usPixelClock; // in 10KHz; for bios convenient
2009 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2010 UCHAR ucAction; // 0: turn off encoder
2011 // 1: setup and turn on encoder
2012 UCHAR ucTruncate; // bit0=0: Disable truncate
2013 // =1: Enable truncate
2016 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2017 // =1: Enable spatial dithering
2020 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2021 // =1: Enable temporal dithering
2024 // bit5=0: Gray level 2
2026 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2027 // =1: 25FRC_SEL pattern F
2028 // bit6:5=0: 50FRC_SEL pattern A
2029 // =1: 50FRC_SEL pattern B
2030 // =2: 50FRC_SEL pattern C
2031 // =3: 50FRC_SEL pattern D
2032 // bit7=0: 75FRC_SEL pattern E
2033 // =1: 75FRC_SEL pattern F
2034 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2036 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2038 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2039 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2041 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2042 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2044 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2045 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2047 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2048 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2050 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2051 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2053 /****************************************************************************/
2054 // Structures used by ###
2055 /****************************************************************************/
2056 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2058 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2059 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2061 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2063 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2065 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
2066 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2067 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2069 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2071 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2073 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
2074 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2075 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2077 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2079 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
2080 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2081 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2083 /****************************************************************************/
2084 // Structures used by DVOEncoderControlTable
2085 /****************************************************************************/
2086 //ucTableFormatRevision=1,ucTableContentRevision=3
2089 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2090 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2091 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2092 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2093 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2094 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2095 #define DVO_ENCODER_CONFIG_24BIT 0x08
2097 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2099 USHORT usPixelClock;
2101 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2103 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
2104 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2106 //ucTableFormatRevision=1
2107 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2108 // bit1=0: non-coherent mode
2109 // =1: coherent mode
2111 //==========================================================================================
2112 //Only change is here next time when changing encoder parameter definitions again!
2113 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2114 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2116 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2117 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2119 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2120 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2122 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2123 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2125 //==========================================================================================
2126 #define PANEL_ENCODER_MISC_DUAL 0x01
2127 #define PANEL_ENCODER_MISC_COHERENT 0x02
2128 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2129 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2131 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2132 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2133 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2135 #define PANEL_ENCODER_TRUNCATE_EN 0x01
2136 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2137 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2138 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2139 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2140 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2141 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2142 #define PANEL_ENCODER_25FRC_MASK 0x10
2143 #define PANEL_ENCODER_25FRC_E 0x00
2144 #define PANEL_ENCODER_25FRC_F 0x10
2145 #define PANEL_ENCODER_50FRC_MASK 0x60
2146 #define PANEL_ENCODER_50FRC_A 0x00
2147 #define PANEL_ENCODER_50FRC_B 0x20
2148 #define PANEL_ENCODER_50FRC_C 0x40
2149 #define PANEL_ENCODER_50FRC_D 0x60
2150 #define PANEL_ENCODER_75FRC_MASK 0x80
2151 #define PANEL_ENCODER_75FRC_E 0x00
2152 #define PANEL_ENCODER_75FRC_F 0x80
2154 /****************************************************************************/
2155 // Structures used by SetVoltageTable
2156 /****************************************************************************/
2157 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2158 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2159 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2160 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2161 #define SET_VOLTAGE_INIT_MODE 5
2162 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2164 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2165 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2166 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2168 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2169 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2170 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2172 typedef struct _SET_VOLTAGE_PARAMETERS
2174 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2175 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2176 UCHAR ucVoltageIndex; // An index to tell which voltage level
2178 }SET_VOLTAGE_PARAMETERS;
2180 typedef struct _SET_VOLTAGE_PARAMETERS_V2
2182 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2183 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2184 USHORT usVoltageLevel; // real voltage level
2185 }SET_VOLTAGE_PARAMETERS_V2;
2188 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2190 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2191 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2192 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2193 }SET_VOLTAGE_PARAMETERS_V1_3;
2196 #define VOLTAGE_TYPE_VDDC 1
2197 #define VOLTAGE_TYPE_MVDDC 2
2198 #define VOLTAGE_TYPE_MVDDQ 3
2199 #define VOLTAGE_TYPE_VDDCI 4
2201 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2202 #define ATOM_SET_VOLTAGE 0 //Set voltage Level
2203 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2204 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase
2205 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3
2206 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID
2208 // define vitual voltage id in usVoltageLevel
2209 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2210 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2211 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2212 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2214 typedef struct _SET_VOLTAGE_PS_ALLOCATION
2216 SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2217 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2218 }SET_VOLTAGE_PS_ALLOCATION;
2220 // New Added from SI for GetVoltageInfoTable, input parameter structure
2221 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2223 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2224 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2225 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2227 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2229 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2230 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2232 ULONG ulVotlageGpioState;
2233 ULONG ulVoltageGPioMask;
2234 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2236 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2237 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2239 USHORT usVoltageLevel;
2240 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2242 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2245 // GetVoltageInfo v1.1 ucVoltageMode
2246 #define ATOM_GET_VOLTAGE_VID 0x00
2247 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2248 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2249 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2250 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2252 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2253 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2254 // undefined power state
2255 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2256 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2258 /****************************************************************************/
2259 // Structures used by TVEncoderControlTable
2260 /****************************************************************************/
2261 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2263 USHORT usPixelClock; // in 10KHz; for bios convenient
2264 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2265 UCHAR ucAction; // 0: turn off encoder
2266 // 1: setup and turn on encoder
2267 }TV_ENCODER_CONTROL_PARAMETERS;
2269 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2271 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2272 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
2273 }TV_ENCODER_CONTROL_PS_ALLOCATION;
2275 //==============================Data Table Portion====================================
2277 /****************************************************************************/
2278 // Structure used in Data.mtb
2279 /****************************************************************************/
2280 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2282 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2283 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2284 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2285 USHORT StandardVESA_Timing; // Only used by Bios
2286 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2287 USHORT PaletteData; // Only used by BIOS
2288 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2289 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2290 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2291 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2292 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2293 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2294 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2295 USHORT VESA_ToInternalModeLUT; // Only used by Bios
2296 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2297 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2298 USHORT CompassionateData; // Will be obsolete from R600
2299 USHORT SaveRestoreInfo; // Only used by Bios
2300 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2301 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2302 USHORT XTMDS_Info; // Will be obsolete from R600
2303 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2304 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2305 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2306 USHORT MC_InitParameter; // Only used by command table
2307 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2308 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2309 USHORT TV_VideoMode; // Only used by command table
2310 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2311 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2312 USHORT IntegratedSystemInfo; // Shared by various SW components
2313 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2314 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2315 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2316 }ATOM_MASTER_LIST_OF_DATA_TABLES;
2318 typedef struct _ATOM_MASTER_DATA_TABLE
2320 ATOM_COMMON_TABLE_HEADER sHeader;
2321 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
2322 }ATOM_MASTER_DATA_TABLE;
2324 // For backward compatible
2325 #define LVDS_Info LCD_Info
2326 #define DAC_Info PaletteData
2327 #define TMDS_Info DIGTransmitterInfo
2329 /****************************************************************************/
2330 // Structure used in MultimediaCapabilityInfoTable
2331 /****************************************************************************/
2332 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2334 ATOM_COMMON_TABLE_HEADER sHeader;
2335 ULONG ulSignature; // HW info table signature string "$ATI"
2336 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2337 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2338 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2339 UCHAR ucHostPortInfo; // Provides host port configuration information
2340 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
2342 /****************************************************************************/
2343 // Structure used in MultimediaConfigInfoTable
2344 /****************************************************************************/
2345 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2347 ATOM_COMMON_TABLE_HEADER sHeader;
2348 ULONG ulSignature; // MM info table signature sting "$MMT"
2349 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2350 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2351 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2352 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2353 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2354 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2355 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2356 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2357 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2358 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2359 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2360 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2361 }ATOM_MULTIMEDIA_CONFIG_INFO;
2364 /****************************************************************************/
2365 // Structures used in FirmwareInfoTable
2366 /****************************************************************************/
2368 // usBIOSCapability Definition:
2369 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2370 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2371 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2373 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2374 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2375 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2376 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2377 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2378 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2379 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2380 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2381 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2382 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2383 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2384 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2385 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2386 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2390 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2391 typedef struct _ATOM_FIRMWARE_CAPABILITY
2395 USHORT SCL2Redefined:1;
2396 USHORT PostWithoutModeSet:1;
2397 USHORT HyperMemory_Size:4;
2398 USHORT HyperMemory_Support:1;
2399 USHORT PPMode_Assigned:1;
2400 USHORT WMI_SUPPORT:1;
2401 USHORT GPUControlsBL:1;
2402 USHORT EngineClockSS_Support:1;
2403 USHORT MemoryClockSS_Support:1;
2404 USHORT ExtendedDesktopSupport:1;
2405 USHORT DualCRTC_Support:1;
2406 USHORT FirmwarePosted:1;
2408 USHORT FirmwarePosted:1;
2409 USHORT DualCRTC_Support:1;
2410 USHORT ExtendedDesktopSupport:1;
2411 USHORT MemoryClockSS_Support:1;
2412 USHORT EngineClockSS_Support:1;
2413 USHORT GPUControlsBL:1;
2414 USHORT WMI_SUPPORT:1;
2415 USHORT PPMode_Assigned:1;
2416 USHORT HyperMemory_Support:1;
2417 USHORT HyperMemory_Size:4;
2418 USHORT PostWithoutModeSet:1;
2419 USHORT SCL2Redefined:1;
2422 }ATOM_FIRMWARE_CAPABILITY;
2424 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2426 ATOM_FIRMWARE_CAPABILITY sbfAccess;
2428 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2432 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2435 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2439 typedef struct _ATOM_FIRMWARE_INFO
2441 ATOM_COMMON_TABLE_HEADER sHeader;
2442 ULONG ulFirmwareRevision;
2443 ULONG ulDefaultEngineClock; //In 10Khz unit
2444 ULONG ulDefaultMemoryClock; //In 10Khz unit
2445 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2446 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2447 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2448 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2449 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2450 ULONG ulASICMaxEngineClock; //In 10Khz unit
2451 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2452 UCHAR ucASICMaxTemperature;
2453 UCHAR ucPadding[3]; //Don't use them
2454 ULONG aulReservedForBIOS[3]; //Don't use them
2455 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2456 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2457 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2458 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2459 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2460 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2461 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2462 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2463 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2464 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2465 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2466 USHORT usReferenceClock; //In 10Khz unit
2467 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2468 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2469 UCHAR ucDesign_ID; //Indicate what is the board design
2470 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2471 }ATOM_FIRMWARE_INFO;
2473 typedef struct _ATOM_FIRMWARE_INFO_V1_2
2475 ATOM_COMMON_TABLE_HEADER sHeader;
2476 ULONG ulFirmwareRevision;
2477 ULONG ulDefaultEngineClock; //In 10Khz unit
2478 ULONG ulDefaultMemoryClock; //In 10Khz unit
2479 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2480 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2481 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2482 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2483 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2484 ULONG ulASICMaxEngineClock; //In 10Khz unit
2485 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2486 UCHAR ucASICMaxTemperature;
2487 UCHAR ucMinAllowedBL_Level;
2488 UCHAR ucPadding[2]; //Don't use them
2489 ULONG aulReservedForBIOS[2]; //Don't use them
2490 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2491 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2492 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2493 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2494 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2495 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2496 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2497 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2498 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2499 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2500 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2501 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2502 USHORT usReferenceClock; //In 10Khz unit
2503 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2504 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2505 UCHAR ucDesign_ID; //Indicate what is the board design
2506 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2507 }ATOM_FIRMWARE_INFO_V1_2;
2509 typedef struct _ATOM_FIRMWARE_INFO_V1_3
2511 ATOM_COMMON_TABLE_HEADER sHeader;
2512 ULONG ulFirmwareRevision;
2513 ULONG ulDefaultEngineClock; //In 10Khz unit
2514 ULONG ulDefaultMemoryClock; //In 10Khz unit
2515 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2516 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2517 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2518 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2519 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2520 ULONG ulASICMaxEngineClock; //In 10Khz unit
2521 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2522 UCHAR ucASICMaxTemperature;
2523 UCHAR ucMinAllowedBL_Level;
2524 UCHAR ucPadding[2]; //Don't use them
2525 ULONG aulReservedForBIOS; //Don't use them
2526 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2527 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2528 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2529 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2530 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2531 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2532 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2533 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2534 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2535 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2536 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2537 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2538 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2539 USHORT usReferenceClock; //In 10Khz unit
2540 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2541 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2542 UCHAR ucDesign_ID; //Indicate what is the board design
2543 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2544 }ATOM_FIRMWARE_INFO_V1_3;
2546 typedef struct _ATOM_FIRMWARE_INFO_V1_4
2548 ATOM_COMMON_TABLE_HEADER sHeader;
2549 ULONG ulFirmwareRevision;
2550 ULONG ulDefaultEngineClock; //In 10Khz unit
2551 ULONG ulDefaultMemoryClock; //In 10Khz unit
2552 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2553 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2554 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2555 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2556 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2557 ULONG ulASICMaxEngineClock; //In 10Khz unit
2558 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2559 UCHAR ucASICMaxTemperature;
2560 UCHAR ucMinAllowedBL_Level;
2561 USHORT usBootUpVDDCVoltage; //In MV unit
2562 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2563 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2564 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2565 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2566 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2567 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2568 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2569 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2570 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2571 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2572 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2573 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2574 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2575 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2576 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2577 USHORT usReferenceClock; //In 10Khz unit
2578 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2579 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2580 UCHAR ucDesign_ID; //Indicate what is the board design
2581 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2582 }ATOM_FIRMWARE_INFO_V1_4;
2584 //the structure below to be used from Cypress
2585 typedef struct _ATOM_FIRMWARE_INFO_V2_1
2587 ATOM_COMMON_TABLE_HEADER sHeader;
2588 ULONG ulFirmwareRevision;
2589 ULONG ulDefaultEngineClock; //In 10Khz unit
2590 ULONG ulDefaultMemoryClock; //In 10Khz unit
2593 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2594 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2595 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2596 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2597 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2598 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2599 UCHAR ucMinAllowedBL_Level;
2600 USHORT usBootUpVDDCVoltage; //In MV unit
2601 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2602 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2603 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2604 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2605 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2606 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2607 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2608 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2609 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2610 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2611 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2612 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2613 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2614 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2615 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2616 USHORT usCoreReferenceClock; //In 10Khz unit
2617 USHORT usMemoryReferenceClock; //In 10Khz unit
2618 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2619 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2620 UCHAR ucReserved4[3];
2621 }ATOM_FIRMWARE_INFO_V2_1;
2623 //the structure below to be used from NI
2624 //ucTableFormatRevision=2
2625 //ucTableContentRevision=2
2626 typedef struct _ATOM_FIRMWARE_INFO_V2_2
2628 ATOM_COMMON_TABLE_HEADER sHeader;
2629 ULONG ulFirmwareRevision;
2630 ULONG ulDefaultEngineClock; //In 10Khz unit
2631 ULONG ulDefaultMemoryClock; //In 10Khz unit
2632 ULONG ulReserved[2];
2633 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2634 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2635 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2636 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2637 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2638 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2639 UCHAR ucMinAllowedBL_Level;
2640 USHORT usBootUpVDDCVoltage; //In MV unit
2641 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2642 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2643 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2644 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2645 UCHAR ucRemoteDisplayConfig;
2646 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2647 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2648 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2649 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
2650 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2651 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2652 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2653 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2654 USHORT usCoreReferenceClock; //In 10Khz unit
2655 USHORT usMemoryReferenceClock; //In 10Khz unit
2656 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2657 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2658 UCHAR ucReserved9[3];
2659 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2660 USHORT usReserved12;
2661 ULONG ulReserved10[3]; // New added comparing to previous version
2662 }ATOM_FIRMWARE_INFO_V2_2;
2664 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
2667 // definition of ucRemoteDisplayConfig
2668 #define REMOTE_DISPLAY_DISABLE 0x00
2669 #define REMOTE_DISPLAY_ENABLE 0x01
2671 /****************************************************************************/
2672 // Structures used in IntegratedSystemInfoTable
2673 /****************************************************************************/
2674 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
2675 #define IGP_CAP_FLAG_AC_CARD 0x4
2676 #define IGP_CAP_FLAG_SDVO_CARD 0x8
2677 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
2679 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2681 ATOM_COMMON_TABLE_HEADER sHeader;
2682 ULONG ulBootUpEngineClock; //in 10kHz unit
2683 ULONG ulBootUpMemoryClock; //in 10kHz unit
2684 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2685 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2686 UCHAR ucNumberOfCyclesInPeriodHi;
2687 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2689 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
2690 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
2691 ULONG ulReserved[2];
2693 USHORT usFSBClock; //In MHz unit
2694 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2695 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2696 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2697 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2698 USHORT usK8MemoryClock; //in MHz unit
2699 USHORT usK8SyncStartDelay; //in 0.01 us unit
2700 USHORT usK8DataReturnTime; //in 0.01 us unit
2701 UCHAR ucMaxNBVoltage;
2702 UCHAR ucMinNBVoltage;
2703 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2704 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2705 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2706 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2707 UCHAR ucMaxNBVoltageHigh;
2708 UCHAR ucMinNBVoltageHigh;
2709 }ATOM_INTEGRATED_SYSTEM_INFO;
2711 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2712 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
2713 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2714 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2715 For AMD IGP,for now this can be 0
2716 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2717 For AMD IGP,for now this can be 0
2719 usFSBClock: For Intel IGP,it's FSB Freq
2720 For AMD IGP,it's HT Link Speed
2722 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
2723 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2724 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2727 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2728 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2730 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2731 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2733 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2734 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2737 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2738 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2743 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2744 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2745 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2747 SW components can access the IGP system infor structure in the same way as before
2751 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2753 ATOM_COMMON_TABLE_HEADER sHeader;
2754 ULONG ulBootUpEngineClock; //in 10kHz unit
2755 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2756 ULONG ulBootUpUMAClock; //in 10kHz unit
2757 ULONG ulBootUpSidePortClock; //in 10kHz unit
2758 ULONG ulMinSidePortClock; //in 10kHz unit
2759 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2760 ULONG ulSystemConfig; //see explanation below
2761 ULONG ulBootUpReqDisplayVector;
2762 ULONG ulOtherDisplayMisc;
2763 ULONG ulDDISlot1Config;
2764 ULONG ulDDISlot2Config;
2765 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2766 UCHAR ucUMAChannelNumber;
2767 UCHAR ucDockingPinBit;
2768 UCHAR ucDockingPinPolarity;
2769 ULONG ulDockingPinCFGInfo;
2771 USHORT usNumberOfCyclesInPeriod;
2772 USHORT usMaxNBVoltage;
2773 USHORT usMinNBVoltage;
2774 USHORT usBootUpNBVoltage;
2775 ULONG ulHTLinkFreq; //in 10Khz
2776 USHORT usMinHTLinkWidth;
2777 USHORT usMaxHTLinkWidth;
2778 USHORT usUMASyncStartDelay;
2779 USHORT usUMADataReturnTime;
2780 USHORT usLinkStatusZeroTime;
2781 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
2782 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2783 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2784 USHORT usMaxUpStreamHTLinkWidth;
2785 USHORT usMaxDownStreamHTLinkWidth;
2786 USHORT usMinUpStreamHTLinkWidth;
2787 USHORT usMinDownStreamHTLinkWidth;
2788 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2789 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2790 ULONG ulReserved3[96]; //must be 0x0
2791 }ATOM_INTEGRATED_SYSTEM_INFO_V2;
2794 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2795 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2796 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2799 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2800 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2801 =0: system boots up at driver control state. Power state depends on PowerPlay table.
2802 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2803 Bit[3]=1: Only one power state(Performance) will be supported.
2804 =0: Multiple power states supported from PowerPlay table.
2805 Bit[4]=1: CLMC is supported and enabled on current system.
2806 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2807 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2808 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2809 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2810 =0: Voltage settings is determined by powerplay table.
2811 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2812 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2813 Bit[8]=1: CDLF is supported and enabled on current system.
2814 =0: CDLF is not supported or enabled on current system.
2815 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2816 =0: DLL Shut Down feature is not enabled or supported on current system.
2818 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2820 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2821 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2823 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2824 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2825 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2826 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2827 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2828 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2830 [15:8] - Lane configuration attribute;
2831 [23:16]- Connector type, possible value:
2832 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2833 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2834 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2835 CONNECTOR_OBJECT_ID_DISPLAYPORT
2836 CONNECTOR_OBJECT_ID_eDP
2839 ulDDISlot2Config: Same as Slot1.
2840 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2841 For IGP, Hypermemory is the only memory type showed in CCC.
2843 ucUMAChannelNumber: how many channels for the UMA;
2845 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2846 ucDockingPinBit: which bit in this register to read the pin status;
2847 ucDockingPinPolarity:Polarity of the pin when docked;
2849 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2851 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2853 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2854 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2855 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2856 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2857 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2859 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2861 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2862 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
2863 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2864 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
2865 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2867 usUMASyncStartDelay: Memory access latency, required for watermark calculation
2868 usUMADataReturnTime: Memory access latency, required for watermark calculation
2869 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
2870 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2871 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2872 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2873 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2874 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2876 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2877 This must be less than or equal to ulHTLinkFreq(bootup frequency).
2878 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2879 This must be less than or equal to ulHighVoltageHTLinkFreq.
2881 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2882 usMaxDownStreamHTLinkWidth: same as above.
2883 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2884 usMinDownStreamHTLinkWidth: same as above.
2887 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2888 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
2889 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2890 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2891 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
2892 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2893 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
2895 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
2897 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
2898 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
2899 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
2900 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
2901 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
2902 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
2903 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
2904 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
2905 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
2906 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
2908 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
2910 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
2911 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
2912 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
2913 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
2914 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
2915 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
2917 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
2918 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
2919 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
2921 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
2923 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2924 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
2926 ATOM_COMMON_TABLE_HEADER sHeader;
2927 ULONG ulBootUpEngineClock; //in 10kHz unit
2928 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2929 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2930 ULONG ulBootUpUMAClock; //in 10kHz unit
2931 ULONG ulReserved1[8]; //must be 0x0 for the reserved
2932 ULONG ulBootUpReqDisplayVector;
2933 ULONG ulOtherDisplayMisc;
2934 ULONG ulReserved2[4]; //must be 0x0 for the reserved
2935 ULONG ulSystemConfig; //TBD
2936 ULONG ulCPUCapInfo; //TBD
2937 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2938 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2939 USHORT usBootUpNBVoltage; //boot up NB voltage
2940 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2941 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2942 ULONG ulReserved3[4]; //must be 0x0 for the reserved
2943 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
2944 ULONG ulDDISlot2Config;
2945 ULONG ulDDISlot3Config;
2946 ULONG ulDDISlot4Config;
2947 ULONG ulReserved4[4]; //must be 0x0 for the reserved
2948 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2949 UCHAR ucUMAChannelNumber;
2951 ULONG ulReserved5[4]; //must be 0x0 for the reserved
2952 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2953 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2954 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2955 ULONG ulReserved6[61]; //must be 0x0
2956 }ATOM_INTEGRATED_SYSTEM_INFO_V5;
2958 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
2959 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
2960 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
2961 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
2962 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
2963 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
2964 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
2965 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
2966 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
2967 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
2968 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
2969 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
2970 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
2971 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
2973 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
2974 #define ASIC_INT_DAC1_ENCODER_ID 0x00
2975 #define ASIC_INT_TV_ENCODER_ID 0x02
2976 #define ASIC_INT_DIG1_ENCODER_ID 0x03
2977 #define ASIC_INT_DAC2_ENCODER_ID 0x04
2978 #define ASIC_EXT_TV_ENCODER_ID 0x06
2979 #define ASIC_INT_DVO_ENCODER_ID 0x07
2980 #define ASIC_INT_DIG2_ENCODER_ID 0x09
2981 #define ASIC_EXT_DIG_ENCODER_ID 0x05
2982 #define ASIC_EXT_DIG2_ENCODER_ID 0x08
2983 #define ASIC_INT_DIG3_ENCODER_ID 0x0a
2984 #define ASIC_INT_DIG4_ENCODER_ID 0x0b
2985 #define ASIC_INT_DIG5_ENCODER_ID 0x0c
2986 #define ASIC_INT_DIG6_ENCODER_ID 0x0d
2987 #define ASIC_INT_DIG7_ENCODER_ID 0x0e
2989 //define Encoder attribute
2990 #define ATOM_ANALOG_ENCODER 0
2991 #define ATOM_DIGITAL_ENCODER 1
2992 #define ATOM_DP_ENCODER 2
2994 #define ATOM_ENCODER_ENUM_MASK 0x70
2995 #define ATOM_ENCODER_ENUM_ID1 0x00
2996 #define ATOM_ENCODER_ENUM_ID2 0x10
2997 #define ATOM_ENCODER_ENUM_ID3 0x20
2998 #define ATOM_ENCODER_ENUM_ID4 0x30
2999 #define ATOM_ENCODER_ENUM_ID5 0x40
3000 #define ATOM_ENCODER_ENUM_ID6 0x50
3002 #define ATOM_DEVICE_CRT1_INDEX 0x00000000
3003 #define ATOM_DEVICE_LCD1_INDEX 0x00000001
3004 #define ATOM_DEVICE_TV1_INDEX 0x00000002
3005 #define ATOM_DEVICE_DFP1_INDEX 0x00000003
3006 #define ATOM_DEVICE_CRT2_INDEX 0x00000004
3007 #define ATOM_DEVICE_LCD2_INDEX 0x00000005
3008 #define ATOM_DEVICE_DFP6_INDEX 0x00000006
3009 #define ATOM_DEVICE_DFP2_INDEX 0x00000007
3010 #define ATOM_DEVICE_CV_INDEX 0x00000008
3011 #define ATOM_DEVICE_DFP3_INDEX 0x00000009
3012 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3013 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3015 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3016 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3017 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3018 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3019 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3020 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3021 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3023 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3025 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3026 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3027 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3028 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3029 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3030 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3031 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3032 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3033 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3034 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3035 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3036 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3038 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3039 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3040 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
3041 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3043 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3044 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3045 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3046 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3047 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3048 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3049 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3050 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3051 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3052 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3053 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3054 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3055 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3056 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3057 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3060 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3061 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3062 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3063 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3064 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3065 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3067 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3069 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3070 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3072 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3073 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3074 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3075 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3076 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3077 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3079 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3080 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3081 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3082 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3085 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3086 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3087 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3088 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3089 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3090 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3091 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3092 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3093 // Bit 8 = 0 - no CV support= 1- CV is supported
3094 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3095 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3096 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3100 /****************************************************************************/
3101 /* Structure used in MclkSS_InfoTable */
3102 /****************************************************************************/
3104 // [7:0] - I2C LINE Associate ID
3106 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3107 // = 0, [6:0]=SW assisted I2C ID
3108 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3109 // = 2, HW engine for Multimedia use
3110 // = 3-7 Reserved for future I2C engines
3111 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3113 typedef struct _ATOM_I2C_ID_CONFIG
3116 UCHAR bfHW_Capable:1;
3117 UCHAR bfHW_EngineID:3;
3118 UCHAR bfI2C_LineMux:4;
3120 UCHAR bfI2C_LineMux:4;
3121 UCHAR bfHW_EngineID:3;
3122 UCHAR bfHW_Capable:1;
3124 }ATOM_I2C_ID_CONFIG;
3126 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3128 ATOM_I2C_ID_CONFIG sbfAccess;
3130 }ATOM_I2C_ID_CONFIG_ACCESS;
3133 /****************************************************************************/
3134 // Structure used in GPIO_I2C_InfoTable
3135 /****************************************************************************/
3136 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3138 USHORT usClkMaskRegisterIndex;
3139 USHORT usClkEnRegisterIndex;
3140 USHORT usClkY_RegisterIndex;
3141 USHORT usClkA_RegisterIndex;
3142 USHORT usDataMaskRegisterIndex;
3143 USHORT usDataEnRegisterIndex;
3144 USHORT usDataY_RegisterIndex;
3145 USHORT usDataA_RegisterIndex;
3146 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3147 UCHAR ucClkMaskShift;
3151 UCHAR ucDataMaskShift;
3152 UCHAR ucDataEnShift;
3153 UCHAR ucDataY_Shift;
3154 UCHAR ucDataA_Shift;
3157 }ATOM_GPIO_I2C_ASSIGMENT;
3159 typedef struct _ATOM_GPIO_I2C_INFO
3161 ATOM_COMMON_TABLE_HEADER sHeader;
3162 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3163 }ATOM_GPIO_I2C_INFO;
3165 /****************************************************************************/
3166 // Common Structure used in other structures
3167 /****************************************************************************/
3171 //Please don't add or expand this bitfield structure below, this one will retire soon.!
3172 typedef struct _ATOM_MODE_MISC_INFO
3177 USHORT DoubleClock:1;
3179 USHORT CompositeSync:1;
3180 USHORT V_ReplicationBy2:1;
3181 USHORT H_ReplicationBy2:1;
3182 USHORT VerticalCutOff:1;
3183 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3184 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3185 USHORT HorizontalCutOff:1;
3187 USHORT HorizontalCutOff:1;
3188 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3189 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3190 USHORT VerticalCutOff:1;
3191 USHORT H_ReplicationBy2:1;
3192 USHORT V_ReplicationBy2:1;
3193 USHORT CompositeSync:1;
3195 USHORT DoubleClock:1;
3199 }ATOM_MODE_MISC_INFO;
3201 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3203 ATOM_MODE_MISC_INFO sbfAccess;
3205 }ATOM_MODE_MISC_INFO_ACCESS;
3209 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3212 }ATOM_MODE_MISC_INFO_ACCESS;
3217 #define ATOM_H_CUTOFF 0x01
3218 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3219 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3220 #define ATOM_V_CUTOFF 0x08
3221 #define ATOM_H_REPLICATIONBY2 0x10
3222 #define ATOM_V_REPLICATIONBY2 0x20
3223 #define ATOM_COMPOSITESYNC 0x40
3224 #define ATOM_INTERLACE 0x80
3225 #define ATOM_DOUBLE_CLOCK_MODE 0x100
3226 #define ATOM_RGB888_MODE 0x200
3229 #define ATOM_REFRESH_43 43
3230 #define ATOM_REFRESH_47 47
3231 #define ATOM_REFRESH_56 56
3232 #define ATOM_REFRESH_60 60
3233 #define ATOM_REFRESH_65 65
3234 #define ATOM_REFRESH_70 70
3235 #define ATOM_REFRESH_72 72
3236 #define ATOM_REFRESH_75 75
3237 #define ATOM_REFRESH_85 85
3239 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3240 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3242 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3243 // = EDID_HA + EDID_HBL
3244 // VESA_HDISP = VESA_ACTIVE = EDID_HA
3245 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3246 // = EDID_HA + EDID_HSO
3247 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3248 // VESA_BORDER = EDID_BORDER
3250 /****************************************************************************/
3251 // Structure used in SetCRTC_UsingDTDTimingTable
3252 /****************************************************************************/
3253 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3256 USHORT usH_Blanking_Time;
3258 USHORT usV_Blanking_Time;
3259 USHORT usH_SyncOffset;
3260 USHORT usH_SyncWidth;
3261 USHORT usV_SyncOffset;
3262 USHORT usV_SyncWidth;
3263 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3264 UCHAR ucH_Border; // From DFP EDID
3266 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3268 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3270 /****************************************************************************/
3271 // Structure used in SetCRTC_TimingTable
3272 /****************************************************************************/
3273 typedef struct _SET_CRTC_TIMING_PARAMETERS
3275 USHORT usH_Total; // horizontal total
3276 USHORT usH_Disp; // horizontal display
3277 USHORT usH_SyncStart; // horozontal Sync start
3278 USHORT usH_SyncWidth; // horizontal Sync width
3279 USHORT usV_Total; // vertical total
3280 USHORT usV_Disp; // vertical display
3281 USHORT usV_SyncStart; // vertical Sync start
3282 USHORT usV_SyncWidth; // vertical Sync width
3283 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3284 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3285 UCHAR ucOverscanRight; // right
3286 UCHAR ucOverscanLeft; // left
3287 UCHAR ucOverscanBottom; // bottom
3288 UCHAR ucOverscanTop; // top
3290 }SET_CRTC_TIMING_PARAMETERS;
3291 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3293 /****************************************************************************/
3294 // Structure used in StandardVESA_TimingTable
3295 // AnalogTV_InfoTable
3296 // ComponentVideoInfoTable
3297 /****************************************************************************/
3298 typedef struct _ATOM_MODE_TIMING
3300 USHORT usCRTC_H_Total;
3301 USHORT usCRTC_H_Disp;
3302 USHORT usCRTC_H_SyncStart;
3303 USHORT usCRTC_H_SyncWidth;
3304 USHORT usCRTC_V_Total;
3305 USHORT usCRTC_V_Disp;
3306 USHORT usCRTC_V_SyncStart;
3307 USHORT usCRTC_V_SyncWidth;
3308 USHORT usPixelClock; //in 10Khz unit
3309 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3310 USHORT usCRTC_OverscanRight;
3311 USHORT usCRTC_OverscanLeft;
3312 USHORT usCRTC_OverscanBottom;
3313 USHORT usCRTC_OverscanTop;
3315 UCHAR ucInternalModeNumber;
3316 UCHAR ucRefreshRate;
3319 typedef struct _ATOM_DTD_FORMAT
3323 USHORT usHBlanking_Time;
3325 USHORT usVBlanking_Time;
3326 USHORT usHSyncOffset;
3327 USHORT usHSyncWidth;
3328 USHORT usVSyncOffset;
3329 USHORT usVSyncWidth;
3330 USHORT usImageHSize;
3331 USHORT usImageVSize;
3334 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3335 UCHAR ucInternalModeNumber;
3336 UCHAR ucRefreshRate;
3339 /****************************************************************************/
3340 // Structure used in LVDS_InfoTable
3341 // * Need a document to describe this table
3342 /****************************************************************************/
3343 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3344 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3345 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3346 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3348 //ucTableFormatRevision=1
3349 //ucTableContentRevision=1
3350 typedef struct _ATOM_LVDS_INFO
3352 ATOM_COMMON_TABLE_HEADER sHeader;
3353 ATOM_DTD_FORMAT sLCDTiming;
3354 USHORT usModePatchTableOffset;
3355 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3356 USHORT usOffDelayInMs;
3357 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3358 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3359 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3360 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3361 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3362 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3363 UCHAR ucPanelDefaultRefreshRate;
3364 UCHAR ucPanelIdentification;
3368 //ucTableFormatRevision=1
3369 //ucTableContentRevision=2
3370 typedef struct _ATOM_LVDS_INFO_V12
3372 ATOM_COMMON_TABLE_HEADER sHeader;
3373 ATOM_DTD_FORMAT sLCDTiming;
3374 USHORT usExtInfoTableOffset;
3375 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3376 USHORT usOffDelayInMs;
3377 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3378 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3379 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3380 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3381 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3382 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3383 UCHAR ucPanelDefaultRefreshRate;
3384 UCHAR ucPanelIdentification;
3386 USHORT usLCDVenderID;
3387 USHORT usLCDProductID;
3388 UCHAR ucLCDPanel_SpecialHandlingCap;
3389 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3390 UCHAR ucReserved[2];
3391 }ATOM_LVDS_INFO_V12;
3393 //Definitions for ucLCDPanel_SpecialHandlingCap:
3395 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3396 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3397 #define LCDPANEL_CAP_READ_EDID 0x1
3399 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3400 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3401 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3402 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3404 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3405 #define LCDPANEL_CAP_eDP 0x4
3408 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3410 // 0 0 0 - Color bit depth is undefined
3411 // 0 0 1 - 6 Bits per Primary Color
3412 // 0 1 0 - 8 Bits per Primary Color
3413 // 0 1 1 - 10 Bits per Primary Color
3414 // 1 0 0 - 12 Bits per Primary Color
3415 // 1 0 1 - 14 Bits per Primary Color
3416 // 1 1 0 - 16 Bits per Primary Color
3419 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3421 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3422 #define PANEL_RANDOM_DITHER 0x80
3423 #define PANEL_RANDOM_DITHER_MASK 0x80
3425 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3427 /****************************************************************************/
3428 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3429 // ASIC Families: NI
3430 // ucTableFormatRevision=1
3431 // ucTableContentRevision=3
3432 /****************************************************************************/
3433 typedef struct _ATOM_LCD_INFO_V13
3435 ATOM_COMMON_TABLE_HEADER sHeader;
3436 ATOM_DTD_FORMAT sLCDTiming;
3437 USHORT usExtInfoTableOffset;
3438 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3440 UCHAR ucLCD_Misc; // Reorganized in V13
3441 // Bit0: {=0:single, =1:dual},
3442 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3443 // Bit3:2: {Grey level}
3444 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3445 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3446 UCHAR ucPanelDefaultRefreshRate;
3447 UCHAR ucPanelIdentification;
3449 USHORT usLCDVenderID;
3450 USHORT usLCDProductID;
3451 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3452 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3453 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3454 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3456 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3457 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3459 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3460 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3461 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3462 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3464 UCHAR ucOffDelay_in4Ms;
3465 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3466 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3469 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3470 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3471 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3472 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3474 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
3475 UCHAR uceDPToLVDSRxId;
3477 ULONG ulReserved[2];
3480 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
3482 //Definitions for ucLCD_Misc
3483 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001
3484 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002
3485 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
3486 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
3487 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
3488 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
3489 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
3491 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3493 // 0 0 0 - Color bit depth is undefined
3494 // 0 0 1 - 6 Bits per Primary Color
3495 // 0 1 0 - 8 Bits per Primary Color
3496 // 0 1 1 - 10 Bits per Primary Color
3497 // 1 0 0 - 12 Bits per Primary Color
3498 // 1 0 1 - 14 Bits per Primary Color
3499 // 1 1 0 - 16 Bits per Primary Color
3502 //Definitions for ucLCDPanel_SpecialHandlingCap:
3504 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3505 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3506 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3508 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3509 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3510 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3511 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
3513 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3514 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
3517 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3518 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
3519 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
3521 typedef struct _ATOM_PATCH_RECORD_MODE
3526 }ATOM_PATCH_RECORD_MODE;
3528 typedef struct _ATOM_LCD_RTS_RECORD
3532 }ATOM_LCD_RTS_RECORD;
3534 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
3535 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
3536 typedef struct _ATOM_LCD_MODE_CONTROL_CAP
3540 }ATOM_LCD_MODE_CONTROL_CAP;
3542 #define LCD_MODE_CAP_BL_OFF 1
3543 #define LCD_MODE_CAP_CRTC_OFF 2
3544 #define LCD_MODE_CAP_PANEL_OFF 4
3546 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
3549 UCHAR ucFakeEDIDLength;
3550 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3551 } ATOM_FAKE_EDID_PATCH_RECORD;
3553 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
3558 }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
3560 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
3561 #define LCD_RTS_RECORD_TYPE 2
3562 #define LCD_CAP_RECORD_TYPE 3
3563 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
3564 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
3565 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
3566 #define ATOM_RECORD_END_TYPE 0xFF
3568 /****************************Spread Spectrum Info Table Definitions **********************/
3570 //ucTableFormatRevision=1
3571 //ucTableContentRevision=2
3572 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
3574 USHORT usSpreadSpectrumPercentage;
3575 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3579 UCHAR ucRecommendedRef_Div;
3580 UCHAR ucSS_Range; //it was reserved for V11
3581 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
3583 #define ATOM_MAX_SS_ENTRY 16
3584 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3585 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3586 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
3587 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
3590 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
3591 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
3592 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
3593 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
3594 #define ATOM_INTERNAL_SS_MASK 0x00000000
3595 #define ATOM_EXTERNAL_SS_MASK 0x00000002
3596 #define EXEC_SS_STEP_SIZE_SHIFT 2
3597 #define EXEC_SS_DELAY_SHIFT 4
3598 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
3600 typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3602 ATOM_COMMON_TABLE_HEADER sHeader;
3603 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
3604 }ATOM_SPREAD_SPECTRUM_INFO;
3606 /****************************************************************************/
3607 // Structure used in AnalogTV_InfoTable (Top level)
3608 /****************************************************************************/
3609 //ucTVBootUpDefaultStd definition:
3620 //ucTVSupportedStd definition:
3621 #define NTSC_SUPPORT 0x1
3622 #define NTSCJ_SUPPORT 0x2
3624 #define PAL_SUPPORT 0x4
3625 #define PALM_SUPPORT 0x8
3626 #define PALCN_SUPPORT 0x10
3627 #define PALN_SUPPORT 0x20
3628 #define PAL60_SUPPORT 0x40
3629 #define SECAM_SUPPORT 0x80
3631 #define MAX_SUPPORTED_TV_TIMING 2
3633 typedef struct _ATOM_ANALOG_TV_INFO
3635 ATOM_COMMON_TABLE_HEADER sHeader;
3636 UCHAR ucTV_SupportedStandard;
3637 UCHAR ucTV_BootUpDefaultStandard;
3638 UCHAR ucExt_TV_ASIC_ID;
3639 UCHAR ucExt_TV_ASIC_SlaveAddr;
3640 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
3641 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
3642 }ATOM_ANALOG_TV_INFO;
3644 #define MAX_SUPPORTED_TV_TIMING_V1_2 3
3646 typedef struct _ATOM_ANALOG_TV_INFO_V1_2
3648 ATOM_COMMON_TABLE_HEADER sHeader;
3649 UCHAR ucTV_SupportedStandard;
3650 UCHAR ucTV_BootUpDefaultStandard;
3651 UCHAR ucExt_TV_ASIC_ID;
3652 UCHAR ucExt_TV_ASIC_SlaveAddr;
3653 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
3654 }ATOM_ANALOG_TV_INFO_V1_2;
3656 typedef struct _ATOM_DPCD_INFO
3658 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3659 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3660 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3661 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3664 #define ATOM_DPCD_MAX_LANE_MASK 0x1F
3666 /**************************************************************************/
3667 // VRAM usage and their defintions
3669 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
3670 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
3671 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
3672 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
3673 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3675 #ifndef VESA_MEMORY_IN_64K_BLOCK
3676 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
3679 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
3680 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
3681 #define ATOM_HWICON_INFOTABLE_SIZE 32
3682 #define MAX_DTD_MODE_IN_VRAM 6
3683 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
3684 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
3685 //20 bytes for Encoder Type and DPCD in STD EDID area
3686 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3687 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
3689 #define ATOM_HWICON1_SURFACE_ADDR 0
3690 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3691 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3692 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
3693 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3694 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3696 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3697 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3698 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3700 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3702 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3703 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3704 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3706 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3707 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3708 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3710 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3711 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3712 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3714 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3715 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3716 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3718 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3719 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3720 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3722 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3723 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3724 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3726 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3727 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3728 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3730 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3731 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3732 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3734 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3735 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3736 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3738 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3740 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3741 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
3743 //The size below is in Kb!
3744 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3746 #define ATOM_VRAM_RESERVE_V2_SIZE 32
3748 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
3749 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
3750 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
3751 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
3753 /***********************************************************************************/
3754 // Structure used in VRAM_UsageByFirmwareTable
3755 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
3757 // note2: From RV770, the memory is more than 32bit addressable, so we will change
3758 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
3759 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
3760 // (in offset to start of memory address) is KB aligned instead of byte aligend.
3761 /***********************************************************************************/
3763 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
3764 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
3766 If (ulStartAddrUsedByFirmware!=0)
3767 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3768 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
3771 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3773 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3775 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
3777 /***********************************************************************************/
3778 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
3780 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
3782 ULONG ulStartAddrUsedByFirmware;
3783 USHORT usFirmwareUseInKb;
3785 }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
3787 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
3789 ATOM_COMMON_TABLE_HEADER sHeader;
3790 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3791 }ATOM_VRAM_USAGE_BY_FIRMWARE;
3793 // change verion to 1.5, when allow driver to allocate the vram area for command table access.
3794 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
3796 ULONG ulStartAddrUsedByFirmware;
3797 USHORT usFirmwareUseInKb;
3798 USHORT usFBUsedByDrvInKb;
3799 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
3801 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
3803 ATOM_COMMON_TABLE_HEADER sHeader;
3804 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3805 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
3807 /****************************************************************************/
3808 // Structure used in GPIO_Pin_LUTTable
3809 /****************************************************************************/
3810 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3812 USHORT usGpioPin_AIndex;
3813 UCHAR ucGpioPinBitShift;
3815 }ATOM_GPIO_PIN_ASSIGNMENT;
3817 typedef struct _ATOM_GPIO_PIN_LUT
3819 ATOM_COMMON_TABLE_HEADER sHeader;
3820 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
3823 /****************************************************************************/
3824 // Structure used in ComponentVideoInfoTable
3825 /****************************************************************************/
3826 #define GPIO_PIN_ACTIVE_HIGH 0x1
3828 #define MAX_SUPPORTED_CV_STANDARDS 5
3830 // definitions for ATOM_D_INFO.ucSettings
3831 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
3832 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
3833 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
3835 typedef struct _ATOM_GPIO_INFO
3842 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
3843 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
3845 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
3846 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
3847 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
3849 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
3850 //Line 3 out put 5V.
3851 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
3852 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
3853 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
3855 //Line 3 out put 2.2V
3856 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
3857 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
3858 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
3861 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
3862 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
3863 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
3865 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
3867 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
3869 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3870 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3871 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3874 typedef struct _ATOM_COMPONENT_VIDEO_INFO
3876 ATOM_COMMON_TABLE_HEADER sHeader;
3877 USHORT usMask_PinRegisterIndex;
3878 USHORT usEN_PinRegisterIndex;
3879 USHORT usY_PinRegisterIndex;
3880 USHORT usA_PinRegisterIndex;
3882 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3883 ATOM_DTD_FORMAT sReserved; // must be zeroed out
3889 UCHAR ucLetterBoxMode;
3890 UCHAR ucReserved[3];
3891 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3892 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3893 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3894 }ATOM_COMPONENT_VIDEO_INFO;
3896 //ucTableFormatRevision=2
3897 //ucTableContentRevision=1
3898 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
3900 ATOM_COMMON_TABLE_HEADER sHeader;
3907 UCHAR ucLetterBoxMode;
3908 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3909 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3910 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3911 }ATOM_COMPONENT_VIDEO_INFO_V21;
3913 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
3915 /****************************************************************************/
3916 // Structure used in object_InfoTable
3917 /****************************************************************************/
3918 typedef struct _ATOM_OBJECT_HEADER
3920 ATOM_COMMON_TABLE_HEADER sHeader;
3921 USHORT usDeviceSupport;
3922 USHORT usConnectorObjectTableOffset;
3923 USHORT usRouterObjectTableOffset;
3924 USHORT usEncoderObjectTableOffset;
3925 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
3926 USHORT usDisplayPathTableOffset;
3927 }ATOM_OBJECT_HEADER;
3929 typedef struct _ATOM_OBJECT_HEADER_V3
3931 ATOM_COMMON_TABLE_HEADER sHeader;
3932 USHORT usDeviceSupport;
3933 USHORT usConnectorObjectTableOffset;
3934 USHORT usRouterObjectTableOffset;
3935 USHORT usEncoderObjectTableOffset;
3936 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
3937 USHORT usDisplayPathTableOffset;
3938 USHORT usMiscObjectTableOffset;
3939 }ATOM_OBJECT_HEADER_V3;
3941 typedef struct _ATOM_DISPLAY_OBJECT_PATH
3943 USHORT usDeviceTag; //supported device
3944 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
3945 USHORT usConnObjectId; //Connector Object ID
3946 USHORT usGPUObjectId; //GPU ID
3947 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
3948 }ATOM_DISPLAY_OBJECT_PATH;
3950 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
3952 USHORT usDeviceTag; //supported device
3953 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
3954 USHORT usConnObjectId; //Connector Object ID
3955 USHORT usGPUObjectId; //GPU ID
3956 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
3957 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
3959 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
3961 UCHAR ucNumOfDispPath;
3964 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
3965 }ATOM_DISPLAY_OBJECT_PATH_TABLE;
3968 typedef struct _ATOM_OBJECT //each object has this structure
3971 USHORT usSrcDstTableOffset;
3972 USHORT usRecordOffset; //this pointing to a bunch of records defined below
3976 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
3978 UCHAR ucNumberOfObjects;
3980 ATOM_OBJECT asObjects[1];
3983 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
3985 UCHAR ucNumberOfSrc;
3986 USHORT usSrcObjectID[1];
3987 UCHAR ucNumberOfDst;
3988 USHORT usDstObjectID[1];
3989 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
3992 //Two definitions below are for OPM on MXM module designs
3994 #define EXT_HPDPIN_LUTINDEX_0 0
3995 #define EXT_HPDPIN_LUTINDEX_1 1
3996 #define EXT_HPDPIN_LUTINDEX_2 2
3997 #define EXT_HPDPIN_LUTINDEX_3 3
3998 #define EXT_HPDPIN_LUTINDEX_4 4
3999 #define EXT_HPDPIN_LUTINDEX_5 5
4000 #define EXT_HPDPIN_LUTINDEX_6 6
4001 #define EXT_HPDPIN_LUTINDEX_7 7
4002 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4004 #define EXT_AUXDDC_LUTINDEX_0 0
4005 #define EXT_AUXDDC_LUTINDEX_1 1
4006 #define EXT_AUXDDC_LUTINDEX_2 2
4007 #define EXT_AUXDDC_LUTINDEX_3 3
4008 #define EXT_AUXDDC_LUTINDEX_4 4
4009 #define EXT_AUXDDC_LUTINDEX_5 5
4010 #define EXT_AUXDDC_LUTINDEX_6 6
4011 #define EXT_AUXDDC_LUTINDEX_7 7
4012 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4014 //ucChannelMapping are defined as following
4015 //for DP connector, eDP, DP to VGA/LVDS
4016 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4017 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4018 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4019 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4020 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4023 UCHAR ucDP_Lane3_Source:2;
4024 UCHAR ucDP_Lane2_Source:2;
4025 UCHAR ucDP_Lane1_Source:2;
4026 UCHAR ucDP_Lane0_Source:2;
4028 UCHAR ucDP_Lane0_Source:2;
4029 UCHAR ucDP_Lane1_Source:2;
4030 UCHAR ucDP_Lane2_Source:2;
4031 UCHAR ucDP_Lane3_Source:2;
4033 }ATOM_DP_CONN_CHANNEL_MAPPING;
4035 //for DVI/HDMI, in dual link case, both links have to have same mapping.
4036 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4037 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4038 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4039 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4040 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4043 UCHAR ucDVI_CLK_Source:2;
4044 UCHAR ucDVI_DATA0_Source:2;
4045 UCHAR ucDVI_DATA1_Source:2;
4046 UCHAR ucDVI_DATA2_Source:2;
4048 UCHAR ucDVI_DATA2_Source:2;
4049 UCHAR ucDVI_DATA1_Source:2;
4050 UCHAR ucDVI_DATA0_Source:2;
4051 UCHAR ucDVI_CLK_Source:2;
4053 }ATOM_DVI_CONN_CHANNEL_MAPPING;
4055 typedef struct _EXT_DISPLAY_PATH
4057 USHORT usDeviceTag; //A bit vector to show what devices are supported
4058 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4059 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
4060 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4061 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4062 USHORT usExtEncoderObjId; //external encoder object id
4064 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4065 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4066 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4068 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4073 #define NUMBER_OF_UCHAR_FOR_GUID 16
4074 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4077 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01
4079 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4081 ATOM_COMMON_TABLE_HEADER sHeader;
4082 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4083 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4084 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4085 UCHAR uc3DStereoPinId; // use for eDP panel
4086 UCHAR ucRemoteDisplayConfig;
4087 UCHAR uceDPToLVDSRxId;
4088 UCHAR Reserved[4]; // for potential expansion
4089 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4091 //Related definitions, all records are different but they have a commond header
4092 typedef struct _ATOM_COMMON_RECORD_HEADER
4094 UCHAR ucRecordType; //An emun to indicate the record type
4095 UCHAR ucRecordSize; //The size of the whole record in byte
4096 }ATOM_COMMON_RECORD_HEADER;
4099 #define ATOM_I2C_RECORD_TYPE 1
4100 #define ATOM_HPD_INT_RECORD_TYPE 2
4101 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
4102 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4103 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4104 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4105 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4106 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4107 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
4108 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
4109 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11
4110 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
4111 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
4112 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
4113 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
4114 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
4115 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
4116 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4117 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
4118 #define ATOM_ENCODER_CAP_RECORD_TYPE 20
4121 //Must be updated when new record type is added,equal to that record definition!
4122 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE
4124 typedef struct _ATOM_I2C_RECORD
4126 ATOM_COMMON_RECORD_HEADER sheader;
4127 ATOM_I2C_ID_CONFIG sucI2cId;
4128 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4131 typedef struct _ATOM_HPD_INT_RECORD
4133 ATOM_COMMON_RECORD_HEADER sheader;
4134 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4135 UCHAR ucPlugged_PinState;
4136 }ATOM_HPD_INT_RECORD;
4139 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
4141 ATOM_COMMON_RECORD_HEADER sheader;
4142 UCHAR ucProtectionFlag;
4144 }ATOM_OUTPUT_PROTECTION_RECORD;
4146 typedef struct _ATOM_CONNECTOR_DEVICE_TAG
4148 ULONG ulACPIDeviceEnum; //Reserved for now
4149 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4151 }ATOM_CONNECTOR_DEVICE_TAG;
4153 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4155 ATOM_COMMON_RECORD_HEADER sheader;
4156 UCHAR ucNumberOfDevice;
4158 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4159 }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4162 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4164 ATOM_COMMON_RECORD_HEADER sheader;
4165 UCHAR ucConfigGPIOID;
4166 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4167 UCHAR ucFlowinGPIPID;
4168 UCHAR ucExtInGPIPID;
4169 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4171 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
4173 ATOM_COMMON_RECORD_HEADER sheader;
4174 UCHAR ucCTL1GPIO_ID;
4175 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4176 UCHAR ucCTL2GPIO_ID;
4177 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4178 UCHAR ucCTL3GPIO_ID;
4179 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4180 UCHAR ucCTLFPGA_IN_ID;
4182 }ATOM_ENCODER_FPGA_CONTROL_RECORD;
4184 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4186 ATOM_COMMON_RECORD_HEADER sheader;
4187 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4188 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4189 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4191 typedef struct _ATOM_JTAG_RECORD
4193 ATOM_COMMON_RECORD_HEADER sheader;
4195 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4197 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4199 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4201 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4206 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4207 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4209 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4210 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4211 }ATOM_GPIO_PIN_CONTROL_PAIR;
4213 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
4215 ATOM_COMMON_RECORD_HEADER sheader;
4216 UCHAR ucFlags; // Future expnadibility
4217 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4218 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
4219 }ATOM_OBJECT_GPIO_CNTL_RECORD;
4221 //Definitions for GPIO pin state
4222 #define GPIO_PIN_TYPE_INPUT 0x00
4223 #define GPIO_PIN_TYPE_OUTPUT 0x10
4224 #define GPIO_PIN_TYPE_HW_CONTROL 0x20
4226 //For GPIO_PIN_TYPE_OUTPUT the following is defined
4227 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01
4228 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0
4229 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0
4230 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
4232 // Indexes to GPIO array in GLSync record
4233 // GLSync record is for Frame Lock/Gen Lock feature.
4234 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
4235 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4236 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4237 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
4238 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4239 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4240 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
4241 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4242 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
4243 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9
4245 typedef struct _ATOM_ENCODER_DVO_CF_RECORD
4247 ATOM_COMMON_RECORD_HEADER sheader;
4248 ULONG ulStrengthControl; // DVOA strength control for CF
4250 }ATOM_ENCODER_DVO_CF_RECORD;
4252 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
4253 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder
4254 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4256 typedef struct _ATOM_ENCODER_CAP_RECORD
4258 ATOM_COMMON_RECORD_HEADER sheader;
4260 USHORT usEncoderCap;
4263 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4264 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4265 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4267 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4268 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4269 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4273 }ATOM_ENCODER_CAP_RECORD;
4275 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4276 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4277 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4279 typedef struct _ATOM_CONNECTOR_CF_RECORD
4281 ATOM_COMMON_RECORD_HEADER sheader;
4283 UCHAR ucFlowCntlGpioId;
4284 UCHAR ucSwapCntlGpioId;
4285 UCHAR ucConnectedDvoBundle;
4287 }ATOM_CONNECTOR_CF_RECORD;
4289 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4291 ATOM_COMMON_RECORD_HEADER sheader;
4292 ATOM_DTD_FORMAT asTiming;
4293 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4295 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4297 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4298 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4300 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4303 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4305 ATOM_COMMON_RECORD_HEADER sheader;
4306 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4307 UCHAR ucMuxControlPin;
4308 UCHAR ucMuxState[2]; //for alligment purpose
4309 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4311 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4313 ATOM_COMMON_RECORD_HEADER sheader;
4315 UCHAR ucMuxControlPin;
4316 UCHAR ucMuxState[2]; //for alligment purpose
4317 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4320 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
4321 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
4323 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4325 ATOM_COMMON_RECORD_HEADER sheader;
4326 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4327 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4329 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4331 ATOM_COMMON_RECORD_HEADER sheader;
4332 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
4333 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4335 typedef struct _ATOM_OBJECT_LINK_RECORD
4337 ATOM_COMMON_RECORD_HEADER sheader;
4338 USHORT usObjectID; //could be connector, encorder or other object in object.h
4339 }ATOM_OBJECT_LINK_RECORD;
4341 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4343 ATOM_COMMON_RECORD_HEADER sheader;
4345 }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4347 /****************************************************************************/
4348 // ASIC voltage data table
4349 /****************************************************************************/
4350 typedef struct _ATOM_VOLTAGE_INFO_HEADER
4352 USHORT usVDDCBaseLevel; //In number of 50mv unit
4353 USHORT usReserved; //For possible extension table offset
4354 UCHAR ucNumOfVoltageEntries;
4355 UCHAR ucBytesPerVoltageEntry;
4356 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4357 UCHAR ucDefaultVoltageEntry;
4358 UCHAR ucVoltageControlI2cLine;
4359 UCHAR ucVoltageControlAddress;
4360 UCHAR ucVoltageControlOffset;
4361 }ATOM_VOLTAGE_INFO_HEADER;
4363 typedef struct _ATOM_VOLTAGE_INFO
4365 ATOM_COMMON_TABLE_HEADER sHeader;
4366 ATOM_VOLTAGE_INFO_HEADER viHeader;
4367 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
4371 typedef struct _ATOM_VOLTAGE_FORMULA
4373 USHORT usVoltageBaseLevel; // In number of 1mv unit
4374 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
4375 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4376 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4377 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
4379 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
4380 }ATOM_VOLTAGE_FORMULA;
4382 typedef struct _VOLTAGE_LUT_ENTRY
4384 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
4385 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
4388 typedef struct _ATOM_VOLTAGE_FORMULA_V2
4390 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4391 UCHAR ucReserved[3];
4392 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
4393 }ATOM_VOLTAGE_FORMULA_V2;
4395 typedef struct _ATOM_VOLTAGE_CONTROL
4397 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
4398 UCHAR ucVoltageControlI2cLine;
4399 UCHAR ucVoltageControlAddress;
4400 UCHAR ucVoltageControlOffset;
4401 USHORT usGpioPin_AIndex; //GPIO_PAD register index
4402 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
4404 }ATOM_VOLTAGE_CONTROL;
4406 // Define ucVoltageControlId
4407 #define VOLTAGE_CONTROLLED_BY_HW 0x00
4408 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
4409 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80
4410 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
4411 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
4412 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
4413 #define VOLTAGE_CONTROL_ID_DS4402 0x04
4414 #define VOLTAGE_CONTROL_ID_UP6266 0x05
4415 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06
4416 #define VOLTAGE_CONTROL_ID_VT1556M 0x07
4417 #define VOLTAGE_CONTROL_ID_CHL822x 0x08
4418 #define VOLTAGE_CONTROL_ID_VT1586M 0x09
4419 #define VOLTAGE_CONTROL_ID_UP1637 0x0A
4421 typedef struct _ATOM_VOLTAGE_OBJECT
4423 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4424 UCHAR ucSize; //Size of Object
4425 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
4426 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
4427 }ATOM_VOLTAGE_OBJECT;
4429 typedef struct _ATOM_VOLTAGE_OBJECT_V2
4431 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4432 UCHAR ucSize; //Size of Object
4433 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
4434 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
4435 }ATOM_VOLTAGE_OBJECT_V2;
4437 typedef struct _ATOM_VOLTAGE_OBJECT_INFO
4439 ATOM_COMMON_TABLE_HEADER sHeader;
4440 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
4441 }ATOM_VOLTAGE_OBJECT_INFO;
4443 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
4445 ATOM_COMMON_TABLE_HEADER sHeader;
4446 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
4447 }ATOM_VOLTAGE_OBJECT_INFO_V2;
4449 typedef struct _ATOM_LEAKID_VOLTAGE
4454 }ATOM_LEAKID_VOLTAGE;
4456 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
4457 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4458 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
4459 USHORT usSize; //Size of Object
4460 }ATOM_VOLTAGE_OBJECT_HEADER_V3;
4462 typedef struct _VOLTAGE_LUT_ENTRY_V2
4464 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4465 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
4466 }VOLTAGE_LUT_ENTRY_V2;
4468 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
4470 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
4472 USHORT usLeakageId; // The corresponding Voltage Value, in mV
4473 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
4475 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
4477 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4478 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
4479 UCHAR ucVoltageControlI2cLine;
4480 UCHAR ucVoltageControlAddress;
4481 UCHAR ucVoltageControlOffset;
4483 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
4484 }ATOM_I2C_VOLTAGE_OBJECT_V3;
4486 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
4488 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4489 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
4490 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
4491 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4493 ULONG ulGpioMaskVal; // GPIO Mask value
4494 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
4495 }ATOM_GPIO_VOLTAGE_OBJECT_V3;
4497 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4499 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4500 UCHAR ucLeakageCntlId; // default is 0
4501 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
4502 UCHAR ucReserved[2];
4503 ULONG ulMaxVoltageLevel;
4504 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
4505 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
4507 typedef union _ATOM_VOLTAGE_OBJECT_V3{
4508 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
4509 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
4510 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
4511 }ATOM_VOLTAGE_OBJECT_V3;
4513 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
4515 ATOM_COMMON_TABLE_HEADER sHeader;
4516 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
4517 }ATOM_VOLTAGE_OBJECT_INFO_V3_1;
4519 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
4524 USHORT usEfuseSpareStartAddr;
4525 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
4526 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
4527 }ATOM_ASIC_PROFILE_VOLTAGE;
4530 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
4531 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
4532 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
4534 typedef struct _ATOM_ASIC_PROFILING_INFO
4536 ATOM_COMMON_TABLE_HEADER asHeader;
4537 ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
4538 }ATOM_ASIC_PROFILING_INFO;
4540 typedef struct _ATOM_POWER_SOURCE_OBJECT
4542 UCHAR ucPwrSrcId; // Power source
4543 UCHAR ucPwrSensorType; // GPIO, I2C or none
4544 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
4545 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
4546 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
4547 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4548 UCHAR ucPwrSensActiveState; // high active or low active
4549 UCHAR ucReserve[3]; // reserve
4550 USHORT usSensPwr; // in unit of watt
4551 }ATOM_POWER_SOURCE_OBJECT;
4553 typedef struct _ATOM_POWER_SOURCE_INFO
4555 ATOM_COMMON_TABLE_HEADER asHeader;
4556 UCHAR asPwrbehave[16];
4557 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
4558 }ATOM_POWER_SOURCE_INFO;
4562 #define POWERSOURCE_PCIE_ID1 0x00
4563 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
4564 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
4565 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
4566 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
4568 //define ucPwrSensorId
4569 #define POWER_SENSOR_ALWAYS 0x00
4570 #define POWER_SENSOR_GPIO 0x01
4571 #define POWER_SENSOR_I2C 0x02
4573 typedef struct _ATOM_CLK_VOLT_CAPABILITY
4575 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4576 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4577 }ATOM_CLK_VOLT_CAPABILITY;
4579 typedef struct _ATOM_AVAILABLE_SCLK_LIST
4581 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4582 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
4583 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
4584 }ATOM_AVAILABLE_SCLK_LIST;
4586 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
4587 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
4589 // this IntegrateSystemInfoTable is used for Liano/Ontario APU
4590 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
4592 ATOM_COMMON_TABLE_HEADER sHeader;
4593 ULONG ulBootUpEngineClock;
4594 ULONG ulDentistVCOFreq;
4595 ULONG ulBootUpUMAClock;
4596 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
4597 ULONG ulBootUpReqDisplayVector;
4598 ULONG ulOtherDisplayMisc;
4600 ULONG ulSB_MMIO_Base_Addr;
4601 USHORT usRequestedPWMFreqInHz;
4604 ULONG ulMinEngineClock;
4605 ULONG ulSystemConfig;
4607 USHORT usNBP0Voltage;
4608 USHORT usNBP1Voltage;
4609 USHORT usBootUpNBVoltage;
4610 USHORT usExtDispConnInfoOffset;
4611 USHORT usPanelRefreshRateRange;
4613 UCHAR ucUMAChannelNumber;
4614 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
4615 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
4616 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
4617 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
4618 ULONG ulGMCRestoreResetTime;
4619 ULONG ulMinimumNClk;
4621 ULONG ulDDR_DLL_PowerUpTime;
4622 ULONG ulDDR_PLL_PowerUpTime;
4623 USHORT usPCIEClkSSPercentage;
4624 USHORT usPCIEClkSSType;
4625 USHORT usLvdsSSPercentage;
4626 USHORT usLvdsSSpreadRateIn10Hz;
4627 USHORT usHDMISSPercentage;
4628 USHORT usHDMISSpreadRateIn10Hz;
4629 USHORT usDVISSPercentage;
4630 USHORT usDVISSpreadRateIn10Hz;
4631 ULONG SclkDpmBoostMargin;
4632 ULONG SclkDpmThrottleMargin;
4633 USHORT SclkDpmTdpLimitPG;
4634 USHORT SclkDpmTdpLimitBoost;
4635 ULONG ulBoostEngineCLock;
4636 UCHAR ulBoostVid_2bit;
4639 USHORT usMaxLVDSPclkFreqInSingleLink;
4641 UCHAR ucLVDSReserved;
4642 ULONG ulReserved3[15];
4643 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4644 }ATOM_INTEGRATED_SYSTEM_INFO_V6;
4647 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
4648 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
4651 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01
4652 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02
4653 #define SYS_INFO_LVDSMISC__888_BPC 0x04
4654 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08
4655 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10
4657 // not used any more
4658 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04
4659 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
4661 /**********************************************************************************************************************
4662 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
4663 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4664 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4665 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4666 sDISPCLK_Voltage: Report Display clock voltage requirement.
4668 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
4669 ATOM_DEVICE_CRT1_SUPPORT 0x0001
4670 ATOM_DEVICE_CRT2_SUPPORT 0x0010
4671 ATOM_DEVICE_DFP1_SUPPORT 0x0008
4672 ATOM_DEVICE_DFP6_SUPPORT 0x0040
4673 ATOM_DEVICE_DFP2_SUPPORT 0x0080
4674 ATOM_DEVICE_DFP3_SUPPORT 0x0200
4675 ATOM_DEVICE_DFP4_SUPPORT 0x0400
4676 ATOM_DEVICE_DFP5_SUPPORT 0x0800
4677 ATOM_DEVICE_LCD1_SUPPORT 0x0002
4678 ulOtherDisplayMisc: Other display related flags, not defined yet.
4679 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4680 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4681 bit[3]=0: Enable HW AUX mode detection logic
4682 =1: Disable HW AUX mode dettion logic
4683 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4685 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4686 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4688 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4689 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4690 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4691 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4692 and enabling VariBri under the driver environment from PP table is optional.
4694 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4695 that BL control from GPU is expected.
4696 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4697 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4699 and enabling VariBri under the driver environment from PP table is optional.
4701 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4702 Threshold on value to enter HTC_active state.
4703 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4704 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4705 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4706 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4707 =1: PCIE Power Gating Enabled
4708 Bit[1]=0: DDR-DLL shut-down feature disabled.
4709 1: DDR-DLL shut-down feature enabled.
4710 Bit[2]=0: DDR-PLL Power down feature disabled.
4711 1: DDR-PLL Power down feature enabled.
4713 usNBP0Voltage: VID for voltage on NB P0 State
4714 usNBP1Voltage: VID for voltage on NB P1 State
4715 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4716 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
4717 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4718 to indicate a range.
4719 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
4720 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
4721 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
4722 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
4723 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4724 ucUMAChannelNumber: System memory channel numbers.
4725 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4726 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4727 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4728 sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high
4729 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4730 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4731 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4732 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4733 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4734 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
4735 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4736 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4737 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4738 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4739 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4740 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4741 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4742 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4743 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4744 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4745 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4746 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4747 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4748 **********************************************************************************************************************/
4750 // this Table is used for Liano/Ontario APU
4751 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
4753 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
4754 ULONG ulPowerplayTable[128];
4755 }ATOM_FUSION_SYSTEM_INFO_V1;
4756 /**********************************************************************************************************************
4757 ATOM_FUSION_SYSTEM_INFO_V1 Description
4758 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
4759 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
4760 **********************************************************************************************************************/
4762 // this IntegrateSystemInfoTable is used for Trinity APU
4763 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
4765 ATOM_COMMON_TABLE_HEADER sHeader;
4766 ULONG ulBootUpEngineClock;
4767 ULONG ulDentistVCOFreq;
4768 ULONG ulBootUpUMAClock;
4769 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
4770 ULONG ulBootUpReqDisplayVector;
4771 ULONG ulOtherDisplayMisc;
4773 ULONG ulSB_MMIO_Base_Addr;
4774 USHORT usRequestedPWMFreqInHz;
4777 ULONG ulMinEngineClock;
4778 ULONG ulSystemConfig;
4780 USHORT usNBP0Voltage;
4781 USHORT usNBP1Voltage;
4782 USHORT usBootUpNBVoltage;
4783 USHORT usExtDispConnInfoOffset;
4784 USHORT usPanelRefreshRateRange;
4786 UCHAR ucUMAChannelNumber;
4787 UCHAR strVBIOSMsg[40];
4788 ULONG ulReserved[20];
4789 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
4790 ULONG ulGMCRestoreResetTime;
4791 ULONG ulMinimumNClk;
4793 ULONG ulDDR_DLL_PowerUpTime;
4794 ULONG ulDDR_PLL_PowerUpTime;
4795 USHORT usPCIEClkSSPercentage;
4796 USHORT usPCIEClkSSType;
4797 USHORT usLvdsSSPercentage;
4798 USHORT usLvdsSSpreadRateIn10Hz;
4799 USHORT usHDMISSPercentage;
4800 USHORT usHDMISSpreadRateIn10Hz;
4801 USHORT usDVISSPercentage;
4802 USHORT usDVISSpreadRateIn10Hz;
4803 ULONG SclkDpmBoostMargin;
4804 ULONG SclkDpmThrottleMargin;
4805 USHORT SclkDpmTdpLimitPG;
4806 USHORT SclkDpmTdpLimitBoost;
4807 ULONG ulBoostEngineCLock;
4808 UCHAR ulBoostVid_2bit;
4811 USHORT usMaxLVDSPclkFreqInSingleLink;
4813 UCHAR ucLVDSReserved;
4814 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
4815 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
4816 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
4817 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
4818 UCHAR ucLVDSOffToOnDelay_in4Ms;
4819 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
4820 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
4821 UCHAR ucLVDSReserved1;
4822 ULONG ulLCDBitDepthControlVal;
4823 ULONG ulNbpStateMemclkFreq[4];
4824 USHORT usNBP2Voltage;
4825 USHORT usNBP3Voltage;
4826 ULONG ulNbpStateNClkFreq[4];
4827 UCHAR ucNBDPMEnable;
4828 UCHAR ucReserved[3];
4829 UCHAR ucDPMState0VclkFid;
4830 UCHAR ucDPMState0DclkFid;
4831 UCHAR ucDPMState1VclkFid;
4832 UCHAR ucDPMState1DclkFid;
4833 UCHAR ucDPMState2VclkFid;
4834 UCHAR ucDPMState2DclkFid;
4835 UCHAR ucDPMState3VclkFid;
4836 UCHAR ucDPMState3DclkFid;
4837 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4838 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
4840 // ulOtherDisplayMisc
4841 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
4842 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02
4843 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04
4844 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08
4847 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
4848 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02
4849 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08
4851 /**********************************************************************************************************************
4852 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
4853 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4854 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4855 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4856 sDISPCLK_Voltage: Report Display clock voltage requirement.
4858 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
4859 ATOM_DEVICE_CRT1_SUPPORT 0x0001
4860 ATOM_DEVICE_DFP1_SUPPORT 0x0008
4861 ATOM_DEVICE_DFP6_SUPPORT 0x0040
4862 ATOM_DEVICE_DFP2_SUPPORT 0x0080
4863 ATOM_DEVICE_DFP3_SUPPORT 0x0200
4864 ATOM_DEVICE_DFP4_SUPPORT 0x0400
4865 ATOM_DEVICE_DFP5_SUPPORT 0x0800
4866 ATOM_DEVICE_LCD1_SUPPORT 0x0002
4867 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
4868 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
4869 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
4870 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
4871 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
4872 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
4873 bit[3]=0: VBIOS fast boot is disable
4874 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
4875 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4876 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4877 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
4878 =1: DP mode use single PLL mode
4879 bit[3]=0: Enable AUX HW mode detection logic
4880 =1: Disable AUX HW mode detection logic
4882 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4884 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4885 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4887 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4888 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4889 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4890 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4891 and enabling VariBri under the driver environment from PP table is optional.
4893 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4894 that BL control from GPU is expected.
4895 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4896 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4898 and enabling VariBri under the driver environment from PP table is optional.
4900 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4901 Threshold on value to enter HTC_active state.
4902 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
4903 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4904 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4905 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
4906 =1: PCIE Power Gating Enabled
4907 Bit[1]=0: DDR-DLL shut-down feature disabled.
4908 1: DDR-DLL shut-down feature enabled.
4909 Bit[2]=0: DDR-PLL Power down feature disabled.
4910 1: DDR-PLL Power down feature enabled.
4912 usNBP0Voltage: VID for voltage on NB P0 State
4913 usNBP1Voltage: VID for voltage on NB P1 State
4914 usNBP2Voltage: VID for voltage on NB P2 State
4915 usNBP3Voltage: VID for voltage on NB P3 State
4916 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4917 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
4918 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4919 to indicate a range.
4920 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
4921 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
4922 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
4923 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
4924 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4925 ucUMAChannelNumber: System memory channel numbers.
4926 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4927 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4928 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4929 sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high
4930 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4933 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4934 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4935 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
4936 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4937 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4938 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4939 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4940 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4941 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
4942 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4943 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4944 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4945 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4946 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4947 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4948 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4949 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
4950 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4951 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4952 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
4953 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4954 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4956 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
4957 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4958 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4960 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
4961 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4962 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4964 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
4965 =0 means to use VBIOS default delay which is 125 ( 500ms ).
4966 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4968 ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
4969 =0 means to use VBIOS default delay which is 0 ( 0ms ).
4970 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4972 ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
4973 =0 means to use VBIOS default delay which is 0 ( 0ms ).
4974 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4976 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
4978 **********************************************************************************************************************/
4980 /**************************************************************************/
4981 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
4982 //Memory SS Info Table
4983 //Define Memory Clock SS chip ID
4987 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
4988 typedef struct _ATOM_I2C_DATA_RECORD
4990 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
4991 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
4992 }ATOM_I2C_DATA_RECORD;
4995 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
4996 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
4998 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
4999 UCHAR ucSSChipID; //SS chip being used
5000 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
5001 UCHAR ucNumOfI2CDataRecords; //number of data block
5002 ATOM_I2C_DATA_RECORD asI2CData[1];
5003 }ATOM_I2C_DEVICE_SETUP_INFO;
5005 //==========================================================================================
5006 typedef struct _ATOM_ASIC_MVDD_INFO
5008 ATOM_COMMON_TABLE_HEADER sHeader;
5009 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
5010 }ATOM_ASIC_MVDD_INFO;
5012 //==========================================================================================
5013 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
5015 //==========================================================================================
5016 /**************************************************************************/
5018 typedef struct _ATOM_ASIC_SS_ASSIGNMENT
5020 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5021 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5022 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
5023 UCHAR ucClockIndication; //Indicate which clock source needs SS
5024 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
5025 UCHAR ucReserved[2];
5026 }ATOM_ASIC_SS_ASSIGNMENT;
5028 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
5029 //SS is not required or enabled if a match is not found.
5030 #define ASIC_INTERNAL_MEMORY_SS 1
5031 #define ASIC_INTERNAL_ENGINE_SS 2
5032 #define ASIC_INTERNAL_UVD_SS 3
5033 #define ASIC_INTERNAL_SS_ON_TMDS 4
5034 #define ASIC_INTERNAL_SS_ON_HDMI 5
5035 #define ASIC_INTERNAL_SS_ON_LVDS 6
5036 #define ASIC_INTERNAL_SS_ON_DP 7
5037 #define ASIC_INTERNAL_SS_ON_DCPLL 8
5038 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
5039 #define ASIC_INTERNAL_VCE_SS 10
5041 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
5043 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5044 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5045 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5046 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
5047 UCHAR ucClockIndication; //Indicate which clock source needs SS
5048 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5049 UCHAR ucReserved[2];
5050 }ATOM_ASIC_SS_ASSIGNMENT_V2;
5052 //ucSpreadSpectrumMode
5053 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
5054 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
5055 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
5056 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
5057 //#define ATOM_INTERNAL_SS_MASK 0x00000000
5058 //#define ATOM_EXTERNAL_SS_MASK 0x00000002
5060 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
5062 ATOM_COMMON_TABLE_HEADER sHeader;
5063 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
5064 }ATOM_ASIC_INTERNAL_SS_INFO;
5066 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
5068 ATOM_COMMON_TABLE_HEADER sHeader;
5069 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
5070 }ATOM_ASIC_INTERNAL_SS_INFO_V2;
5072 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
5074 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5075 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5076 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
5077 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
5078 UCHAR ucClockIndication; //Indicate which clock source needs SS
5079 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5080 UCHAR ucReserved[2];
5081 }ATOM_ASIC_SS_ASSIGNMENT_V3;
5083 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
5085 ATOM_COMMON_TABLE_HEADER sHeader;
5086 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
5087 }ATOM_ASIC_INTERNAL_SS_INFO_V3;
5090 //==============================Scratch Pad Definition Portion===============================
5091 #define ATOM_DEVICE_CONNECT_INFO_DEF 0
5092 #define ATOM_ROM_LOCATION_DEF 1
5093 #define ATOM_TV_STANDARD_DEF 2
5094 #define ATOM_ACTIVE_INFO_DEF 3
5095 #define ATOM_LCD_INFO_DEF 4
5096 #define ATOM_DOS_REQ_INFO_DEF 5
5097 #define ATOM_ACC_CHANGE_INFO_DEF 6
5098 #define ATOM_DOS_MODE_INFO_DEF 7
5099 #define ATOM_I2C_CHANNEL_STATUS_DEF 8
5100 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9
5101 #define ATOM_INTERNAL_TIMER_DEF 10
5103 // BIOS_0_SCRATCH Definition
5104 #define ATOM_S0_CRT1_MONO 0x00000001L
5105 #define ATOM_S0_CRT1_COLOR 0x00000002L
5106 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
5108 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
5109 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L
5110 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
5112 #define ATOM_S0_CV_A 0x00000010L
5113 #define ATOM_S0_CV_DIN_A 0x00000020L
5114 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
5117 #define ATOM_S0_CRT2_MONO 0x00000100L
5118 #define ATOM_S0_CRT2_COLOR 0x00000200L
5119 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
5121 #define ATOM_S0_TV1_COMPOSITE 0x00000400L
5122 #define ATOM_S0_TV1_SVIDEO 0x00000800L
5123 #define ATOM_S0_TV1_SCART 0x00004000L
5124 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
5126 #define ATOM_S0_CV 0x00001000L
5127 #define ATOM_S0_CV_DIN 0x00002000L
5128 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
5130 #define ATOM_S0_DFP1 0x00010000L
5131 #define ATOM_S0_DFP2 0x00020000L
5132 #define ATOM_S0_LCD1 0x00040000L
5133 #define ATOM_S0_LCD2 0x00080000L
5134 #define ATOM_S0_DFP6 0x00100000L
5135 #define ATOM_S0_DFP3 0x00200000L
5136 #define ATOM_S0_DFP4 0x00400000L
5137 #define ATOM_S0_DFP5 0x00800000L
5139 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
5141 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
5142 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
5144 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
5145 #define ATOM_S0_THERMAL_STATE_SHIFT 26
5147 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
5148 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
5150 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
5151 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
5152 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
5153 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
5155 //Byte aligned definition for BIOS usage
5156 #define ATOM_S0_CRT1_MONOb0 0x01
5157 #define ATOM_S0_CRT1_COLORb0 0x02
5158 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
5160 #define ATOM_S0_TV1_COMPOSITEb0 0x04
5161 #define ATOM_S0_TV1_SVIDEOb0 0x08
5162 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
5164 #define ATOM_S0_CVb0 0x10
5165 #define ATOM_S0_CV_DINb0 0x20
5166 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
5168 #define ATOM_S0_CRT2_MONOb1 0x01
5169 #define ATOM_S0_CRT2_COLORb1 0x02
5170 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
5172 #define ATOM_S0_TV1_COMPOSITEb1 0x04
5173 #define ATOM_S0_TV1_SVIDEOb1 0x08
5174 #define ATOM_S0_TV1_SCARTb1 0x40
5175 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
5177 #define ATOM_S0_CVb1 0x10
5178 #define ATOM_S0_CV_DINb1 0x20
5179 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
5181 #define ATOM_S0_DFP1b2 0x01
5182 #define ATOM_S0_DFP2b2 0x02
5183 #define ATOM_S0_LCD1b2 0x04
5184 #define ATOM_S0_LCD2b2 0x08
5185 #define ATOM_S0_DFP6b2 0x10
5186 #define ATOM_S0_DFP3b2 0x20
5187 #define ATOM_S0_DFP4b2 0x40
5188 #define ATOM_S0_DFP5b2 0x80
5191 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
5192 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2
5194 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
5195 #define ATOM_S0_LCD1_SHIFT 18
5197 // BIOS_1_SCRATCH Definition
5198 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
5199 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
5201 // BIOS_2_SCRATCH Definition
5202 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
5203 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
5204 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
5206 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
5207 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
5208 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
5210 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
5211 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
5213 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
5214 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
5215 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
5216 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
5217 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
5218 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
5221 //Byte aligned definition for BIOS usage
5222 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
5223 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
5224 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
5226 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
5227 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
5228 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
5229 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
5230 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
5231 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
5234 // BIOS_3_SCRATCH Definition
5235 #define ATOM_S3_CRT1_ACTIVE 0x00000001L
5236 #define ATOM_S3_LCD1_ACTIVE 0x00000002L
5237 #define ATOM_S3_TV1_ACTIVE 0x00000004L
5238 #define ATOM_S3_DFP1_ACTIVE 0x00000008L
5239 #define ATOM_S3_CRT2_ACTIVE 0x00000010L
5240 #define ATOM_S3_LCD2_ACTIVE 0x00000020L
5241 #define ATOM_S3_DFP6_ACTIVE 0x00000040L
5242 #define ATOM_S3_DFP2_ACTIVE 0x00000080L
5243 #define ATOM_S3_CV_ACTIVE 0x00000100L
5244 #define ATOM_S3_DFP3_ACTIVE 0x00000200L
5245 #define ATOM_S3_DFP4_ACTIVE 0x00000400L
5246 #define ATOM_S3_DFP5_ACTIVE 0x00000800L
5248 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
5250 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
5251 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
5253 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
5254 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
5255 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
5256 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
5257 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
5258 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
5259 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
5260 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
5261 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
5262 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
5263 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
5264 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
5266 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
5267 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
5268 //Below two definitions are not supported in pplib, but in the old powerplay in DAL
5269 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
5270 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
5272 //Byte aligned definition for BIOS usage
5273 #define ATOM_S3_CRT1_ACTIVEb0 0x01
5274 #define ATOM_S3_LCD1_ACTIVEb0 0x02
5275 #define ATOM_S3_TV1_ACTIVEb0 0x04
5276 #define ATOM_S3_DFP1_ACTIVEb0 0x08
5277 #define ATOM_S3_CRT2_ACTIVEb0 0x10
5278 #define ATOM_S3_LCD2_ACTIVEb0 0x20
5279 #define ATOM_S3_DFP6_ACTIVEb0 0x40
5280 #define ATOM_S3_DFP2_ACTIVEb0 0x80
5281 #define ATOM_S3_CV_ACTIVEb1 0x01
5282 #define ATOM_S3_DFP3_ACTIVEb1 0x02
5283 #define ATOM_S3_DFP4_ACTIVEb1 0x04
5284 #define ATOM_S3_DFP5_ACTIVEb1 0x08
5286 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
5288 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
5289 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
5290 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
5291 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
5292 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
5293 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
5294 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
5295 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
5296 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
5297 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
5298 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
5299 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
5301 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
5303 // BIOS_4_SCRATCH Definition
5304 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
5305 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
5306 #define ATOM_S4_LCD1_REFRESH_SHIFT 8
5308 //Byte aligned definition for BIOS usage
5309 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
5310 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
5311 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
5313 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
5314 #define ATOM_S5_DOS_REQ_CRT1b0 0x01
5315 #define ATOM_S5_DOS_REQ_LCD1b0 0x02
5316 #define ATOM_S5_DOS_REQ_TV1b0 0x04
5317 #define ATOM_S5_DOS_REQ_DFP1b0 0x08
5318 #define ATOM_S5_DOS_REQ_CRT2b0 0x10
5319 #define ATOM_S5_DOS_REQ_LCD2b0 0x20
5320 #define ATOM_S5_DOS_REQ_DFP6b0 0x40
5321 #define ATOM_S5_DOS_REQ_DFP2b0 0x80
5322 #define ATOM_S5_DOS_REQ_CVb1 0x01
5323 #define ATOM_S5_DOS_REQ_DFP3b1 0x02
5324 #define ATOM_S5_DOS_REQ_DFP4b1 0x04
5325 #define ATOM_S5_DOS_REQ_DFP5b1 0x08
5327 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
5329 #define ATOM_S5_DOS_REQ_CRT1 0x0001
5330 #define ATOM_S5_DOS_REQ_LCD1 0x0002
5331 #define ATOM_S5_DOS_REQ_TV1 0x0004
5332 #define ATOM_S5_DOS_REQ_DFP1 0x0008
5333 #define ATOM_S5_DOS_REQ_CRT2 0x0010
5334 #define ATOM_S5_DOS_REQ_LCD2 0x0020
5335 #define ATOM_S5_DOS_REQ_DFP6 0x0040
5336 #define ATOM_S5_DOS_REQ_DFP2 0x0080
5337 #define ATOM_S5_DOS_REQ_CV 0x0100
5338 #define ATOM_S5_DOS_REQ_DFP3 0x0200
5339 #define ATOM_S5_DOS_REQ_DFP4 0x0400
5340 #define ATOM_S5_DOS_REQ_DFP5 0x0800
5342 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
5343 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
5344 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
5345 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
5346 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
5347 (ATOM_S5_DOS_FORCE_CVb3<<8))
5349 // BIOS_6_SCRATCH Definition
5350 #define ATOM_S6_DEVICE_CHANGE 0x00000001L
5351 #define ATOM_S6_SCALER_CHANGE 0x00000002L
5352 #define ATOM_S6_LID_CHANGE 0x00000004L
5353 #define ATOM_S6_DOCKING_CHANGE 0x00000008L
5354 #define ATOM_S6_ACC_MODE 0x00000010L
5355 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
5356 #define ATOM_S6_LID_STATE 0x00000040L
5357 #define ATOM_S6_DOCK_STATE 0x00000080L
5358 #define ATOM_S6_CRITICAL_STATE 0x00000100L
5359 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
5360 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
5361 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
5362 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
5363 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
5365 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
5366 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
5368 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L
5369 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L
5370 #define ATOM_S6_ACC_REQ_TV1 0x00040000L
5371 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L
5372 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L
5373 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L
5374 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L
5375 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L
5376 #define ATOM_S6_ACC_REQ_CV 0x01000000L
5377 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L
5378 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L
5379 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L
5381 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
5382 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
5383 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
5384 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
5385 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
5387 //Byte aligned definition for BIOS usage
5388 #define ATOM_S6_DEVICE_CHANGEb0 0x01
5389 #define ATOM_S6_SCALER_CHANGEb0 0x02
5390 #define ATOM_S6_LID_CHANGEb0 0x04
5391 #define ATOM_S6_DOCKING_CHANGEb0 0x08
5392 #define ATOM_S6_ACC_MODEb0 0x10
5393 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
5394 #define ATOM_S6_LID_STATEb0 0x40
5395 #define ATOM_S6_DOCK_STATEb0 0x80
5396 #define ATOM_S6_CRITICAL_STATEb1 0x01
5397 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
5398 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
5399 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
5400 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
5401 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
5403 #define ATOM_S6_ACC_REQ_CRT1b2 0x01
5404 #define ATOM_S6_ACC_REQ_LCD1b2 0x02
5405 #define ATOM_S6_ACC_REQ_TV1b2 0x04
5406 #define ATOM_S6_ACC_REQ_DFP1b2 0x08
5407 #define ATOM_S6_ACC_REQ_CRT2b2 0x10
5408 #define ATOM_S6_ACC_REQ_LCD2b2 0x20
5409 #define ATOM_S6_ACC_REQ_DFP6b2 0x40
5410 #define ATOM_S6_ACC_REQ_DFP2b2 0x80
5411 #define ATOM_S6_ACC_REQ_CVb3 0x01
5412 #define ATOM_S6_ACC_REQ_DFP3b3 0x02
5413 #define ATOM_S6_ACC_REQ_DFP4b3 0x04
5414 #define ATOM_S6_ACC_REQ_DFP5b3 0x08
5416 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
5417 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
5418 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
5419 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
5420 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
5422 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0
5423 #define ATOM_S6_SCALER_CHANGE_SHIFT 1
5424 #define ATOM_S6_LID_CHANGE_SHIFT 2
5425 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3
5426 #define ATOM_S6_ACC_MODE_SHIFT 4
5427 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
5428 #define ATOM_S6_LID_STATE_SHIFT 6
5429 #define ATOM_S6_DOCK_STATE_SHIFT 7
5430 #define ATOM_S6_CRITICAL_STATE_SHIFT 8
5431 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
5432 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
5433 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
5434 #define ATOM_S6_REQ_SCALER_SHIFT 12
5435 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
5436 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
5437 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
5438 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
5439 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
5440 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
5441 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
5443 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
5444 #define ATOM_S7_DOS_MODE_TYPEb0 0x03
5445 #define ATOM_S7_DOS_MODE_VGAb0 0x00
5446 #define ATOM_S7_DOS_MODE_VESAb0 0x01
5447 #define ATOM_S7_DOS_MODE_EXTb0 0x02
5448 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
5449 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
5450 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
5451 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
5453 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
5455 // BIOS_8_SCRATCH Definition
5456 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
5457 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
5459 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
5460 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
5462 // BIOS_9_SCRATCH Definition
5463 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
5464 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
5466 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
5467 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
5469 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
5470 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
5472 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
5473 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
5477 #define ATOM_FLAG_SET 0x20
5478 #define ATOM_FLAG_CLEAR 0
5479 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
5480 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
5481 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
5482 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
5483 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
5485 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
5486 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
5488 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
5489 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
5490 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
5492 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
5493 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
5494 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
5496 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
5497 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
5499 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
5500 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
5502 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
5503 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
5505 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5507 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5509 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
5510 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
5511 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
5512 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
5514 /****************************************************************************/
5515 //Portion II: Definitinos only used in Driver
5516 /****************************************************************************/
5518 // Macros used by driver
5520 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
5522 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
5523 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
5524 #else // not __cplusplus
5525 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
5527 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
5528 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
5529 #endif // __cplusplus
5531 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
5532 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
5534 /****************************************************************************/
5535 //Portion III: Definitinos only used in VBIOS
5536 /****************************************************************************/
5537 #define ATOM_DAC_SRC 0x80
5538 #define ATOM_SRC_DAC1 0
5539 #define ATOM_SRC_DAC2 0x80
5541 typedef struct _MEMORY_PLLINIT_PARAMETERS
5543 ULONG ulTargetMemoryClock; //In 10Khz unit
5544 UCHAR ucAction; //not define yet
5545 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
5546 UCHAR ucFbDiv; //FB value
5547 UCHAR ucPostDiv; //Post div
5548 }MEMORY_PLLINIT_PARAMETERS;
5550 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
5553 #define GPIO_PIN_WRITE 0x01
5554 #define GPIO_PIN_READ 0x00
5556 typedef struct _GPIO_PIN_CONTROL_PARAMETERS
5558 UCHAR ucGPIO_ID; //return value, read from GPIO pins
5559 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
5560 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
5561 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
5562 }GPIO_PIN_CONTROL_PARAMETERS;
5564 typedef struct _ENABLE_SCALER_PARAMETERS
5566 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
5567 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
5568 UCHAR ucTVStandard; //
5570 }ENABLE_SCALER_PARAMETERS;
5571 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
5574 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
5575 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
5576 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2
5577 #define SCALER_ENABLE_MULTITAP_MODE 3
5579 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
5581 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
5582 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
5583 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
5584 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
5585 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5586 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
5588 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
5590 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
5591 ENABLE_CRTC_PARAMETERS sReserved;
5592 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
5594 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
5596 USHORT usHight; // Image Hight
5597 USHORT usWidth; // Image Width
5598 UCHAR ucSurface; // Surface 1 or 2
5600 }ENABLE_GRAPH_SURFACE_PARAMETERS;
5602 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
5604 USHORT usHight; // Image Hight
5605 USHORT usWidth; // Image Width
5606 UCHAR ucSurface; // Surface 1 or 2
5607 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5609 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
5611 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
5613 USHORT usHight; // Image Hight
5614 USHORT usWidth; // Image Width
5615 UCHAR ucSurface; // Surface 1 or 2
5616 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5617 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
5618 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
5620 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
5622 USHORT usHight; // Image Hight
5623 USHORT usWidth; // Image Width
5624 USHORT usGraphPitch;
5626 UCHAR ucPixelFormat;
5627 UCHAR ucSurface; // Surface 1 or 2
5628 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
5631 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
5634 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f
5635 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10
5637 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
5639 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
5640 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
5641 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
5643 typedef struct _MEMORY_CLEAN_UP_PARAMETERS
5645 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
5646 USHORT usMemorySize; //8Kb blocks aligned
5647 }MEMORY_CLEAN_UP_PARAMETERS;
5648 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
5650 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
5652 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
5654 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
5656 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
5659 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
5663 USHORT usDispXStart;
5664 USHORT usDispYStart;
5665 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
5668 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
5672 USHORT usLutStartIndex;
5674 USHORT usLutOffsetInVram;
5675 }PALETTE_DATA_CONTROL_PARAMETERS_V3;
5678 #define PALETTE_DATA_AUTO_FILL 1
5679 #define PALETTE_DATA_READ 2
5680 #define PALETTE_DATA_WRITE 3
5683 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
5685 UCHAR ucInterruptId;
5689 }INTERRUPT_SERVICE_PARAMETER_V2;
5692 #define HDP1_INTERRUPT_ID 1
5693 #define HDP2_INTERRUPT_ID 2
5694 #define HDP3_INTERRUPT_ID 3
5695 #define HDP4_INTERRUPT_ID 4
5696 #define HDP5_INTERRUPT_ID 5
5697 #define HDP6_INTERRUPT_ID 6
5698 #define SW_INTERRUPT_ID 11
5701 #define INTERRUPT_SERVICE_GEN_SW_INT 1
5702 #define INTERRUPT_SERVICE_GET_STATUS 2
5705 #define INTERRUPT_STATUS__INT_TRIGGER 1
5706 #define INTERRUPT_STATUS__HPD_HIGH 2
5708 typedef struct _INDIRECT_IO_ACCESS
5710 ATOM_COMMON_TABLE_HEADER sHeader;
5711 UCHAR IOAccessSequence[256];
5712 } INDIRECT_IO_ACCESS;
5714 #define INDIRECT_READ 0x00
5715 #define INDIRECT_WRITE 0x80
5717 #define INDIRECT_IO_MM 0
5718 #define INDIRECT_IO_PLL 1
5719 #define INDIRECT_IO_MC 2
5720 #define INDIRECT_IO_PCIE 3
5721 #define INDIRECT_IO_PCIEP 4
5722 #define INDIRECT_IO_NBMISC 5
5724 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
5725 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
5726 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
5727 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
5728 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
5729 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
5730 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
5731 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
5732 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
5733 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
5735 typedef struct _ATOM_OEM_INFO
5737 ATOM_COMMON_TABLE_HEADER sHeader;
5738 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
5741 typedef struct _ATOM_TV_MODE
5743 UCHAR ucVMode_Num; //Video mode number
5744 UCHAR ucTV_Mode_Num; //Internal TV mode number
5747 typedef struct _ATOM_BIOS_INT_TVSTD_MODE
5749 ATOM_COMMON_TABLE_HEADER sHeader;
5750 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
5751 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
5752 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
5753 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
5754 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
5755 }ATOM_BIOS_INT_TVSTD_MODE;
5758 typedef struct _ATOM_TV_MODE_SCALER_PTR
5760 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
5761 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
5762 UCHAR ucTV_Mode_Num;
5763 }ATOM_TV_MODE_SCALER_PTR;
5765 typedef struct _ATOM_STANDARD_VESA_TIMING
5767 ATOM_COMMON_TABLE_HEADER sHeader;
5768 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
5769 }ATOM_STANDARD_VESA_TIMING;
5772 typedef struct _ATOM_STD_FORMAT
5776 USHORT usSTD_RefreshRate;
5780 typedef struct _ATOM_VESA_TO_EXTENDED_MODE
5782 USHORT usVESA_ModeNumber;
5783 USHORT usExtendedModeNumber;
5784 }ATOM_VESA_TO_EXTENDED_MODE;
5786 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
5788 ATOM_COMMON_TABLE_HEADER sHeader;
5789 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
5790 }ATOM_VESA_TO_INTENAL_MODE_LUT;
5792 /*************** ATOM Memory Related Data Structure ***********************/
5793 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
5795 UCHAR ucMemoryVendor;
5798 ULONG ulDllResetClkRange;
5799 }ATOM_MEMORY_VENDOR_BLOCK;
5802 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
5805 ULONG ulMemClockRange:24;
5807 ULONG ulMemClockRange:24;
5810 }ATOM_MEMORY_SETTING_ID_CONFIG;
5812 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
5814 ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
5816 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
5819 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
5820 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
5821 ULONG aulMemData[1];
5822 }ATOM_MEMORY_SETTING_DATA_BLOCK;
5825 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
5826 USHORT usRegIndex; // MC register index
5827 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
5828 }ATOM_INIT_REG_INDEX_FORMAT;
5831 typedef struct _ATOM_INIT_REG_BLOCK{
5832 USHORT usRegIndexTblSize; //size of asRegIndexBuf
5833 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
5834 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
5835 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
5836 }ATOM_INIT_REG_BLOCK;
5838 #define END_OF_REG_INDEX_BLOCK 0x0ffff
5839 #define END_OF_REG_DATA_BLOCK 0x00000000
5840 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
5841 #define CLOCK_RANGE_HIGHEST 0x00ffffff
5843 #define VALUE_DWORD SIZEOF ULONG
5844 #define VALUE_SAME_AS_ABOVE 0
5845 #define VALUE_MASK_DWORD 0x84
5847 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
5848 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
5849 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
5850 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
5851 #define ACCESS_PLACEHOLDER 0x80
5853 typedef struct _ATOM_MC_INIT_PARAM_TABLE
5855 ATOM_COMMON_TABLE_HEADER sHeader;
5856 USHORT usAdjustARB_SEQDataOffset;
5857 USHORT usMCInitMemTypeTblOffset;
5858 USHORT usMCInitCommonTblOffset;
5859 USHORT usMCInitPowerDownTblOffset;
5860 ULONG ulARB_SEQDataBuf[32];
5861 ATOM_INIT_REG_BLOCK asMCInitMemType;
5862 ATOM_INIT_REG_BLOCK asMCInitCommon;
5863 }ATOM_MC_INIT_PARAM_TABLE;
5870 #define _16Mx16 0x22
5871 #define _16Mx32 0x23
5872 #define _32Mx16 0x32
5873 #define _32Mx32 0x33
5875 #define _64Mx16 0x42
5876 #define _64Mx32 0x43
5877 #define _128Mx8 0x51
5878 #define _128Mx16 0x52
5879 #define _256Mx8 0x61
5880 #define _256Mx16 0x62
5883 #define INFINEON 0x2
5893 #define QIMONDA INFINEON
5894 #define PROMOS MOSEL
5895 #define KRETON INFINEON
5896 #define ELIXIR NANYA
5898 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
5900 #define UCODE_ROM_START_ADDRESS 0x1b800
5901 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
5903 //uCode block header for reference
5905 typedef struct _MCuCodeHeader
5912 USHORT usParametersLength;
5913 USHORT usUCodeLength;
5918 //////////////////////////////////////////////////////////////////////////////////
5920 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
5922 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
5923 typedef struct _ATOM_VRAM_MODULE_V1
5929 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5930 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
5931 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
5932 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5933 UCHAR ucRow; // Number of Row,in power of 2;
5934 UCHAR ucColumn; // Number of Column,in power of 2;
5935 UCHAR ucBank; // Nunber of Bank;
5936 UCHAR ucRank; // Number of Rank, in power of 2
5937 UCHAR ucChannelNum; // Number of channel;
5938 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5939 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5940 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5941 UCHAR ucReserved[2];
5942 }ATOM_VRAM_MODULE_V1;
5945 typedef struct _ATOM_VRAM_MODULE_V2
5948 ULONG ulFlags; // To enable/disable functionalities based on memory type
5949 ULONG ulEngineClock; // Override of default engine clock for particular memory type
5950 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
5951 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
5952 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
5956 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5957 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
5958 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
5959 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5960 UCHAR ucRow; // Number of Row,in power of 2;
5961 UCHAR ucColumn; // Number of Column,in power of 2;
5962 UCHAR ucBank; // Nunber of Bank;
5963 UCHAR ucRank; // Number of Rank, in power of 2
5964 UCHAR ucChannelNum; // Number of channel;
5965 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5966 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5967 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5968 UCHAR ucRefreshRateFactor;
5969 UCHAR ucReserved[3];
5970 }ATOM_VRAM_MODULE_V2;
5973 typedef struct _ATOM_MEMORY_TIMING_FORMAT
5975 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
5977 USHORT usMRS; // mode register
5981 USHORT usEMRS; // extended mode register
5984 UCHAR ucCL; // CAS latency
5985 UCHAR ucWL; // WRITE Latency
5986 UCHAR uctRAS; // tRAS
5988 UCHAR uctRFC; // tRFC
5989 UCHAR uctRCDR; // tRCDR
5990 UCHAR uctRCDW; // tRCDW
5992 UCHAR uctRRD; // tRRD
5994 UCHAR uctWTR; // tWTR
5995 UCHAR uctPDIX; // tPDIX
5996 UCHAR uctFAW; // tFAW
5997 UCHAR uctAOND; // tAOND
6001 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6006 }ATOM_MEMORY_TIMING_FORMAT;
6009 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
6011 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6012 USHORT usMRS; // mode register
6013 USHORT usEMRS; // extended mode register
6014 UCHAR ucCL; // CAS latency
6015 UCHAR ucWL; // WRITE Latency
6016 UCHAR uctRAS; // tRAS
6018 UCHAR uctRFC; // tRFC
6019 UCHAR uctRCDR; // tRCDR
6020 UCHAR uctRCDW; // tRCDW
6022 UCHAR uctRRD; // tRRD
6024 UCHAR uctWTR; // tWTR
6025 UCHAR uctPDIX; // tPDIX
6026 UCHAR uctFAW; // tFAW
6027 UCHAR uctAOND; // tAOND
6028 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6029 ////////////////////////////////////GDDR parameters///////////////////////////////////
6040 }ATOM_MEMORY_TIMING_FORMAT_V1;
6042 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
6044 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6045 USHORT usMRS; // mode register
6046 USHORT usEMRS; // extended mode register
6047 UCHAR ucCL; // CAS latency
6048 UCHAR ucWL; // WRITE Latency
6049 UCHAR uctRAS; // tRAS
6051 UCHAR uctRFC; // tRFC
6052 UCHAR uctRCDR; // tRCDR
6053 UCHAR uctRCDW; // tRCDW
6055 UCHAR uctRRD; // tRRD
6057 UCHAR uctWTR; // tWTR
6058 UCHAR uctPDIX; // tPDIX
6059 UCHAR uctFAW; // tFAW
6060 UCHAR uctAOND; // tAOND
6061 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6062 ////////////////////////////////////GDDR parameters///////////////////////////////////
6076 }ATOM_MEMORY_TIMING_FORMAT_V2;
6078 typedef struct _ATOM_MEMORY_FORMAT
6080 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
6082 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6083 USHORT usDDR3_Reserved; // Not used for DDR3 memory
6086 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6087 USHORT usDDR3_MR3; // Used for DDR3 memory
6089 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
6090 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
6091 UCHAR ucRow; // Number of Row,in power of 2;
6092 UCHAR ucColumn; // Number of Column,in power of 2;
6093 UCHAR ucBank; // Nunber of Bank;
6094 UCHAR ucRank; // Number of Rank, in power of 2
6095 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6096 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
6097 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
6098 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6099 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6100 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
6101 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
6102 }ATOM_MEMORY_FORMAT;
6105 typedef struct _ATOM_VRAM_MODULE_V3
6107 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
6108 USHORT usSize; // size of ATOM_VRAM_MODULE_V3
6109 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
6110 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
6111 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6112 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
6113 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
6114 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6115 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6116 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6117 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
6118 }ATOM_VRAM_MODULE_V3;
6121 //ATOM_VRAM_MODULE_V3.ucNPL_RT
6122 #define NPL_RT_MASK 0x0f
6123 #define BATTERY_ODT_MASK 0xc0
6125 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
6127 typedef struct _ATOM_VRAM_MODULE_V4
6129 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6130 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6131 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6132 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6134 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6135 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6136 UCHAR ucChannelNum; // Number of channels present in this module config
6137 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6138 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6139 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6140 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6141 UCHAR ucVREFI; // board dependent parameter
6142 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6143 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6144 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6145 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6146 UCHAR ucReserved[3];
6148 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6150 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6151 USHORT usDDR3_Reserved;
6154 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6155 USHORT usDDR3_MR3; // Used for DDR3 memory
6157 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6158 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6159 UCHAR ucReserved2[2];
6160 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6161 }ATOM_VRAM_MODULE_V4;
6163 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
6164 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
6165 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4
6166 #define VRAM_MODULE_V4_MISC_BL8 0x4
6167 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
6169 typedef struct _ATOM_VRAM_MODULE_V5
6171 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6172 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6173 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6174 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6176 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6177 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6178 UCHAR ucChannelNum; // Number of channels present in this module config
6179 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6180 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6181 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6182 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6183 UCHAR ucVREFI; // board dependent parameter
6184 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6185 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6186 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6187 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6188 UCHAR ucReserved[3];
6190 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6191 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6192 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6193 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6194 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6195 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6196 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6197 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6198 }ATOM_VRAM_MODULE_V5;
6200 typedef struct _ATOM_VRAM_MODULE_V6
6202 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6203 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6204 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6205 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6207 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6208 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6209 UCHAR ucChannelNum; // Number of channels present in this module config
6210 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6211 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6212 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6213 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6214 UCHAR ucVREFI; // board dependent parameter
6215 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6216 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6217 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6218 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6219 UCHAR ucReserved[3];
6221 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6222 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6223 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6224 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
6225 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6226 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6227 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6228 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6229 }ATOM_VRAM_MODULE_V6;
6231 typedef struct _ATOM_VRAM_MODULE_V7
6233 // Design Specific Values
6234 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
6235 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
6236 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6237 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
6238 UCHAR ucExtMemoryID; // Current memory module ID
6239 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
6240 UCHAR ucChannelNum; // Number of mem. channels supported in this module
6241 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
6242 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6243 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
6244 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
6245 UCHAR ucVREFI; // Not used.
6246 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6247 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6248 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6249 USHORT usSEQSettingOffset;
6251 // Memory Module specific values
6252 USHORT usEMRS2Value; // EMRS2/MR2 Value.
6253 USHORT usEMRS3Value; // EMRS3/MR3 Value.
6254 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6255 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6256 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
6257 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6258 char strMemPNString[20]; // part number end with '0'.
6259 }ATOM_VRAM_MODULE_V7;
6261 typedef struct _ATOM_VRAM_INFO_V2
6263 ATOM_COMMON_TABLE_HEADER sHeader;
6264 UCHAR ucNumOfVRAMModule;
6265 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6268 typedef struct _ATOM_VRAM_INFO_V3
6270 ATOM_COMMON_TABLE_HEADER sHeader;
6271 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6272 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6274 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6275 UCHAR ucNumOfVRAMModule;
6276 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6277 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
6278 // ATOM_INIT_REG_BLOCK aMemAdjust;
6281 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
6283 typedef struct _ATOM_VRAM_INFO_V4
6285 ATOM_COMMON_TABLE_HEADER sHeader;
6286 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6287 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6289 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
6290 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6291 UCHAR ucReservde[4];
6292 UCHAR ucNumOfVRAMModule;
6293 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6294 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
6295 // ATOM_INIT_REG_BLOCK aMemAdjust;
6298 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
6300 ATOM_COMMON_TABLE_HEADER sHeader;
6301 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6302 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6303 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
6304 USHORT usReserved[3];
6305 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
6306 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
6307 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
6309 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6310 }ATOM_VRAM_INFO_HEADER_V2_1;
6313 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
6315 ATOM_COMMON_TABLE_HEADER sHeader;
6316 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
6317 }ATOM_VRAM_GPIO_DETECTION_INFO;
6320 typedef struct _ATOM_MEMORY_TRAINING_INFO
6322 ATOM_COMMON_TABLE_HEADER sHeader;
6323 UCHAR ucTrainingLoop;
6324 UCHAR ucReserved[3];
6325 ATOM_INIT_REG_BLOCK asMemTrainingSetting;
6326 }ATOM_MEMORY_TRAINING_INFO;
6329 typedef struct SW_I2C_CNTL_DATA_PARAMETERS
6335 } SW_I2C_CNTL_DATA_PARAMETERS;
6337 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
6339 typedef struct _SW_I2C_IO_DATA_PARAMETERS
6344 } SW_I2C_IO_DATA_PARAMETERS;
6346 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
6348 /****************************SW I2C CNTL DEFINITIONS**********************/
6349 #define SW_I2C_IO_RESET 0
6350 #define SW_I2C_IO_GET 1
6351 #define SW_I2C_IO_DRIVE 2
6352 #define SW_I2C_IO_SET 3
6353 #define SW_I2C_IO_START 4
6355 #define SW_I2C_IO_CLOCK 0
6356 #define SW_I2C_IO_DATA 0x80
6358 #define SW_I2C_IO_ZERO 0
6359 #define SW_I2C_IO_ONE 0x100
6361 #define SW_I2C_CNTL_READ 0
6362 #define SW_I2C_CNTL_WRITE 1
6363 #define SW_I2C_CNTL_START 2
6364 #define SW_I2C_CNTL_STOP 3
6365 #define SW_I2C_CNTL_OPEN 4
6366 #define SW_I2C_CNTL_CLOSE 5
6367 #define SW_I2C_CNTL_WRITE1BIT 6
6369 //==============================VESA definition Portion===============================
6370 #define VESA_OEM_PRODUCT_REV "01.00"
6371 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
6372 #define VESA_MODE_WIN_ATTRIBUTE 7
6373 #define VESA_WIN_SIZE 64
6375 typedef struct _PTR_32_BIT_STRUCTURE
6379 } PTR_32_BIT_STRUCTURE;
6381 typedef union _PTR_32_BIT_UNION
6383 PTR_32_BIT_STRUCTURE SegmentOffset;
6387 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
6389 UCHAR VbeSignature[4];
6391 PTR_32_BIT_UNION OemStringPtr;
6392 UCHAR Capabilities[4];
6393 PTR_32_BIT_UNION VideoModePtr;
6395 } VBE_1_2_INFO_BLOCK_UPDATABLE;
6398 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
6400 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
6402 PTR_32_BIT_UNION OemVendorNamePtr;
6403 PTR_32_BIT_UNION OemProductNamePtr;
6404 PTR_32_BIT_UNION OemProductRevPtr;
6405 } VBE_2_0_INFO_BLOCK_UPDATABLE;
6407 typedef union _VBE_VERSION_UNION
6409 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
6410 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
6411 } VBE_VERSION_UNION;
6413 typedef struct _VBE_INFO_BLOCK
6415 VBE_VERSION_UNION UpdatableVBE_Info;
6416 UCHAR Reserved[222];
6420 typedef struct _VBE_FP_INFO
6429 ULONG RsvdOffScrnMemSize;
6430 ULONG RsvdOffScrnMEmPtr;
6434 typedef struct _VESA_MODE_INFO_BLOCK
6436 // Mandatory information for all VBE revisions
6437 USHORT ModeAttributes; // dw ? ; mode attributes
6438 UCHAR WinAAttributes; // db ? ; window A attributes
6439 UCHAR WinBAttributes; // db ? ; window B attributes
6440 USHORT WinGranularity; // dw ? ; window granularity
6441 USHORT WinSize; // dw ? ; window size
6442 USHORT WinASegment; // dw ? ; window A start segment
6443 USHORT WinBSegment; // dw ? ; window B start segment
6444 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6445 USHORT BytesPerScanLine;// dw ? ; bytes per scan line
6447 //; Mandatory information for VBE 1.2 and above
6448 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
6449 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
6450 UCHAR XCharSize; // db ? ; character cell width in pixels
6451 UCHAR YCharSize; // db ? ; character cell height in pixels
6452 UCHAR NumberOfPlanes; // db ? ; number of memory planes
6453 UCHAR BitsPerPixel; // db ? ; bits per pixel
6454 UCHAR NumberOfBanks; // db ? ; number of banks
6455 UCHAR MemoryModel; // db ? ; memory model type
6456 UCHAR BankSize; // db ? ; bank size in KB
6457 UCHAR NumberOfImagePages;// db ? ; number of images
6458 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
6460 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
6461 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
6462 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
6463 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
6464 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
6465 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
6466 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
6467 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
6468 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
6469 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
6471 //; Mandatory information for VBE 2.0 and above
6472 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
6473 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6474 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6476 //; Mandatory information for VBE 3.0 and above
6477 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
6478 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
6479 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
6480 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
6481 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
6482 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
6483 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
6484 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
6485 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
6486 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
6487 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
6488 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
6489 UCHAR Reserved; // db 190 dup (0)
6490 } VESA_MODE_INFO_BLOCK;
6492 // BIOS function CALLS
6493 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
6494 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00
6495 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
6496 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
6497 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
6498 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
6499 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
6500 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
6501 #define ATOM_BIOS_FUNCTION_STV_STD 0x16
6502 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
6503 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
6505 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
6506 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
6507 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
6508 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
6509 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
6510 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
6511 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
6513 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
6514 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
6515 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
6516 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
6517 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
6518 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
6519 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
6520 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
6521 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
6522 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
6525 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
6526 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
6527 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
6528 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
6529 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
6530 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
6531 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
6532 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
6534 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
6535 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
6536 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
6538 // structure used for VBIOS only
6541 typedef struct _ASIC_TRANSMITTER_INFO
6543 USHORT usTransmitterObjId;
6544 USHORT usSupportDevice;
6545 UCHAR ucTransmitterCmdTblId;
6547 UCHAR ucEncoderID; //available 1st encoder ( default )
6548 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
6549 UCHAR uc2ndEncoderID;
6551 }ASIC_TRANSMITTER_INFO;
6553 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
6554 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
6555 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
6556 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
6557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
6558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
6559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
6560 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
6561 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
6563 typedef struct _ASIC_ENCODER_INFO
6566 UCHAR ucEncoderConfig;
6567 USHORT usEncoderCmdTblId;
6570 typedef struct _ATOM_DISP_OUT_INFO
6572 ATOM_COMMON_TABLE_HEADER sHeader;
6573 USHORT ptrTransmitterInfo;
6574 USHORT ptrEncoderInfo;
6575 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
6576 ASIC_ENCODER_INFO asEncoderInfo[1];
6577 }ATOM_DISP_OUT_INFO;
6579 typedef struct _ATOM_DISP_OUT_INFO_V2
6581 ATOM_COMMON_TABLE_HEADER sHeader;
6582 USHORT ptrTransmitterInfo;
6583 USHORT ptrEncoderInfo;
6584 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
6585 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
6586 ASIC_ENCODER_INFO asEncoderInfo[1];
6587 }ATOM_DISP_OUT_INFO_V2;
6590 typedef struct _ATOM_DISP_CLOCK_ID {
6592 UCHAR ucPpllAttribute;
6593 }ATOM_DISP_CLOCK_ID;
6596 #define CLOCK_SOURCE_SHAREABLE 0x01
6597 #define CLOCK_SOURCE_DP_MODE 0x02
6598 #define CLOCK_SOURCE_NONE_DP_MODE 0x04
6601 typedef struct _ASIC_TRANSMITTER_INFO_V2
6603 USHORT usTransmitterObjId;
6604 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
6605 UCHAR ucTransmitterCmdTblId;
6607 UCHAR ucEncoderID; // available 1st encoder ( default )
6608 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
6609 UCHAR uc2ndEncoderID;
6611 }ASIC_TRANSMITTER_INFO_V2;
6613 typedef struct _ATOM_DISP_OUT_INFO_V3
6615 ATOM_COMMON_TABLE_HEADER sHeader;
6616 USHORT ptrTransmitterInfo;
6617 USHORT ptrEncoderInfo;
6618 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
6620 UCHAR ucDCERevision;
6621 UCHAR ucMaxDispEngineNum;
6622 UCHAR ucMaxActiveDispEngineNum;
6624 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
6625 UCHAR ucReserved[3];
6626 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
6627 }ATOM_DISP_OUT_INFO_V3;
6629 typedef enum CORE_REF_CLK_SOURCE{
6633 }CORE_REF_CLK_SOURCE;
6635 // DispDevicePriorityInfo
6636 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
6638 ATOM_COMMON_TABLE_HEADER sHeader;
6639 USHORT asDevicePriority[16];
6640 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
6642 //ProcessAuxChannelTransactionTable
6643 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6645 USHORT lpAuxRequest;
6650 UCHAR ucReplyStatus;
6655 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
6657 //ProcessAuxChannelTransactionTable
6658 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
6660 USHORT lpAuxRequest;
6665 UCHAR ucReplyStatus;
6669 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
6670 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
6672 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6676 typedef struct _DP_ENCODER_SERVICE_PARAMETERS
6681 UCHAR ucConfig; // for DP training command
6682 UCHAR ucI2cId; // use for GET_SINK_TYPE command
6687 UCHAR ucReserved[2];
6688 }DP_ENCODER_SERVICE_PARAMETERS;
6691 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
6693 #define ATOM_DP_ACTION_TRAINING_START 0x02
6694 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
6695 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
6696 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
6697 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
6698 #define ATOM_DP_ACTION_BLANKING 0x07
6701 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
6702 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
6703 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
6704 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
6705 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
6706 #define ATOM_DP_CONFIG_LINK_A 0x00
6707 #define ATOM_DP_CONFIG_LINK_B 0x04
6709 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
6712 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
6714 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6717 UCHAR ucSinkType; // Iput and Output parameters.
6718 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6719 UCHAR ucReserved[2];
6720 }DP_ENCODER_SERVICE_PARAMETERS_V2;
6722 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
6724 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
6725 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
6726 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
6729 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
6730 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
6733 // DP_TRAINING_TABLE
6734 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
6735 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
6736 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
6737 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
6738 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
6739 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
6740 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
6741 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
6742 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
6743 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
6744 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
6745 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
6746 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
6748 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6756 USHORT lpI2CDataOut;
6761 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
6763 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6766 #define HW_I2C_WRITE 1
6767 #define HW_I2C_READ 0
6768 #define I2C_2BYTE_ADDR 0x02
6770 /****************************************************************************/
6771 // Structures used by HW_Misc_OperationTable
6772 /****************************************************************************/
6773 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
6775 UCHAR ucCmd; // Input: To tell which action to take
6776 UCHAR ucReserved[3];
6778 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
6780 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
6782 UCHAR ucReturnCode; // Output: Return value base on action was taken
6783 UCHAR ucReserved[3];
6785 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
6788 #define ATOM_GET_SDI_SUPPORT 0xF0
6791 #define ATOM_UNKNOWN_CMD 0
6792 #define ATOM_FEATURE_NOT_SUPPORTED 1
6793 #define ATOM_FEATURE_SUPPORTED 2
6795 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
6797 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;
6798 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;
6799 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
6801 /****************************************************************************/
6803 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
6805 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
6806 UCHAR ucReserved[3];
6807 }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
6809 #define HWBLKINST_INSTANCE_MASK 0x07
6810 #define HWBLKINST_HWBLK_MASK 0xF0
6811 #define HWBLKINST_HWBLK_SHIFT 0x04
6814 #define SELECT_DISP_ENGINE 0
6815 #define SELECT_DISP_PLL 1
6816 #define SELECT_DCIO_UNIPHY_LINK0 2
6817 #define SELECT_DCIO_UNIPHY_LINK1 3
6818 #define SELECT_DCIO_IMPCAL 4
6819 #define SELECT_DCIO_DIG 6
6820 #define SELECT_CRTC_PIXEL_RATE 7
6821 #define SELECT_VGA_BLK 8
6823 // DIGTransmitterInfoTable structure used to program UNIPHY settings
6824 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
6825 ATOM_COMMON_TABLE_HEADER sHeader;
6826 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
6827 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
6828 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
6829 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
6830 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
6831 }DIG_TRANSMITTER_INFO_HEADER_V3_1;
6833 typedef struct _CLOCK_CONDITION_REGESTER_INFO{
6834 USHORT usRegisterIndex;
6837 }CLOCK_CONDITION_REGESTER_INFO;
6839 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
6840 USHORT usMaxClockFreq;
6843 ULONG ulAnalogSetting[1];
6844 }CLOCK_CONDITION_SETTING_ENTRY;
6846 typedef struct _CLOCK_CONDITION_SETTING_INFO{
6848 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
6849 }CLOCK_CONDITION_SETTING_INFO;
6851 typedef struct _PHY_CONDITION_REG_VAL{
6854 }PHY_CONDITION_REG_VAL;
6856 typedef struct _PHY_CONDITION_REG_INFO{
6859 PHY_CONDITION_REG_VAL asRegVal[1];
6860 }PHY_CONDITION_REG_INFO;
6862 typedef struct _PHY_ANALOG_SETTING_INFO{
6866 PHY_CONDITION_REG_INFO asAnalogSetting[1];
6867 }PHY_ANALOG_SETTING_INFO;
6869 /****************************************************************************/
6870 //Portion VI: Definitinos for vbios MC scratch registers that driver used
6871 /****************************************************************************/
6873 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
6874 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
6875 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
6876 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
6877 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
6878 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
6879 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
6881 /****************************************************************************/
6882 //Portion VI: Definitinos being oboselete
6883 /****************************************************************************/
6885 //==========================================================================================
6886 //Remove the definitions below when driver is ready!
6887 typedef struct _ATOM_DAC_INFO
6889 ATOM_COMMON_TABLE_HEADER sHeader;
6890 USHORT usMaxFrequency; // in 10kHz unit
6895 typedef struct _COMPASSIONATE_DATA
6897 ATOM_COMMON_TABLE_HEADER sHeader;
6899 //============================== DAC1 portion
6900 UCHAR ucDAC1_BG_Adjustment;
6901 UCHAR ucDAC1_DAC_Adjustment;
6902 USHORT usDAC1_FORCE_Data;
6903 //============================== DAC2 portion
6904 UCHAR ucDAC2_CRT2_BG_Adjustment;
6905 UCHAR ucDAC2_CRT2_DAC_Adjustment;
6906 USHORT usDAC2_CRT2_FORCE_Data;
6907 USHORT usDAC2_CRT2_MUX_RegisterIndex;
6908 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6909 UCHAR ucDAC2_NTSC_BG_Adjustment;
6910 UCHAR ucDAC2_NTSC_DAC_Adjustment;
6911 USHORT usDAC2_TV1_FORCE_Data;
6912 USHORT usDAC2_TV1_MUX_RegisterIndex;
6913 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6914 UCHAR ucDAC2_CV_BG_Adjustment;
6915 UCHAR ucDAC2_CV_DAC_Adjustment;
6916 USHORT usDAC2_CV_FORCE_Data;
6917 USHORT usDAC2_CV_MUX_RegisterIndex;
6918 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6919 UCHAR ucDAC2_PAL_BG_Adjustment;
6920 UCHAR ucDAC2_PAL_DAC_Adjustment;
6921 USHORT usDAC2_TV2_FORCE_Data;
6922 }COMPASSIONATE_DATA;
6924 /****************************Supported Device Info Table Definitions**********************/
6926 // [7:4] - connector type
6927 // = 1 - VGA connector
6934 // = 8 - DIGITAL LINK
6936 // = 0xA - HDMI_type A
6937 // = 0xB - HDMI_type B
6938 // = 0xE - Special case1 (DVI+DIN)
6940 // [3:0] - DAC Associated
6944 // = 3 - External DAC
6948 typedef struct _ATOM_CONNECTOR_INFO
6951 UCHAR bfConnectorType:4;
6952 UCHAR bfAssociatedDAC:4;
6954 UCHAR bfAssociatedDAC:4;
6955 UCHAR bfConnectorType:4;
6957 }ATOM_CONNECTOR_INFO;
6959 typedef union _ATOM_CONNECTOR_INFO_ACCESS
6961 ATOM_CONNECTOR_INFO sbfAccess;
6963 }ATOM_CONNECTOR_INFO_ACCESS;
6965 typedef struct _ATOM_CONNECTOR_INFO_I2C
6967 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
6968 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
6969 }ATOM_CONNECTOR_INFO_I2C;
6972 typedef struct _ATOM_SUPPORTED_DEVICES_INFO
6974 ATOM_COMMON_TABLE_HEADER sHeader;
6975 USHORT usDeviceSupport;
6976 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
6977 }ATOM_SUPPORTED_DEVICES_INFO;
6979 #define NO_INT_SRC_MAPPED 0xFF
6981 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
6983 UCHAR ucIntSrcBitmap;
6984 }ATOM_CONNECTOR_INC_SRC_BITMAP;
6986 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
6988 ATOM_COMMON_TABLE_HEADER sHeader;
6989 USHORT usDeviceSupport;
6990 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6991 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6992 }ATOM_SUPPORTED_DEVICES_INFO_2;
6994 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
6996 ATOM_COMMON_TABLE_HEADER sHeader;
6997 USHORT usDeviceSupport;
6998 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
6999 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
7000 }ATOM_SUPPORTED_DEVICES_INFO_2d1;
7002 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
7006 typedef struct _ATOM_MISC_CONTROL_INFO
7009 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7010 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
7011 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
7012 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
7013 }ATOM_MISC_CONTROL_INFO;
7016 #define ATOM_MAX_MISC_INFO 4
7018 typedef struct _ATOM_TMDS_INFO
7020 ATOM_COMMON_TABLE_HEADER sHeader;
7021 USHORT usMaxFrequency; // in 10Khz
7022 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
7026 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
7028 UCHAR ucTVStandard; //Same as TV standards defined above,
7030 }ATOM_ENCODER_ANALOG_ATTRIBUTE;
7032 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
7034 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
7036 }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
7038 typedef union _ATOM_ENCODER_ATTRIBUTE
7040 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
7041 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
7042 }ATOM_ENCODER_ATTRIBUTE;
7045 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
7047 USHORT usPixelClock;
7049 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
7050 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
7051 ATOM_ENCODER_ATTRIBUTE usDevAttr;
7052 }DVO_ENCODER_CONTROL_PARAMETERS;
7054 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
7056 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
7057 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
7058 }DVO_ENCODER_CONTROL_PS_ALLOCATION;
7061 #define ATOM_XTMDS_ASIC_SI164_ID 1
7062 #define ATOM_XTMDS_ASIC_SI178_ID 2
7063 #define ATOM_XTMDS_ASIC_TFP513_ID 3
7064 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
7065 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
7066 #define ATOM_XTMDS_MVPU_FPGA 0x00000004
7069 typedef struct _ATOM_XTMDS_INFO
7071 ATOM_COMMON_TABLE_HEADER sHeader;
7072 USHORT usSingleLinkMaxFrequency;
7073 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
7074 UCHAR ucXtransimitterID;
7075 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
7076 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
7077 // due to design. This ID is used to alert driver that the sequence is not "standard"!
7078 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
7079 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
7082 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
7084 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
7085 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
7087 }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
7089 /****************************Legacy Power Play Table Definitions **********************/
7091 //Definitions for ulPowerPlayMiscInfo
7092 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
7093 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
7094 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
7096 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
7097 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
7099 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
7101 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
7102 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
7103 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
7105 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
7106 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
7107 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
7108 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
7109 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
7110 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
7111 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
7113 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
7114 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
7115 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
7116 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
7117 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
7119 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
7120 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
7122 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
7123 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
7124 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
7125 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
7126 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
7127 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
7129 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
7130 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
7131 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
7133 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
7134 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
7135 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
7136 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
7137 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
7138 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
7139 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
7140 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
7141 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
7142 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
7143 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
7145 //ucTableFormatRevision=1
7146 //ucTableContentRevision=1
7147 typedef struct _ATOM_POWERMODE_INFO
7149 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7150 ULONG ulReserved1; // must set to 0
7151 ULONG ulReserved2; // must set to 0
7152 USHORT usEngineClock;
7153 USHORT usMemoryClock;
7154 UCHAR ucVoltageDropIndex; // index to GPIO table
7155 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7156 UCHAR ucMinTemperature;
7157 UCHAR ucMaxTemperature;
7158 UCHAR ucNumPciELanes; // number of PCIE lanes
7159 }ATOM_POWERMODE_INFO;
7161 //ucTableFormatRevision=2
7162 //ucTableContentRevision=1
7163 typedef struct _ATOM_POWERMODE_INFO_V2
7165 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7167 ULONG ulEngineClock;
7168 ULONG ulMemoryClock;
7169 UCHAR ucVoltageDropIndex; // index to GPIO table
7170 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7171 UCHAR ucMinTemperature;
7172 UCHAR ucMaxTemperature;
7173 UCHAR ucNumPciELanes; // number of PCIE lanes
7174 }ATOM_POWERMODE_INFO_V2;
7176 //ucTableFormatRevision=2
7177 //ucTableContentRevision=2
7178 typedef struct _ATOM_POWERMODE_INFO_V3
7180 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7182 ULONG ulEngineClock;
7183 ULONG ulMemoryClock;
7184 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
7185 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7186 UCHAR ucMinTemperature;
7187 UCHAR ucMaxTemperature;
7188 UCHAR ucNumPciELanes; // number of PCIE lanes
7189 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
7190 }ATOM_POWERMODE_INFO_V3;
7193 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
7195 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
7196 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
7198 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
7199 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
7200 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
7201 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
7202 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
7203 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
7204 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
7207 typedef struct _ATOM_POWERPLAY_INFO
7209 ATOM_COMMON_TABLE_HEADER sHeader;
7210 UCHAR ucOverdriveThermalController;
7211 UCHAR ucOverdriveI2cLine;
7212 UCHAR ucOverdriveIntBitmap;
7213 UCHAR ucOverdriveControllerAddress;
7214 UCHAR ucSizeOfPowerModeEntry;
7215 UCHAR ucNumOfPowerModeEntries;
7216 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7217 }ATOM_POWERPLAY_INFO;
7219 typedef struct _ATOM_POWERPLAY_INFO_V2
7221 ATOM_COMMON_TABLE_HEADER sHeader;
7222 UCHAR ucOverdriveThermalController;
7223 UCHAR ucOverdriveI2cLine;
7224 UCHAR ucOverdriveIntBitmap;
7225 UCHAR ucOverdriveControllerAddress;
7226 UCHAR ucSizeOfPowerModeEntry;
7227 UCHAR ucNumOfPowerModeEntries;
7228 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7229 }ATOM_POWERPLAY_INFO_V2;
7231 typedef struct _ATOM_POWERPLAY_INFO_V3
7233 ATOM_COMMON_TABLE_HEADER sHeader;
7234 UCHAR ucOverdriveThermalController;
7235 UCHAR ucOverdriveI2cLine;
7236 UCHAR ucOverdriveIntBitmap;
7237 UCHAR ucOverdriveControllerAddress;
7238 UCHAR ucSizeOfPowerModeEntry;
7239 UCHAR ucNumOfPowerModeEntries;
7240 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7241 }ATOM_POWERPLAY_INFO_V3;
7244 /**************************************************************************/
7245 typedef struct _ATOM_PPLIB_THERMALCONTROLLER
7248 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
7249 UCHAR ucI2cLine; // as interpreted by DAL I2C
7251 UCHAR ucFanParameters; // Fan Control Parameters.
7252 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
7253 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
7254 UCHAR ucReserved; // ----
7255 UCHAR ucFlags; // to be defined
7256 } ATOM_PPLIB_THERMALCONTROLLER;
7258 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
7259 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
7261 #define ATOM_PP_THERMALCONTROLLER_NONE 0
7262 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
7263 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
7264 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
7265 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
7266 #define ATOM_PP_THERMALCONTROLLER_LM64 5
7267 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
7268 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7
7269 #define ATOM_PP_THERMALCONTROLLER_RV770 8
7270 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9
7271 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11
7272 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
7273 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
7274 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
7275 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
7276 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16
7277 #define ATOM_PP_THERMALCONTROLLER_LM96163 17
7279 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
7280 // We probably should reserve the bit 0x80 for this use.
7281 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
7282 // The driver can pick the correct internal controller based on the ASIC.
7284 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
7285 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
7287 typedef struct _ATOM_PPLIB_STATE
7289 UCHAR ucNonClockStateIndex;
7290 UCHAR ucClockStateIndices[1]; // variable-sized
7294 typedef struct _ATOM_PPLIB_FANTABLE
7296 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
7297 UCHAR ucTHyst; // Temperature hysteresis. Integer.
7298 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
7299 USHORT usTMed; // The middle temperature where we change slopes.
7300 USHORT usTHigh; // The high point above TMed for adjusting the second slope.
7301 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
7302 USHORT usPWMMed; // The PWM value (in percent) at TMed.
7303 USHORT usPWMHigh; // The PWM value at THigh.
7304 } ATOM_PPLIB_FANTABLE;
7306 typedef struct _ATOM_PPLIB_FANTABLE2
7308 ATOM_PPLIB_FANTABLE basicTable;
7309 USHORT usTMax; // The max temperature
7310 } ATOM_PPLIB_FANTABLE2;
7312 typedef struct _ATOM_PPLIB_EXTENDEDHEADER
7315 ULONG ulMaxEngineClock; // For Overdrive.
7316 ULONG ulMaxMemoryClock; // For Overdrive.
7317 // Add extra system parameters here, always adjust size to include all fields.
7318 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
7319 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
7320 } ATOM_PPLIB_EXTENDEDHEADER;
7322 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
7323 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
7324 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
7325 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
7326 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
7327 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
7328 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
7329 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
7330 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
7331 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
7332 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
7333 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
7334 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
7335 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
7336 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
7337 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
7338 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC.
7339 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
7340 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
7343 typedef struct _ATOM_PPLIB_POWERPLAYTABLE
7345 ATOM_COMMON_TABLE_HEADER sHeader;
7347 UCHAR ucDataRevision;
7350 UCHAR ucStateEntrySize;
7351 UCHAR ucClockInfoSize;
7352 UCHAR ucNonClockSize;
7354 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
7355 USHORT usStateArrayOffset;
7357 // offset from start of this table to array of ASIC-specific structures,
7358 // currently ATOM_PPLIB_CLOCK_INFO.
7359 USHORT usClockInfoArrayOffset;
7361 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
7362 USHORT usNonClockInfoArrayOffset;
7364 USHORT usBackbiasTime; // in microseconds
7365 USHORT usVoltageTime; // in microseconds
7366 USHORT usTableSize; //the size of this structure, or the extended structure
7368 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
7370 ATOM_PPLIB_THERMALCONTROLLER sThermalController;
7372 USHORT usBootClockInfoOffset;
7373 USHORT usBootNonClockInfoOffset;
7375 } ATOM_PPLIB_POWERPLAYTABLE;
7377 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
7379 ATOM_PPLIB_POWERPLAYTABLE basicTable;
7380 UCHAR ucNumCustomThermalPolicy;
7381 USHORT usCustomThermalPolicyArrayOffset;
7382 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
7384 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
7386 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
7387 USHORT usFormatID; // To be used ONLY by PPGen.
7388 USHORT usFanTableOffset;
7389 USHORT usExtendendedHeaderOffset;
7390 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
7392 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
7394 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
7395 ULONG ulGoldenPPID; // PPGen use only
7396 ULONG ulGoldenRevision; // PPGen use only
7397 USHORT usVddcDependencyOnSCLKOffset;
7398 USHORT usVddciDependencyOnMCLKOffset;
7399 USHORT usVddcDependencyOnMCLKOffset;
7400 USHORT usMaxClockVoltageOnDCOffset;
7401 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
7403 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
7405 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
7407 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
7409 ULONG ulNearTDPLimit;
7410 ULONG ulSQRampingThreshold;
7411 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table
7412 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table
7413 USHORT usTDPODLimit;
7414 USHORT usLoadLineSlope; // in milliOhms * 100
7415 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
7417 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification
7418 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
7419 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
7420 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
7421 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
7422 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
7423 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
7424 // 2, 4, 6, 7 are reserved
7426 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
7427 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
7428 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
7429 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
7430 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
7431 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
7432 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
7433 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
7434 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
7435 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
7436 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000
7437 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
7438 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
7440 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
7441 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
7442 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
7443 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D)
7445 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
7446 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
7447 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
7449 // 0 is 2.5Gb/s, 1 is 5Gb/s
7450 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
7451 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
7453 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
7454 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
7455 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
7457 // lookup into reduced refresh-rate table
7458 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
7459 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
7461 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
7462 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
7463 // 2-15 TBD as needed.
7465 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
7466 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
7468 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
7470 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
7472 //memory related flags
7473 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000
7475 //M3 Arb //2bits, current 3 sets of parameters in total
7476 #define ATOM_PPLIB_M3ARB_MASK 0x00060000
7477 #define ATOM_PPLIB_M3ARB_SHIFT 17
7479 #define ATOM_PPLIB_ENABLE_DRR 0x00080000
7481 // remaining 16 bits are reserved
7482 typedef struct _ATOM_PPLIB_THERMAL_STATE
7484 UCHAR ucMinTemperature;
7485 UCHAR ucMaxTemperature;
7486 UCHAR ucThermalAction;
7487 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
7489 // Contained in an array starting at the offset
7490 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
7491 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
7492 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12
7493 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24
7494 typedef struct _ATOM_PPLIB_NONCLOCK_INFO
7496 USHORT usClassification;
7497 UCHAR ucMinTemperature;
7498 UCHAR ucMaxTemperature;
7499 ULONG ulCapsAndSettings;
7500 UCHAR ucRequiredPower;
7501 USHORT usClassification2;
7505 } ATOM_PPLIB_NONCLOCK_INFO;
7507 // Contained in an array starting at the offset
7508 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
7509 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices
7510 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
7512 USHORT usEngineClockLow;
7513 UCHAR ucEngineClockHigh;
7515 USHORT usMemoryClockLow;
7516 UCHAR ucMemoryClockHigh;
7522 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7524 } ATOM_PPLIB_R600_CLOCK_INFO;
7526 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
7527 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
7528 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
7529 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
7530 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
7531 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
7532 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0).
7534 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
7536 USHORT usEngineClockLow;
7537 UCHAR ucEngineClockHigh;
7539 USHORT usMemoryClockLow;
7540 UCHAR ucMemoryClockHigh;
7546 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7548 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
7550 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
7552 USHORT usEngineClockLow;
7553 UCHAR ucEngineClockHigh;
7555 USHORT usMemoryClockLow;
7556 UCHAR ucMemoryClockHigh;
7563 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
7565 } ATOM_PPLIB_SI_CLOCK_INFO;
7568 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
7571 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
7572 UCHAR ucLowEngineClockHigh;
7573 USHORT usHighEngineClockLow; // High Engine clock in MHz.
7574 UCHAR ucHighEngineClockHigh;
7575 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
7576 UCHAR ucMemoryClockHigh; // Currentyl unused.
7577 UCHAR ucPadding; // For proper alignment and size.
7578 USHORT usVDDC; // For the 780, use: None, Low, High, Variable
7579 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
7580 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
7581 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
7583 } ATOM_PPLIB_RS780_CLOCK_INFO;
7585 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
7586 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
7587 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
7588 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
7590 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
7591 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1
7592 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
7594 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
7595 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
7596 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
7598 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
7599 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
7600 UCHAR ucEngineClockHigh; //clockfrequency >> 16.
7601 UCHAR vddcIndex; //2-bit vddc index;
7603 //please initialize to 0
7605 //please initialize to 0s
7607 }ATOM_PPLIB_SUMO_CLOCK_INFO;
7611 typedef struct _ATOM_PPLIB_STATE_V2
7613 //number of valid dpm levels in this state; Driver uses it to calculate the whole
7614 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
7615 UCHAR ucNumDPMLevels;
7617 //a index to the array of nonClockInfos
7618 UCHAR nonClockInfoIndex;
7620 * Driver will read the first ucNumDPMLevels in this array
7622 UCHAR clockInfoIndex[1];
7623 } ATOM_PPLIB_STATE_V2;
7625 typedef struct _StateArray{
7626 //how many states we have
7629 ATOM_PPLIB_STATE_V2 states[1];
7633 typedef struct _ClockInfoArray{
7634 //how many clock levels we have
7637 //sizeof(ATOM_PPLIB_CLOCK_INFO)
7643 typedef struct _NonClockInfoArray{
7645 //how many non-clock levels we have. normally should be same as number of states
7647 //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
7650 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
7653 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
7658 }ATOM_PPLIB_Clock_Voltage_Dependency_Record;
7660 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
7662 UCHAR ucNumEntries; // Number of entries.
7663 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
7664 }ATOM_PPLIB_Clock_Voltage_Dependency_Table;
7666 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
7674 }ATOM_PPLIB_Clock_Voltage_Limit_Record;
7676 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
7678 UCHAR ucNumEntries; // Number of entries.
7679 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
7680 }ATOM_PPLIB_Clock_Voltage_Limit_Table;
7682 typedef struct _ATOM_PPLIB_CAC_Leakage_Record
7684 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations
7685 ULONG ulLeakageValue;
7686 }ATOM_PPLIB_CAC_Leakage_Record;
7688 typedef struct _ATOM_PPLIB_CAC_Leakage_Table
7690 UCHAR ucNumEntries; // Number of entries.
7691 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries.
7692 }ATOM_PPLIB_CAC_Leakage_Table;
7694 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
7701 }ATOM_PPLIB_PhaseSheddingLimits_Record;
7703 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
7705 UCHAR ucNumEntries; // Number of entries.
7706 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries.
7707 }ATOM_PPLIB_PhaseSheddingLimits_Table;
7709 typedef struct _VCEClockInfo{
7716 typedef struct _VCEClockInfoArray{
7718 VCEClockInfo entries[1];
7721 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
7724 UCHAR ucVCEClockInfoIndex;
7725 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record;
7727 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
7730 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
7731 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
7733 typedef struct _ATOM_PPLIB_VCE_State_Record
7735 UCHAR ucVCEClockInfoIndex;
7736 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7737 }ATOM_PPLIB_VCE_State_Record;
7739 typedef struct _ATOM_PPLIB_VCE_State_Table
7742 ATOM_PPLIB_VCE_State_Record entries[1];
7743 }ATOM_PPLIB_VCE_State_Table;
7746 typedef struct _ATOM_PPLIB_VCE_Table
7749 // VCEClockInfoArray array;
7750 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits;
7751 // ATOM_PPLIB_VCE_State_Table states;
7752 }ATOM_PPLIB_VCE_Table;
7755 typedef struct _UVDClockInfo{
7762 typedef struct _UVDClockInfoArray{
7764 UVDClockInfo entries[1];
7767 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
7770 UCHAR ucUVDClockInfoIndex;
7771 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record;
7773 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
7776 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
7777 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
7779 typedef struct _ATOM_PPLIB_UVD_State_Record
7781 UCHAR ucUVDClockInfoIndex;
7782 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7783 }ATOM_PPLIB_UVD_State_Record;
7785 typedef struct _ATOM_PPLIB_UVD_State_Table
7788 ATOM_PPLIB_UVD_State_Record entries[1];
7789 }ATOM_PPLIB_UVD_State_Table;
7792 typedef struct _ATOM_PPLIB_UVD_Table
7795 // UVDClockInfoArray array;
7796 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits;
7797 // ATOM_PPLIB_UVD_State_Table states;
7798 }ATOM_PPLIB_UVD_Table;
7800 /**************************************************************************/
7803 // Following definitions are for compatibility issue in different SW components.
7804 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01
7805 #define Object_Info Object_Header
7806 #define AdjustARB_SEQ MC_InitParameter
7807 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo
7808 #define ASIC_VDDCI_Info ASIC_ProfilingInfo
7809 #define ASIC_MVDDQ_Info MemoryTrainingInfo
7810 #define SS_Info PPLL_SS_Info
7811 #define ASIC_MVDDC_Info ASIC_InternalSS_Info
7812 #define DispDevicePriorityInfo SaveRestoreInfo
7813 #define DispOutInfo TV_VideoMode
7816 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
7817 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
7819 //New device naming, remove them when both DAL/VBIOS is ready
7820 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
7821 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
7823 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
7824 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
7826 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
7827 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
7829 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
7830 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
7832 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
7833 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
7835 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009
7836 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
7838 #define ATOM_S0_DFP1I ATOM_S0_DFP1
7839 #define ATOM_S0_DFP1X ATOM_S0_DFP2
7841 #define ATOM_S0_DFP2I 0x00200000L
7842 #define ATOM_S0_DFP2Ib2 0x20
7844 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
7845 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
7847 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
7848 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
7850 #define ATOM_S3_DFP2I_ACTIVEb1 0x02
7852 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
7853 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
7855 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L
7857 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
7858 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
7859 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
7861 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
7862 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
7864 #define ATOM_S5_DOS_REQ_DFP2I 0x0200
7865 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
7866 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
7868 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
7869 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
7871 #define TMDS1XEncoderControl DVOEncoderControl
7872 #define DFP1XOutputControl DVOOutputControl
7874 #define ExternalDFPOutputControl DFP1XOutputControl
7875 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl
7877 #define DFP1IOutputControl TMDSAOutputControl
7878 #define DFP2IOutputControl LVTMAOutputControl
7880 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
7881 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7883 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
7884 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7886 #define ucDac1Standard ucDacStandard
7887 #define ucDac2Standard ucDacStandard
7889 #define TMDS1EncoderControl TMDSAEncoderControl
7890 #define TMDS2EncoderControl LVTMAEncoderControl
7892 #define DFP1OutputControl TMDSAOutputControl
7893 #define DFP2OutputControl LVTMAOutputControl
7894 #define CRT1OutputControl DAC1OutputControl
7895 #define CRT2OutputControl DAC2OutputControl
7897 //These two lines will be removed for sure in a few days, will follow up with Michael V.
7898 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
7899 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
7901 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
7902 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7903 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7904 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7905 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
7907 #define ATOM_S6_ACC_REQ_TV2 0x00400000L
7908 #define ATOM_DEVICE_TV2_INDEX 0x00000006
7909 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
7910 #define ATOM_S0_TV2 0x00100000L
7911 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
7912 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
7915 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
7916 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
7917 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L
7918 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
7919 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
7920 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
7921 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L
7922 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
7923 #define ATOM_S2_CV_DPMS_STATE 0x01000000L
7924 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
7925 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L
7926 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L
7928 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01
7929 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02
7930 #define ATOM_S2_TV1_DPMS_STATEb2 0x04
7931 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08
7932 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10
7933 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20
7934 #define ATOM_S2_TV2_DPMS_STATEb2 0x40
7935 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80
7936 #define ATOM_S2_CV_DPMS_STATEb3 0x01
7937 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02
7938 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04
7939 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08
7941 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
7942 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
7943 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
7945 /*********************************************************************************/
7947 #pragma pack() // BIOS data must use byte aligment
7956 ULONG TableLength; //Length
7960 UCHAR OemTableId[8]; //UINT64 OemTableId;
7963 ULONG CreatorRevision;
7964 } AMD_ACPI_DESCRIPTION_HEADER;
7966 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
7968 UINT32 Signature; //0x0
7969 UINT32 Length; //0x4
7970 UINT8 Revision; //0x8
7971 UINT8 Checksum; //0x9
7972 UINT8 OemId[6]; //0xA
7973 UINT64 OemTableId; //0x10
7974 UINT32 OemRevision; //0x18
7975 UINT32 CreatorId; //0x1C
7976 UINT32 CreatorRevision; //0x20
7977 }EFI_ACPI_DESCRIPTION_HEADER;
7980 AMD_ACPI_DESCRIPTION_HEADER SHeader;
7981 UCHAR TableUUID[16]; //0x24
7982 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
7983 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
7984 ULONG Reserved[4]; //0x3C
7988 ULONG PCIBus; //0x4C
7989 ULONG PCIDevice; //0x50
7990 ULONG PCIFunction; //0x54
7991 USHORT VendorID; //0x58
7992 USHORT DeviceID; //0x5A
7993 USHORT SSVID; //0x5C
7995 ULONG Revision; //0x60
7996 ULONG ImageLength; //0x64
8001 VFCT_IMAGE_HEADER VbiosHeader;
8002 UCHAR VbiosContent[1];
8006 VFCT_IMAGE_HEADER Lib1Header;
8007 UCHAR Lib1Content[1];
8013 #endif /* _ATOMBIOS_H */