2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/drm_crtc_helper.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
34 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
38 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
43 if (rdev->family >= CHIP_R600)
44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
51 return backlight_level;
55 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
60 if (rdev->family >= CHIP_R600)
61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
67 ATOM_S2_CURRENT_BL_LEVEL_MASK);
69 if (rdev->family >= CHIP_R600)
70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
76 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
78 struct drm_device *dev = radeon_encoder->base.dev;
79 struct radeon_device *rdev = dev->dev_private;
81 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
84 return radeon_atom_get_backlight_level_from_reg(rdev);
88 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
90 struct drm_encoder *encoder = &radeon_encoder->base;
91 struct drm_device *dev = radeon_encoder->base.dev;
92 struct radeon_device *rdev = dev->dev_private;
93 struct radeon_encoder_atom_dig *dig;
94 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
97 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
100 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
101 radeon_encoder->enc_priv) {
102 dig = radeon_encoder->enc_priv;
103 dig->backlight_level = level;
104 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
106 switch (radeon_encoder->encoder_id) {
107 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
108 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
109 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
110 if (dig->backlight_level == 0) {
111 args.ucAction = ATOM_LCD_BLOFF;
112 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 args.ucAction = ATOM_LCD_BLON;
117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
124 if (dig->backlight_level == 0)
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
128 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
137 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
139 static u8 radeon_atom_bl_level(struct backlight_device *bd)
143 /* Convert brightness to hardware level */
144 if (bd->props.brightness < 0)
146 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
147 level = RADEON_MAX_BL_LEVEL;
149 level = bd->props.brightness;
154 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
156 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
157 struct radeon_encoder *radeon_encoder = pdata->encoder;
159 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
164 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
166 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
167 struct radeon_encoder *radeon_encoder = pdata->encoder;
168 struct drm_device *dev = radeon_encoder->base.dev;
169 struct radeon_device *rdev = dev->dev_private;
171 return radeon_atom_get_backlight_level_from_reg(rdev);
174 static const struct backlight_ops radeon_atom_backlight_ops = {
175 .get_brightness = radeon_atom_backlight_get_brightness,
176 .update_status = radeon_atom_backlight_update_status,
179 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
180 struct drm_connector *drm_connector)
182 struct drm_device *dev = radeon_encoder->base.dev;
183 struct radeon_device *rdev = dev->dev_private;
184 struct backlight_device *bd;
185 struct backlight_properties props;
186 struct radeon_backlight_privdata *pdata;
187 struct radeon_encoder_atom_dig *dig;
191 if (!radeon_encoder->enc_priv)
194 if (!rdev->is_atom_bios)
197 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
200 pdata = malloc(sizeof(struct radeon_backlight_privdata), DRM_MEM_DRIVER, M_NOWAIT);
202 DRM_ERROR("Memory allocation failed\n");
206 memset(&props, 0, sizeof(props));
207 props.max_brightness = RADEON_MAX_BL_LEVEL;
208 props.type = BACKLIGHT_RAW;
209 snprintf(bl_name, sizeof(bl_name),
210 "radeon_bl%d", dev->primary->index);
211 bd = backlight_device_register(bl_name, &drm_connector->kdev,
212 pdata, &radeon_atom_backlight_ops, &props);
214 DRM_ERROR("Backlight registration failed\n");
218 pdata->encoder = radeon_encoder;
220 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
222 dig = radeon_encoder->enc_priv;
225 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
226 bd->props.power = FB_BLANK_UNBLANK;
227 backlight_update_status(bd);
229 DRM_INFO("radeon atom DIG backlight initialized\n");
234 free(pdata, DRM_MEM_DRIVER);
238 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
240 struct drm_device *dev = radeon_encoder->base.dev;
241 struct radeon_device *rdev = dev->dev_private;
242 struct backlight_device *bd = NULL;
243 struct radeon_encoder_atom_dig *dig;
245 if (!radeon_encoder->enc_priv)
248 if (!rdev->is_atom_bios)
251 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
254 dig = radeon_encoder->enc_priv;
259 struct radeon_legacy_backlight_privdata *pdata;
261 pdata = bl_get_data(bd);
262 backlight_device_unregister(bd);
263 free(pdata, DRM_MEM_DRIVER);
265 DRM_INFO("radeon atom LVDS backlight unloaded\n");
269 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
271 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
272 struct drm_connector *drm_connector)
276 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
282 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
283 /* evil but including atombios.h is much worse */
284 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
285 struct drm_display_mode *mode);
289 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 switch (radeon_encoder->encoder_id) {
293 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
294 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
296 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
297 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
298 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
299 case ENCODER_OBJECT_ID_INTERNAL_DDI:
300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
310 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
311 const struct drm_display_mode *mode,
312 struct drm_display_mode *adjusted_mode)
314 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
315 struct drm_device *dev = encoder->dev;
316 struct radeon_device *rdev = dev->dev_private;
318 /* set the active encoder to connector routing */
319 radeon_encoder_set_active_device(encoder);
320 drm_mode_set_crtcinfo(adjusted_mode, 0);
323 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
324 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
325 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
327 /* get the native mode for LVDS */
328 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
329 radeon_panel_mode_fixup(encoder, adjusted_mode);
331 /* get the native mode for TV */
332 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
333 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
335 if (tv_dac->tv_std == TV_STD_NTSC ||
336 tv_dac->tv_std == TV_STD_NTSC_J ||
337 tv_dac->tv_std == TV_STD_PAL_M)
338 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
340 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
344 if (ASIC_IS_DCE3(rdev) &&
345 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
346 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
347 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
348 radeon_dp_set_link_config(connector, adjusted_mode);
355 atombios_dac_setup(struct drm_encoder *encoder, int action)
357 struct drm_device *dev = encoder->dev;
358 struct radeon_device *rdev = dev->dev_private;
359 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
360 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
362 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
364 memset(&args, 0, sizeof(args));
366 switch (radeon_encoder->encoder_id) {
367 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
369 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
371 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
373 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
377 args.ucAction = action;
379 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
380 args.ucDacStandard = ATOM_DAC1_PS2;
381 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
382 args.ucDacStandard = ATOM_DAC1_CV;
384 switch (dac_info->tv_std) {
387 case TV_STD_SCART_PAL:
390 args.ucDacStandard = ATOM_DAC1_PAL;
396 args.ucDacStandard = ATOM_DAC1_NTSC;
400 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
402 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
407 atombios_tv_setup(struct drm_encoder *encoder, int action)
409 struct drm_device *dev = encoder->dev;
410 struct radeon_device *rdev = dev->dev_private;
411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
412 TV_ENCODER_CONTROL_PS_ALLOCATION args;
414 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
416 memset(&args, 0, sizeof(args));
418 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
420 args.sTVEncoder.ucAction = action;
422 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
423 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
425 switch (dac_info->tv_std) {
427 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
439 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
441 case TV_STD_SCART_PAL:
442 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
445 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
448 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
451 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
456 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
462 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
464 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
468 bpc = radeon_get_monitor_bpc(connector);
472 return PANEL_BPC_UNDEFINE;
474 return PANEL_6BIT_PER_COLOR;
477 return PANEL_8BIT_PER_COLOR;
479 return PANEL_10BIT_PER_COLOR;
481 return PANEL_12BIT_PER_COLOR;
483 return PANEL_16BIT_PER_COLOR;
488 union dvo_encoder_control {
489 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
491 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
495 atombios_dvo_setup(struct drm_encoder *encoder, int action)
497 struct drm_device *dev = encoder->dev;
498 struct radeon_device *rdev = dev->dev_private;
499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
500 union dvo_encoder_control args;
501 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
504 memset(&args, 0, sizeof(args));
506 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
509 /* some R4xx chips have the wrong frev */
510 if (rdev->family <= CHIP_RV410)
518 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
520 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
521 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 args.dvo.sDVOEncoder.ucAction = action;
528 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
529 /* DFP1, CRT1, TV1 depending on the type of port */
530 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
532 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
533 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
537 args.dvo_v3.ucAction = action;
538 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
539 args.dvo_v3.ucDVOConfig = 0; /* XXX */
542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
547 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
551 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
554 union lvds_encoder_control {
555 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
556 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
560 atombios_digital_setup(struct drm_encoder *encoder, int action)
562 struct drm_device *dev = encoder->dev;
563 struct radeon_device *rdev = dev->dev_private;
564 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
565 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
566 union lvds_encoder_control args;
568 int hdmi_detected = 0;
574 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
577 memset(&args, 0, sizeof(args));
579 switch (radeon_encoder->encoder_id) {
580 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
581 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
583 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
585 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
587 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
589 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
591 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
595 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
604 args.v1.ucAction = action;
606 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
607 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
608 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
609 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
615 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
616 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
617 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 /*if (pScrn->rgbBits == 8) */
619 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
625 args.v2.ucAction = action;
627 if (dig->coherent_mode)
628 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
631 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
632 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
633 args.v2.ucTruncate = 0;
634 args.v2.ucSpatial = 0;
635 args.v2.ucTemporal = 0;
637 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
638 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
639 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
641 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
643 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
645 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
646 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
647 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
648 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
649 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
654 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
655 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
656 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
665 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
673 atombios_get_encoder_mode(struct drm_encoder *encoder)
675 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
676 struct drm_connector *connector;
677 struct radeon_connector *radeon_connector;
678 struct radeon_connector_atom_dig *dig_connector;
680 /* dp bridges are always DP */
681 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
682 return ATOM_ENCODER_MODE_DP;
684 /* DVO is always DVO */
685 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
686 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
687 return ATOM_ENCODER_MODE_DVO;
689 connector = radeon_get_connector_for_encoder(encoder);
690 /* if we don't have an active device yet, just use one of
691 * the connectors tied to the encoder.
694 connector = radeon_get_connector_for_encoder_init(encoder);
695 radeon_connector = to_radeon_connector(connector);
697 switch (connector->connector_type) {
698 case DRM_MODE_CONNECTOR_DVII:
699 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
700 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
702 return ATOM_ENCODER_MODE_HDMI;
703 else if (radeon_connector->use_digital)
704 return ATOM_ENCODER_MODE_DVI;
706 return ATOM_ENCODER_MODE_CRT;
708 case DRM_MODE_CONNECTOR_DVID:
709 case DRM_MODE_CONNECTOR_HDMIA:
711 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
713 return ATOM_ENCODER_MODE_HDMI;
715 return ATOM_ENCODER_MODE_DVI;
717 case DRM_MODE_CONNECTOR_LVDS:
718 return ATOM_ENCODER_MODE_LVDS;
720 case DRM_MODE_CONNECTOR_DisplayPort:
721 dig_connector = radeon_connector->con_priv;
722 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
723 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
724 return ATOM_ENCODER_MODE_DP;
725 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
727 return ATOM_ENCODER_MODE_HDMI;
729 return ATOM_ENCODER_MODE_DVI;
731 case DRM_MODE_CONNECTOR_eDP:
732 return ATOM_ENCODER_MODE_DP;
733 case DRM_MODE_CONNECTOR_DVIA:
734 case DRM_MODE_CONNECTOR_VGA:
735 return ATOM_ENCODER_MODE_CRT;
737 case DRM_MODE_CONNECTOR_Composite:
738 case DRM_MODE_CONNECTOR_SVIDEO:
739 case DRM_MODE_CONNECTOR_9PinDIN:
741 return ATOM_ENCODER_MODE_TV;
742 /*return ATOM_ENCODER_MODE_CV;*/
748 * DIG Encoder/Transmitter Setup
751 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
752 * Supports up to 3 digital outputs
753 * - 2 DIG encoder blocks.
754 * DIG1 can drive UNIPHY link A or link B
755 * DIG2 can drive UNIPHY link B or LVTMA
758 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
759 * Supports up to 5 digital outputs
760 * - 2 DIG encoder blocks.
761 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 6 DIG encoder blocks.
767 * - DIG to PHY mapping is hardcoded
768 * DIG1 drives UNIPHY0 link A, A+B
769 * DIG2 drives UNIPHY0 link B
770 * DIG3 drives UNIPHY1 link A, A+B
771 * DIG4 drives UNIPHY1 link B
772 * DIG5 drives UNIPHY2 link A, A+B
773 * DIG6 drives UNIPHY2 link B
776 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
777 * Supports up to 6 digital outputs
778 * - 2 DIG encoder blocks.
780 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
782 * DIG1 drives UNIPHY0/1/2 link A
783 * DIG2 drives UNIPHY0/1/2 link B
786 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
788 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
789 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
790 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
791 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
794 union dig_encoder_control {
795 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
796 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
797 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
798 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
802 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
804 struct drm_device *dev = encoder->dev;
805 struct radeon_device *rdev = dev->dev_private;
806 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
807 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
808 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
809 union dig_encoder_control args;
813 int dp_lane_count = 0;
814 int hpd_id = RADEON_HPD_NONE;
817 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
818 struct radeon_connector_atom_dig *dig_connector =
819 radeon_connector->con_priv;
821 dp_clock = dig_connector->dp_clock;
822 dp_lane_count = dig_connector->dp_lane_count;
823 hpd_id = radeon_connector->hpd.hpd;
826 /* no dig encoder assigned */
827 if (dig->dig_encoder == -1)
830 memset(&args, 0, sizeof(args));
832 if (ASIC_IS_DCE4(rdev))
833 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
835 if (dig->dig_encoder)
836 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
838 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
848 args.v1.ucAction = action;
849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
850 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
851 args.v3.ucPanelMode = panel_mode;
853 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
855 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
856 args.v1.ucLaneNum = dp_lane_count;
857 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
858 args.v1.ucLaneNum = 8;
860 args.v1.ucLaneNum = 4;
862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
863 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
864 switch (radeon_encoder->encoder_id) {
865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
866 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
870 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
883 args.v3.ucAction = action;
884 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
885 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
886 args.v3.ucPanelMode = panel_mode;
888 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
890 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
891 args.v3.ucLaneNum = dp_lane_count;
892 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
893 args.v3.ucLaneNum = 8;
895 args.v3.ucLaneNum = 4;
897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
899 args.v3.acConfig.ucDigSel = dig->dig_encoder;
900 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
903 args.v4.ucAction = action;
904 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
905 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
906 args.v4.ucPanelMode = panel_mode;
908 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
910 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
911 args.v4.ucLaneNum = dp_lane_count;
912 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
913 args.v4.ucLaneNum = 8;
915 args.v4.ucLaneNum = 4;
917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
918 if (dp_clock == 270000)
919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
920 else if (dp_clock == 540000)
921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
923 args.v4.acConfig.ucDigSel = dig->dig_encoder;
924 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
925 if (hpd_id == RADEON_HPD_NONE)
926 args.v4.ucHPD_ID = 0;
928 args.v4.ucHPD_ID = hpd_id + 1;
931 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
936 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
944 union dig_transmitter_control {
945 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
946 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
947 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
948 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
949 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
953 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
955 struct drm_device *dev = encoder->dev;
956 struct radeon_device *rdev = dev->dev_private;
957 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
959 struct drm_connector *connector;
960 union dig_transmitter_control args;
966 int dp_lane_count = 0;
967 int connector_object_id = 0;
968 int igp_lane_info = 0;
969 int dig_encoder = dig->dig_encoder;
970 int hpd_id = RADEON_HPD_NONE;
972 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
973 connector = radeon_get_connector_for_encoder_init(encoder);
974 /* just needed to avoid bailing in the encoder check. the encoder
975 * isn't used for init
979 connector = radeon_get_connector_for_encoder(encoder);
982 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
983 struct radeon_connector_atom_dig *dig_connector =
984 radeon_connector->con_priv;
986 hpd_id = radeon_connector->hpd.hpd;
987 dp_clock = dig_connector->dp_clock;
988 dp_lane_count = dig_connector->dp_lane_count;
989 connector_object_id =
990 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
991 igp_lane_info = dig_connector->igp_lane_info;
995 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
996 pll_id = radeon_crtc->pll_id;
999 /* no dig encoder assigned */
1000 if (dig_encoder == -1)
1003 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1006 memset(&args, 0, sizeof(args));
1008 switch (radeon_encoder->encoder_id) {
1009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1010 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1015 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1017 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1018 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1022 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1029 args.v1.ucAction = action;
1030 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1031 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1032 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1033 args.v1.asMode.ucLaneSel = lane_num;
1034 args.v1.asMode.ucLaneSet = lane_set;
1037 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1038 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1039 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1041 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1044 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1047 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1049 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1051 if ((rdev->flags & RADEON_IS_IGP) &&
1052 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1054 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1055 if (igp_lane_info & 0x1)
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1057 else if (igp_lane_info & 0x2)
1058 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1059 else if (igp_lane_info & 0x4)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1061 else if (igp_lane_info & 0x8)
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1064 if (igp_lane_info & 0x3)
1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1066 else if (igp_lane_info & 0xc)
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1078 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1079 if (dig->coherent_mode)
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1081 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1086 args.v2.ucAction = action;
1087 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1088 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1089 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1090 args.v2.asMode.ucLaneSel = lane_num;
1091 args.v2.asMode.ucLaneSet = lane_set;
1094 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1095 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1096 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1098 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1101 args.v2.acConfig.ucEncoderSel = dig_encoder;
1103 args.v2.acConfig.ucLinkSel = 1;
1105 switch (radeon_encoder->encoder_id) {
1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1107 args.v2.acConfig.ucTransmitterSel = 0;
1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1110 args.v2.acConfig.ucTransmitterSel = 1;
1112 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1113 args.v2.acConfig.ucTransmitterSel = 2;
1118 args.v2.acConfig.fCoherentMode = 1;
1119 args.v2.acConfig.fDPConnector = 1;
1120 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1121 if (dig->coherent_mode)
1122 args.v2.acConfig.fCoherentMode = 1;
1123 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1124 args.v2.acConfig.fDualLinkConnector = 1;
1128 args.v3.ucAction = action;
1129 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1130 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1131 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1132 args.v3.asMode.ucLaneSel = lane_num;
1133 args.v3.asMode.ucLaneSet = lane_set;
1136 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1137 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1138 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1140 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1144 args.v3.ucLaneNum = dp_lane_count;
1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1146 args.v3.ucLaneNum = 8;
1148 args.v3.ucLaneNum = 4;
1151 args.v3.acConfig.ucLinkSel = 1;
1152 if (dig_encoder & 1)
1153 args.v3.acConfig.ucEncoderSel = 1;
1155 /* Select the PLL for the PHY
1156 * DP PHY should be clocked from external src if there is
1159 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1160 if (is_dp && rdev->clock.dp_extclk)
1161 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1163 args.v3.acConfig.ucRefClkSource = pll_id;
1165 switch (radeon_encoder->encoder_id) {
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1167 args.v3.acConfig.ucTransmitterSel = 0;
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1170 args.v3.acConfig.ucTransmitterSel = 1;
1172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1173 args.v3.acConfig.ucTransmitterSel = 2;
1178 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1179 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1180 if (dig->coherent_mode)
1181 args.v3.acConfig.fCoherentMode = 1;
1182 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1183 args.v3.acConfig.fDualLinkConnector = 1;
1187 args.v4.ucAction = action;
1188 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1189 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1190 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1191 args.v4.asMode.ucLaneSel = lane_num;
1192 args.v4.asMode.ucLaneSet = lane_set;
1195 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1196 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1197 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1199 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1203 args.v4.ucLaneNum = dp_lane_count;
1204 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1205 args.v4.ucLaneNum = 8;
1207 args.v4.ucLaneNum = 4;
1210 args.v4.acConfig.ucLinkSel = 1;
1211 if (dig_encoder & 1)
1212 args.v4.acConfig.ucEncoderSel = 1;
1214 /* Select the PLL for the PHY
1215 * DP PHY should be clocked from external src if there is
1218 /* On DCE5 DCPLL usually generates the DP ref clock */
1220 if (rdev->clock.dp_extclk)
1221 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1223 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1225 args.v4.acConfig.ucRefClkSource = pll_id;
1227 switch (radeon_encoder->encoder_id) {
1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1229 args.v4.acConfig.ucTransmitterSel = 0;
1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1232 args.v4.acConfig.ucTransmitterSel = 1;
1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1235 args.v4.acConfig.ucTransmitterSel = 2;
1240 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1241 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1242 if (dig->coherent_mode)
1243 args.v4.acConfig.fCoherentMode = 1;
1244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1245 args.v4.acConfig.fDualLinkConnector = 1;
1249 args.v5.ucAction = action;
1251 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1253 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1255 switch (radeon_encoder->encoder_id) {
1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1272 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1276 args.v5.ucLaneNum = dp_lane_count;
1277 else if (radeon_encoder->pixel_clock > 165000)
1278 args.v5.ucLaneNum = 8;
1280 args.v5.ucLaneNum = 4;
1281 args.v5.ucConnObjId = connector_object_id;
1282 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1284 if (is_dp && rdev->clock.dp_extclk)
1285 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1287 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1290 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1291 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1292 if (dig->coherent_mode)
1293 args.v5.asConfig.ucCoherentMode = 1;
1295 if (hpd_id == RADEON_HPD_NONE)
1296 args.v5.asConfig.ucHPDSel = 0;
1298 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1299 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1300 args.v5.ucDPLaneSet = lane_set;
1303 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1308 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1312 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1316 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1318 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1319 struct drm_device *dev = radeon_connector->base.dev;
1320 struct radeon_device *rdev = dev->dev_private;
1321 union dig_transmitter_control args;
1322 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1325 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1328 if (!ASIC_IS_DCE4(rdev))
1331 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1332 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1335 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1338 memset(&args, 0, sizeof(args));
1340 args.v1.ucAction = action;
1342 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1344 /* wait for the panel to power up */
1345 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1348 for (i = 0; i < 300; i++) {
1349 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1359 union external_encoder_control {
1360 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1361 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1365 atombios_external_encoder_setup(struct drm_encoder *encoder,
1366 struct drm_encoder *ext_encoder,
1369 struct drm_device *dev = encoder->dev;
1370 struct radeon_device *rdev = dev->dev_private;
1371 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1372 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1373 union external_encoder_control args;
1374 struct drm_connector *connector;
1375 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1378 int dp_lane_count = 0;
1379 int connector_object_id = 0;
1380 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1382 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1383 connector = radeon_get_connector_for_encoder_init(encoder);
1385 connector = radeon_get_connector_for_encoder(encoder);
1388 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1389 struct radeon_connector_atom_dig *dig_connector =
1390 radeon_connector->con_priv;
1392 dp_clock = dig_connector->dp_clock;
1393 dp_lane_count = dig_connector->dp_lane_count;
1394 connector_object_id =
1395 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1398 memset(&args, 0, sizeof(args));
1400 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1405 /* no params on frev 1 */
1411 args.v1.sDigEncoder.ucAction = action;
1412 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1413 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1415 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1416 if (dp_clock == 270000)
1417 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1418 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1419 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1420 args.v1.sDigEncoder.ucLaneNum = 8;
1422 args.v1.sDigEncoder.ucLaneNum = 4;
1425 args.v3.sExtEncoder.ucAction = action;
1426 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1427 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1429 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1430 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1432 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1433 if (dp_clock == 270000)
1434 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1435 else if (dp_clock == 540000)
1436 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1437 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1438 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1439 args.v3.sExtEncoder.ucLaneNum = 8;
1441 args.v3.sExtEncoder.ucLaneNum = 4;
1443 case GRAPH_OBJECT_ENUM_ID1:
1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1446 case GRAPH_OBJECT_ENUM_ID2:
1447 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1449 case GRAPH_OBJECT_ENUM_ID3:
1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1453 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1456 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1461 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1468 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1470 struct drm_device *dev = encoder->dev;
1471 struct radeon_device *rdev = dev->dev_private;
1472 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1473 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1474 ENABLE_YUV_PS_ALLOCATION args;
1475 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1478 memset(&args, 0, sizeof(args));
1480 if (rdev->family >= CHIP_R600)
1481 reg = R600_BIOS_3_SCRATCH;
1483 reg = RADEON_BIOS_3_SCRATCH;
1485 /* XXX: fix up scratch reg handling */
1487 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1488 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1489 (radeon_crtc->crtc_id << 18)));
1490 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1491 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1496 args.ucEnable = ATOM_ENABLE;
1497 args.ucCRTC = radeon_crtc->crtc_id;
1499 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1505 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1507 struct drm_device *dev = encoder->dev;
1508 struct radeon_device *rdev = dev->dev_private;
1509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1510 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1513 memset(&args, 0, sizeof(args));
1515 switch (radeon_encoder->encoder_id) {
1516 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1518 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1520 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1521 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1522 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1523 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1525 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1526 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1528 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1529 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1530 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1532 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1534 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1536 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1537 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1538 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1539 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1541 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1543 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1545 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1546 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1547 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1548 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1550 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1557 case DRM_MODE_DPMS_ON:
1558 args.ucAction = ATOM_ENABLE;
1559 /* workaround for DVOOutputControl on some RS690 systems */
1560 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1561 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1562 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1564 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1567 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1568 args.ucAction = ATOM_LCD_BLON;
1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1572 case DRM_MODE_DPMS_STANDBY:
1573 case DRM_MODE_DPMS_SUSPEND:
1574 case DRM_MODE_DPMS_OFF:
1575 args.ucAction = ATOM_DISABLE;
1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1577 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1578 args.ucAction = ATOM_LCD_BLOFF;
1579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1586 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1588 struct drm_device *dev = encoder->dev;
1589 struct radeon_device *rdev = dev->dev_private;
1590 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1591 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1592 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1593 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1594 struct radeon_connector *radeon_connector = NULL;
1595 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1598 radeon_connector = to_radeon_connector(connector);
1599 radeon_dig_connector = radeon_connector->con_priv;
1603 case DRM_MODE_DPMS_ON:
1604 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1606 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1608 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1610 /* setup and enable the encoder */
1611 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1612 atombios_dig_encoder_setup(encoder,
1613 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1616 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1617 atombios_external_encoder_setup(encoder, ext_encoder,
1618 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1621 } else if (ASIC_IS_DCE4(rdev)) {
1622 /* setup and enable the encoder */
1623 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1624 /* enable the transmitter */
1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1628 /* setup and enable the encoder and transmitter */
1629 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1630 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1631 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1632 /* some early dce3.2 boards have a bug in their transmitter control table */
1633 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1634 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1636 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1637 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1638 atombios_set_edp_panel_power(connector,
1639 ATOM_TRANSMITTER_ACTION_POWER_ON);
1640 radeon_dig_connector->edp_on = true;
1642 radeon_dp_link_train(encoder, connector);
1643 if (ASIC_IS_DCE4(rdev))
1644 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1646 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1647 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1649 case DRM_MODE_DPMS_STANDBY:
1650 case DRM_MODE_DPMS_SUSPEND:
1651 case DRM_MODE_DPMS_OFF:
1652 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1653 /* disable the transmitter */
1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1655 } else if (ASIC_IS_DCE4(rdev)) {
1656 /* disable the transmitter */
1657 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1660 /* disable the encoder and transmitter */
1661 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1662 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1663 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1665 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1666 if (ASIC_IS_DCE4(rdev))
1667 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1668 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1669 atombios_set_edp_panel_power(connector,
1670 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1671 radeon_dig_connector->edp_on = false;
1674 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1675 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1681 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1682 struct drm_encoder *ext_encoder,
1685 struct drm_device *dev = encoder->dev;
1686 struct radeon_device *rdev = dev->dev_private;
1689 case DRM_MODE_DPMS_ON:
1691 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1692 atombios_external_encoder_setup(encoder, ext_encoder,
1693 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1694 atombios_external_encoder_setup(encoder, ext_encoder,
1695 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1697 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1699 case DRM_MODE_DPMS_STANDBY:
1700 case DRM_MODE_DPMS_SUSPEND:
1701 case DRM_MODE_DPMS_OFF:
1702 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1703 atombios_external_encoder_setup(encoder, ext_encoder,
1704 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1705 atombios_external_encoder_setup(encoder, ext_encoder,
1706 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1708 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1714 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1716 struct drm_device *dev = encoder->dev;
1717 struct radeon_device *rdev = dev->dev_private;
1718 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1719 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1721 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1722 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1723 radeon_encoder->active_device);
1724 switch (radeon_encoder->encoder_id) {
1725 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1727 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1728 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1729 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1730 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1731 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1733 radeon_atom_encoder_dpms_avivo(encoder, mode);
1735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1739 radeon_atom_encoder_dpms_dig(encoder, mode);
1741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1742 if (ASIC_IS_DCE5(rdev)) {
1744 case DRM_MODE_DPMS_ON:
1745 atombios_dvo_setup(encoder, ATOM_ENABLE);
1747 case DRM_MODE_DPMS_STANDBY:
1748 case DRM_MODE_DPMS_SUSPEND:
1749 case DRM_MODE_DPMS_OFF:
1750 atombios_dvo_setup(encoder, ATOM_DISABLE);
1753 } else if (ASIC_IS_DCE3(rdev))
1754 radeon_atom_encoder_dpms_dig(encoder, mode);
1756 radeon_atom_encoder_dpms_avivo(encoder, mode);
1758 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1760 if (ASIC_IS_DCE5(rdev)) {
1762 case DRM_MODE_DPMS_ON:
1763 atombios_dac_setup(encoder, ATOM_ENABLE);
1765 case DRM_MODE_DPMS_STANDBY:
1766 case DRM_MODE_DPMS_SUSPEND:
1767 case DRM_MODE_DPMS_OFF:
1768 atombios_dac_setup(encoder, ATOM_DISABLE);
1772 radeon_atom_encoder_dpms_avivo(encoder, mode);
1779 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1781 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1785 union crtc_source_param {
1786 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1787 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1791 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1793 struct drm_device *dev = encoder->dev;
1794 struct radeon_device *rdev = dev->dev_private;
1795 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1796 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1797 union crtc_source_param args;
1798 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1800 struct radeon_encoder_atom_dig *dig;
1802 memset(&args, 0, sizeof(args));
1804 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1812 if (ASIC_IS_AVIVO(rdev))
1813 args.v1.ucCRTC = radeon_crtc->crtc_id;
1815 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1816 args.v1.ucCRTC = radeon_crtc->crtc_id;
1818 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1821 switch (radeon_encoder->encoder_id) {
1822 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1824 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1826 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1827 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1828 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1829 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1831 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1833 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1834 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1836 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1838 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1840 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1841 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1842 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1843 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1845 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1847 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1849 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1850 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1851 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1852 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1854 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1859 args.v2.ucCRTC = radeon_crtc->crtc_id;
1860 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1861 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1863 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1864 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1865 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1866 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1868 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1870 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1871 switch (radeon_encoder->encoder_id) {
1872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1876 dig = radeon_encoder->enc_priv;
1877 switch (dig->dig_encoder) {
1879 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1882 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1885 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1888 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1891 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1894 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1899 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1902 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1903 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1904 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1905 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1907 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1909 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1910 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1911 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1912 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1913 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1915 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1922 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1928 /* update scratch regs with new routing */
1929 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1933 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1934 struct drm_display_mode *mode)
1936 struct drm_device *dev = encoder->dev;
1937 struct radeon_device *rdev = dev->dev_private;
1938 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1939 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1941 /* Funky macbooks */
1942 if ((dev->pci_device == 0x71C5) &&
1943 (dev->pci_subvendor == 0x106b) &&
1944 (dev->pci_subdevice == 0x0080)) {
1945 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1946 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1948 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1949 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1951 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1955 /* set scaler clears this on some chips */
1956 if (ASIC_IS_AVIVO(rdev) &&
1957 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1958 if (ASIC_IS_DCE4(rdev)) {
1959 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1960 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1961 EVERGREEN_INTERLEAVE_EN);
1963 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1965 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1966 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1967 AVIVO_D1MODE_INTERLEAVE_EN);
1969 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1974 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1976 struct drm_device *dev = encoder->dev;
1977 struct radeon_device *rdev = dev->dev_private;
1978 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1979 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1980 struct drm_encoder *test_encoder;
1981 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1982 uint32_t dig_enc_in_use = 0;
1984 if (ASIC_IS_DCE6(rdev)) {
1986 switch (radeon_encoder->encoder_id) {
1987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2006 } else if (ASIC_IS_DCE4(rdev)) {
2008 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2009 /* ontario follows DCE4 */
2010 if (rdev->family == CHIP_PALM) {
2016 /* llano follows DCE3.2 */
2017 return radeon_crtc->crtc_id;
2019 switch (radeon_encoder->encoder_id) {
2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2042 /* on DCE32 and encoder can driver any block so just crtc id */
2043 if (ASIC_IS_DCE32(rdev)) {
2044 return radeon_crtc->crtc_id;
2047 /* on DCE3 - LVTMA can only be driven by DIGB */
2048 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2049 struct radeon_encoder *radeon_test_encoder;
2051 if (encoder == test_encoder)
2054 if (!radeon_encoder_is_digital(test_encoder))
2057 radeon_test_encoder = to_radeon_encoder(test_encoder);
2058 dig = radeon_test_encoder->enc_priv;
2060 if (dig->dig_encoder >= 0)
2061 dig_enc_in_use |= (1 << dig->dig_encoder);
2064 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2065 if (dig_enc_in_use & 0x2)
2066 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2069 if (!(dig_enc_in_use & 1))
2074 /* This only needs to be called once at startup */
2076 radeon_atom_encoder_init(struct radeon_device *rdev)
2078 struct drm_device *dev = rdev->ddev;
2079 struct drm_encoder *encoder;
2081 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2082 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2083 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2085 switch (radeon_encoder->encoder_id) {
2086 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2087 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2089 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2090 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2096 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2097 atombios_external_encoder_setup(encoder, ext_encoder,
2098 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2103 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2104 struct drm_display_mode *mode,
2105 struct drm_display_mode *adjusted_mode)
2107 struct drm_device *dev = encoder->dev;
2108 struct radeon_device *rdev = dev->dev_private;
2109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2111 radeon_encoder->pixel_clock = adjusted_mode->clock;
2113 /* need to call this here rather than in prepare() since we need some crtc info */
2114 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2116 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2117 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2118 atombios_yuv_setup(encoder, true);
2120 atombios_yuv_setup(encoder, false);
2123 switch (radeon_encoder->encoder_id) {
2124 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2126 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2127 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2128 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2133 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2134 /* handled in dpms */
2136 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2137 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2139 atombios_dvo_setup(encoder, ATOM_ENABLE);
2141 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2143 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2145 atombios_dac_setup(encoder, ATOM_ENABLE);
2146 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2147 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2148 atombios_tv_setup(encoder, ATOM_ENABLE);
2150 atombios_tv_setup(encoder, ATOM_DISABLE);
2155 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2157 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2158 r600_hdmi_enable(encoder);
2159 if (ASIC_IS_DCE6(rdev))
2160 ; /* TODO (use pointers instead of if-s?) */
2161 else if (ASIC_IS_DCE4(rdev))
2162 evergreen_hdmi_setmode(encoder, adjusted_mode);
2164 r600_hdmi_setmode(encoder, adjusted_mode);
2169 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2171 struct drm_device *dev = encoder->dev;
2172 struct radeon_device *rdev = dev->dev_private;
2173 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2174 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2176 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2177 ATOM_DEVICE_CV_SUPPORT |
2178 ATOM_DEVICE_CRT_SUPPORT)) {
2179 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2180 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2183 memset(&args, 0, sizeof(args));
2185 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2188 args.sDacload.ucMisc = 0;
2190 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2191 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2192 args.sDacload.ucDacType = ATOM_DAC_A;
2194 args.sDacload.ucDacType = ATOM_DAC_B;
2196 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2197 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2198 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2199 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2200 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2201 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2203 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2204 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2205 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2207 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2217 static enum drm_connector_status
2218 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2220 struct drm_device *dev = encoder->dev;
2221 struct radeon_device *rdev = dev->dev_private;
2222 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2223 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2224 uint32_t bios_0_scratch;
2226 if (!atombios_dac_load_detect(encoder, connector)) {
2227 DRM_DEBUG_KMS("detect returned false \n");
2228 return connector_status_unknown;
2231 if (rdev->family >= CHIP_R600)
2232 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2234 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2236 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2237 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2238 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2239 return connector_status_connected;
2241 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2242 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2243 return connector_status_connected;
2245 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2246 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2247 return connector_status_connected;
2249 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2250 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2251 return connector_status_connected; /* CTV */
2252 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2253 return connector_status_connected; /* STV */
2255 return connector_status_disconnected;
2258 static enum drm_connector_status
2259 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2261 struct drm_device *dev = encoder->dev;
2262 struct radeon_device *rdev = dev->dev_private;
2263 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2264 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2265 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2268 if (!ASIC_IS_DCE4(rdev))
2269 return connector_status_unknown;
2272 return connector_status_unknown;
2274 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2275 return connector_status_unknown;
2277 /* load detect on the dp bridge */
2278 atombios_external_encoder_setup(encoder, ext_encoder,
2279 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2281 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2283 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2284 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2285 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2286 return connector_status_connected;
2288 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2289 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2290 return connector_status_connected;
2292 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2293 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2294 return connector_status_connected;
2296 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2297 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2298 return connector_status_connected; /* CTV */
2299 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2300 return connector_status_connected; /* STV */
2302 return connector_status_disconnected;
2306 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2308 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2311 /* ddc_setup on the dp bridge */
2312 atombios_external_encoder_setup(encoder, ext_encoder,
2313 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2317 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2319 struct radeon_device *rdev = encoder->dev->dev_private;
2320 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2321 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2323 if ((radeon_encoder->active_device &
2324 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2325 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2326 ENCODER_OBJECT_ID_NONE)) {
2327 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2329 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2330 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2331 if (rdev->family >= CHIP_R600)
2332 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2334 /* RS600/690/740 have only 1 afmt block */
2335 dig->afmt = rdev->mode_info.afmt[0];
2340 radeon_atom_output_lock(encoder, true);
2343 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2345 /* select the clock/data port if it uses a router */
2346 if (radeon_connector->router.cd_valid)
2347 radeon_router_select_cd_port(radeon_connector);
2349 /* turn eDP panel on for mode set */
2350 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2351 atombios_set_edp_panel_power(connector,
2352 ATOM_TRANSMITTER_ACTION_POWER_ON);
2355 /* this is needed for the pll/ss setup to work correctly in some cases */
2356 atombios_set_encoder_crtc_source(encoder);
2359 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2361 /* need to call this here as we need the crtc set up */
2362 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2363 radeon_atom_output_lock(encoder, false);
2366 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2368 struct drm_device *dev = encoder->dev;
2369 struct radeon_device *rdev = dev->dev_private;
2370 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2371 struct radeon_encoder_atom_dig *dig;
2373 /* check for pre-DCE3 cards with shared encoders;
2374 * can't really use the links individually, so don't disable
2375 * the encoder if it's in use by another connector
2377 if (!ASIC_IS_DCE3(rdev)) {
2378 struct drm_encoder *other_encoder;
2379 struct radeon_encoder *other_radeon_encoder;
2381 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2382 other_radeon_encoder = to_radeon_encoder(other_encoder);
2383 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2384 drm_helper_encoder_in_use(other_encoder))
2389 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2391 switch (radeon_encoder->encoder_id) {
2392 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2394 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2395 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2396 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2398 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2399 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2400 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2402 /* handled in dpms */
2404 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2405 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2407 atombios_dvo_setup(encoder, ATOM_DISABLE);
2409 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2410 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2411 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2413 atombios_dac_setup(encoder, ATOM_DISABLE);
2414 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2415 atombios_tv_setup(encoder, ATOM_DISABLE);
2420 if (radeon_encoder_is_digital(encoder)) {
2421 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2422 r600_hdmi_disable(encoder);
2423 dig = radeon_encoder->enc_priv;
2424 dig->dig_encoder = -1;
2426 radeon_encoder->active_device = 0;
2429 /* these are handled by the primary encoders */
2430 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2435 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2441 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2442 struct drm_display_mode *mode,
2443 struct drm_display_mode *adjusted_mode)
2448 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2454 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2459 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2460 const struct drm_display_mode *mode,
2461 struct drm_display_mode *adjusted_mode)
2466 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2467 .dpms = radeon_atom_ext_dpms,
2468 .mode_fixup = radeon_atom_ext_mode_fixup,
2469 .prepare = radeon_atom_ext_prepare,
2470 .mode_set = radeon_atom_ext_mode_set,
2471 .commit = radeon_atom_ext_commit,
2472 .disable = radeon_atom_ext_disable,
2473 /* no detect for TMDS/LVDS yet */
2476 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2477 .dpms = radeon_atom_encoder_dpms,
2478 .mode_fixup = radeon_atom_mode_fixup,
2479 .prepare = radeon_atom_encoder_prepare,
2480 .mode_set = radeon_atom_encoder_mode_set,
2481 .commit = radeon_atom_encoder_commit,
2482 .disable = radeon_atom_encoder_disable,
2483 .detect = radeon_atom_dig_detect,
2486 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2487 .dpms = radeon_atom_encoder_dpms,
2488 .mode_fixup = radeon_atom_mode_fixup,
2489 .prepare = radeon_atom_encoder_prepare,
2490 .mode_set = radeon_atom_encoder_mode_set,
2491 .commit = radeon_atom_encoder_commit,
2492 .detect = radeon_atom_dac_detect,
2495 void radeon_enc_destroy(struct drm_encoder *encoder)
2497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2498 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2499 radeon_atom_backlight_exit(radeon_encoder);
2500 free(radeon_encoder->enc_priv, DRM_MEM_DRIVER);
2501 drm_encoder_cleanup(encoder);
2502 free(radeon_encoder, DRM_MEM_DRIVER);
2505 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2506 .destroy = radeon_enc_destroy,
2509 static struct radeon_encoder_atom_dac *
2510 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2512 struct drm_device *dev = radeon_encoder->base.dev;
2513 struct radeon_device *rdev = dev->dev_private;
2514 struct radeon_encoder_atom_dac *dac = malloc(sizeof(struct radeon_encoder_atom_dac),
2515 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2520 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2524 static struct radeon_encoder_atom_dig *
2525 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2527 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2528 struct radeon_encoder_atom_dig *dig = malloc(sizeof(struct radeon_encoder_atom_dig),
2529 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2534 /* coherent mode by default */
2535 dig->coherent_mode = true;
2536 dig->dig_encoder = -1;
2538 if (encoder_enum == 2)
2547 radeon_add_atom_encoder(struct drm_device *dev,
2548 uint32_t encoder_enum,
2549 uint32_t supported_device,
2552 struct radeon_device *rdev = dev->dev_private;
2553 struct drm_encoder *encoder;
2554 struct radeon_encoder *radeon_encoder;
2556 /* see if we already added it */
2557 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2558 radeon_encoder = to_radeon_encoder(encoder);
2559 if (radeon_encoder->encoder_enum == encoder_enum) {
2560 radeon_encoder->devices |= supported_device;
2567 radeon_encoder = malloc(sizeof(struct radeon_encoder),
2568 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2569 if (!radeon_encoder)
2572 encoder = &radeon_encoder->base;
2573 switch (rdev->num_crtc) {
2575 encoder->possible_crtcs = 0x1;
2579 encoder->possible_crtcs = 0x3;
2582 encoder->possible_crtcs = 0xf;
2585 encoder->possible_crtcs = 0x3f;
2589 radeon_encoder->enc_priv = NULL;
2591 radeon_encoder->encoder_enum = encoder_enum;
2592 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2593 radeon_encoder->devices = supported_device;
2594 radeon_encoder->rmx_type = RMX_OFF;
2595 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2596 radeon_encoder->is_ext_encoder = false;
2597 radeon_encoder->caps = caps;
2599 switch (radeon_encoder->encoder_id) {
2600 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2601 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2603 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2604 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2605 radeon_encoder->rmx_type = RMX_FULL;
2606 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2607 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2609 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2610 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2612 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2614 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2615 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2616 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2617 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2619 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2620 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2621 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2622 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2623 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2624 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2626 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2628 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2634 radeon_encoder->rmx_type = RMX_FULL;
2635 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2636 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2637 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2639 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2641 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2642 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2644 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2646 case ENCODER_OBJECT_ID_SI170B:
2647 case ENCODER_OBJECT_ID_CH7303:
2648 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2649 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2650 case ENCODER_OBJECT_ID_TITFP513:
2651 case ENCODER_OBJECT_ID_VT1623:
2652 case ENCODER_OBJECT_ID_HDMI_SI1930:
2653 case ENCODER_OBJECT_ID_TRAVIS:
2654 case ENCODER_OBJECT_ID_NUTMEG:
2655 /* these are handled by the primary encoders */
2656 radeon_encoder->is_ext_encoder = true;
2657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2658 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2659 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2660 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2662 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2663 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);