2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
32 #include "radeon_reg.h"
33 #include "radeon_asic.h"
37 * check if enc_priv stores radeon_encoder_atom_dig
39 static bool radeon_dig_encoder(struct drm_encoder *encoder)
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60 * check if the chipset is supported
62 static int r600_audio_chipset_supported(struct radeon_device *rdev)
64 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
65 || rdev->family == CHIP_RS600
66 || rdev->family == CHIP_RS690
67 || rdev->family == CHIP_RS740;
70 struct r600_audio r600_audio_status(struct radeon_device *rdev)
72 struct r600_audio status;
75 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
77 /* number of channels */
78 status.channels = (value & 0x7) + 1;
81 switch ((value & 0xF0) >> 4) {
83 status.bits_per_sample = 8;
86 status.bits_per_sample = 16;
89 status.bits_per_sample = 20;
92 status.bits_per_sample = 24;
95 status.bits_per_sample = 32;
98 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
100 status.bits_per_sample = 16;
103 /* current sampling rate in HZ */
108 status.rate *= ((value >> 11) & 0x7) + 1;
109 status.rate /= ((value >> 8) & 0x7) + 1;
111 value = RREG32(R600_AUDIO_STATUS_BITS);
113 /* iec 60958 status bits */
114 status.status_bits = value & 0xff;
116 /* iec 60958 category code */
117 status.category_code = (value >> 8) & 0xff;
123 * update all hdmi interfaces with current audio parameters
125 void r600_audio_update_hdmi(void *arg, int pending)
127 struct radeon_device *rdev = arg;
128 struct drm_device *dev = rdev->ddev;
129 struct r600_audio audio_status = r600_audio_status(rdev);
130 struct drm_encoder *encoder;
131 bool changed = false;
133 if (rdev->audio_status.channels != audio_status.channels ||
134 rdev->audio_status.rate != audio_status.rate ||
135 rdev->audio_status.bits_per_sample != audio_status.bits_per_sample ||
136 rdev->audio_status.status_bits != audio_status.status_bits ||
137 rdev->audio_status.category_code != audio_status.category_code) {
138 rdev->audio_status = audio_status;
142 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
143 if (!radeon_dig_encoder(encoder))
145 if (changed || r600_hdmi_buffer_status_changed(encoder))
146 r600_hdmi_update_audio_settings(encoder);
151 * turn on/off audio engine
153 static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable)
156 DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling");
157 if (ASIC_IS_DCE4(rdev)) {
159 value |= 0x81000000; /* Required to enable audio */
160 value |= 0x0e1000f0; /* fglrx sets that too */
162 WREG32(EVERGREEN_AUDIO_ENABLE, value);
164 WREG32_P(R600_AUDIO_ENABLE,
165 enable ? 0x81000000 : 0x0, ~0x81000000);
167 rdev->audio_enabled = enable;
171 * initialize the audio vars
173 int r600_audio_init(struct radeon_device *rdev)
175 if (!radeon_audio || !r600_audio_chipset_supported(rdev))
178 r600_audio_engine_enable(rdev, true);
180 rdev->audio_status.channels = -1;
181 rdev->audio_status.rate = -1;
182 rdev->audio_status.bits_per_sample = -1;
183 rdev->audio_status.status_bits = 0;
184 rdev->audio_status.category_code = 0;
190 * atach the audio codec to the clock source of the encoder
192 void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
194 struct drm_device *dev = encoder->dev;
195 struct radeon_device *rdev = dev->dev_private;
196 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
197 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
199 int base_rate = 48000;
201 switch (radeon_encoder->encoder_id) {
202 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
203 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
204 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
209 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
210 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
213 dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
214 radeon_encoder->encoder_id);
218 if (ASIC_IS_DCE4(rdev)) {
219 /* TODO: other PLLs? */
220 WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);
221 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
222 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
224 /* Select DTO source */
225 WREG32(0x5ac, radeon_crtc->crtc_id);
227 switch (dig->dig_encoder) {
229 WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
230 WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
231 WREG32(R600_AUDIO_CLK_SRCSEL, 0);
235 WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
236 WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
237 WREG32(R600_AUDIO_CLK_SRCSEL, 1);
241 "Unsupported DIG on encoder 0x%02X\n",
242 radeon_encoder->encoder_id);
249 * release the audio timer
250 * TODO: How to do this correctly on SMP systems?
252 void r600_audio_fini(struct radeon_device *rdev)
254 if (!rdev->audio_enabled)
257 r600_audio_engine_enable(rdev, false);