2 * Copyright 2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
33 * R6xx+ cards need to use the 3D engine to blit data which requires
34 * quite a bit of hw state setup. Rather than pull the whole 3D driver
35 * (which normally generates the 3D state) into the DRM, we opt to use
36 * statically generated state tables. The regsiter state and shaders
37 * were hand generated to support blitting functionality. See the 3D
38 * driver or documentation for descriptions of the registers and
39 * shader instructions.
42 const u32 r6xx_default_state[] =
44 0xc0002400, /* START_3D_CMDBUF */
47 0xc0012800, /* CONTEXT_CONTROL */
53 0x00008000, /* WAIT_UNTIL */
57 0x07000003, /* TA_CNTL_AUX */
61 0x00000000, /* VC_ENHANCE */
65 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
69 0x82000000, /* DB_DEBUG */
73 0x01020204, /* DB_WATERMARKS */
77 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
78 0x00000000, /* SQ_VTX_START_INST_LOC */
82 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
94 0x00000000, /* DB_DEPTH_INFO */
98 0x00000000, /* DB_STENCIL_CLEAR */
99 0x00000000, /* DB_DEPTH_CLEAR */
103 0x00000000, /* DB_DEPTH_CONTROL */
107 0x00000060, /* DB_RENDER_CONTROL */
108 0x00000040, /* DB_RENDER_OVERRIDE */
112 0x0000aa00, /* DB_ALPHA_TO_MASK */
116 0x00000800, /* VGT_MAX_VTX_INDX */
117 0x00000000, /* VGT_MIN_VTX_INDX */
118 0x00000000, /* VGT_INDX_OFFSET */
119 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
120 0x00000000, /* SX_ALPHA_TEST_CONTROL */
121 0x00000000, /* CB_BLEND_RED */
125 0x00000000, /* CB_FOG_RED */
128 0x00000000, /* DB_STENCILREFMASK */
129 0x00000000, /* DB_STENCILREFMASK_BF */
130 0x00000000, /* SX_ALPHA_REF */
134 0x01000000, /* CB_CLRCMP_CNTL */
141 0x3f800000, /* CB_CLEAR_RED */
148 0x00000000, /* PA_SC_WINDOW_OFFSET */
152 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
153 0x00000000, /* PA_SC_CLIPRECT_0_TL */
161 0x00000000, /* PA_SC_EDGERULE */
165 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
166 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
167 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
197 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
232 0x00000000, /* PA_SC_MPASS_PS_CNTL */
233 0x00004010, /* PA_SC_MODE_CNTL */
237 0x00000000, /* PA_SC_LINE_CNTL */
238 0x00000000, /* PA_SC_AA_CONFIG */
239 0x0000002d, /* PA_SU_VTX_CNTL */
240 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
244 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
249 0xffffffff, /* PA_SC_AA_MASK */
253 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
254 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
255 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
256 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
257 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
258 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
262 0x00000000, /* SPI_INPUT_Z */
263 0x00000000, /* SPI_FOG_CNTL */
264 0x00000000, /* SPI_FOG_FUNC_SCALE */
265 0x00000000, /* SPI_FOG_FUNC_BIAS */
269 0x00000000, /* SQ_PGM_START_FS */
273 0x00000000, /* SQ_PGM_RESOURCES_FS */
277 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
281 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
282 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
286 0x00000000, /* PA_SU_POINT_SIZE */
287 0x00000000, /* PA_SU_POINT_MINMAX */
288 0x00000008, /* PA_SU_LINE_CNTL */
289 0x00000000, /* PA_SC_LINE_STIPPLE */
290 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
291 0x00000000, /* VGT_HOS_CNTL */
292 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
293 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
294 0x00000000, /* VGT_HOS_REUSE_DEPTH */
295 0x00000000, /* VGT_GROUP_PRIM_TYPE */
296 0x00000000, /* VGT_GROUP_FIRST_DECR */
297 0x00000000, /* VGT_GROUP_DECR */
298 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
299 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
300 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
301 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
302 0x00000000, /* VGT_GS_MODE */
306 0x00000000, /* VGT_PRIMITIVEID_EN */
310 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
314 0x00000000, /* VGT_STRMOUT_EN */
315 0x00000000, /* VGT_REUSE_OFF */
316 0x00000000, /* VGT_VTX_CNT_EN */
320 0x00000000, /* SX_MISC */
324 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
328 0x00cc0000, /* CB_COLOR_CONTROL */
329 0x00000210, /* DB_SHADER_CNTL */
330 0x00010000, /* PA_CL_CLIP_CNTL */
331 0x00000244, /* PA_SU_SC_MODE_CNTL */
332 0x00000100, /* PA_CL_VTE_CNTL */
333 0x00000000, /* PA_CL_VS_OUT_CNTL */
334 0x00000000, /* PA_CL_NANINF_CNTL */
338 0x0000000f, /* CB_TARGET_MASK */
339 0x0000000f, /* CB_SHADER_MASK */
343 0x00000001, /* CB_SHADER_CONTROL */
347 0x00000000, /* SPI_VS_OUT_ID_0 */
351 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
355 0x00000000, /* SPI_VS_OUT_CONFIG */
356 0x00000000, /* SPI_THREAD_GROUPING */
357 0x00000001, /* SPI_PS_IN_CONTROL_0 */
358 0x00000000, /* SPI_PS_IN_CONTROL_1 */
359 0x00000000, /* SPI_INTERP_CONTROL_0 */
361 0xc0036e00, /* SET_SAMPLER */
368 const u32 r7xx_default_state[] =
370 0xc0012800, /* CONTEXT_CONTROL */
376 0x00008000, /* WAIT_UNTIL */
380 0x07000002, /* TA_CNTL_AUX */
384 0x00000000, /* VC_ENHANCE */
388 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
392 0x00000000, /* DB_DEBUG */
396 0x00420204, /* DB_WATERMARKS */
400 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
401 0x00000000, /* SQ_VTX_START_INST_LOC */
405 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
417 0x00000000, /* DB_DEPTH_INFO */
421 0x00000000, /* DB_STENCIL_CLEAR */
422 0x00000000, /* DB_DEPTH_CLEAR */
426 0x00000000, /* DB_DEPTH_CONTROL */
430 0x00000060, /* DB_RENDER_CONTROL */
431 0x00000000, /* DB_RENDER_OVERRIDE */
435 0x0000aa00, /* DB_ALPHA_TO_MASK */
439 0x00000800, /* VGT_MAX_VTX_INDX */
440 0x00000000, /* VGT_MIN_VTX_INDX */
441 0x00000000, /* VGT_INDX_OFFSET */
442 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
443 0x00000000, /* SX_ALPHA_TEST_CONTROL */
444 0x00000000, /* CB_BLEND_RED */
451 0x00000000, /* DB_STENCILREFMASK */
452 0x00000000, /* DB_STENCILREFMASK_BF */
453 0x00000000, /* SX_ALPHA_REF */
456 0x0000030c, /* CB_CLRCMP_CNTL */
464 0x00000000, /* PA_SC_WINDOW_OFFSET */
468 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
469 0x00000000, /* PA_SC_CLIPRECT_0_TL */
477 0xaaaaaaaa, /* PA_SC_EDGERULE */
481 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
482 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
483 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
513 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
548 0x00000000, /* PA_SC_MPASS_PS_CNTL */
549 0x00514000, /* PA_SC_MODE_CNTL */
553 0x00000000, /* PA_SC_LINE_CNTL */
554 0x00000000, /* PA_SC_AA_CONFIG */
555 0x0000002d, /* PA_SU_VTX_CNTL */
556 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
560 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
565 0xffffffff, /* PA_SC_AA_MASK */
569 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
570 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
571 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
572 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
573 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
574 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
578 0x00000000, /* SPI_INPUT_Z */
579 0x00000000, /* SPI_FOG_CNTL */
580 0x00000000, /* SPI_FOG_FUNC_SCALE */
581 0x00000000, /* SPI_FOG_FUNC_BIAS */
585 0x00000000, /* SQ_PGM_START_FS */
589 0x00000000, /* SQ_PGM_RESOURCES_FS */
593 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
597 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
598 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
602 0x00000000, /* PA_SU_POINT_SIZE */
603 0x00000000, /* PA_SU_POINT_MINMAX */
604 0x00000008, /* PA_SU_LINE_CNTL */
605 0x00000000, /* PA_SC_LINE_STIPPLE */
606 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
607 0x00000000, /* VGT_HOS_CNTL */
608 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
609 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
610 0x00000000, /* VGT_HOS_REUSE_DEPTH */
611 0x00000000, /* VGT_GROUP_PRIM_TYPE */
612 0x00000000, /* VGT_GROUP_FIRST_DECR */
613 0x00000000, /* VGT_GROUP_DECR */
614 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
615 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
616 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
617 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
618 0x00000000, /* VGT_GS_MODE */
622 0x00000000, /* VGT_PRIMITIVEID_EN */
626 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
630 0x00000000, /* VGT_STRMOUT_EN */
631 0x00000000, /* VGT_REUSE_OFF */
632 0x00000000, /* VGT_VTX_CNT_EN */
636 0x00000000, /* SX_MISC */
640 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
644 0x00cc0000, /* CB_COLOR_CONTROL */
645 0x00000210, /* DB_SHADER_CNTL */
646 0x00010000, /* PA_CL_CLIP_CNTL */
647 0x00000244, /* PA_SU_SC_MODE_CNTL */
648 0x00000100, /* PA_CL_VTE_CNTL */
649 0x00000000, /* PA_CL_VS_OUT_CNTL */
650 0x00000000, /* PA_CL_NANINF_CNTL */
654 0x0000000f, /* CB_TARGET_MASK */
655 0x0000000f, /* CB_SHADER_MASK */
659 0x00000001, /* CB_SHADER_CONTROL */
663 0x00000000, /* SPI_VS_OUT_ID_0 */
667 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
671 0x00000000, /* SPI_VS_OUT_CONFIG */
672 0x00000001, /* SPI_THREAD_GROUPING */
673 0x00000001, /* SPI_PS_IN_CONTROL_0 */
674 0x00000000, /* SPI_PS_IN_CONTROL_1 */
675 0x00000000, /* SPI_INTERP_CONTROL_0 */
677 0xc0036e00, /* SET_SAMPLER */
684 /* same for r6xx/r7xx */
685 const u32 r6xx_vs[] =
705 const u32 r6xx_ps[] =
717 const u32 r6xx_ps_size = DRM_ARRAY_SIZE(r6xx_ps);
718 const u32 r6xx_vs_size = DRM_ARRAY_SIZE(r6xx_vs);
719 const u32 r6xx_default_size = DRM_ARRAY_SIZE(r6xx_default_state);
720 const u32 r7xx_default_size = DRM_ARRAY_SIZE(r7xx_default_state);