2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/radeon/radeon_drm.h>
33 #include "radeon_asic.h"
40 enum r600_hdmi_color_format {
47 * IEC60958 status bits
49 enum r600_hdmi_iec_status_bits {
50 AUDIO_STATUS_DIG_ENABLE = 0x01,
51 AUDIO_STATUS_V = 0x02,
52 AUDIO_STATUS_VCFG = 0x04,
53 AUDIO_STATUS_EMPHASIS = 0x08,
54 AUDIO_STATUS_COPYRIGHT = 0x10,
55 AUDIO_STATUS_NONAUDIO = 0x20,
56 AUDIO_STATUS_PROFESSIONAL = 0x40,
57 AUDIO_STATUS_LEVEL = 0x80
60 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
61 /* 32kHz 44.1kHz 48kHz */
62 /* Clock N CTS N CTS N CTS */
63 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
64 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
65 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
66 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
67 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
68 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
69 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
70 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
71 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
72 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
73 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
77 * calculate CTS value if it's not found in the table
79 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
82 *CTS = clock * N / (128 * freq) * 1000;
83 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
87 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
89 struct radeon_hdmi_acr res;
92 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
93 r600_hdmi_predefined_acr[i].clock != 0; i++)
95 res = r600_hdmi_predefined_acr[i];
97 /* In case some CTS are missing */
98 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
99 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
100 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
106 * update the N and CTS parameters for a given pixel clock rate
108 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
110 struct drm_device *dev = encoder->dev;
111 struct radeon_device *rdev = dev->dev_private;
112 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
114 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
115 uint32_t offset = dig->afmt->offset;
117 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
118 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
120 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
121 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
123 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
124 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
128 * calculate the crc for a given info frame
130 static void r600_hdmi_infoframe_checksum(uint8_t packetType,
131 uint8_t versionNumber,
136 frame[0] = packetType + versionNumber + length;
137 for (i = 1; i <= length; i++)
138 frame[0] += frame[i];
139 frame[0] = 0x100 - frame[0];
143 * build a HDMI Video Info Frame
145 static void r600_hdmi_videoinfoframe(
146 struct drm_encoder *encoder,
147 enum r600_hdmi_color_format color_format,
148 int active_information_present,
149 uint8_t active_format_aspect_ratio,
150 uint8_t scan_information,
152 uint8_t ex_colorimetry,
153 uint8_t quantization,
155 uint8_t picture_aspect_ratio,
156 uint8_t video_format_identification,
157 uint8_t pixel_repetition,
158 uint8_t non_uniform_picture_scaling,
159 uint8_t bar_info_data_valid,
166 struct drm_device *dev = encoder->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
169 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
170 uint32_t offset = dig->afmt->offset;
176 (scan_information & 0x3) |
177 ((bar_info_data_valid & 0x3) << 2) |
178 ((active_information_present & 0x1) << 4) |
179 ((color_format & 0x3) << 5);
181 (active_format_aspect_ratio & 0xF) |
182 ((picture_aspect_ratio & 0x3) << 4) |
183 ((colorimetry & 0x3) << 6);
185 (non_uniform_picture_scaling & 0x3) |
186 ((quantization & 0x3) << 2) |
187 ((ex_colorimetry & 0x7) << 4) |
189 frame[0x4] = (video_format_identification & 0x7F);
190 frame[0x5] = (pixel_repetition & 0xF);
191 frame[0x6] = (top_bar & 0xFF);
192 frame[0x7] = (top_bar >> 8);
193 frame[0x8] = (bottom_bar & 0xFF);
194 frame[0x9] = (bottom_bar >> 8);
195 frame[0xA] = (left_bar & 0xFF);
196 frame[0xB] = (left_bar >> 8);
197 frame[0xC] = (right_bar & 0xFF);
198 frame[0xD] = (right_bar >> 8);
200 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
201 /* Our header values (type, version, length) should be alright, Intel
202 * is using the same. Checksum function also seems to be OK, it works
203 * fine for audio infoframe. However calculated value is always lower
204 * by 2 in comparison to fglrx. It breaks displaying anything in case
205 * of TVs that strictly check the checksum. Hack it manually here to
206 * workaround this issue. */
209 WREG32(HDMI0_AVI_INFO0 + offset,
210 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
211 WREG32(HDMI0_AVI_INFO1 + offset,
212 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
213 WREG32(HDMI0_AVI_INFO2 + offset,
214 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
215 WREG32(HDMI0_AVI_INFO3 + offset,
216 frame[0xC] | (frame[0xD] << 8));
220 * build a Audio Info Frame
222 static void r600_hdmi_audioinfoframe(
223 struct drm_encoder *encoder,
224 uint8_t channel_count,
227 uint8_t sample_frequency,
229 uint8_t channel_allocation,
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
238 uint32_t offset = dig->afmt->offset;
243 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
244 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
246 frame[0x4] = channel_allocation;
247 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
254 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
256 WREG32(HDMI0_AUDIO_INFO0 + offset,
257 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
258 WREG32(HDMI0_AUDIO_INFO1 + offset,
259 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
263 * test if audio buffer is filled enough to start playing
265 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
267 struct drm_device *dev = encoder->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
270 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
271 uint32_t offset = dig->afmt->offset;
273 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
277 * have buffer status changed since last call?
279 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
281 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
282 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
285 if (!dig->afmt || !dig->afmt->enabled)
288 status = r600_hdmi_is_audio_buffer_filled(encoder);
289 result = dig->afmt->last_buffer_filled_status != status;
290 dig->afmt->last_buffer_filled_status = status;
296 * write the audio workaround status to the hardware
298 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
302 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
303 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
304 uint32_t offset = dig->afmt->offset;
305 bool hdmi_audio_workaround = false; /* FIXME */
308 if (!hdmi_audio_workaround ||
309 r600_hdmi_is_audio_buffer_filled(encoder))
310 value = 0; /* disable workaround */
312 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
313 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
314 value, ~HDMI0_AUDIO_TEST_EN);
319 * update the info frames with the data from the current display mode
321 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
323 struct drm_device *dev = encoder->dev;
324 struct radeon_device *rdev = dev->dev_private;
325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
326 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
329 /* Silent, r600_hdmi_enable will raise WARN for us */
330 if (!dig->afmt->enabled)
332 offset = dig->afmt->offset;
334 r600_audio_set_clock(encoder, mode->clock);
336 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
337 HDMI0_NULL_SEND); /* send null packets when required */
339 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
341 if (ASIC_IS_DCE32(rdev)) {
342 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
343 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
344 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
345 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
346 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
347 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
349 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
350 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
351 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
352 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
353 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
356 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
357 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
358 HDMI0_ACR_SOURCE); /* select SW CTS value */
360 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
361 HDMI0_NULL_SEND | /* send null packets when required */
362 HDMI0_GC_SEND | /* send general control packets */
363 HDMI0_GC_CONT); /* send general control packets every frame */
365 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
366 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
367 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
368 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
369 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
370 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
372 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
373 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
374 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
376 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
378 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
379 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
381 r600_hdmi_update_ACR(encoder, mode->clock);
383 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
384 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
385 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
386 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
387 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
389 r600_hdmi_audio_workaround(encoder);
393 * update settings with current parameters from audio engine
395 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
397 struct drm_device *dev = encoder->dev;
398 struct radeon_device *rdev = dev->dev_private;
399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
400 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
401 struct r600_audio audio = r600_audio_status(rdev);
405 if (!dig->afmt || !dig->afmt->enabled)
407 offset = dig->afmt->offset;
409 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
410 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
411 audio.channels, audio.rate, audio.bits_per_sample);
412 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
413 (int)audio.status_bits, (int)audio.category_code);
416 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
418 if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
420 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
422 if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
425 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
427 switch (audio.rate) {
429 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
432 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
435 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
438 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
441 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
444 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
447 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
451 WREG32(HDMI0_60958_0 + offset, iec);
454 switch (audio.bits_per_sample) {
456 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
459 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
462 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
465 if (audio.status_bits & AUDIO_STATUS_V)
467 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
469 r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0,
472 r600_hdmi_audio_workaround(encoder);
476 * enable the HDMI engine
478 void r600_hdmi_enable(struct drm_encoder *encoder)
480 struct drm_device *dev = encoder->dev;
481 struct radeon_device *rdev = dev->dev_private;
482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
487 if (ASIC_IS_DCE6(rdev))
490 /* Silent, r600_hdmi_enable will raise WARN for us */
491 if (dig->afmt->enabled)
493 offset = dig->afmt->offset;
495 /* Older chipsets require setting HDMI and routing manually */
496 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
497 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
498 switch (radeon_encoder->encoder_id) {
499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
500 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
501 ~AVIVO_TMDSA_CNTL_HDMI_EN);
502 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
504 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
505 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
506 ~AVIVO_LVTMA_CNTL_HDMI_EN);
507 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
509 case ENCODER_OBJECT_ID_INTERNAL_DDI:
510 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
511 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
513 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
514 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
517 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
518 radeon_encoder->encoder_id);
521 WREG32(HDMI0_CONTROL + offset, hdmi);
524 if (rdev->irq.installed) {
525 /* if irq is available use it */
526 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
529 dig->afmt->enabled = true;
531 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
532 offset, radeon_encoder->encoder_id);
536 * disable the HDMI engine
538 void r600_hdmi_disable(struct drm_encoder *encoder)
540 struct drm_device *dev = encoder->dev;
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
546 if (ASIC_IS_DCE6(rdev))
549 /* Called for ATOM_ENCODER_MODE_HDMI only */
550 if (!dig || !dig->afmt) {
551 DRM_ERROR("%s: !dig || !dig->afmt", __func__);
554 if (!dig->afmt->enabled)
556 offset = dig->afmt->offset;
558 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
559 offset, radeon_encoder->encoder_id);
562 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
564 /* Older chipsets not handled by AtomBIOS */
565 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
566 switch (radeon_encoder->encoder_id) {
567 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
568 WREG32_P(AVIVO_TMDSA_CNTL, 0,
569 ~AVIVO_TMDSA_CNTL_HDMI_EN);
571 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
572 WREG32_P(AVIVO_LVTMA_CNTL, 0,
573 ~AVIVO_LVTMA_CNTL_HDMI_EN);
575 case ENCODER_OBJECT_ID_INTERNAL_DDI:
576 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
581 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
582 radeon_encoder->encoder_id);
585 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
588 dig->afmt->enabled = false;