2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __R600_REG_H__
29 #define __R600_REG_H__
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #define R600_PCIE_PORT_INDEX 0x0038
35 #define R600_PCIE_PORT_DATA 0x003c
37 #define R600_MC_VM_FB_LOCATION 0x2180
38 #define R600_MC_FB_BASE_MASK 0x0000FFFF
39 #define R600_MC_FB_BASE_SHIFT 0
40 #define R600_MC_FB_TOP_MASK 0xFFFF0000
41 #define R600_MC_FB_TOP_SHIFT 16
42 #define R600_MC_VM_AGP_TOP 0x2184
43 #define R600_MC_AGP_TOP_MASK 0x0003FFFF
44 #define R600_MC_AGP_TOP_SHIFT 0
45 #define R600_MC_VM_AGP_BOT 0x2188
46 #define R600_MC_AGP_BOT_MASK 0x0003FFFF
47 #define R600_MC_AGP_BOT_SHIFT 0
48 #define R600_MC_VM_AGP_BASE 0x218c
49 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
50 #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
51 #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
52 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
53 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
55 #define R700_MC_VM_FB_LOCATION 0x2024
56 #define R700_MC_FB_BASE_MASK 0x0000FFFF
57 #define R700_MC_FB_BASE_SHIFT 0
58 #define R700_MC_FB_TOP_MASK 0xFFFF0000
59 #define R700_MC_FB_TOP_SHIFT 16
60 #define R700_MC_VM_AGP_TOP 0x2028
61 #define R700_MC_AGP_TOP_MASK 0x0003FFFF
62 #define R700_MC_AGP_TOP_SHIFT 0
63 #define R700_MC_VM_AGP_BOT 0x202c
64 #define R700_MC_AGP_BOT_MASK 0x0003FFFF
65 #define R700_MC_AGP_BOT_SHIFT 0
66 #define R700_MC_VM_AGP_BASE 0x2030
67 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
68 #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
69 #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0
70 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
71 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
73 #define R600_RAMCFG 0x2408
74 # define R600_CHANSIZE (1 << 7)
75 # define R600_CHANSIZE_OVERRIDE (1 << 10)
78 #define R600_GENERAL_PWRMGT 0x618
79 # define R600_OPEN_DRAIN_PADS (1 << 11)
81 #define R600_LOWER_GPIO_ENABLE 0x710
82 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
83 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
84 #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
85 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
87 #define R600_D1GRPH_SWAP_CONTROL 0x610C
88 # define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
89 # define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
90 # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
91 # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
93 #define R600_HDP_NONSURFACE_BASE 0x2c04
95 #define R600_BUS_CNTL 0x5420
96 # define R600_BIOS_ROM_DIS (1 << 1)
97 #define R600_CONFIG_CNTL 0x5424
98 #define R600_CONFIG_MEMSIZE 0x5428
99 #define R600_CONFIG_F0_BASE 0x542C
100 #define R600_CONFIG_APER_SIZE 0x5430
102 #define R600_BIF_FB_EN 0x5490
103 #define R600_FB_READ_EN (1 << 0)
104 #define R600_FB_WRITE_EN (1 << 1)
106 #define R600_CITF_CNTL 0x200c
107 #define R600_BLACKOUT_MASK 0x00000003
109 #define R700_MC_CITF_CNTL 0x25c0
111 #define R600_ROM_CNTL 0x1600
112 # define R600_SCK_OVERWRITE (1 << 1)
113 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
114 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
116 #define R600_CG_SPLL_FUNC_CNTL 0x600
117 # define R600_SPLL_BYPASS_EN (1 << 3)
118 #define R600_CG_SPLL_STATUS 0x60c
119 # define R600_SPLL_CHG_STATUS (1 << 1)
121 #define R600_BIOS_0_SCRATCH 0x1724
122 #define R600_BIOS_1_SCRATCH 0x1728
123 #define R600_BIOS_2_SCRATCH 0x172c
124 #define R600_BIOS_3_SCRATCH 0x1730
125 #define R600_BIOS_4_SCRATCH 0x1734
126 #define R600_BIOS_5_SCRATCH 0x1738
127 #define R600_BIOS_6_SCRATCH 0x173c
128 #define R600_BIOS_7_SCRATCH 0x1740
130 /* Audio, these regs were reverse enginered,
131 * so the chance is high that the naming is wrong
135 #define R600_AUDIO_PLL1_MUL 0x0514
136 #define R600_AUDIO_PLL1_DIV 0x0518
137 #define R600_AUDIO_PLL2_MUL 0x0524
138 #define R600_AUDIO_PLL2_DIV 0x0528
139 #define R600_AUDIO_CLK_SRCSEL 0x0534
142 #define R600_AUDIO_ENABLE 0x7300
143 #define R600_AUDIO_TIMING 0x7344
146 #define R600_AUDIO_VENDOR_ID 0x7380
147 #define R600_AUDIO_REVISION_ID 0x7384
148 #define R600_AUDIO_ROOT_NODE_COUNT 0x7388
149 #define R600_AUDIO_NID1_NODE_COUNT 0x738c
150 #define R600_AUDIO_NID1_TYPE 0x7390
151 #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
152 #define R600_AUDIO_SUPPORTED_CODEC 0x7398
153 #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
154 #define R600_AUDIO_NID2_CAPS 0x73a0
155 #define R600_AUDIO_NID3_CAPS 0x73a4
156 #define R600_AUDIO_NID3_PIN_CAPS 0x73a8
158 /* Audio conn list */
159 #define R600_AUDIO_CONN_LIST_LEN 0x73ac
160 #define R600_AUDIO_CONN_LIST 0x73b0
163 #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
164 #define R600_AUDIO_PLAYING 0x73c4
165 #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
166 #define R600_AUDIO_CONFIG_DEFAULT 0x73cc
167 #define R600_AUDIO_PIN_SENSE 0x73d0
168 #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
169 #define R600_AUDIO_STATUS_BITS 0x73d8
171 #define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400)
172 #define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400)
173 /* DCE3.2 second instance starts at 0x7800 */
174 #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400)
175 #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400)