2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/radeon/radeon_drm.h>
33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
36 #include "atom-bits.h"
38 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
39 /* from radeon_encoder.c */
41 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 extern void radeon_link_encoder_connector(struct drm_device *dev);
45 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
46 uint32_t supported_device, u16 caps);
48 /* from radeon_connector.c */
50 radeon_add_atom_connector(struct drm_device *dev,
51 uint32_t connector_id,
52 uint32_t supported_device,
54 struct radeon_i2c_bus_rec *i2c_bus,
55 uint32_t igp_lane_info,
56 uint16_t connector_object_id,
57 struct radeon_hpd *hpd,
58 struct radeon_router *router);
60 /* from radeon_legacy_encoder.c */
62 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
63 uint32_t supported_device);
67 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
68 u16 voltage_id, u16 *voltage);
70 union atom_supported_devices {
71 struct _ATOM_SUPPORTED_DEVICES_INFO info;
72 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
73 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
76 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
77 ATOM_GPIO_I2C_ASSIGMENT *gpio,
80 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
81 if ((rdev->family == CHIP_R420) ||
82 (rdev->family == CHIP_R423) ||
83 (rdev->family == CHIP_RV410)) {
84 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
85 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
86 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
87 gpio->ucClkMaskShift = 0x19;
88 gpio->ucDataMaskShift = 0x18;
92 /* some evergreen boards have bad data for this entry */
93 if (ASIC_IS_DCE4(rdev)) {
95 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
96 (gpio->sucI2cId.ucAccess == 0)) {
97 gpio->sucI2cId.ucAccess = 0x97;
98 gpio->ucDataMaskShift = 8;
99 gpio->ucDataEnShift = 8;
100 gpio->ucDataY_Shift = 8;
101 gpio->ucDataA_Shift = 8;
105 /* some DCE3 boards have bad data for this entry */
106 if (ASIC_IS_DCE3(rdev)) {
108 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
109 (gpio->sucI2cId.ucAccess == 0x94))
110 gpio->sucI2cId.ucAccess = 0x14;
114 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
116 struct radeon_i2c_bus_rec i2c;
118 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
120 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
121 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
122 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
123 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
124 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
125 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
126 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
127 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
128 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
129 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
130 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
131 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
132 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
133 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
134 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
135 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
137 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
138 i2c.hw_capable = true;
140 i2c.hw_capable = false;
142 if (gpio->sucI2cId.ucAccess == 0xa0)
147 i2c.i2c_id = gpio->sucI2cId.ucAccess;
149 if (i2c.mask_clk_reg)
157 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
160 struct atom_context *ctx = rdev->mode_info.atom_context;
161 ATOM_GPIO_I2C_ASSIGMENT *gpio;
162 struct radeon_i2c_bus_rec i2c;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
164 struct _ATOM_GPIO_I2C_INFO *i2c_info;
165 uint16_t data_offset, size;
168 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
171 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
172 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
174 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
175 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
177 for (i = 0; i < num_indices; i++) {
178 gpio = &i2c_info->asGPIO_Info[i];
180 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
182 if (gpio->sucI2cId.ucAccess == id) {
183 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
192 void radeon_atombios_i2c_init(struct radeon_device *rdev)
194 struct atom_context *ctx = rdev->mode_info.atom_context;
195 ATOM_GPIO_I2C_ASSIGMENT *gpio;
196 struct radeon_i2c_bus_rec i2c;
197 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
198 struct _ATOM_GPIO_I2C_INFO *i2c_info;
199 uint16_t data_offset, size;
203 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
204 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
206 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
207 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
209 for (i = 0; i < num_indices; i++) {
210 gpio = &i2c_info->asGPIO_Info[i];
212 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
214 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
217 sprintf(stmp, "0x%x", i2c.i2c_id);
218 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
224 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
227 struct atom_context *ctx = rdev->mode_info.atom_context;
228 struct radeon_gpio_rec gpio;
229 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
230 struct _ATOM_GPIO_PIN_LUT *gpio_info;
231 ATOM_GPIO_PIN_ASSIGNMENT *pin;
232 u16 data_offset, size;
235 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
238 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
239 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset);
241 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
242 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
244 for (i = 0; i < num_indices; i++) {
245 pin = &gpio_info->asGPIO_Pin[i];
246 if (id == pin->ucGPIO_ID) {
247 gpio.id = pin->ucGPIO_ID;
248 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
249 gpio.mask = (1 << pin->ucGpioPinBitShift);
259 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
260 struct radeon_gpio_rec *gpio)
262 struct radeon_hpd hpd;
265 memset(&hpd, 0, sizeof(struct radeon_hpd));
267 if (ASIC_IS_DCE6(rdev))
268 reg = SI_DC_GPIO_HPD_A;
269 else if (ASIC_IS_DCE4(rdev))
270 reg = EVERGREEN_DC_GPIO_HPD_A;
272 reg = AVIVO_DC_GPIO_HPD_A;
275 if (gpio->reg == reg) {
278 hpd.hpd = RADEON_HPD_1;
281 hpd.hpd = RADEON_HPD_2;
284 hpd.hpd = RADEON_HPD_3;
287 hpd.hpd = RADEON_HPD_4;
290 hpd.hpd = RADEON_HPD_5;
293 hpd.hpd = RADEON_HPD_6;
296 hpd.hpd = RADEON_HPD_NONE;
300 hpd.hpd = RADEON_HPD_NONE;
304 static bool radeon_atom_apply_quirks(struct drm_device *dev,
305 uint32_t supported_device,
307 struct radeon_i2c_bus_rec *i2c_bus,
309 struct radeon_hpd *hpd)
312 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
313 if ((dev->pci_device == 0x791e) &&
314 (dev->pci_subvendor == 0x1043) &&
315 (dev->pci_subdevice == 0x826d)) {
316 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
317 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
318 *connector_type = DRM_MODE_CONNECTOR_DVID;
321 /* Asrock RS600 board lists the DVI port as HDMI */
322 if ((dev->pci_device == 0x7941) &&
323 (dev->pci_subvendor == 0x1849) &&
324 (dev->pci_subdevice == 0x7941)) {
325 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
326 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
327 *connector_type = DRM_MODE_CONNECTOR_DVID;
330 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
331 if ((dev->pci_device == 0x796e) &&
332 (dev->pci_subvendor == 0x1462) &&
333 (dev->pci_subdevice == 0x7302)) {
334 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
335 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
339 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
340 if ((dev->pci_device == 0x7941) &&
341 (dev->pci_subvendor == 0x147b) &&
342 (dev->pci_subdevice == 0x2412)) {
343 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
347 /* Falcon NW laptop lists vga ddc line for LVDS */
348 if ((dev->pci_device == 0x5653) &&
349 (dev->pci_subvendor == 0x1462) &&
350 (dev->pci_subdevice == 0x0291)) {
351 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
352 i2c_bus->valid = false;
357 /* HIS X1300 is DVI+VGA, not DVI+DVI */
358 if ((dev->pci_device == 0x7146) &&
359 (dev->pci_subvendor == 0x17af) &&
360 (dev->pci_subdevice == 0x2058)) {
361 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
365 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
366 if ((dev->pci_device == 0x7142) &&
367 (dev->pci_subvendor == 0x1458) &&
368 (dev->pci_subdevice == 0x2134)) {
369 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 if ((dev->pci_device == 0x71C5) &&
376 (dev->pci_subvendor == 0x106b) &&
377 (dev->pci_subdevice == 0x0080)) {
378 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
379 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
381 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
385 /* mac rv630, rv730, others */
386 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
387 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
388 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
389 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
392 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
393 if ((dev->pci_device == 0x9598) &&
394 (dev->pci_subvendor == 0x1043) &&
395 (dev->pci_subdevice == 0x01da)) {
396 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
397 *connector_type = DRM_MODE_CONNECTOR_DVII;
401 /* ASUS HD 3600 board lists the DVI port as HDMI */
402 if ((dev->pci_device == 0x9598) &&
403 (dev->pci_subvendor == 0x1043) &&
404 (dev->pci_subdevice == 0x01e4)) {
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 *connector_type = DRM_MODE_CONNECTOR_DVII;
410 /* ASUS HD 3450 board lists the DVI port as HDMI */
411 if ((dev->pci_device == 0x95C5) &&
412 (dev->pci_subvendor == 0x1043) &&
413 (dev->pci_subdevice == 0x01e2)) {
414 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
415 *connector_type = DRM_MODE_CONNECTOR_DVII;
419 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
420 * HDMI + VGA reporting as HDMI
422 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
423 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
424 *connector_type = DRM_MODE_CONNECTOR_VGA;
429 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
430 * on the laptop and a DVI port on the docking station and
431 * both share the same encoder, hpd pin, and ddc line.
432 * So while the bios table is technically correct,
433 * we drop the DVI port here since xrandr has no concept of
434 * encoders and will try and drive both connectors
435 * with different crtcs which isn't possible on the hardware
436 * side and leaves no crtcs for LVDS or VGA.
438 if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) &&
439 (dev->pci_subvendor == 0x1025) &&
440 (dev->pci_subdevice == 0x013c)) {
441 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
442 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
443 /* actually it's a DVI-D port not DVI-I */
444 *connector_type = DRM_MODE_CONNECTOR_DVID;
449 /* XFX Pine Group device rv730 reports no VGA DDC lines
450 * even though they are wired up to record 0x93
452 if ((dev->pci_device == 0x9498) &&
453 (dev->pci_subvendor == 0x1682) &&
454 (dev->pci_subdevice == 0x2452) &&
455 (i2c_bus->valid == false) &&
456 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
457 struct radeon_device *rdev = dev->dev_private;
458 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
461 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
462 if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) &&
463 (dev->pci_subvendor == 0x1734) &&
464 (dev->pci_subdevice == 0x11bd)) {
465 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
466 *connector_type = DRM_MODE_CONNECTOR_DVII;
468 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
469 *connector_type = DRM_MODE_CONNECTOR_DVII;
477 const int supported_devices_connector_convert[] = {
478 DRM_MODE_CONNECTOR_Unknown,
479 DRM_MODE_CONNECTOR_VGA,
480 DRM_MODE_CONNECTOR_DVII,
481 DRM_MODE_CONNECTOR_DVID,
482 DRM_MODE_CONNECTOR_DVIA,
483 DRM_MODE_CONNECTOR_SVIDEO,
484 DRM_MODE_CONNECTOR_Composite,
485 DRM_MODE_CONNECTOR_LVDS,
486 DRM_MODE_CONNECTOR_Unknown,
487 DRM_MODE_CONNECTOR_Unknown,
488 DRM_MODE_CONNECTOR_HDMIA,
489 DRM_MODE_CONNECTOR_HDMIB,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_Unknown,
492 DRM_MODE_CONNECTOR_9PinDIN,
493 DRM_MODE_CONNECTOR_DisplayPort
496 const uint16_t supported_devices_connector_object_id_convert[] = {
497 CONNECTOR_OBJECT_ID_NONE,
498 CONNECTOR_OBJECT_ID_VGA,
499 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
500 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
501 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
502 CONNECTOR_OBJECT_ID_COMPOSITE,
503 CONNECTOR_OBJECT_ID_SVIDEO,
504 CONNECTOR_OBJECT_ID_LVDS,
505 CONNECTOR_OBJECT_ID_9PIN_DIN,
506 CONNECTOR_OBJECT_ID_9PIN_DIN,
507 CONNECTOR_OBJECT_ID_DISPLAYPORT,
508 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
509 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
510 CONNECTOR_OBJECT_ID_SVIDEO
513 const int object_connector_convert[] = {
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_DVII,
516 DRM_MODE_CONNECTOR_DVII,
517 DRM_MODE_CONNECTOR_DVID,
518 DRM_MODE_CONNECTOR_DVID,
519 DRM_MODE_CONNECTOR_VGA,
520 DRM_MODE_CONNECTOR_Composite,
521 DRM_MODE_CONNECTOR_SVIDEO,
522 DRM_MODE_CONNECTOR_Unknown,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_9PinDIN,
525 DRM_MODE_CONNECTOR_Unknown,
526 DRM_MODE_CONNECTOR_HDMIA,
527 DRM_MODE_CONNECTOR_HDMIB,
528 DRM_MODE_CONNECTOR_LVDS,
529 DRM_MODE_CONNECTOR_9PinDIN,
530 DRM_MODE_CONNECTOR_Unknown,
531 DRM_MODE_CONNECTOR_Unknown,
532 DRM_MODE_CONNECTOR_Unknown,
533 DRM_MODE_CONNECTOR_DisplayPort,
534 DRM_MODE_CONNECTOR_eDP,
535 DRM_MODE_CONNECTOR_Unknown
538 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
540 struct radeon_device *rdev = dev->dev_private;
541 struct radeon_mode_info *mode_info = &rdev->mode_info;
542 struct atom_context *ctx = mode_info->atom_context;
543 int index = GetIndexIntoMasterTable(DATA, Object_Header);
544 u16 size, data_offset;
546 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
547 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
548 ATOM_OBJECT_TABLE *router_obj;
549 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
550 ATOM_OBJECT_HEADER *obj_header;
551 int i, j, k, path_size, device_support;
553 u16 igp_lane_info, conn_id, connector_object_id;
554 struct radeon_i2c_bus_rec ddc_bus;
555 struct radeon_router router;
556 struct radeon_gpio_rec gpio;
557 struct radeon_hpd hpd;
559 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
565 obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset);
566 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
567 ((char *)ctx->bios + data_offset +
568 le16_to_cpu(obj_header->usDisplayPathTableOffset));
569 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
570 ((char *)ctx->bios + data_offset +
571 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
572 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
573 ((char *)ctx->bios + data_offset +
574 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
575 router_obj = (ATOM_OBJECT_TABLE *)
576 ((char *)ctx->bios + data_offset +
577 le16_to_cpu(obj_header->usRouterObjectTableOffset));
578 device_support = le16_to_cpu(obj_header->usDeviceSupport);
581 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
582 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
583 ATOM_DISPLAY_OBJECT_PATH *path;
585 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
586 path_size += le16_to_cpu(path->usSize);
588 if (device_support & le16_to_cpu(path->usDeviceTag)) {
589 uint8_t con_obj_id, con_obj_num, con_obj_type;
592 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
595 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
598 (le16_to_cpu(path->usConnObjectId) &
599 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
601 /* TODO CV support */
602 if (le16_to_cpu(path->usDeviceTag) ==
603 ATOM_DEVICE_CV_SUPPORT)
607 if ((rdev->flags & RADEON_IS_IGP) &&
609 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
610 uint16_t igp_offset = 0;
611 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
614 GetIndexIntoMasterTable(DATA,
615 IntegratedSystemInfo);
617 if (atom_parse_data_header(ctx, index, &size, &frev,
618 &crev, &igp_offset)) {
622 (ATOM_INTEGRATED_SYSTEM_INFO_V2
623 *) ((char *)ctx->bios + igp_offset);
626 uint32_t slot_config, ct;
628 if (con_obj_num == 1)
637 ct = (slot_config >> 16) & 0xff;
639 object_connector_convert
641 connector_object_id = ct;
643 slot_config & 0xffff;
651 object_connector_convert[con_obj_id];
652 connector_object_id = con_obj_id;
657 object_connector_convert[con_obj_id];
658 connector_object_id = con_obj_id;
661 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
664 router.ddc_valid = false;
665 router.cd_valid = false;
666 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
667 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
670 (le16_to_cpu(path->usGraphicObjIds[j]) &
671 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
673 (le16_to_cpu(path->usGraphicObjIds[j]) &
674 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
676 (le16_to_cpu(path->usGraphicObjIds[j]) &
677 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
679 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
680 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
681 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
682 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
683 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
684 ((char *)ctx->bios + data_offset +
685 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
686 ATOM_ENCODER_CAP_RECORD *cap_record;
689 while (record->ucRecordSize > 0 &&
690 record->ucRecordType > 0 &&
691 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
692 switch (record->ucRecordType) {
693 case ATOM_ENCODER_CAP_RECORD_TYPE:
694 cap_record =(ATOM_ENCODER_CAP_RECORD *)
696 caps = le16_to_cpu(cap_record->usEncoderCap);
699 record = (ATOM_COMMON_RECORD_HEADER *)
700 ((char *)record + record->ucRecordSize);
702 radeon_add_atom_encoder(dev,
710 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
711 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
712 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
713 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
714 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
715 ((char *)ctx->bios + data_offset +
716 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
717 ATOM_I2C_RECORD *i2c_record;
718 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
719 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
720 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
721 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
722 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
723 ((char *)ctx->bios + data_offset +
724 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
727 router.router_id = router_obj_id;
728 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
730 if (le16_to_cpu(path->usConnObjectId) ==
731 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
735 while (record->ucRecordSize > 0 &&
736 record->ucRecordType > 0 &&
737 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
738 switch (record->ucRecordType) {
739 case ATOM_I2C_RECORD_TYPE:
744 (ATOM_I2C_ID_CONFIG_ACCESS *)
745 &i2c_record->sucI2cId;
747 radeon_lookup_i2c_gpio(rdev,
750 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
752 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
753 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
755 router.ddc_valid = true;
756 router.ddc_mux_type = ddc_path->ucMuxType;
757 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
758 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
760 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
761 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
763 router.cd_valid = true;
764 router.cd_mux_type = cd_path->ucMuxType;
765 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
766 router.cd_mux_state = cd_path->ucMuxState[enum_id];
769 record = (ATOM_COMMON_RECORD_HEADER *)
770 ((char *)record + record->ucRecordSize);
777 /* look up gpio for ddc, hpd */
778 ddc_bus.valid = false;
779 hpd.hpd = RADEON_HPD_NONE;
780 if ((le16_to_cpu(path->usDeviceTag) &
781 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
782 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
783 if (le16_to_cpu(path->usConnObjectId) ==
784 le16_to_cpu(con_obj->asObjects[j].
786 ATOM_COMMON_RECORD_HEADER
788 (ATOM_COMMON_RECORD_HEADER
790 ((char *)ctx->bios + data_offset +
791 le16_to_cpu(con_obj->
794 ATOM_I2C_RECORD *i2c_record;
795 ATOM_HPD_INT_RECORD *hpd_record;
796 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
798 while (record->ucRecordSize > 0 &&
799 record->ucRecordType > 0 &&
800 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
801 switch (record->ucRecordType) {
802 case ATOM_I2C_RECORD_TYPE:
807 (ATOM_I2C_ID_CONFIG_ACCESS *)
808 &i2c_record->sucI2cId;
809 ddc_bus = radeon_lookup_i2c_gpio(rdev,
813 case ATOM_HPD_INT_RECORD_TYPE:
815 (ATOM_HPD_INT_RECORD *)
817 gpio = radeon_lookup_gpio(rdev,
818 hpd_record->ucHPDIntGPIOID);
819 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
820 hpd.plugged_state = hpd_record->ucPlugged_PinState;
824 (ATOM_COMMON_RECORD_HEADER
835 /* needed for aux chan transactions */
836 ddc_bus.hpd = hpd.hpd;
838 conn_id = le16_to_cpu(path->usConnObjectId);
840 if (!radeon_atom_apply_quirks
841 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
842 &ddc_bus, &conn_id, &hpd))
845 radeon_add_atom_connector(dev,
849 connector_type, &ddc_bus,
858 radeon_link_encoder_connector(dev);
863 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
867 struct radeon_device *rdev = dev->dev_private;
869 if (rdev->flags & RADEON_IS_IGP) {
870 return supported_devices_connector_object_id_convert
872 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
873 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
874 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
875 struct radeon_mode_info *mode_info = &rdev->mode_info;
876 struct atom_context *ctx = mode_info->atom_context;
877 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
878 uint16_t size, data_offset;
880 ATOM_XTMDS_INFO *xtmds;
882 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
883 xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset);
885 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
886 if (connector_type == DRM_MODE_CONNECTOR_DVII)
887 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
889 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
891 if (connector_type == DRM_MODE_CONNECTOR_DVII)
892 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
894 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
897 return supported_devices_connector_object_id_convert
900 return supported_devices_connector_object_id_convert
905 struct bios_connector {
910 struct radeon_i2c_bus_rec ddc_bus;
911 struct radeon_hpd hpd;
914 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
918 struct radeon_device *rdev = dev->dev_private;
919 struct radeon_mode_info *mode_info = &rdev->mode_info;
920 struct atom_context *ctx = mode_info->atom_context;
921 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
922 uint16_t size, data_offset;
924 uint16_t device_support;
926 union atom_supported_devices *supported_devices;
927 int i, j, max_device;
928 struct bios_connector *bios_connectors;
929 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
930 struct radeon_router router;
932 router.ddc_valid = false;
933 router.cd_valid = false;
935 bios_connectors = malloc(bc_size, DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
936 if (!bios_connectors)
939 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
941 free(bios_connectors, DRM_MEM_DRIVER);
946 (union atom_supported_devices *)((char *)ctx->bios + data_offset);
948 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
951 max_device = ATOM_MAX_SUPPORTED_DEVICE;
953 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
955 for (i = 0; i < max_device; i++) {
956 ATOM_CONNECTOR_INFO_I2C ci =
957 supported_devices->info.asConnInfo[i];
959 bios_connectors[i].valid = false;
961 if (!(device_support & (1 << i))) {
965 if (i == ATOM_DEVICE_CV_INDEX) {
966 DRM_DEBUG_KMS("Skipping Component Video\n");
970 bios_connectors[i].connector_type =
971 supported_devices_connector_convert[ci.sucConnectorInfo.
975 if (bios_connectors[i].connector_type ==
976 DRM_MODE_CONNECTOR_Unknown)
979 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
981 bios_connectors[i].line_mux =
982 ci.sucI2cId.ucAccess;
984 /* give tv unique connector ids */
985 if (i == ATOM_DEVICE_TV1_INDEX) {
986 bios_connectors[i].ddc_bus.valid = false;
987 bios_connectors[i].line_mux = 50;
988 } else if (i == ATOM_DEVICE_TV2_INDEX) {
989 bios_connectors[i].ddc_bus.valid = false;
990 bios_connectors[i].line_mux = 51;
991 } else if (i == ATOM_DEVICE_CV_INDEX) {
992 bios_connectors[i].ddc_bus.valid = false;
993 bios_connectors[i].line_mux = 52;
995 bios_connectors[i].ddc_bus =
996 radeon_lookup_i2c_gpio(rdev,
997 bios_connectors[i].line_mux);
999 if ((crev > 1) && (frev > 1)) {
1000 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1006 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1009 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1013 if (i == ATOM_DEVICE_DFP1_INDEX)
1014 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1015 else if (i == ATOM_DEVICE_DFP2_INDEX)
1016 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1018 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1021 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1022 * shared with a DVI port, we'll pick up the DVI connector when we
1023 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1025 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1026 bios_connectors[i].connector_type =
1027 DRM_MODE_CONNECTOR_VGA;
1029 if (!radeon_atom_apply_quirks
1030 (dev, (1 << i), &bios_connectors[i].connector_type,
1031 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1032 &bios_connectors[i].hpd))
1035 bios_connectors[i].valid = true;
1036 bios_connectors[i].devices = (1 << i);
1038 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1039 radeon_add_atom_encoder(dev,
1040 radeon_get_encoder_enum(dev,
1046 radeon_add_legacy_encoder(dev,
1047 radeon_get_encoder_enum(dev,
1053 /* combine shared connectors */
1054 for (i = 0; i < max_device; i++) {
1055 if (bios_connectors[i].valid) {
1056 for (j = 0; j < max_device; j++) {
1057 if (bios_connectors[j].valid && (i != j)) {
1058 if (bios_connectors[i].line_mux ==
1059 bios_connectors[j].line_mux) {
1060 /* make sure not to combine LVDS */
1061 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1062 bios_connectors[i].line_mux = 53;
1063 bios_connectors[i].ddc_bus.valid = false;
1066 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1067 bios_connectors[j].line_mux = 53;
1068 bios_connectors[j].ddc_bus.valid = false;
1071 /* combine analog and digital for DVI-I */
1072 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1073 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1074 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1075 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1076 bios_connectors[i].devices |=
1077 bios_connectors[j].devices;
1078 bios_connectors[i].connector_type =
1079 DRM_MODE_CONNECTOR_DVII;
1080 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1081 bios_connectors[i].hpd =
1082 bios_connectors[j].hpd;
1083 bios_connectors[j].valid = false;
1091 /* add the connectors */
1092 for (i = 0; i < max_device; i++) {
1093 if (bios_connectors[i].valid) {
1094 uint16_t connector_object_id =
1095 atombios_get_connector_object_id(dev,
1096 bios_connectors[i].connector_type,
1097 bios_connectors[i].devices);
1098 radeon_add_atom_connector(dev,
1099 bios_connectors[i].line_mux,
1100 bios_connectors[i].devices,
1103 &bios_connectors[i].ddc_bus,
1105 connector_object_id,
1106 &bios_connectors[i].hpd,
1111 radeon_link_encoder_connector(dev);
1113 free(bios_connectors, DRM_MEM_DRIVER);
1117 union firmware_info {
1118 ATOM_FIRMWARE_INFO info;
1119 ATOM_FIRMWARE_INFO_V1_2 info_12;
1120 ATOM_FIRMWARE_INFO_V1_3 info_13;
1121 ATOM_FIRMWARE_INFO_V1_4 info_14;
1122 ATOM_FIRMWARE_INFO_V2_1 info_21;
1123 ATOM_FIRMWARE_INFO_V2_2 info_22;
1126 bool radeon_atom_get_clock_info(struct drm_device *dev)
1128 struct radeon_device *rdev = dev->dev_private;
1129 struct radeon_mode_info *mode_info = &rdev->mode_info;
1130 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1131 union firmware_info *firmware_info;
1133 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1134 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1135 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1136 struct radeon_pll *spll = &rdev->clock.spll;
1137 struct radeon_pll *mpll = &rdev->clock.mpll;
1138 uint16_t data_offset;
1140 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1141 &frev, &crev, &data_offset)) {
1143 (union firmware_info *)((char *)mode_info->atom_context->bios +
1146 p1pll->reference_freq =
1147 le16_to_cpu(firmware_info->info.usReferenceClock);
1148 p1pll->reference_div = 0;
1151 p1pll->pll_out_min =
1152 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1154 p1pll->pll_out_min =
1155 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1156 p1pll->pll_out_max =
1157 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1160 p1pll->lcd_pll_out_min =
1161 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1162 if (p1pll->lcd_pll_out_min == 0)
1163 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1164 p1pll->lcd_pll_out_max =
1165 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1166 if (p1pll->lcd_pll_out_max == 0)
1167 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1169 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1170 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1173 if (p1pll->pll_out_min == 0) {
1174 if (ASIC_IS_AVIVO(rdev))
1175 p1pll->pll_out_min = 64800;
1177 p1pll->pll_out_min = 20000;
1181 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1183 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1188 if (ASIC_IS_DCE4(rdev))
1189 spll->reference_freq =
1190 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1192 spll->reference_freq =
1193 le16_to_cpu(firmware_info->info.usReferenceClock);
1194 spll->reference_div = 0;
1197 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1199 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1202 if (spll->pll_out_min == 0) {
1203 if (ASIC_IS_AVIVO(rdev))
1204 spll->pll_out_min = 64800;
1206 spll->pll_out_min = 20000;
1210 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1212 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1215 if (ASIC_IS_DCE4(rdev))
1216 mpll->reference_freq =
1217 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1219 mpll->reference_freq =
1220 le16_to_cpu(firmware_info->info.usReferenceClock);
1221 mpll->reference_div = 0;
1224 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1226 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1229 if (mpll->pll_out_min == 0) {
1230 if (ASIC_IS_AVIVO(rdev))
1231 mpll->pll_out_min = 64800;
1233 mpll->pll_out_min = 20000;
1237 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1239 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1241 rdev->clock.default_sclk =
1242 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1243 rdev->clock.default_mclk =
1244 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1246 if (ASIC_IS_DCE4(rdev)) {
1247 rdev->clock.default_dispclk =
1248 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1249 if (rdev->clock.default_dispclk == 0) {
1250 if (ASIC_IS_DCE5(rdev))
1251 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1253 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255 rdev->clock.dp_extclk =
1256 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1260 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1261 if (rdev->clock.max_pixel_clock == 0)
1262 rdev->clock.max_pixel_clock = 40000;
1264 /* not technically a clock, but... */
1265 rdev->mode_info.firmware_flags =
1266 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1275 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1276 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1277 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1278 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1281 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1283 struct radeon_mode_info *mode_info = &rdev->mode_info;
1284 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1285 union igp_info *igp_info;
1289 /* sideport is AMD only */
1290 if (rdev->family == CHIP_RS600)
1293 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1294 &frev, &crev, &data_offset)) {
1295 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios +
1299 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1303 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1307 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1314 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1315 struct radeon_encoder_int_tmds *tmds)
1317 struct drm_device *dev = encoder->base.dev;
1318 struct radeon_device *rdev = dev->dev_private;
1319 struct radeon_mode_info *mode_info = &rdev->mode_info;
1320 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1321 uint16_t data_offset;
1322 struct _ATOM_TMDS_INFO *tmds_info;
1327 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1328 &frev, &crev, &data_offset)) {
1330 (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios +
1333 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1334 for (i = 0; i < 4; i++) {
1335 tmds->tmds_pll[i].freq =
1336 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1337 tmds->tmds_pll[i].value =
1338 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1339 tmds->tmds_pll[i].value |=
1340 (tmds_info->asMiscInfo[i].
1341 ucPLL_VCO_Gain & 0x3f) << 6;
1342 tmds->tmds_pll[i].value |=
1343 (tmds_info->asMiscInfo[i].
1344 ucPLL_DutyCycle & 0xf) << 12;
1345 tmds->tmds_pll[i].value |=
1346 (tmds_info->asMiscInfo[i].
1347 ucPLL_VoltageSwing & 0xf) << 16;
1349 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1350 tmds->tmds_pll[i].freq,
1351 tmds->tmds_pll[i].value);
1353 if (maxfreq == tmds->tmds_pll[i].freq) {
1354 tmds->tmds_pll[i].freq = 0xffffffff;
1363 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1364 struct radeon_atom_ss *ss,
1367 struct radeon_mode_info *mode_info = &rdev->mode_info;
1368 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1369 uint16_t data_offset, size;
1370 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1374 memset(ss, 0, sizeof(struct radeon_atom_ss));
1375 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1376 &frev, &crev, &data_offset)) {
1378 (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1380 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1381 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1383 for (i = 0; i < num_indices; i++) {
1384 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1386 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1387 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1388 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1389 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1390 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1391 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1399 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1400 struct radeon_atom_ss *ss,
1403 struct radeon_mode_info *mode_info = &rdev->mode_info;
1404 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1405 u16 data_offset, size;
1406 union igp_info *igp_info;
1408 u16 percentage = 0, rate = 0;
1410 /* get any igp specific overrides */
1411 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1412 &frev, &crev, &data_offset)) {
1413 igp_info = (union igp_info *)
1414 ((char *)mode_info->atom_context->bios + data_offset);
1418 case ASIC_INTERNAL_SS_ON_TMDS:
1419 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1420 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1422 case ASIC_INTERNAL_SS_ON_HDMI:
1423 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1424 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1426 case ASIC_INTERNAL_SS_ON_LVDS:
1427 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1428 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1434 case ASIC_INTERNAL_SS_ON_TMDS:
1435 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1436 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1438 case ASIC_INTERNAL_SS_ON_HDMI:
1439 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1440 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1442 case ASIC_INTERNAL_SS_ON_LVDS:
1443 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1444 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1449 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1453 ss->percentage = percentage;
1459 union asic_ss_info {
1460 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1461 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1462 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1465 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1466 struct radeon_atom_ss *ss,
1469 struct radeon_mode_info *mode_info = &rdev->mode_info;
1470 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1471 uint16_t data_offset, size;
1472 union asic_ss_info *ss_info;
1476 memset(ss, 0, sizeof(struct radeon_atom_ss));
1477 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1478 &frev, &crev, &data_offset)) {
1481 (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset);
1485 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1486 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1488 for (i = 0; i < num_indices; i++) {
1489 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1490 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1492 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1500 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1501 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1502 for (i = 0; i < num_indices; i++) {
1503 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1504 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1506 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1507 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1508 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1514 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1515 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1516 for (i = 0; i < num_indices; i++) {
1517 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1518 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1520 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1521 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1522 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1523 if (rdev->flags & RADEON_IS_IGP)
1524 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1530 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1539 struct _ATOM_LVDS_INFO info;
1540 struct _ATOM_LVDS_INFO_V12 info_12;
1543 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1547 struct drm_device *dev = encoder->base.dev;
1548 struct radeon_device *rdev = dev->dev_private;
1549 struct radeon_mode_info *mode_info = &rdev->mode_info;
1550 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1551 uint16_t data_offset, misc;
1552 union lvds_info *lvds_info;
1554 struct radeon_encoder_atom_dig *lvds = NULL;
1555 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1557 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1558 &frev, &crev, &data_offset)) {
1560 (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
1562 malloc(sizeof(struct radeon_encoder_atom_dig),
1563 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1568 lvds->native_mode.clock =
1569 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1570 lvds->native_mode.hdisplay =
1571 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1572 lvds->native_mode.vdisplay =
1573 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1574 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1575 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1576 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1577 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1578 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1579 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1580 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1581 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1582 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1583 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1584 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1585 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1586 lvds->panel_pwr_delay =
1587 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1588 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1590 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1591 if (misc & ATOM_VSYNC_POLARITY)
1592 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1593 if (misc & ATOM_HSYNC_POLARITY)
1594 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1595 if (misc & ATOM_COMPOSITESYNC)
1596 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1597 if (misc & ATOM_INTERLACE)
1598 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1599 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1600 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1602 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1603 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1605 /* set crtc values */
1606 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1608 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1610 encoder->native_mode = lvds->native_mode;
1612 if (encoder_enum == 2)
1615 lvds->linkb = false;
1617 /* parse the lcd record table */
1618 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1619 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1620 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1621 bool bad_record = false;
1624 if ((frev == 1) && (crev < 2))
1626 record = (u8 *)((char *)mode_info->atom_context->bios +
1627 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1630 record = (u8 *)((char *)mode_info->atom_context->bios +
1632 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1633 while (*record != ATOM_RECORD_END_TYPE) {
1635 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1636 record += sizeof(ATOM_PATCH_RECORD_MODE);
1638 case LCD_RTS_RECORD_TYPE:
1639 record += sizeof(ATOM_LCD_RTS_RECORD);
1641 case LCD_CAP_RECORD_TYPE:
1642 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1644 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1645 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1646 if (fake_edid_record->ucFakeEDIDLength) {
1649 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1650 edid = malloc(edid_size, DRM_MEM_KMS, M_NOWAIT);
1652 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1653 fake_edid_record->ucFakeEDIDLength);
1655 if (drm_edid_is_valid(edid)) {
1656 rdev->mode_info.bios_hardcoded_edid = edid;
1657 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1659 free(edid, DRM_MEM_KMS);
1662 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1664 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1665 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1666 lvds->native_mode.width_mm = panel_res_record->usHSize;
1667 lvds->native_mode.height_mm = panel_res_record->usVSize;
1668 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1671 DRM_ERROR("Bad LCD record %d\n", *record);
1683 struct radeon_encoder_primary_dac *
1684 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1686 struct drm_device *dev = encoder->base.dev;
1687 struct radeon_device *rdev = dev->dev_private;
1688 struct radeon_mode_info *mode_info = &rdev->mode_info;
1689 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1690 uint16_t data_offset;
1691 struct _COMPASSIONATE_DATA *dac_info;
1694 struct radeon_encoder_primary_dac *p_dac = NULL;
1696 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1697 &frev, &crev, &data_offset)) {
1698 dac_info = (struct _COMPASSIONATE_DATA *)
1699 ((char *)mode_info->atom_context->bios + data_offset);
1701 p_dac = malloc(sizeof(struct radeon_encoder_primary_dac),
1702 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1707 bg = dac_info->ucDAC1_BG_Adjustment;
1708 dac = dac_info->ucDAC1_DAC_Adjustment;
1709 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1715 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1716 struct drm_display_mode *mode)
1718 struct radeon_mode_info *mode_info = &rdev->mode_info;
1719 ATOM_ANALOG_TV_INFO *tv_info;
1720 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1721 ATOM_DTD_FORMAT *dtd_timings;
1722 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1724 u16 data_offset, misc;
1726 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1727 &frev, &crev, &data_offset))
1732 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1733 if (index >= MAX_SUPPORTED_TV_TIMING)
1736 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1737 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1738 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1739 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1740 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1742 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1743 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1744 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1745 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1746 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1749 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1750 if (misc & ATOM_VSYNC_POLARITY)
1751 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1752 if (misc & ATOM_HSYNC_POLARITY)
1753 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1754 if (misc & ATOM_COMPOSITESYNC)
1755 mode->flags |= DRM_MODE_FLAG_CSYNC;
1756 if (misc & ATOM_INTERLACE)
1757 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1758 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1759 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1761 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1764 /* PAL timings appear to have wrong values for totals */
1765 mode->crtc_htotal -= 1;
1766 mode->crtc_vtotal -= 1;
1770 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset);
1771 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1774 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1775 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1776 le16_to_cpu(dtd_timings->usHBlanking_Time);
1777 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1778 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1779 le16_to_cpu(dtd_timings->usHSyncOffset);
1780 mode->crtc_hsync_end = mode->crtc_hsync_start +
1781 le16_to_cpu(dtd_timings->usHSyncWidth);
1783 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1784 le16_to_cpu(dtd_timings->usVBlanking_Time);
1785 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1786 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1787 le16_to_cpu(dtd_timings->usVSyncOffset);
1788 mode->crtc_vsync_end = mode->crtc_vsync_start +
1789 le16_to_cpu(dtd_timings->usVSyncWidth);
1792 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1793 if (misc & ATOM_VSYNC_POLARITY)
1794 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1795 if (misc & ATOM_HSYNC_POLARITY)
1796 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1797 if (misc & ATOM_COMPOSITESYNC)
1798 mode->flags |= DRM_MODE_FLAG_CSYNC;
1799 if (misc & ATOM_INTERLACE)
1800 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1801 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1802 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1804 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1811 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1813 struct radeon_mode_info *mode_info = &rdev->mode_info;
1814 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1815 uint16_t data_offset;
1817 struct _ATOM_ANALOG_TV_INFO *tv_info;
1818 enum radeon_tv_std tv_std = TV_STD_NTSC;
1820 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1821 &frev, &crev, &data_offset)) {
1823 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1824 ((char *)mode_info->atom_context->bios + data_offset);
1826 switch (tv_info->ucTV_BootUpDefaultStandard) {
1828 tv_std = TV_STD_NTSC;
1829 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1832 tv_std = TV_STD_NTSC_J;
1833 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1836 tv_std = TV_STD_PAL;
1837 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1840 tv_std = TV_STD_PAL_M;
1841 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1844 tv_std = TV_STD_PAL_N;
1845 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1848 tv_std = TV_STD_PAL_CN;
1849 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1852 tv_std = TV_STD_PAL_60;
1853 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1856 tv_std = TV_STD_SECAM;
1857 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1860 tv_std = TV_STD_NTSC;
1861 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1868 struct radeon_encoder_tv_dac *
1869 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1871 struct drm_device *dev = encoder->base.dev;
1872 struct radeon_device *rdev = dev->dev_private;
1873 struct radeon_mode_info *mode_info = &rdev->mode_info;
1874 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1875 uint16_t data_offset;
1876 struct _COMPASSIONATE_DATA *dac_info;
1879 struct radeon_encoder_tv_dac *tv_dac = NULL;
1881 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1882 &frev, &crev, &data_offset)) {
1884 dac_info = (struct _COMPASSIONATE_DATA *)
1885 ((char *)mode_info->atom_context->bios + data_offset);
1887 tv_dac = malloc(sizeof(struct radeon_encoder_tv_dac),
1888 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1893 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1894 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1895 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1897 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1898 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1899 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1901 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1902 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1903 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1905 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1910 static const char *thermal_controller_names[] = {
1921 static const char *pp_lib_thermal_controller_names[] = {
1943 struct _ATOM_POWERPLAY_INFO info;
1944 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1945 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1946 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1947 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1948 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1951 union pplib_clock_info {
1952 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1953 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1954 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1955 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1956 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1959 union pplib_power_state {
1960 struct _ATOM_PPLIB_STATE v1;
1961 struct _ATOM_PPLIB_STATE_V2 v2;
1964 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1966 u32 misc, u32 misc2)
1968 rdev->pm.power_state[state_index].misc = misc;
1969 rdev->pm.power_state[state_index].misc2 = misc2;
1970 /* order matters! */
1971 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1972 rdev->pm.power_state[state_index].type =
1973 POWER_STATE_TYPE_POWERSAVE;
1974 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1975 rdev->pm.power_state[state_index].type =
1976 POWER_STATE_TYPE_BATTERY;
1977 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1978 rdev->pm.power_state[state_index].type =
1979 POWER_STATE_TYPE_BATTERY;
1980 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1981 rdev->pm.power_state[state_index].type =
1982 POWER_STATE_TYPE_BALANCED;
1983 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1984 rdev->pm.power_state[state_index].type =
1985 POWER_STATE_TYPE_PERFORMANCE;
1986 rdev->pm.power_state[state_index].flags &=
1987 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1989 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1990 rdev->pm.power_state[state_index].type =
1991 POWER_STATE_TYPE_BALANCED;
1992 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1993 rdev->pm.power_state[state_index].type =
1994 POWER_STATE_TYPE_DEFAULT;
1995 rdev->pm.default_power_state_index = state_index;
1996 rdev->pm.power_state[state_index].default_clock_mode =
1997 &rdev->pm.power_state[state_index].clock_info[0];
1998 } else if (state_index == 0) {
1999 rdev->pm.power_state[state_index].clock_info[0].flags |=
2000 RADEON_PM_MODE_NO_DISPLAY;
2004 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2006 struct radeon_mode_info *mode_info = &rdev->mode_info;
2007 u32 misc, misc2 = 0;
2008 int num_modes = 0, i;
2009 int state_index = 0;
2010 struct radeon_i2c_bus_rec i2c_bus;
2011 union power_info *power_info;
2012 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2016 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2017 &frev, &crev, &data_offset))
2019 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2021 /* add the i2c bus for thermal/fan chip */
2022 if ((power_info->info.ucOverdriveThermalController > 0) &&
2023 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2024 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2025 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2026 power_info->info.ucOverdriveControllerAddress >> 1);
2027 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2028 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2030 if (rdev->pm.i2c_bus) {
2031 struct i2c_board_info info = { };
2032 const char *name = thermal_controller_names[power_info->info.
2033 ucOverdriveThermalController];
2034 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2035 strlcpy(info.type, name, sizeof(info.type));
2036 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2038 #endif /* FREEBSD_WIP */
2040 num_modes = power_info->info.ucNumOfPowerModeEntries;
2041 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2042 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2045 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) * num_modes,
2046 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2047 if (!rdev->pm.power_state)
2049 /* last mode is usually default, array is low to high */
2050 for (i = 0; i < num_modes; i++) {
2051 rdev->pm.power_state[state_index].clock_info =
2052 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2053 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2054 if (!rdev->pm.power_state[state_index].clock_info)
2056 rdev->pm.power_state[state_index].num_clock_modes = 1;
2057 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2060 rdev->pm.power_state[state_index].clock_info[0].mclk =
2061 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2062 rdev->pm.power_state[state_index].clock_info[0].sclk =
2063 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2064 /* skip invalid modes */
2065 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2066 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2068 rdev->pm.power_state[state_index].pcie_lanes =
2069 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2070 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2071 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2072 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2073 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2075 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2076 radeon_lookup_gpio(rdev,
2077 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2078 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2082 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2084 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2085 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2087 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2088 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2090 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2091 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2095 rdev->pm.power_state[state_index].clock_info[0].mclk =
2096 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2097 rdev->pm.power_state[state_index].clock_info[0].sclk =
2098 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2099 /* skip invalid modes */
2100 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2101 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2103 rdev->pm.power_state[state_index].pcie_lanes =
2104 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2105 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2106 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2107 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2108 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2109 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2111 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2112 radeon_lookup_gpio(rdev,
2113 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2114 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2115 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2120 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2121 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2123 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2124 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2126 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2127 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2131 rdev->pm.power_state[state_index].clock_info[0].mclk =
2132 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2133 rdev->pm.power_state[state_index].clock_info[0].sclk =
2134 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2135 /* skip invalid modes */
2136 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2137 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2139 rdev->pm.power_state[state_index].pcie_lanes =
2140 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2141 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2142 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2143 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2144 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2145 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2147 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2148 radeon_lookup_gpio(rdev,
2149 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2150 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2151 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2156 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2157 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2160 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2161 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2165 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2168 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2169 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2174 /* last mode is usually default */
2175 if (rdev->pm.default_power_state_index == -1) {
2176 rdev->pm.power_state[state_index - 1].type =
2177 POWER_STATE_TYPE_DEFAULT;
2178 rdev->pm.default_power_state_index = state_index - 1;
2179 rdev->pm.power_state[state_index - 1].default_clock_mode =
2180 &rdev->pm.power_state[state_index - 1].clock_info[0];
2181 rdev->pm.power_state[state_index].flags &=
2182 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2183 rdev->pm.power_state[state_index].misc = 0;
2184 rdev->pm.power_state[state_index].misc2 = 0;
2189 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2190 ATOM_PPLIB_THERMALCONTROLLER *controller)
2192 struct radeon_i2c_bus_rec i2c_bus;
2194 /* add the i2c bus for thermal/fan chip */
2195 if (controller->ucType > 0) {
2196 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2197 DRM_INFO("Internal thermal controller %s fan control\n",
2198 (controller->ucFanParameters &
2199 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2200 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2201 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2202 DRM_INFO("Internal thermal controller %s fan control\n",
2203 (controller->ucFanParameters &
2204 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2205 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2206 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2207 DRM_INFO("Internal thermal controller %s fan control\n",
2208 (controller->ucFanParameters &
2209 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2210 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2211 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2212 DRM_INFO("Internal thermal controller %s fan control\n",
2213 (controller->ucFanParameters &
2214 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2215 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2216 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2217 DRM_INFO("Internal thermal controller %s fan control\n",
2218 (controller->ucFanParameters &
2219 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2220 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2221 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2222 DRM_INFO("Internal thermal controller %s fan control\n",
2223 (controller->ucFanParameters &
2224 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2225 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2226 } else if ((controller->ucType ==
2227 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2228 (controller->ucType ==
2229 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2230 (controller->ucType ==
2231 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2232 DRM_INFO("Special thermal controller config\n");
2233 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2234 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2235 pp_lib_thermal_controller_names[controller->ucType],
2236 controller->ucI2cAddress >> 1,
2237 (controller->ucFanParameters &
2238 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2239 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2240 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2242 if (rdev->pm.i2c_bus) {
2243 struct i2c_board_info info = { };
2244 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2245 info.addr = controller->ucI2cAddress >> 1;
2246 strlcpy(info.type, name, sizeof(info.type));
2247 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2249 #endif /* FREEBSD_WIP */
2251 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2253 controller->ucI2cAddress >> 1,
2254 (controller->ucFanParameters &
2255 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2260 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2261 u16 *vddc, u16 *vddci)
2263 struct radeon_mode_info *mode_info = &rdev->mode_info;
2264 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2267 union firmware_info *firmware_info;
2272 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2273 &frev, &crev, &data_offset)) {
2275 (union firmware_info *)((char *)mode_info->atom_context->bios +
2277 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2278 if ((frev == 2) && (crev >= 2))
2279 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2283 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2284 int state_index, int mode_index,
2285 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2288 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2289 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2292 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2294 rdev->pm.power_state[state_index].misc = misc;
2295 rdev->pm.power_state[state_index].misc2 = misc2;
2296 rdev->pm.power_state[state_index].pcie_lanes =
2297 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2298 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2299 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2300 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2301 rdev->pm.power_state[state_index].type =
2302 POWER_STATE_TYPE_BATTERY;
2304 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2305 rdev->pm.power_state[state_index].type =
2306 POWER_STATE_TYPE_BALANCED;
2308 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2309 rdev->pm.power_state[state_index].type =
2310 POWER_STATE_TYPE_PERFORMANCE;
2312 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2313 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2314 rdev->pm.power_state[state_index].type =
2315 POWER_STATE_TYPE_PERFORMANCE;
2318 rdev->pm.power_state[state_index].flags = 0;
2319 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2320 rdev->pm.power_state[state_index].flags |=
2321 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2322 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2323 rdev->pm.power_state[state_index].type =
2324 POWER_STATE_TYPE_DEFAULT;
2325 rdev->pm.default_power_state_index = state_index;
2326 rdev->pm.power_state[state_index].default_clock_mode =
2327 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2328 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2329 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2330 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2331 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2332 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2333 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2335 /* patch the table values with the default slck/mclk from firmware info */
2336 for (j = 0; j < mode_index; j++) {
2337 rdev->pm.power_state[state_index].clock_info[j].mclk =
2338 rdev->clock.default_mclk;
2339 rdev->pm.power_state[state_index].clock_info[j].sclk =
2340 rdev->clock.default_sclk;
2342 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2349 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2350 int state_index, int mode_index,
2351 union pplib_clock_info *clock_info)
2356 if (rdev->flags & RADEON_IS_IGP) {
2357 if (rdev->family >= CHIP_PALM) {
2358 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2359 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2360 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2362 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2363 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2364 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2366 } else if (ASIC_IS_DCE6(rdev)) {
2367 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2368 sclk |= clock_info->si.ucEngineClockHigh << 16;
2369 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2370 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2371 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2372 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2373 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2375 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2376 le16_to_cpu(clock_info->si.usVDDC);
2377 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2378 le16_to_cpu(clock_info->si.usVDDCI);
2379 } else if (ASIC_IS_DCE4(rdev)) {
2380 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2381 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2382 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2383 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2384 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2385 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2386 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2388 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2389 le16_to_cpu(clock_info->evergreen.usVDDC);
2390 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2391 le16_to_cpu(clock_info->evergreen.usVDDCI);
2393 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2394 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2395 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2396 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2397 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2398 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2399 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2401 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2402 le16_to_cpu(clock_info->r600.usVDDC);
2405 /* patch up vddc if necessary */
2406 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2407 case ATOM_VIRTUAL_VOLTAGE_ID0:
2408 case ATOM_VIRTUAL_VOLTAGE_ID1:
2409 case ATOM_VIRTUAL_VOLTAGE_ID2:
2410 case ATOM_VIRTUAL_VOLTAGE_ID3:
2411 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2412 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2414 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2420 if (rdev->flags & RADEON_IS_IGP) {
2421 /* skip invalid modes */
2422 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2425 /* skip invalid modes */
2426 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2427 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2433 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2435 struct radeon_mode_info *mode_info = &rdev->mode_info;
2436 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2437 union pplib_power_state *power_state;
2439 int state_index = 0, mode_index = 0;
2440 union pplib_clock_info *clock_info;
2442 union power_info *power_info;
2443 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2447 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2448 &frev, &crev, &data_offset))
2450 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2452 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2453 if (power_info->pplib.ucNumStates == 0)
2455 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2456 power_info->pplib.ucNumStates,
2457 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2458 if (!rdev->pm.power_state)
2460 /* first mode is usually default, followed by low to high */
2461 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2463 power_state = (union pplib_power_state *)
2464 ((char *)mode_info->atom_context->bios + data_offset +
2465 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2466 i * power_info->pplib.ucStateEntrySize);
2467 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2468 ((char *)mode_info->atom_context->bios + data_offset +
2469 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2470 (power_state->v1.ucNonClockStateIndex *
2471 power_info->pplib.ucNonClockSize));
2472 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2473 ((power_info->pplib.ucStateEntrySize - 1) ?
2474 (power_info->pplib.ucStateEntrySize - 1) : 1),
2475 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2476 if (!rdev->pm.power_state[i].clock_info)
2478 if (power_info->pplib.ucStateEntrySize - 1) {
2479 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2480 clock_info = (union pplib_clock_info *)
2481 ((char *)mode_info->atom_context->bios + data_offset +
2482 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2483 (power_state->v1.ucClockStateIndices[j] *
2484 power_info->pplib.ucClockInfoSize));
2485 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2486 state_index, mode_index,
2492 rdev->pm.power_state[state_index].clock_info[0].mclk =
2493 rdev->clock.default_mclk;
2494 rdev->pm.power_state[state_index].clock_info[0].sclk =
2495 rdev->clock.default_sclk;
2498 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2500 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2505 /* if multiple clock modes, mark the lowest as no display */
2506 for (i = 0; i < state_index; i++) {
2507 if (rdev->pm.power_state[i].num_clock_modes > 1)
2508 rdev->pm.power_state[i].clock_info[0].flags |=
2509 RADEON_PM_MODE_NO_DISPLAY;
2511 /* first mode is usually default */
2512 if (rdev->pm.default_power_state_index == -1) {
2513 rdev->pm.power_state[0].type =
2514 POWER_STATE_TYPE_DEFAULT;
2515 rdev->pm.default_power_state_index = 0;
2516 rdev->pm.power_state[0].default_clock_mode =
2517 &rdev->pm.power_state[0].clock_info[0];
2522 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2524 struct radeon_mode_info *mode_info = &rdev->mode_info;
2525 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2526 union pplib_power_state *power_state;
2527 int i, j, non_clock_array_index, clock_array_index;
2528 int state_index = 0, mode_index = 0;
2529 union pplib_clock_info *clock_info;
2530 struct _StateArray *state_array;
2531 struct _ClockInfoArray *clock_info_array;
2532 struct _NonClockInfoArray *non_clock_info_array;
2534 union power_info *power_info;
2535 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2538 u8 *power_state_offset;
2540 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2541 &frev, &crev, &data_offset))
2543 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2545 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2546 state_array = (struct _StateArray *)
2547 ((char *)mode_info->atom_context->bios + data_offset +
2548 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2549 clock_info_array = (struct _ClockInfoArray *)
2550 ((char *)mode_info->atom_context->bios + data_offset +
2551 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2552 non_clock_info_array = (struct _NonClockInfoArray *)
2553 ((char *)mode_info->atom_context->bios + data_offset +
2554 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2555 if (state_array->ucNumEntries == 0)
2557 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2558 state_array->ucNumEntries,
2559 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2560 if (!rdev->pm.power_state)
2562 power_state_offset = (u8 *)state_array->states;
2563 for (i = 0; i < state_array->ucNumEntries; i++) {
2565 power_state = (union pplib_power_state *)power_state_offset;
2566 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2567 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2568 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2569 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2570 (power_state->v2.ucNumDPMLevels ?
2571 power_state->v2.ucNumDPMLevels : 1),
2572 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2573 if (!rdev->pm.power_state[i].clock_info)
2575 if (power_state->v2.ucNumDPMLevels) {
2576 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2577 clock_array_index = power_state->v2.clockInfoIndex[j];
2578 clock_info = (union pplib_clock_info *)
2579 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2580 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2581 state_index, mode_index,
2587 rdev->pm.power_state[state_index].clock_info[0].mclk =
2588 rdev->clock.default_mclk;
2589 rdev->pm.power_state[state_index].clock_info[0].sclk =
2590 rdev->clock.default_sclk;
2593 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2595 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2599 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2601 /* if multiple clock modes, mark the lowest as no display */
2602 for (i = 0; i < state_index; i++) {
2603 if (rdev->pm.power_state[i].num_clock_modes > 1)
2604 rdev->pm.power_state[i].clock_info[0].flags |=
2605 RADEON_PM_MODE_NO_DISPLAY;
2607 /* first mode is usually default */
2608 if (rdev->pm.default_power_state_index == -1) {
2609 rdev->pm.power_state[0].type =
2610 POWER_STATE_TYPE_DEFAULT;
2611 rdev->pm.default_power_state_index = 0;
2612 rdev->pm.power_state[0].default_clock_mode =
2613 &rdev->pm.power_state[0].clock_info[0];
2618 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2620 struct radeon_mode_info *mode_info = &rdev->mode_info;
2621 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2624 int state_index = 0;
2626 rdev->pm.default_power_state_index = -1;
2628 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2629 &frev, &crev, &data_offset)) {
2634 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2638 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2641 state_index = radeon_atombios_parse_power_table_6(rdev);
2648 if (state_index == 0) {
2649 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state),
2650 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2651 if (rdev->pm.power_state) {
2652 rdev->pm.power_state[0].clock_info =
2653 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2654 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2655 if (rdev->pm.power_state[0].clock_info) {
2656 /* add the default mode */
2657 rdev->pm.power_state[state_index].type =
2658 POWER_STATE_TYPE_DEFAULT;
2659 rdev->pm.power_state[state_index].num_clock_modes = 1;
2660 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2661 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2662 rdev->pm.power_state[state_index].default_clock_mode =
2663 &rdev->pm.power_state[state_index].clock_info[0];
2664 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2665 rdev->pm.power_state[state_index].pcie_lanes = 16;
2666 rdev->pm.default_power_state_index = state_index;
2667 rdev->pm.power_state[state_index].flags = 0;
2673 rdev->pm.num_power_states = state_index;
2675 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2676 rdev->pm.current_clock_mode_index = 0;
2677 if (rdev->pm.default_power_state_index >= 0)
2678 rdev->pm.current_vddc =
2679 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2681 rdev->pm.current_vddc = 0;
2684 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2686 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2687 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2689 args.ucEnable = enable;
2691 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2694 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2696 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2697 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2699 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2700 return le32_to_cpu(args.ulReturnEngineClock);
2703 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2705 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2706 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2708 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2709 return le32_to_cpu(args.ulReturnMemoryClock);
2712 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2715 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2716 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2718 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2720 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2723 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2726 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2727 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2729 if (rdev->flags & RADEON_IS_IGP)
2732 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2734 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2738 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2739 struct _SET_VOLTAGE_PARAMETERS v1;
2740 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2741 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2744 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2746 union set_voltage args;
2747 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2748 u8 frev, crev, volt_index = voltage_level;
2750 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2753 /* 0xff01 is a flag rather then an actual voltage */
2754 if (voltage_level == 0xff01)
2759 args.v1.ucVoltageType = voltage_type;
2760 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2761 args.v1.ucVoltageIndex = volt_index;
2764 args.v2.ucVoltageType = voltage_type;
2765 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2766 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2769 args.v3.ucVoltageType = voltage_type;
2770 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2771 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2774 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2778 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2781 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2782 u16 voltage_id, u16 *voltage)
2784 union set_voltage args;
2785 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2795 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2796 args.v2.ucVoltageMode = 0;
2797 args.v2.usVoltageLevel = 0;
2799 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2801 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2804 args.v3.ucVoltageType = voltage_type;
2805 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2806 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2808 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2810 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2813 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2820 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2822 struct radeon_device *rdev = dev->dev_private;
2823 uint32_t bios_2_scratch, bios_6_scratch;
2825 if (rdev->family >= CHIP_R600) {
2826 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2827 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2829 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2830 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2833 /* let the bios control the backlight */
2834 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2836 /* tell the bios not to handle mode switching */
2837 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2839 if (rdev->family >= CHIP_R600) {
2840 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2841 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2843 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2844 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2849 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2851 uint32_t scratch_reg;
2854 if (rdev->family >= CHIP_R600)
2855 scratch_reg = R600_BIOS_0_SCRATCH;
2857 scratch_reg = RADEON_BIOS_0_SCRATCH;
2859 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2860 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2863 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2865 uint32_t scratch_reg;
2868 if (rdev->family >= CHIP_R600)
2869 scratch_reg = R600_BIOS_0_SCRATCH;
2871 scratch_reg = RADEON_BIOS_0_SCRATCH;
2873 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2874 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2877 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2879 struct drm_device *dev = encoder->dev;
2880 struct radeon_device *rdev = dev->dev_private;
2881 uint32_t bios_6_scratch;
2883 if (rdev->family >= CHIP_R600)
2884 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2886 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2889 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2890 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2892 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2893 bios_6_scratch |= ATOM_S6_ACC_MODE;
2896 if (rdev->family >= CHIP_R600)
2897 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2899 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2902 /* at some point we may want to break this out into individual functions */
2904 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2905 struct drm_encoder *encoder,
2908 struct drm_device *dev = connector->dev;
2909 struct radeon_device *rdev = dev->dev_private;
2910 struct radeon_connector *radeon_connector =
2911 to_radeon_connector(connector);
2912 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2913 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2915 if (rdev->family >= CHIP_R600) {
2916 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2917 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2918 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2920 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2921 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2922 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2925 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2926 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2928 DRM_DEBUG_KMS("TV1 connected\n");
2929 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2930 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2932 DRM_DEBUG_KMS("TV1 disconnected\n");
2933 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2934 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2935 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2938 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2939 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2941 DRM_DEBUG_KMS("CV connected\n");
2942 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2943 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2945 DRM_DEBUG_KMS("CV disconnected\n");
2946 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2947 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2948 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2951 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2952 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2954 DRM_DEBUG_KMS("LCD1 connected\n");
2955 bios_0_scratch |= ATOM_S0_LCD1;
2956 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2957 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2959 DRM_DEBUG_KMS("LCD1 disconnected\n");
2960 bios_0_scratch &= ~ATOM_S0_LCD1;
2961 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2962 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2965 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2966 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2968 DRM_DEBUG_KMS("CRT1 connected\n");
2969 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2970 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2971 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2973 DRM_DEBUG_KMS("CRT1 disconnected\n");
2974 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2975 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2976 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2979 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2980 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2982 DRM_DEBUG_KMS("CRT2 connected\n");
2983 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2984 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2985 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2987 DRM_DEBUG_KMS("CRT2 disconnected\n");
2988 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2989 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2990 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2993 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2994 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2996 DRM_DEBUG_KMS("DFP1 connected\n");
2997 bios_0_scratch |= ATOM_S0_DFP1;
2998 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2999 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
3001 DRM_DEBUG_KMS("DFP1 disconnected\n");
3002 bios_0_scratch &= ~ATOM_S0_DFP1;
3003 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
3004 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
3007 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3008 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3010 DRM_DEBUG_KMS("DFP2 connected\n");
3011 bios_0_scratch |= ATOM_S0_DFP2;
3012 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
3013 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
3015 DRM_DEBUG_KMS("DFP2 disconnected\n");
3016 bios_0_scratch &= ~ATOM_S0_DFP2;
3017 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
3018 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
3021 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
3022 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
3024 DRM_DEBUG_KMS("DFP3 connected\n");
3025 bios_0_scratch |= ATOM_S0_DFP3;
3026 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
3027 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
3029 DRM_DEBUG_KMS("DFP3 disconnected\n");
3030 bios_0_scratch &= ~ATOM_S0_DFP3;
3031 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
3032 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
3035 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3036 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3038 DRM_DEBUG_KMS("DFP4 connected\n");
3039 bios_0_scratch |= ATOM_S0_DFP4;
3040 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3041 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3043 DRM_DEBUG_KMS("DFP4 disconnected\n");
3044 bios_0_scratch &= ~ATOM_S0_DFP4;
3045 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3046 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3049 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3050 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3052 DRM_DEBUG_KMS("DFP5 connected\n");
3053 bios_0_scratch |= ATOM_S0_DFP5;
3054 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3055 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3057 DRM_DEBUG_KMS("DFP5 disconnected\n");
3058 bios_0_scratch &= ~ATOM_S0_DFP5;
3059 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3060 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3063 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3064 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3066 DRM_DEBUG_KMS("DFP6 connected\n");
3067 bios_0_scratch |= ATOM_S0_DFP6;
3068 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3069 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3071 DRM_DEBUG_KMS("DFP6 disconnected\n");
3072 bios_0_scratch &= ~ATOM_S0_DFP6;
3073 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3074 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3078 if (rdev->family >= CHIP_R600) {
3079 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3080 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3081 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3083 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3084 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3085 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3090 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3092 struct drm_device *dev = encoder->dev;
3093 struct radeon_device *rdev = dev->dev_private;
3094 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3095 uint32_t bios_3_scratch;
3097 if (ASIC_IS_DCE4(rdev))
3100 if (rdev->family >= CHIP_R600)
3101 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3103 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3105 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3106 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3107 bios_3_scratch |= (crtc << 18);
3109 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3110 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3111 bios_3_scratch |= (crtc << 24);
3113 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3114 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3115 bios_3_scratch |= (crtc << 16);
3117 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3118 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3119 bios_3_scratch |= (crtc << 20);
3121 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3122 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3123 bios_3_scratch |= (crtc << 17);
3125 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3126 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3127 bios_3_scratch |= (crtc << 19);
3129 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3130 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3131 bios_3_scratch |= (crtc << 23);
3133 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3134 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3135 bios_3_scratch |= (crtc << 25);
3138 if (rdev->family >= CHIP_R600)
3139 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3141 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3145 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3147 struct drm_device *dev = encoder->dev;
3148 struct radeon_device *rdev = dev->dev_private;
3149 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3150 uint32_t bios_2_scratch;
3152 if (ASIC_IS_DCE4(rdev))
3155 if (rdev->family >= CHIP_R600)
3156 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3158 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3160 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3162 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3164 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3166 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3168 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3170 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3172 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3174 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3176 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3178 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3180 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3182 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3184 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3186 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3188 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3190 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3192 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3194 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3196 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3198 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3200 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3202 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3204 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3206 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3208 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3210 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3212 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3214 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3216 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3218 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3221 if (rdev->family >= CHIP_R600)
3222 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3224 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);