2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include "radeon_reg.h"
41 /* If you boot an IGP board with a discrete card as the primary,
42 * the IGP rom is not accessible via the rom bar as the IGP rom is
43 * part of the system bios. On boot, the system bios puts a
44 * copy of the igp rom at the start of vram if a discrete card is
47 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
49 struct drm_local_map bios_map;
50 uint8_t __iomem *bios;
51 resource_size_t vram_base;
52 resource_size_t size = 256 * 1024; /* ??? */
54 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__);
56 if (!(rdev->flags & RADEON_IS_IGP))
57 if (!radeon_card_posted(rdev)) {
58 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n",
64 vram_base = drm_get_resource_start(rdev->ddev, 0);
65 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base);
67 bios_map.offset = vram_base;
72 drm_core_ioremap(&bios_map, rdev->ddev);
73 if (bios_map.handle == NULL) {
74 DRM_INFO("%s: failed to ioremap\n", __func__);
77 bios = bios_map.handle;
79 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size);
81 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
83 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
85 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
86 __func__, bios[0], bios[1]);
88 drm_core_ioremapfree(&bios_map, rdev->ddev);
91 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_NOWAIT);
92 if (rdev->bios == NULL) {
93 drm_core_ioremapfree(&bios_map, rdev->ddev);
96 memcpy_fromio(rdev->bios, bios, size);
97 drm_core_ioremapfree(&bios_map, rdev->ddev);
101 static bool radeon_read_bios(struct radeon_device *rdev)
104 uint8_t __iomem *bios;
107 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__);
109 vga_dev = device_get_parent(rdev->dev);
111 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
112 bios = vga_pci_map_bios(vga_dev, &size);
116 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size);
118 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
120 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
122 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
123 __func__, bios[0], bios[1]);
125 vga_pci_unmap_bios(vga_dev, bios);
128 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_NOWAIT);
129 if (rdev->bios == NULL) {
130 vga_pci_unmap_bios(vga_dev, bios);
133 memcpy(rdev->bios, bios, size);
134 vga_pci_unmap_bios(vga_dev, bios);
139 /* ATRM is used to get the BIOS on the discrete cards in
142 /* retrieve the ROM in 4k blocks */
143 #define ATRM_BIOS_PAGE 4096
145 * radeon_atrm_call - fetch a chunk of the vbios
147 * @atrm_handle: acpi ATRM handle
148 * @bios: vbios image pointer
149 * @offset: offset of vbios image data to fetch
150 * @len: length of vbios image data to fetch
152 * Executes ATRM to fetch a chunk of the discrete
153 * vbios image on PX systems (all asics).
154 * Returns the length of the buffer fetched.
156 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
160 ACPI_OBJECT atrm_arg_elements[2], *obj;
161 ACPI_OBJECT_LIST atrm_arg;
162 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
165 atrm_arg.Pointer = &atrm_arg_elements[0];
167 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
168 atrm_arg_elements[0].Integer.Value = offset;
170 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
171 atrm_arg_elements[1].Integer.Value = len;
173 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
174 if (ACPI_FAILURE(status)) {
175 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
179 obj = (ACPI_OBJECT *)buffer.Pointer;
180 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
181 len = obj->Buffer.Length;
182 AcpiOsFree(buffer.Pointer);
186 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
189 int size = 256 * 1024;
192 ACPI_HANDLE dhandle, atrm_handle;
196 DRM_INFO("%s: ===> Try ATRM...\n", __func__);
198 /* ATRM is for the discrete card only */
199 if (rdev->flags & RADEON_IS_IGP) {
200 DRM_INFO("%s: IGP card detected, skipping this method...\n",
206 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
207 #endif /* FREEBSD_WIP */
208 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
209 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
214 pci_get_function(dev),
216 pci_get_device(dev));
217 DRM_INFO("%s: Get ACPI device handle\n", __func__);
218 dhandle = acpi_get_handle(dev);
222 #endif /* FREEBSD_WIP */
226 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
227 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
228 if (!ACPI_FAILURE(status)) {
232 #endif /* FREEBSD_WIP */
234 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
235 __func__, AcpiFormatException(status));
242 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_NOWAIT);
244 DRM_ERROR("Unable to allocate bios\n");
248 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
249 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
250 ret = radeon_atrm_call(atrm_handle,
252 (i * ATRM_BIOS_PAGE),
254 if (ret < ATRM_BIOS_PAGE)
258 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
260 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
262 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
263 __func__, rdev->bios[0], rdev->bios[1]);
265 free(rdev->bios, DRM_MEM_DRIVER);
271 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
277 static bool ni_read_disabled_bios(struct radeon_device *rdev)
282 u32 vga_render_control;
286 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
288 bus_cntl = RREG32(R600_BUS_CNTL);
289 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
290 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
291 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
292 rom_cntl = RREG32(R600_ROM_CNTL);
295 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
296 /* Disable VGA mode */
297 WREG32(AVIVO_D1VGA_CONTROL,
298 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
299 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
300 WREG32(AVIVO_D2VGA_CONTROL,
301 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
302 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
303 WREG32(AVIVO_VGA_RENDER_CONTROL,
304 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
305 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
307 r = radeon_read_bios(rdev);
310 WREG32(R600_BUS_CNTL, bus_cntl);
311 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
312 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
313 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
314 WREG32(R600_ROM_CNTL, rom_cntl);
318 static bool r700_read_disabled_bios(struct radeon_device *rdev)
320 uint32_t viph_control;
322 uint32_t d1vga_control;
323 uint32_t d2vga_control;
324 uint32_t vga_render_control;
326 uint32_t cg_spll_func_cntl = 0;
327 uint32_t cg_spll_status;
330 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
332 viph_control = RREG32(RADEON_VIPH_CONTROL);
333 bus_cntl = RREG32(R600_BUS_CNTL);
334 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
335 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
336 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
337 rom_cntl = RREG32(R600_ROM_CNTL);
340 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
342 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
343 /* Disable VGA mode */
344 WREG32(AVIVO_D1VGA_CONTROL,
345 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
346 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
347 WREG32(AVIVO_D2VGA_CONTROL,
348 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
349 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
350 WREG32(AVIVO_VGA_RENDER_CONTROL,
351 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
353 if (rdev->family == CHIP_RV730) {
354 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
356 /* enable bypass mode */
357 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
358 R600_SPLL_BYPASS_EN));
360 /* wait for SPLL_CHG_STATUS to change to 1 */
362 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
363 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
365 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
367 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
369 r = radeon_read_bios(rdev);
372 if (rdev->family == CHIP_RV730) {
373 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
375 /* wait for SPLL_CHG_STATUS to change to 1 */
377 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
378 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
380 WREG32(RADEON_VIPH_CONTROL, viph_control);
381 WREG32(R600_BUS_CNTL, bus_cntl);
382 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
383 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
384 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
385 WREG32(R600_ROM_CNTL, rom_cntl);
389 static bool r600_read_disabled_bios(struct radeon_device *rdev)
391 uint32_t viph_control;
393 uint32_t d1vga_control;
394 uint32_t d2vga_control;
395 uint32_t vga_render_control;
397 uint32_t general_pwrmgt;
398 uint32_t low_vid_lower_gpio_cntl;
399 uint32_t medium_vid_lower_gpio_cntl;
400 uint32_t high_vid_lower_gpio_cntl;
401 uint32_t ctxsw_vid_lower_gpio_cntl;
402 uint32_t lower_gpio_enable;
405 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
407 viph_control = RREG32(RADEON_VIPH_CONTROL);
408 bus_cntl = RREG32(R600_BUS_CNTL);
409 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
410 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
411 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
412 rom_cntl = RREG32(R600_ROM_CNTL);
413 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
414 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
415 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
416 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
417 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
418 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
421 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
423 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
424 /* Disable VGA mode */
425 WREG32(AVIVO_D1VGA_CONTROL,
426 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
427 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
428 WREG32(AVIVO_D2VGA_CONTROL,
429 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
430 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
431 WREG32(AVIVO_VGA_RENDER_CONTROL,
432 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
434 WREG32(R600_ROM_CNTL,
435 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
436 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
437 R600_SCK_OVERWRITE));
439 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
440 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
441 (low_vid_lower_gpio_cntl & ~0x400));
442 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
443 (medium_vid_lower_gpio_cntl & ~0x400));
444 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
445 (high_vid_lower_gpio_cntl & ~0x400));
446 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
447 (ctxsw_vid_lower_gpio_cntl & ~0x400));
448 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
450 r = radeon_read_bios(rdev);
453 WREG32(RADEON_VIPH_CONTROL, viph_control);
454 WREG32(R600_BUS_CNTL, bus_cntl);
455 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
456 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
457 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
458 WREG32(R600_ROM_CNTL, rom_cntl);
459 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
460 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
461 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
462 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
463 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
464 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
468 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
470 uint32_t seprom_cntl1;
471 uint32_t viph_control;
473 uint32_t d1vga_control;
474 uint32_t d2vga_control;
475 uint32_t vga_render_control;
478 uint32_t gpiopad_mask;
481 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
483 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
484 viph_control = RREG32(RADEON_VIPH_CONTROL);
485 bus_cntl = RREG32(RV370_BUS_CNTL);
486 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
487 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
488 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
489 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
490 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
491 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
493 WREG32(RADEON_SEPROM_CNTL1,
494 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
495 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
496 WREG32(RADEON_GPIOPAD_A, 0);
497 WREG32(RADEON_GPIOPAD_EN, 0);
498 WREG32(RADEON_GPIOPAD_MASK, 0);
501 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
504 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
506 /* Disable VGA mode */
507 WREG32(AVIVO_D1VGA_CONTROL,
508 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
509 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
510 WREG32(AVIVO_D2VGA_CONTROL,
511 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
512 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
513 WREG32(AVIVO_VGA_RENDER_CONTROL,
514 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
516 r = radeon_read_bios(rdev);
519 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
520 WREG32(RADEON_VIPH_CONTROL, viph_control);
521 WREG32(RV370_BUS_CNTL, bus_cntl);
522 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
523 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
524 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
525 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
526 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
527 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
531 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
533 uint32_t seprom_cntl1;
534 uint32_t viph_control;
536 uint32_t crtc_gen_cntl;
537 uint32_t crtc2_gen_cntl;
538 uint32_t crtc_ext_cntl;
539 uint32_t fp2_gen_cntl;
542 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
544 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
545 viph_control = RREG32(RADEON_VIPH_CONTROL);
546 if (rdev->flags & RADEON_IS_PCIE)
547 bus_cntl = RREG32(RV370_BUS_CNTL);
549 bus_cntl = RREG32(RADEON_BUS_CNTL);
550 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
552 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
555 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
557 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
558 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
561 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
562 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
565 WREG32(RADEON_SEPROM_CNTL1,
566 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
567 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
570 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
573 if (rdev->flags & RADEON_IS_PCIE)
574 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
576 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
578 /* Turn off mem requests and CRTC for both controllers */
579 WREG32(RADEON_CRTC_GEN_CNTL,
580 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
581 (RADEON_CRTC_DISP_REQ_EN_B |
582 RADEON_CRTC_EXT_DISP_EN)));
583 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
584 WREG32(RADEON_CRTC2_GEN_CNTL,
585 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
586 RADEON_CRTC2_DISP_REQ_EN_B));
589 WREG32(RADEON_CRTC_EXT_CNTL,
590 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
591 (RADEON_CRTC_SYNC_TRISTAT |
592 RADEON_CRTC_DISPLAY_DIS)));
594 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
595 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
598 r = radeon_read_bios(rdev);
601 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
602 WREG32(RADEON_VIPH_CONTROL, viph_control);
603 if (rdev->flags & RADEON_IS_PCIE)
604 WREG32(RV370_BUS_CNTL, bus_cntl);
606 WREG32(RADEON_BUS_CNTL, bus_cntl);
607 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
608 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
609 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
611 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
612 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
613 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
618 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
620 if (rdev->flags & RADEON_IS_IGP)
621 return igp_read_bios_from_vram(rdev);
622 else if (rdev->family >= CHIP_BARTS)
623 return ni_read_disabled_bios(rdev);
624 else if (rdev->family >= CHIP_RV770)
625 return r700_read_disabled_bios(rdev);
626 else if (rdev->family >= CHIP_R600)
627 return r600_read_disabled_bios(rdev);
628 else if (rdev->family >= CHIP_RS600)
629 return avivo_read_disabled_bios(rdev);
631 return legacy_read_disabled_bios(rdev);
635 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
638 ACPI_TABLE_HEADER *hdr;
640 UEFI_ACPI_VFCT *vfct;
641 GOP_VBIOS_CONTENT *vbios;
642 VFCT_IMAGE_HEADER *vhdr;
645 DRM_INFO("%s: ===> Try VFCT...\n", __func__);
647 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
648 status = AcpiGetTable("VFCT", 1, &hdr);
649 if (!ACPI_SUCCESS(status)) {
650 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
651 __func__, AcpiFormatException(status));
654 tbl_size = hdr->Length;
655 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
656 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
660 vfct = (UEFI_ACPI_VFCT *)hdr;
661 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
662 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
666 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
667 vhdr = &vbios->VbiosHeader;
668 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
669 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
670 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
672 if (vhdr->PCIBus != rdev->ddev->pci_bus ||
673 vhdr->PCIDevice != rdev->ddev->pci_slot ||
674 vhdr->PCIFunction != rdev->ddev->pci_func ||
675 vhdr->VendorID != rdev->ddev->pci_vendor ||
676 vhdr->DeviceID != rdev->ddev->pci_device) {
677 DRM_INFO("ACPI VFCT table is not for this card\n");
681 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
682 DRM_ERROR("ACPI VFCT image truncated\n");
686 rdev->bios = malloc(vhdr->ImageLength, DRM_MEM_DRIVER, M_NOWAIT);
688 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
695 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
701 bool radeon_get_bios(struct radeon_device *rdev)
706 r = radeon_atrm_get_bios(rdev);
708 r = radeon_acpi_vfct_bios(rdev);
710 r = igp_read_bios_from_vram(rdev);
712 r = radeon_read_bios(rdev);
714 r = radeon_read_disabled_bios(rdev);
716 if (r == false || rdev->bios == NULL) {
717 DRM_ERROR("Unable to locate a BIOS ROM\n");
721 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
722 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
727 if (RBIOS8(tmp + 0x14) != 0x0) {
728 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
732 rdev->bios_header_start = RBIOS16(0x48);
733 if (!rdev->bios_header_start) {
736 tmp = rdev->bios_header_start + 4;
737 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
738 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
739 rdev->is_atom_bios = true;
741 rdev->is_atom_bios = false;
744 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
747 free(rdev->bios, DRM_MEM_DRIVER);