2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include "radeon_reg.h"
41 /* If you boot an IGP board with a discrete card as the primary,
42 * the IGP rom is not accessible via the rom bar as the IGP rom is
43 * part of the system bios. On boot, the system bios puts a
44 * copy of the igp rom at the start of vram if a discrete card is
47 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
49 drm_local_map_t bios_map;
50 uint8_t __iomem *bios;
51 resource_size_t vram_base;
52 resource_size_t size = 256 * 1024; /* ??? */
54 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__);
56 if (!(rdev->flags & RADEON_IS_IGP))
57 if (!radeon_card_posted(rdev)) {
58 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n",
64 vram_base = drm_get_resource_start(rdev->ddev, 0);
65 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base);
67 bios_map.offset = vram_base;
72 drm_core_ioremap(&bios_map, rdev->ddev);
73 if (bios_map.virtual == NULL) {
74 DRM_INFO("%s: failed to ioremap\n", __func__);
77 bios = bios_map.virtual;
79 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size);
81 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
83 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
85 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
86 __func__, bios[0], bios[1]);
88 drm_core_ioremapfree(&bios_map, rdev->ddev);
91 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK);
92 if (rdev->bios == NULL) {
93 drm_core_ioremapfree(&bios_map, rdev->ddev);
96 memcpy_fromio(rdev->bios, bios, size);
97 drm_core_ioremapfree(&bios_map, rdev->ddev);
101 static bool radeon_read_bios(struct radeon_device *rdev)
104 uint8_t __iomem *bios;
107 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__);
109 vga_dev = device_get_parent(rdev->dev);
111 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
112 bios = vga_pci_map_bios(vga_dev, &size);
116 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size);
118 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
120 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
122 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
123 __func__, bios[0], bios[1]);
125 vga_pci_unmap_bios(vga_dev, bios);
128 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK);
129 memcpy(rdev->bios, bios, size);
130 vga_pci_unmap_bios(vga_dev, bios);
134 /* ATRM is used to get the BIOS on the discrete cards in
137 /* retrieve the ROM in 4k blocks */
138 #define ATRM_BIOS_PAGE 4096
140 * radeon_atrm_call - fetch a chunk of the vbios
142 * @atrm_handle: acpi ATRM handle
143 * @bios: vbios image pointer
144 * @offset: offset of vbios image data to fetch
145 * @len: length of vbios image data to fetch
147 * Executes ATRM to fetch a chunk of the discrete
148 * vbios image on PX systems (all asics).
149 * Returns the length of the buffer fetched.
151 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
155 ACPI_OBJECT atrm_arg_elements[2], *obj;
156 ACPI_OBJECT_LIST atrm_arg;
157 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
160 atrm_arg.Pointer = &atrm_arg_elements[0];
162 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
163 atrm_arg_elements[0].Integer.Value = offset;
165 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
166 atrm_arg_elements[1].Integer.Value = len;
168 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
169 if (ACPI_FAILURE(status)) {
170 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
174 obj = (ACPI_OBJECT *)buffer.Pointer;
175 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
176 len = obj->Buffer.Length;
177 AcpiOsFree(buffer.Pointer);
181 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
184 int size = 256 * 1024;
187 ACPI_HANDLE dhandle, atrm_handle;
191 DRM_INFO("%s: ===> Try ATRM...\n", __func__);
193 /* ATRM is for the discrete card only */
194 if (rdev->flags & RADEON_IS_IGP) {
195 DRM_INFO("%s: IGP card detected, skipping this method...\n",
201 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
202 #endif /* DUMBBELL_WIP */
203 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
204 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
209 pci_get_function(dev),
211 pci_get_device(dev));
212 DRM_INFO("%s: Get ACPI device handle\n", __func__);
213 dhandle = acpi_get_handle(dev);
217 #endif /* DUMBBELL_WIP */
221 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
222 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
223 if (!ACPI_FAILURE(status)) {
227 #endif /* DUMBBELL_WIP */
229 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
230 __func__, AcpiFormatException(status));
237 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK);
239 DRM_ERROR("Unable to allocate bios\n");
243 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
244 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
245 ret = radeon_atrm_call(atrm_handle,
247 (i * ATRM_BIOS_PAGE),
249 if (ret < ATRM_BIOS_PAGE)
253 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
255 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
257 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
258 __func__, rdev->bios[0], rdev->bios[1]);
260 free(rdev->bios, DRM_MEM_DRIVER);
266 static bool ni_read_disabled_bios(struct radeon_device *rdev)
271 u32 vga_render_control;
275 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
277 bus_cntl = RREG32(R600_BUS_CNTL);
278 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
279 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
280 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
281 rom_cntl = RREG32(R600_ROM_CNTL);
284 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
285 /* Disable VGA mode */
286 WREG32(AVIVO_D1VGA_CONTROL,
287 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
288 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
289 WREG32(AVIVO_D2VGA_CONTROL,
290 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
291 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
292 WREG32(AVIVO_VGA_RENDER_CONTROL,
293 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
294 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
296 r = radeon_read_bios(rdev);
299 WREG32(R600_BUS_CNTL, bus_cntl);
300 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
301 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
302 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
303 WREG32(R600_ROM_CNTL, rom_cntl);
307 static bool r700_read_disabled_bios(struct radeon_device *rdev)
309 uint32_t viph_control;
311 uint32_t d1vga_control;
312 uint32_t d2vga_control;
313 uint32_t vga_render_control;
315 uint32_t cg_spll_func_cntl = 0;
316 uint32_t cg_spll_status;
319 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
321 viph_control = RREG32(RADEON_VIPH_CONTROL);
322 bus_cntl = RREG32(R600_BUS_CNTL);
323 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
324 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
325 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
326 rom_cntl = RREG32(R600_ROM_CNTL);
329 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
331 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
332 /* Disable VGA mode */
333 WREG32(AVIVO_D1VGA_CONTROL,
334 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
335 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
336 WREG32(AVIVO_D2VGA_CONTROL,
337 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
338 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
339 WREG32(AVIVO_VGA_RENDER_CONTROL,
340 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
342 if (rdev->family == CHIP_RV730) {
343 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
345 /* enable bypass mode */
346 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
347 R600_SPLL_BYPASS_EN));
349 /* wait for SPLL_CHG_STATUS to change to 1 */
351 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
352 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
354 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
356 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
358 r = radeon_read_bios(rdev);
361 if (rdev->family == CHIP_RV730) {
362 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
364 /* wait for SPLL_CHG_STATUS to change to 1 */
366 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
367 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
369 WREG32(RADEON_VIPH_CONTROL, viph_control);
370 WREG32(R600_BUS_CNTL, bus_cntl);
371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
374 WREG32(R600_ROM_CNTL, rom_cntl);
378 static bool r600_read_disabled_bios(struct radeon_device *rdev)
380 uint32_t viph_control;
382 uint32_t d1vga_control;
383 uint32_t d2vga_control;
384 uint32_t vga_render_control;
386 uint32_t general_pwrmgt;
387 uint32_t low_vid_lower_gpio_cntl;
388 uint32_t medium_vid_lower_gpio_cntl;
389 uint32_t high_vid_lower_gpio_cntl;
390 uint32_t ctxsw_vid_lower_gpio_cntl;
391 uint32_t lower_gpio_enable;
394 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
396 viph_control = RREG32(RADEON_VIPH_CONTROL);
397 bus_cntl = RREG32(R600_BUS_CNTL);
398 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
399 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
400 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
401 rom_cntl = RREG32(R600_ROM_CNTL);
402 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
403 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
404 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
405 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
406 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
407 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
410 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
412 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
413 /* Disable VGA mode */
414 WREG32(AVIVO_D1VGA_CONTROL,
415 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
416 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
417 WREG32(AVIVO_D2VGA_CONTROL,
418 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
419 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
420 WREG32(AVIVO_VGA_RENDER_CONTROL,
421 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
423 WREG32(R600_ROM_CNTL,
424 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
425 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
426 R600_SCK_OVERWRITE));
428 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
429 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
430 (low_vid_lower_gpio_cntl & ~0x400));
431 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
432 (medium_vid_lower_gpio_cntl & ~0x400));
433 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
434 (high_vid_lower_gpio_cntl & ~0x400));
435 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
436 (ctxsw_vid_lower_gpio_cntl & ~0x400));
437 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
439 r = radeon_read_bios(rdev);
442 WREG32(RADEON_VIPH_CONTROL, viph_control);
443 WREG32(R600_BUS_CNTL, bus_cntl);
444 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
445 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
446 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
447 WREG32(R600_ROM_CNTL, rom_cntl);
448 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
449 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
450 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
451 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
452 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
453 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
457 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
459 uint32_t seprom_cntl1;
460 uint32_t viph_control;
462 uint32_t d1vga_control;
463 uint32_t d2vga_control;
464 uint32_t vga_render_control;
467 uint32_t gpiopad_mask;
470 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
472 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
473 viph_control = RREG32(RADEON_VIPH_CONTROL);
474 bus_cntl = RREG32(RV370_BUS_CNTL);
475 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
476 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
477 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
478 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
479 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
480 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
482 WREG32(RADEON_SEPROM_CNTL1,
483 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
484 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
485 WREG32(RADEON_GPIOPAD_A, 0);
486 WREG32(RADEON_GPIOPAD_EN, 0);
487 WREG32(RADEON_GPIOPAD_MASK, 0);
490 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
493 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
495 /* Disable VGA mode */
496 WREG32(AVIVO_D1VGA_CONTROL,
497 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
498 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
499 WREG32(AVIVO_D2VGA_CONTROL,
500 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
501 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
502 WREG32(AVIVO_VGA_RENDER_CONTROL,
503 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
505 r = radeon_read_bios(rdev);
508 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
509 WREG32(RADEON_VIPH_CONTROL, viph_control);
510 WREG32(RV370_BUS_CNTL, bus_cntl);
511 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
512 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
513 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
514 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
515 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
516 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
520 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
522 uint32_t seprom_cntl1;
523 uint32_t viph_control;
525 uint32_t crtc_gen_cntl;
526 uint32_t crtc2_gen_cntl;
527 uint32_t crtc_ext_cntl;
528 uint32_t fp2_gen_cntl;
531 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
533 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
534 viph_control = RREG32(RADEON_VIPH_CONTROL);
535 if (rdev->flags & RADEON_IS_PCIE)
536 bus_cntl = RREG32(RV370_BUS_CNTL);
538 bus_cntl = RREG32(RADEON_BUS_CNTL);
539 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
541 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
544 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
546 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
547 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
550 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
551 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
554 WREG32(RADEON_SEPROM_CNTL1,
555 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
556 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
559 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
562 if (rdev->flags & RADEON_IS_PCIE)
563 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
565 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
567 /* Turn off mem requests and CRTC for both controllers */
568 WREG32(RADEON_CRTC_GEN_CNTL,
569 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
570 (RADEON_CRTC_DISP_REQ_EN_B |
571 RADEON_CRTC_EXT_DISP_EN)));
572 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
573 WREG32(RADEON_CRTC2_GEN_CNTL,
574 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
575 RADEON_CRTC2_DISP_REQ_EN_B));
578 WREG32(RADEON_CRTC_EXT_CNTL,
579 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
580 (RADEON_CRTC_SYNC_TRISTAT |
581 RADEON_CRTC_DISPLAY_DIS)));
583 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
584 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
587 r = radeon_read_bios(rdev);
590 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
591 WREG32(RADEON_VIPH_CONTROL, viph_control);
592 if (rdev->flags & RADEON_IS_PCIE)
593 WREG32(RV370_BUS_CNTL, bus_cntl);
595 WREG32(RADEON_BUS_CNTL, bus_cntl);
596 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
597 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
598 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
600 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
601 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
602 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
607 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
609 if (rdev->flags & RADEON_IS_IGP)
610 return igp_read_bios_from_vram(rdev);
611 else if (rdev->family >= CHIP_BARTS)
612 return ni_read_disabled_bios(rdev);
613 else if (rdev->family >= CHIP_RV770)
614 return r700_read_disabled_bios(rdev);
615 else if (rdev->family >= CHIP_R600)
616 return r600_read_disabled_bios(rdev);
617 else if (rdev->family >= CHIP_RS600)
618 return avivo_read_disabled_bios(rdev);
620 return legacy_read_disabled_bios(rdev);
623 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
626 ACPI_TABLE_HEADER *hdr;
628 UEFI_ACPI_VFCT *vfct;
629 GOP_VBIOS_CONTENT *vbios;
630 VFCT_IMAGE_HEADER *vhdr;
633 DRM_INFO("%s: ===> Try VFCT...\n", __func__);
635 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
636 status = AcpiGetTable("VFCT", 1, &hdr);
637 if (!ACPI_SUCCESS(status)) {
638 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
639 __func__, AcpiFormatException(status));
642 tbl_size = hdr->Length;
643 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
644 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
648 vfct = (UEFI_ACPI_VFCT *)hdr;
649 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
650 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
654 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
655 vhdr = &vbios->VbiosHeader;
656 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
657 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
658 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
660 if (vhdr->PCIBus != rdev->ddev->pci_bus ||
661 vhdr->PCIDevice != rdev->ddev->pci_slot ||
662 vhdr->PCIFunction != rdev->ddev->pci_func ||
663 vhdr->VendorID != rdev->ddev->pci_vendor ||
664 vhdr->DeviceID != rdev->ddev->pci_device) {
665 DRM_INFO("ACPI VFCT table is not for this card\n");
669 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
670 DRM_ERROR("ACPI VFCT image truncated\n");
674 rdev->bios = malloc(vhdr->ImageLength, DRM_MEM_DRIVER, M_WAITOK);
675 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
682 bool radeon_get_bios(struct radeon_device *rdev)
687 r = radeon_atrm_get_bios(rdev);
689 r = radeon_acpi_vfct_bios(rdev);
691 r = igp_read_bios_from_vram(rdev);
693 r = radeon_read_bios(rdev);
695 r = radeon_read_disabled_bios(rdev);
697 if (r == false || rdev->bios == NULL) {
698 DRM_ERROR("Unable to locate a BIOS ROM\n");
702 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
703 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
708 if (RBIOS8(tmp + 0x14) != 0x0) {
709 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
713 rdev->bios_header_start = RBIOS16(0x48);
714 if (!rdev->bios_header_start) {
717 tmp = rdev->bios_header_start + 4;
718 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
719 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
720 rdev->is_atom_bios = true;
722 rdev->is_atom_bios = false;
725 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
728 free(rdev->bios, DRM_MEM_DRIVER);