1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
40 #include <dev/drm2/drmP.h>
41 #include <dev/drm2/radeon/radeon_drm.h>
42 #include "radeon_drv.h"
45 #define RADEON_FIFO_DEBUG 0
48 #define FIRMWARE_R100 "radeonkmsfw_R100_cp"
49 #define FIRMWARE_R200 "radeonkmsfw_R200_cp"
50 #define FIRMWARE_R300 "radeonkmsfw_R300_cp"
51 #define FIRMWARE_R420 "radeonkmsfw_R420_cp"
52 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp"
53 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp"
54 #define FIRMWARE_R520 "radeonkmsfw_R520_cp"
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
66 static int radeon_do_cleanup_cp(struct drm_device * dev);
67 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
69 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
73 if (dev_priv->flags & RADEON_IS_AGP) {
74 val = DRM_READ32(dev_priv->ring_rptr, off);
76 val = *(((volatile u32 *)
77 dev_priv->ring_rptr->handle) +
79 val = le32_to_cpu(val);
84 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
86 if (dev_priv->writeback_works)
87 return radeon_read_ring_rptr(dev_priv, 0);
89 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
90 return RADEON_READ(R600_CP_RB_RPTR);
92 return RADEON_READ(RADEON_CP_RB_RPTR);
96 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
98 if (dev_priv->flags & RADEON_IS_AGP)
99 DRM_WRITE32(dev_priv->ring_rptr, off, val);
101 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
102 (off / sizeof(u32))) = cpu_to_le32(val);
105 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
107 radeon_write_ring_rptr(dev_priv, 0, val);
110 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
112 if (dev_priv->writeback_works) {
113 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
114 return radeon_read_ring_rptr(dev_priv,
115 R600_SCRATCHOFF(index));
117 return radeon_read_ring_rptr(dev_priv,
118 RADEON_SCRATCHOFF(index));
120 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
121 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
123 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
127 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
130 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
131 ret = RADEON_READ(R520_MC_IND_DATA);
132 RADEON_WRITE(R520_MC_IND_INDEX, 0);
136 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
139 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
140 ret = RADEON_READ(RS480_NB_MC_DATA);
141 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
145 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
148 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
149 ret = RADEON_READ(RS690_MC_DATA);
150 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
154 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
157 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
158 RS600_MC_IND_CITF_ARB0));
159 ret = RADEON_READ(RS600_MC_DATA);
163 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
165 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
166 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
167 return RS690_READ_MCIND(dev_priv, addr);
168 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
169 return RS600_READ_MCIND(dev_priv, addr);
171 return RS480_READ_MCIND(dev_priv, addr);
174 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
177 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
178 return RADEON_READ(R700_MC_VM_FB_LOCATION);
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
180 return RADEON_READ(R600_MC_VM_FB_LOCATION);
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
182 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
183 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
185 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
186 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
187 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
188 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
189 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
191 return RADEON_READ(RADEON_MC_FB_LOCATION);
194 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
196 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
197 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
199 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
201 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
202 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
203 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
204 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
205 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
206 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
207 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
208 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
210 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
213 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
215 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
216 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
217 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
218 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
219 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
220 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
221 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
222 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
223 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
224 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
225 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
226 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
227 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
228 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
229 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
230 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
232 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
235 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
237 u32 agp_base_hi = upper_32_bits(agp_base);
238 u32 agp_base_lo = agp_base & 0xffffffff;
239 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
241 /* R6xx/R7xx must be aligned to a 4MB boundary */
242 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
243 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
244 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
245 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
246 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
247 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
248 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
249 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
250 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
251 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
252 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
253 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
254 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
255 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
256 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
257 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
258 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
259 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
260 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
261 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
262 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
264 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
265 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
266 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
270 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
273 /* Turn on bus mastering */
274 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
276 /* rs600/rs690/rs740 */
277 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
278 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
279 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
280 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
282 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
283 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
284 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
285 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
286 } /* PCIE cards appears to not need this */
289 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
291 drm_radeon_private_t *dev_priv = dev->dev_private;
293 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
294 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
297 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
299 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
300 return RADEON_READ(RADEON_PCIE_DATA);
303 #if RADEON_FIFO_DEBUG
304 static void radeon_status(drm_radeon_private_t * dev_priv)
306 printk("%s:\n", __func__);
307 printk("RBBM_STATUS = 0x%08x\n",
308 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
309 printk("CP_RB_RTPR = 0x%08x\n",
310 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
311 printk("CP_RB_WTPR = 0x%08x\n",
312 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
313 printk("AIC_CNTL = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
315 printk("AIC_STAT = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
317 printk("AIC_PT_BASE = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
319 printk("TLB_ADDR = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
321 printk("TLB_DATA = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
326 /* ================================================================
327 * Engine, FIFO control
330 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
335 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
337 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
338 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
339 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
340 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
342 for (i = 0; i < dev_priv->usec_timeout; i++) {
343 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
344 & RADEON_RB3D_DC_BUSY)) {
350 /* don't flush or purge cache here or lockup */
354 #if RADEON_FIFO_DEBUG
355 DRM_ERROR("failed!\n");
356 radeon_status(dev_priv);
361 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
365 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
367 for (i = 0; i < dev_priv->usec_timeout; i++) {
368 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
369 & RADEON_RBBM_FIFOCNT_MASK);
370 if (slots >= entries)
374 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
375 RADEON_READ(RADEON_RBBM_STATUS),
376 RADEON_READ(R300_VAP_CNTL_STATUS));
378 #if RADEON_FIFO_DEBUG
379 DRM_ERROR("failed!\n");
380 radeon_status(dev_priv);
385 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
389 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
391 ret = radeon_do_wait_for_fifo(dev_priv, 64);
395 for (i = 0; i < dev_priv->usec_timeout; i++) {
396 if (!(RADEON_READ(RADEON_RBBM_STATUS)
397 & RADEON_RBBM_ACTIVE)) {
398 radeon_do_pixcache_flush(dev_priv);
403 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
404 RADEON_READ(RADEON_RBBM_STATUS),
405 RADEON_READ(R300_VAP_CNTL_STATUS));
407 #if RADEON_FIFO_DEBUG
408 DRM_ERROR("failed!\n");
409 radeon_status(dev_priv);
414 static void radeon_init_pipes(struct drm_device *dev)
416 drm_radeon_private_t *dev_priv = dev->dev_private;
417 uint32_t gb_tile_config, gb_pipe_sel = 0;
419 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
420 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
421 if ((z_pipe_sel & 3) == 3)
422 dev_priv->num_z_pipes = 2;
424 dev_priv->num_z_pipes = 1;
426 dev_priv->num_z_pipes = 1;
428 /* RS4xx/RS6xx/R4xx/R5xx */
429 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
430 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
431 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
432 /* SE cards have 1 pipe */
433 if ((dev->pci_device == 0x5e4c) ||
434 (dev->pci_device == 0x5e4f))
435 dev_priv->num_gb_pipes = 1;
438 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
439 dev->pci_device != 0x4144) ||
440 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
441 dev->pci_device != 0x4148)) {
442 dev_priv->num_gb_pipes = 2;
444 /* RV3xx/R300 AD/R350 AH */
445 dev_priv->num_gb_pipes = 1;
448 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
450 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
452 switch (dev_priv->num_gb_pipes) {
453 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
454 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
455 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
457 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
460 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
461 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
462 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
464 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
465 radeon_do_wait_for_idle(dev_priv);
466 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
467 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
468 R300_DC_AUTOFLUSH_ENABLE |
469 R300_DC_DC_DISABLE_IGNORE_PE));
474 /* ================================================================
475 * CP control, initialization
478 /* Load the microcode for the CP */
479 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
481 const char *fw_name = NULL;
486 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
487 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
488 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
491 DRM_INFO("Loading R100 Microcode\n");
492 fw_name = FIRMWARE_R100;
493 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
497 DRM_INFO("Loading R200 Microcode\n");
498 fw_name = FIRMWARE_R200;
499 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
500 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
505 DRM_INFO("Loading R300 Microcode\n");
506 fw_name = FIRMWARE_R300;
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
510 DRM_INFO("Loading R400 Microcode\n");
511 fw_name = FIRMWARE_R420;
512 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
513 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
514 DRM_INFO("Loading RS690/RS740 Microcode\n");
515 fw_name = FIRMWARE_RS690;
516 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
517 DRM_INFO("Loading RS600 Microcode\n");
518 fw_name = FIRMWARE_RS600;
519 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
520 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
521 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
525 DRM_INFO("Loading R500 Microcode\n");
526 fw_name = FIRMWARE_R520;
531 dev_priv->me_fw = firmware_get(fw_name);
532 if (dev_priv->me_fw == NULL) {
534 DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n",
536 } else if (dev_priv->me_fw->datasize % 8) {
538 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
539 dev_priv->me_fw->datasize, fw_name);
541 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
542 dev_priv->me_fw = NULL;
547 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
549 const __be32 *fw_data;
552 radeon_do_wait_for_idle(dev_priv);
554 if (dev_priv->me_fw) {
555 size = dev_priv->me_fw->datasize / 4;
556 fw_data = (const __be32 *)dev_priv->me_fw->data;
557 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
558 for (i = 0; i < size; i += 2) {
559 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
560 be32_to_cpup(&fw_data[i]));
561 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
562 be32_to_cpup(&fw_data[i + 1]));
567 /* Flush any pending commands to the CP. This should only be used just
568 * prior to a wait for idle, as it informs the engine that the command
571 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
577 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31);
578 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
582 /* Wait for the CP to go idle.
584 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
591 RADEON_PURGE_CACHE();
592 RADEON_PURGE_ZCACHE();
593 RADEON_WAIT_UNTIL_IDLE();
598 return radeon_do_wait_for_idle(dev_priv);
601 /* Start the Command Processor.
603 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
608 radeon_do_wait_for_idle(dev_priv);
610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
612 dev_priv->cp_running = 1;
614 /* on r420, any DMA from CP to system memory while 2D is active
615 * can cause a hang. workaround is to queue a CP RESYNC token
617 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
620 OUT_RING(5); /* scratch reg 5 */
621 OUT_RING(0xdeadbeef);
627 /* isync can only be written through cp on r5xx write it here */
628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
629 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
630 RADEON_ISYNC_ANY3D_IDLE2D |
631 RADEON_ISYNC_WAIT_IDLEGUI |
632 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
633 RADEON_PURGE_CACHE();
634 RADEON_PURGE_ZCACHE();
635 RADEON_WAIT_UNTIL_IDLE();
639 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
642 /* Reset the Command Processor. This will not flush any pending
643 * commands, so you must wait for the CP command stream to complete
644 * before calling this routine.
646 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
651 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
652 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
653 SET_RING_HEAD(dev_priv, cur_read_ptr);
654 dev_priv->ring.tail = cur_read_ptr;
657 /* Stop the Command Processor. This will not flush any pending
658 * commands, so you must flush the command stream and wait for the CP
659 * to go idle before calling this routine.
661 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
666 /* finish the pending CP_RESYNC token */
667 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
670 OUT_RING(R300_RB3D_DC_FINISH);
673 radeon_do_wait_for_idle(dev_priv);
676 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
678 dev_priv->cp_running = 0;
681 /* Reset the engine. This will stop the CP if it is running.
683 static int radeon_do_engine_reset(struct drm_device * dev)
685 drm_radeon_private_t *dev_priv = dev->dev_private;
686 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
689 radeon_do_pixcache_flush(dev_priv);
691 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
692 /* may need something similar for newer chips */
693 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
694 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
696 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
697 RADEON_FORCEON_MCLKA |
698 RADEON_FORCEON_MCLKB |
699 RADEON_FORCEON_YCLKA |
700 RADEON_FORCEON_YCLKB |
702 RADEON_FORCEON_AIC));
705 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
707 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
708 RADEON_SOFT_RESET_CP |
709 RADEON_SOFT_RESET_HI |
710 RADEON_SOFT_RESET_SE |
711 RADEON_SOFT_RESET_RE |
712 RADEON_SOFT_RESET_PP |
713 RADEON_SOFT_RESET_E2 |
714 RADEON_SOFT_RESET_RB));
715 RADEON_READ(RADEON_RBBM_SOFT_RESET);
716 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
717 ~(RADEON_SOFT_RESET_CP |
718 RADEON_SOFT_RESET_HI |
719 RADEON_SOFT_RESET_SE |
720 RADEON_SOFT_RESET_RE |
721 RADEON_SOFT_RESET_PP |
722 RADEON_SOFT_RESET_E2 |
723 RADEON_SOFT_RESET_RB)));
724 RADEON_READ(RADEON_RBBM_SOFT_RESET);
726 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
727 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
728 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
729 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
732 /* setup the raster pipes */
733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
734 radeon_init_pipes(dev);
736 /* Reset the CP ring */
737 radeon_do_cp_reset(dev_priv);
739 /* The CP is no longer running after an engine reset */
740 dev_priv->cp_running = 0;
742 /* Reset any pending vertex, indirect buffers */
743 radeon_freelist_reset(dev);
748 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
749 drm_radeon_private_t *dev_priv,
750 struct drm_file *file_priv)
752 struct drm_radeon_master_private *master_priv;
753 u32 ring_start, cur_read_ptr;
755 /* Initialize the memory controller. With new memory map, the fb location
756 * is not changed, it should have been properly initialized already. Part
757 * of the problem is that the code below is bogus, assuming the GART is
758 * always appended to the fb which is not necessarily the case
760 if (!dev_priv->new_memmap)
761 radeon_write_fb_location(dev_priv,
762 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
763 | (dev_priv->fb_location >> 16));
766 if (dev_priv->flags & RADEON_IS_AGP) {
767 radeon_write_agp_base(dev_priv, dev->agp->base);
769 radeon_write_agp_location(dev_priv,
770 (((dev_priv->gart_vm_start - 1 +
771 dev_priv->gart_size) & 0xffff0000) |
772 (dev_priv->gart_vm_start >> 16)));
774 ring_start = (dev_priv->cp_ring->offset
776 + dev_priv->gart_vm_start);
779 ring_start = (dev_priv->cp_ring->offset
780 - (unsigned long)dev->sg->vaddr
781 + dev_priv->gart_vm_start);
783 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
785 /* Set the write pointer delay */
786 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
788 /* Initialize the ring buffer's read and write pointers */
789 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
790 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
791 SET_RING_HEAD(dev_priv, cur_read_ptr);
792 dev_priv->ring.tail = cur_read_ptr;
795 if (dev_priv->flags & RADEON_IS_AGP) {
796 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
797 dev_priv->ring_rptr->offset
798 - dev->agp->base + dev_priv->gart_vm_start);
802 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
803 dev_priv->ring_rptr->offset
804 - ((unsigned long) dev->sg->vaddr)
805 + dev_priv->gart_vm_start);
808 /* Set ring buffer size */
810 RADEON_WRITE(RADEON_CP_RB_CNTL,
811 RADEON_BUF_SWAP_32BIT |
812 (dev_priv->ring.fetch_size_l2ow << 18) |
813 (dev_priv->ring.rptr_update_l2qw << 8) |
814 dev_priv->ring.size_l2qw);
816 RADEON_WRITE(RADEON_CP_RB_CNTL,
817 (dev_priv->ring.fetch_size_l2ow << 18) |
818 (dev_priv->ring.rptr_update_l2qw << 8) |
819 dev_priv->ring.size_l2qw);
823 /* Initialize the scratch register pointer. This will cause
824 * the scratch register values to be written out to memory
825 * whenever they are updated.
827 * We simply put this behind the ring read pointer, this works
828 * with PCI GART as well as (whatever kind of) AGP GART
830 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
831 + RADEON_SCRATCH_REG_OFFSET);
833 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
835 radeon_enable_bm(dev_priv);
837 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
838 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
840 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
841 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
843 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
844 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
846 /* reset sarea copies of these */
847 master_priv = file_priv->master->driver_priv;
848 if (master_priv->sarea_priv) {
849 master_priv->sarea_priv->last_frame = 0;
850 master_priv->sarea_priv->last_dispatch = 0;
851 master_priv->sarea_priv->last_clear = 0;
854 radeon_do_wait_for_idle(dev_priv);
856 /* Sync everything up */
857 RADEON_WRITE(RADEON_ISYNC_CNTL,
858 (RADEON_ISYNC_ANY2D_IDLE3D |
859 RADEON_ISYNC_ANY3D_IDLE2D |
860 RADEON_ISYNC_WAIT_IDLEGUI |
861 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
865 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
869 /* Start with assuming that writeback doesn't work */
870 dev_priv->writeback_works = 0;
872 /* Writeback doesn't seem to work everywhere, test it here and possibly
873 * enable it if it appears to work
875 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
877 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
879 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
882 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
883 if (val == 0xdeadbeef)
888 if (tmp < dev_priv->usec_timeout) {
889 dev_priv->writeback_works = 1;
890 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
892 dev_priv->writeback_works = 0;
893 DRM_INFO("writeback test failed\n");
895 if (radeon_no_wb == 1) {
896 dev_priv->writeback_works = 0;
897 DRM_INFO("writeback forced off\n");
900 if (!dev_priv->writeback_works) {
901 /* Disable writeback to avoid unnecessary bus master transfer */
902 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
903 RADEON_RB_NO_UPDATE);
904 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
908 /* Enable or disable IGP GART on the chip */
909 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
914 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
915 dev_priv->gart_vm_start,
916 (long)dev_priv->gart_info.bus_addr,
917 dev_priv->gart_size);
919 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
920 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
922 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
923 RS690_BLOCK_GFX_D3_EN));
925 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
927 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
928 RS480_VA_SIZE_32MB));
930 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
931 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
936 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
937 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
938 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
940 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
941 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
942 RS480_REQ_TYPE_SNOOP_DIS));
944 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
946 dev_priv->gart_size = 32*1024*1024;
947 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
948 0xffff0000) | (dev_priv->gart_vm_start >> 16));
950 radeon_write_agp_location(dev_priv, temp);
952 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
953 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
954 RS480_VA_SIZE_32MB));
957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
958 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
963 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
964 RS480_GART_CACHE_INVALIDATE);
967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
968 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
973 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
975 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
979 /* Enable or disable IGP GART on the chip */
980 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
986 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
987 dev_priv->gart_vm_start,
988 (long)dev_priv->gart_info.bus_addr,
989 dev_priv->gart_size);
991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
992 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
994 for (i = 0; i < 19; i++)
995 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
996 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
997 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
998 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
999 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1000 RS600_ENABLE_FRAGMENT_PROCESSING |
1001 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1003 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1004 RS600_PAGE_TABLE_TYPE_FLAT));
1006 /* disable all other contexts */
1007 for (i = 1; i < 8; i++)
1008 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1010 /* setup the page table aperture */
1011 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1012 dev_priv->gart_info.bus_addr);
1013 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1014 dev_priv->gart_vm_start);
1015 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1016 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1017 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1019 /* setup the system aperture */
1020 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1021 dev_priv->gart_vm_start);
1022 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1023 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1025 /* enable page tables */
1026 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1027 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1029 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1030 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1032 /* invalidate the cache */
1033 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1035 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1036 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1037 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1039 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1040 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1041 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1043 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1044 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1045 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1048 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1049 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1050 temp &= ~RS600_ENABLE_PAGE_TABLES;
1051 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1055 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1057 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1060 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1061 dev_priv->gart_vm_start,
1062 (long)dev_priv->gart_info.bus_addr,
1063 dev_priv->gart_size);
1064 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1065 dev_priv->gart_vm_start);
1066 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1067 dev_priv->gart_info.bus_addr);
1068 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1069 dev_priv->gart_vm_start);
1070 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1071 dev_priv->gart_vm_start +
1072 dev_priv->gart_size - 1);
1074 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1076 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1077 RADEON_PCIE_TX_GART_EN);
1079 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1080 tmp & ~RADEON_PCIE_TX_GART_EN);
1084 /* Enable or disable PCI GART on the chip */
1085 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1089 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1090 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1091 (dev_priv->flags & RADEON_IS_IGPGART)) {
1092 radeon_set_igpgart(dev_priv, on);
1096 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1097 rs600_set_igpgart(dev_priv, on);
1101 if (dev_priv->flags & RADEON_IS_PCIE) {
1102 radeon_set_pciegart(dev_priv, on);
1106 tmp = RADEON_READ(RADEON_AIC_CNTL);
1109 RADEON_WRITE(RADEON_AIC_CNTL,
1110 tmp | RADEON_PCIGART_TRANSLATE_EN);
1112 /* set PCI GART page-table base address
1114 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1116 /* set address range for PCI address translate
1118 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1119 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1120 + dev_priv->gart_size - 1);
1122 /* Turn off AGP aperture -- is this required for PCI GART?
1124 radeon_write_agp_location(dev_priv, 0xffffffc0);
1125 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1127 RADEON_WRITE(RADEON_AIC_CNTL,
1128 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1132 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1134 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1135 struct radeon_virt_surface *vp;
1138 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1139 if (!dev_priv->virt_surfaces[i].file_priv ||
1140 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1143 if (i >= 2 * RADEON_MAX_SURFACES)
1145 vp = &dev_priv->virt_surfaces[i];
1147 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1148 struct radeon_surface *sp = &dev_priv->surfaces[i];
1152 vp->surface_index = i;
1153 vp->lower = gart_info->bus_addr;
1154 vp->upper = vp->lower + gart_info->table_size;
1156 vp->file_priv = PCIGART_FILE_PRIV;
1159 sp->lower = vp->lower;
1160 sp->upper = vp->upper;
1163 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1164 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1165 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1172 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1173 struct drm_file *file_priv)
1175 drm_radeon_private_t *dev_priv = dev->dev_private;
1176 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1180 /* if we require new memory map but we don't have it fail */
1181 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1182 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1183 radeon_do_cleanup_cp(dev);
1187 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1188 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1189 dev_priv->flags &= ~RADEON_IS_AGP;
1190 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1192 DRM_DEBUG("Restoring AGP flag\n");
1193 dev_priv->flags |= RADEON_IS_AGP;
1196 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1197 DRM_ERROR("PCI GART memory not allocated!\n");
1198 radeon_do_cleanup_cp(dev);
1202 dev_priv->usec_timeout = init->usec_timeout;
1203 if (dev_priv->usec_timeout < 1 ||
1204 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1205 DRM_DEBUG("TIMEOUT problem!\n");
1206 radeon_do_cleanup_cp(dev);
1210 /* Enable vblank on CRTC1 for older X servers
1212 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1214 switch(init->func) {
1215 case RADEON_INIT_R200_CP:
1216 dev_priv->microcode_version = UCODE_R200;
1218 case RADEON_INIT_R300_CP:
1219 dev_priv->microcode_version = UCODE_R300;
1222 dev_priv->microcode_version = UCODE_R100;
1225 dev_priv->do_boxes = 0;
1226 dev_priv->cp_mode = init->cp_mode;
1228 /* We don't support anything other than bus-mastering ring mode,
1229 * but the ring can be in either AGP or PCI space for the ring
1232 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1233 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1234 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1235 radeon_do_cleanup_cp(dev);
1239 switch (init->fb_bpp) {
1241 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1245 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1248 dev_priv->front_offset = init->front_offset;
1249 dev_priv->front_pitch = init->front_pitch;
1250 dev_priv->back_offset = init->back_offset;
1251 dev_priv->back_pitch = init->back_pitch;
1253 switch (init->depth_bpp) {
1255 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1259 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1262 dev_priv->depth_offset = init->depth_offset;
1263 dev_priv->depth_pitch = init->depth_pitch;
1265 /* Hardware state for depth clears. Remove this if/when we no
1266 * longer clear the depth buffer with a 3D rectangle. Hard-code
1267 * all values to prevent unwanted 3D state from slipping through
1268 * and screwing with the clear operation.
1270 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1271 (dev_priv->color_fmt << 10) |
1272 (dev_priv->microcode_version ==
1273 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1275 dev_priv->depth_clear.rb3d_zstencilcntl =
1276 (dev_priv->depth_fmt |
1277 RADEON_Z_TEST_ALWAYS |
1278 RADEON_STENCIL_TEST_ALWAYS |
1279 RADEON_STENCIL_S_FAIL_REPLACE |
1280 RADEON_STENCIL_ZPASS_REPLACE |
1281 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1283 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1284 RADEON_BFACE_SOLID |
1285 RADEON_FFACE_SOLID |
1286 RADEON_FLAT_SHADE_VTX_LAST |
1287 RADEON_DIFFUSE_SHADE_FLAT |
1288 RADEON_ALPHA_SHADE_FLAT |
1289 RADEON_SPECULAR_SHADE_FLAT |
1290 RADEON_FOG_SHADE_FLAT |
1291 RADEON_VTX_PIX_CENTER_OGL |
1292 RADEON_ROUND_MODE_TRUNC |
1293 RADEON_ROUND_PREC_8TH_PIX);
1296 dev_priv->ring_offset = init->ring_offset;
1297 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1298 dev_priv->buffers_offset = init->buffers_offset;
1299 dev_priv->gart_textures_offset = init->gart_textures_offset;
1301 master_priv->sarea = drm_getsarea(dev);
1302 if (!master_priv->sarea) {
1303 DRM_ERROR("could not find sarea!\n");
1304 radeon_do_cleanup_cp(dev);
1308 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1309 if (!dev_priv->cp_ring) {
1310 DRM_ERROR("could not find cp ring region!\n");
1311 radeon_do_cleanup_cp(dev);
1314 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1315 if (!dev_priv->ring_rptr) {
1316 DRM_ERROR("could not find ring read pointer!\n");
1317 radeon_do_cleanup_cp(dev);
1320 dev->agp_buffer_token = init->buffers_offset;
1321 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1322 if (!dev->agp_buffer_map) {
1323 DRM_ERROR("could not find dma buffer region!\n");
1324 radeon_do_cleanup_cp(dev);
1328 if (init->gart_textures_offset) {
1329 dev_priv->gart_textures =
1330 drm_core_findmap(dev, init->gart_textures_offset);
1331 if (!dev_priv->gart_textures) {
1332 DRM_ERROR("could not find GART texture region!\n");
1333 radeon_do_cleanup_cp(dev);
1339 if (dev_priv->flags & RADEON_IS_AGP) {
1340 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1341 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1342 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1343 if (!dev_priv->cp_ring->handle ||
1344 !dev_priv->ring_rptr->handle ||
1345 !dev->agp_buffer_map->handle) {
1346 DRM_ERROR("could not find ioremap agp regions!\n");
1347 radeon_do_cleanup_cp(dev);
1353 dev_priv->cp_ring->handle =
1354 (void *)(unsigned long)dev_priv->cp_ring->offset;
1355 dev_priv->ring_rptr->handle =
1356 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1357 dev->agp_buffer_map->handle =
1358 (void *)(unsigned long)dev->agp_buffer_map->offset;
1360 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1361 dev_priv->cp_ring->handle);
1362 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1363 dev_priv->ring_rptr->handle);
1364 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1365 dev->agp_buffer_map->handle);
1368 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1370 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1371 - dev_priv->fb_location;
1373 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1374 ((dev_priv->front_offset
1375 + dev_priv->fb_location) >> 10));
1377 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1378 ((dev_priv->back_offset
1379 + dev_priv->fb_location) >> 10));
1381 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1382 ((dev_priv->depth_offset
1383 + dev_priv->fb_location) >> 10));
1385 dev_priv->gart_size = init->gart_size;
1387 /* New let's set the memory map ... */
1388 if (dev_priv->new_memmap) {
1391 DRM_INFO("Setting GART location based on new memory map\n");
1393 /* If using AGP, try to locate the AGP aperture at the same
1394 * location in the card and on the bus, though we have to
1398 if (dev_priv->flags & RADEON_IS_AGP) {
1399 base = dev->agp->base;
1400 /* Check if valid */
1401 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1402 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1403 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1409 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1411 base = dev_priv->fb_location + dev_priv->fb_size;
1412 if (base < dev_priv->fb_location ||
1413 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1414 base = dev_priv->fb_location
1415 - dev_priv->gart_size;
1417 dev_priv->gart_vm_start = base & 0xffc00000u;
1418 if (dev_priv->gart_vm_start != base)
1419 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1420 base, dev_priv->gart_vm_start);
1422 DRM_INFO("Setting GART location based on old memory map\n");
1423 dev_priv->gart_vm_start = dev_priv->fb_location +
1424 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1428 if (dev_priv->flags & RADEON_IS_AGP)
1429 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1431 + dev_priv->gart_vm_start);
1434 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1435 - (unsigned long)dev->sg->vaddr
1436 + dev_priv->gart_vm_start);
1438 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1439 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1440 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1441 dev_priv->gart_buffers_offset);
1443 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1444 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1445 + init->ring_size / sizeof(u32));
1446 dev_priv->ring.size = init->ring_size;
1447 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1449 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1450 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1452 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1453 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1454 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1456 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1459 if (dev_priv->flags & RADEON_IS_AGP) {
1460 /* Turn off PCI GART */
1461 radeon_set_pcigart(dev_priv, 0);
1468 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1469 /* if we have an offset set from userspace */
1470 if (dev_priv->pcigart_offset_set) {
1471 dev_priv->gart_info.bus_addr =
1472 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1473 dev_priv->gart_info.mapping.offset =
1474 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1475 dev_priv->gart_info.mapping.size =
1476 dev_priv->gart_info.table_size;
1478 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1479 dev_priv->gart_info.addr =
1480 dev_priv->gart_info.mapping.handle;
1482 if (dev_priv->flags & RADEON_IS_PCIE)
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1485 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1486 dev_priv->gart_info.gart_table_location =
1489 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1490 dev_priv->gart_info.addr,
1491 dev_priv->pcigart_offset);
1493 if (dev_priv->flags & RADEON_IS_IGPGART)
1494 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1496 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1497 dev_priv->gart_info.gart_table_location =
1499 dev_priv->gart_info.addr = NULL;
1500 dev_priv->gart_info.bus_addr = 0;
1501 if (dev_priv->flags & RADEON_IS_PCIE) {
1503 ("Cannot use PCI Express without GART in FB memory\n");
1504 radeon_do_cleanup_cp(dev);
1509 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1510 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1511 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1512 ret = r600_page_table_init(dev);
1514 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1515 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1518 DRM_ERROR("failed to init PCI GART!\n");
1519 radeon_do_cleanup_cp(dev);
1523 ret = radeon_setup_pcigart_surface(dev_priv);
1525 DRM_ERROR("failed to setup GART surface!\n");
1526 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1527 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1529 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1530 radeon_do_cleanup_cp(dev);
1534 /* Turn on PCI GART */
1535 radeon_set_pcigart(dev_priv, 1);
1538 if (!dev_priv->me_fw) {
1539 int err = radeon_cp_init_microcode(dev_priv);
1541 DRM_ERROR("Failed to load firmware!\n");
1542 radeon_do_cleanup_cp(dev);
1546 radeon_cp_load_microcode(dev_priv);
1547 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1549 dev_priv->last_buf = 0;
1551 radeon_do_engine_reset(dev);
1552 radeon_test_writeback(dev_priv);
1557 static int radeon_do_cleanup_cp(struct drm_device * dev)
1559 drm_radeon_private_t *dev_priv = dev->dev_private;
1562 /* Make sure interrupts are disabled here because the uninstall ioctl
1563 * may not have been called from userspace and after dev_private
1564 * is freed, it's too late.
1566 if (dev->irq_enabled)
1567 drm_irq_uninstall(dev);
1570 if (dev_priv->flags & RADEON_IS_AGP) {
1571 if (dev_priv->cp_ring != NULL) {
1572 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1573 dev_priv->cp_ring = NULL;
1575 if (dev_priv->ring_rptr != NULL) {
1576 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1577 dev_priv->ring_rptr = NULL;
1579 if (dev->agp_buffer_map != NULL) {
1580 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1581 dev->agp_buffer_map = NULL;
1587 if (dev_priv->gart_info.bus_addr) {
1588 /* Turn off PCI GART */
1589 radeon_set_pcigart(dev_priv, 0);
1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1591 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1593 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1594 DRM_ERROR("failed to cleanup PCI GART!\n");
1598 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1600 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1601 dev_priv->gart_info.addr = NULL;
1604 /* only clear to the start of flags */
1605 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1610 /* This code will reinit the Radeon CP hardware after a resume from disc.
1611 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1612 * here we make sure that all Radeon hardware initialisation is re-done without
1613 * affecting running applications.
1615 * Charl P. Botha <http://cpbotha.net>
1617 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1619 drm_radeon_private_t *dev_priv = dev->dev_private;
1622 DRM_ERROR("Called with no initialization\n");
1626 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1629 if (dev_priv->flags & RADEON_IS_AGP) {
1630 /* Turn off PCI GART */
1631 radeon_set_pcigart(dev_priv, 0);
1635 /* Turn on PCI GART */
1636 radeon_set_pcigart(dev_priv, 1);
1639 radeon_cp_load_microcode(dev_priv);
1640 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1642 dev_priv->have_z_offset = 0;
1643 radeon_do_engine_reset(dev);
1644 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1646 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1651 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1653 drm_radeon_private_t *dev_priv = dev->dev_private;
1654 drm_radeon_init_t *init = data;
1656 LOCK_TEST_WITH_RETURN(dev, file_priv);
1658 if (init->func == RADEON_INIT_R300_CP)
1659 r300_init_reg_flags(dev);
1661 switch (init->func) {
1662 case RADEON_INIT_CP:
1663 case RADEON_INIT_R200_CP:
1664 case RADEON_INIT_R300_CP:
1665 return radeon_do_init_cp(dev, init, file_priv);
1666 case RADEON_INIT_R600_CP:
1667 return r600_do_init_cp(dev, init, file_priv);
1668 case RADEON_CLEANUP_CP:
1669 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1670 return r600_do_cleanup_cp(dev);
1672 return radeon_do_cleanup_cp(dev);
1678 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1680 drm_radeon_private_t *dev_priv = dev->dev_private;
1683 LOCK_TEST_WITH_RETURN(dev, file_priv);
1685 if (dev_priv->cp_running) {
1686 DRM_DEBUG("while CP running\n");
1689 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1690 DRM_DEBUG("called with bogus CP mode (%d)\n",
1695 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1696 r600_do_cp_start(dev_priv);
1698 radeon_do_cp_start(dev_priv);
1703 /* Stop the CP. The engine must have been idled before calling this
1706 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1708 drm_radeon_private_t *dev_priv = dev->dev_private;
1709 drm_radeon_cp_stop_t *stop = data;
1713 LOCK_TEST_WITH_RETURN(dev, file_priv);
1715 if (!dev_priv->cp_running)
1718 /* Flush any pending CP commands. This ensures any outstanding
1719 * commands are exectuted by the engine before we turn it off.
1722 radeon_do_cp_flush(dev_priv);
1725 /* If we fail to make the engine go idle, we return an error
1726 * code so that the DRM ioctl wrapper can try again.
1729 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1730 ret = r600_do_cp_idle(dev_priv);
1732 ret = radeon_do_cp_idle(dev_priv);
1737 /* Finally, we can turn off the CP. If the engine isn't idle,
1738 * we will get some dropped triangles as they won't be fully
1739 * rendered before the CP is shut down.
1741 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742 r600_do_cp_stop(dev_priv);
1744 radeon_do_cp_stop(dev_priv);
1746 /* Reset the engine */
1747 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1748 r600_do_engine_reset(dev);
1750 radeon_do_engine_reset(dev);
1755 void radeon_do_release(struct drm_device * dev)
1757 drm_radeon_private_t *dev_priv = dev->dev_private;
1761 if (dev_priv->cp_running) {
1763 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1764 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1765 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1769 tsleep(&ret, PZERO, "rdnrel", 1);
1773 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1774 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1778 tsleep(&ret, PZERO, "rdnrel", 1);
1782 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1783 r600_do_cp_stop(dev_priv);
1784 r600_do_engine_reset(dev);
1786 radeon_do_cp_stop(dev_priv);
1787 radeon_do_engine_reset(dev);
1791 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1792 /* Disable *all* interrupts */
1793 if (dev_priv->mmio) /* remove this after permanent addmaps */
1794 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1796 if (dev_priv->mmio) { /* remove all surfaces */
1797 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1798 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1799 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1801 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1807 /* Free memory heap structures */
1808 radeon_mem_takedown(&(dev_priv->gart_heap));
1809 radeon_mem_takedown(&(dev_priv->fb_heap));
1811 /* deallocate kernel resources */
1812 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1813 r600_do_cleanup_cp(dev);
1815 radeon_do_cleanup_cp(dev);
1816 if (dev_priv->me_fw != NULL) {
1817 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
1818 dev_priv->me_fw = NULL;
1820 if (dev_priv->pfp_fw != NULL) {
1821 firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
1822 dev_priv->pfp_fw = NULL;
1827 /* Just reset the CP ring. Called as part of an X Server engine reset.
1829 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1831 drm_radeon_private_t *dev_priv = dev->dev_private;
1834 LOCK_TEST_WITH_RETURN(dev, file_priv);
1837 DRM_DEBUG("called before init done\n");
1841 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1842 r600_do_cp_reset(dev_priv);
1844 radeon_do_cp_reset(dev_priv);
1846 /* The CP is no longer running after an engine reset */
1847 dev_priv->cp_running = 0;
1852 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1854 drm_radeon_private_t *dev_priv = dev->dev_private;
1857 LOCK_TEST_WITH_RETURN(dev, file_priv);
1859 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1860 return r600_do_cp_idle(dev_priv);
1862 return radeon_do_cp_idle(dev_priv);
1865 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1867 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1869 drm_radeon_private_t *dev_priv = dev->dev_private;
1872 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1873 return r600_do_resume_cp(dev, file_priv);
1875 return radeon_do_resume_cp(dev, file_priv);
1878 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1880 drm_radeon_private_t *dev_priv = dev->dev_private;
1883 LOCK_TEST_WITH_RETURN(dev, file_priv);
1885 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1886 return r600_do_engine_reset(dev);
1888 return radeon_do_engine_reset(dev);
1891 /* ================================================================
1895 /* KW: Deprecated to say the least:
1897 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1902 /* ================================================================
1903 * Freelist management
1906 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1907 * bufs until freelist code is used. Note this hides a problem with
1908 * the scratch register * (used to keep track of last buffer
1909 * completed) being written to before * the last buffer has actually
1910 * completed rendering.
1912 * KW: It's also a good way to find free buffers quickly.
1914 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1915 * sleep. However, bugs in older versions of radeon_accel.c mean that
1916 * we essentially have to do this, else old clients will break.
1918 * However, it does leave open a potential deadlock where all the
1919 * buffers are held by other clients, which can't release them because
1920 * they can't get the lock.
1923 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1925 struct drm_device_dma *dma = dev->dma;
1926 drm_radeon_private_t *dev_priv = dev->dev_private;
1927 drm_radeon_buf_priv_t *buf_priv;
1928 struct drm_buf *buf;
1932 if (++dev_priv->last_buf >= dma->buf_count)
1933 dev_priv->last_buf = 0;
1935 start = dev_priv->last_buf;
1937 for (t = 0; t < dev_priv->usec_timeout; t++) {
1938 u32 done_age = GET_SCRATCH(dev_priv, 1);
1939 DRM_DEBUG("done_age = %d\n", done_age);
1940 for (i = 0; i < dma->buf_count; i++) {
1941 buf = dma->buflist[start];
1942 buf_priv = buf->dev_private;
1943 if (buf->file_priv == NULL || (buf->pending &&
1946 dev_priv->stats.requested_bufs++;
1950 if (++start >= dma->buf_count)
1956 dev_priv->stats.freelist_loops++;
1963 void radeon_freelist_reset(struct drm_device * dev)
1965 struct drm_device_dma *dma = dev->dma;
1966 drm_radeon_private_t *dev_priv = dev->dev_private;
1969 dev_priv->last_buf = 0;
1970 for (i = 0; i < dma->buf_count; i++) {
1971 struct drm_buf *buf = dma->buflist[i];
1972 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1977 /* ================================================================
1978 * CP command submission
1981 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1983 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1985 u32 last_head = GET_RING_HEAD(dev_priv);
1987 for (i = 0; i < dev_priv->usec_timeout; i++) {
1988 u32 head = GET_RING_HEAD(dev_priv);
1990 ring->space = (head - ring->tail) * sizeof(u32);
1991 if (ring->space <= 0)
1992 ring->space += ring->size;
1993 if (ring->space > n)
1996 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1998 if (head != last_head)
2005 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2006 #if RADEON_FIFO_DEBUG
2007 radeon_status(dev_priv);
2008 DRM_ERROR("failed!\n");
2013 static int radeon_cp_get_buffers(struct drm_device *dev,
2014 struct drm_file *file_priv,
2018 struct drm_buf *buf;
2020 for (i = d->granted_count; i < d->request_count; i++) {
2021 buf = radeon_freelist_get(dev);
2023 return -EBUSY; /* NOTE: broken client */
2025 buf->file_priv = file_priv;
2027 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2030 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2031 sizeof(buf->total)))
2039 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2041 struct drm_device_dma *dma = dev->dma;
2043 struct drm_dma *d = data;
2045 LOCK_TEST_WITH_RETURN(dev, file_priv);
2047 /* Please don't send us buffers.
2049 if (d->send_count != 0) {
2050 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2051 DRM_CURRENTPID, d->send_count);
2055 /* We'll send you buffers.
2057 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2058 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2059 DRM_CURRENTPID, d->request_count, dma->buf_count);
2063 d->granted_count = 0;
2065 if (d->request_count) {
2066 ret = radeon_cp_get_buffers(dev, file_priv, d);
2072 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2074 drm_radeon_private_t *dev_priv;
2077 dev_priv = malloc(sizeof(drm_radeon_private_t),
2078 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2079 if (dev_priv == NULL)
2082 dev->dev_private = (void *)dev_priv;
2083 dev_priv->flags = flags;
2085 switch (flags & RADEON_FAMILY_MASK) {
2098 dev_priv->flags |= RADEON_HAS_HIERZ;
2101 /* all other chips have no hierarchical z buffer */
2105 pci_enable_busmaster(dev->dev);
2107 if (drm_pci_device_is_agp(dev))
2108 dev_priv->flags |= RADEON_IS_AGP;
2109 else if (drm_pci_device_is_pcie(dev))
2110 dev_priv->flags |= RADEON_IS_PCIE;
2112 dev_priv->flags |= RADEON_IS_PCI;
2114 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2115 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2116 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2120 ret = drm_vblank_init(dev, 2);
2122 radeon_driver_unload(dev);
2126 DRM_DEBUG("%s card detected\n",
2127 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2131 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2133 struct drm_radeon_master_private *master_priv;
2134 unsigned long sareapage;
2137 master_priv = malloc(sizeof(*master_priv),
2138 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2142 /* prebuild the SAREA */
2143 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2144 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2145 &master_priv->sarea);
2147 DRM_ERROR("SAREA setup failed\n");
2148 free(master_priv, DRM_MEM_DRIVER);
2151 master_priv->sarea_priv = (drm_radeon_sarea_t *)((char *)master_priv->sarea->handle) +
2152 sizeof(struct drm_sarea);
2153 master_priv->sarea_priv->pfCurrentPage = 0;
2155 master->driver_priv = master_priv;
2159 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2161 struct drm_radeon_master_private *master_priv = master->driver_priv;
2166 if (master_priv->sarea_priv &&
2167 master_priv->sarea_priv->pfCurrentPage != 0)
2168 radeon_cp_dispatch_flip(dev, master);
2170 master_priv->sarea_priv = NULL;
2171 if (master_priv->sarea)
2172 drm_rmmap_locked(dev, master_priv->sarea);
2174 free(master_priv, DRM_MEM_DRIVER);
2176 master->driver_priv = NULL;
2179 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2180 * have to find them.
2182 int radeon_driver_firstopen(struct drm_device *dev)
2185 drm_local_map_t *map;
2186 drm_radeon_private_t *dev_priv = dev->dev_private;
2188 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2190 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2191 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2192 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2193 _DRM_WRITE_COMBINING, &map);
2200 int radeon_driver_unload(struct drm_device *dev)
2202 drm_radeon_private_t *dev_priv = dev->dev_private;
2206 drm_rmmap(dev, dev_priv->mmio);
2208 free(dev_priv, DRM_MEM_DRIVER);
2210 dev->dev_private = NULL;
2214 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2220 /* check if the ring is padded out to 16-dword alignment */
2222 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2224 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2226 ring = dev_priv->ring.start;
2227 /* pad with some CP_PACKET2 */
2228 for (i = 0; i < num_p2; i++)
2229 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2231 dev_priv->ring.tail += i;
2233 dev_priv->ring.space -= num_p2 * sizeof(u32);
2236 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2238 DRM_MEMORYBARRIER();
2239 GET_RING_HEAD( dev_priv );
2241 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2242 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2243 /* read from PCI bus to ensure correct posting */
2244 RADEON_READ(R600_CP_RB_RPTR);
2246 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2247 /* read from PCI bus to ensure correct posting */
2248 RADEON_READ(RADEON_CP_RB_RPTR);