sys/dev/drm2/radeon/radeon_ioc32.c

   1 /**
   2  * \file radeon_ioc32.c
   3  *
   4  * 32-bit ioctl compatibility routines for the Radeon DRM.
   5  *
   6  * \author Paul Mackerras <paulus@samba.org>
   7  *
   8  * Copyright (C) Paul Mackerras 2005
   9  * All Rights Reserved.
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a
  12  * copy of this software and associated documentation files (the "Software"),
  13  * to deal in the Software without restriction, including without limitation
  14  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15  * and/or sell copies of the Software, and to permit persons to whom the
  16  * Software is furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the next
  19  * paragraph) shall be included in all copies or substantial portions of the
  20  * Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  25  * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  26  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  28  * IN THE SOFTWARE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #ifdef COMPAT_FREEBSD32
  35
  36 #include <dev/drm2/drmP.h>
  37 #include <dev/drm2/drm.h>
  38 #include <dev/drm2/radeon/radeon_drm.h>
  39 #include "radeon_drv.h"
  40
  41 typedef struct drm_radeon_init32 {
  42         int func;
  43         u32 sarea_priv_offset;
  44         int is_pci;
  45         int cp_mode;
  46         int gart_size;
  47         int ring_size;
  48         int usec_timeout;
  49
  50         unsigned int fb_bpp;
  51         unsigned int front_offset, front_pitch;
  52         unsigned int back_offset, back_pitch;
  53         unsigned int depth_bpp;
  54         unsigned int depth_offset, depth_pitch;
  55
  56         u32 fb_offset;
  57         u32 mmio_offset;
  58         u32 ring_offset;
  59         u32 ring_rptr_offset;
  60         u32 buffers_offset;
  61         u32 gart_textures_offset;
  62 } drm_radeon_init32_t;
  63
  64 static int compat_radeon_cp_init(struct drm_device *dev, void *arg,
  65                                  struct drm_file *file_priv)
  66 {
  67         drm_radeon_init32_t *init32;
  68         drm_radeon_init_t __user init;
  69
  70         init32 = arg;
  71
  72         init.func = init32->func;
  73         init.sarea_priv_offset = (unsigned long)init32->sarea_priv_offset;
  74         init.is_pci = init32->is_pci;
  75         init.cp_mode = init32->cp_mode;
  76         init.gart_size = init32->gart_size;
  77         init.ring_size = init32->ring_size;
  78         init.usec_timeout = init32->usec_timeout;
  79         init.fb_bpp = init32->fb_bpp;
  80         init.front_offset = init32->front_offset;
  81         init.front_pitch = init32->front_pitch;
  82         init.back_offset = init32->back_offset;
  83         init.back_pitch = init32->back_pitch;
  84         init.depth_bpp = init32->depth_bpp;
  85         init.depth_offset = init32->depth_offset;
  86         init.depth_pitch = init32->depth_pitch;
  87         init.fb_offset = (unsigned long)init32->fb_offset;
  88         init.mmio_offset = (unsigned long)init32->mmio_offset;
  89         init.ring_offset = (unsigned long)init32->ring_offset;
  90         init.ring_rptr_offset = (unsigned long)init32->ring_rptr_offset;
  91         init.buffers_offset = (unsigned long)init32->buffers_offset;
  92         init.gart_textures_offset = (unsigned long)init32->gart_textures_offset;
  93
  94         return radeon_cp_init(dev, &init, file_priv);
  95 }
  96
  97 typedef struct drm_radeon_clear32 {
  98         unsigned int flags;
  99         unsigned int clear_color;
 100         unsigned int clear_depth;
 101         unsigned int color_mask;
 102         unsigned int depth_mask;        /* misnamed field:  should be stencil */
 103         u32 depth_boxes;
 104 } drm_radeon_clear32_t;
 105
 106 static int compat_radeon_cp_clear(struct drm_device *dev, void *arg,
 107                                   struct drm_file *file_priv)
 108 {
 109         drm_radeon_clear32_t *clr32;
 110         drm_radeon_clear_t __user clr;
 111
 112         clr32 = arg;
 113
 114         clr.flags = clr32->flags;
 115         clr.clear_color = clr32->clear_color;
 116         clr.clear_depth = clr32->clear_depth;
 117         clr.color_mask = clr32->color_mask;
 118         clr.depth_mask = clr32->depth_mask;
 119         clr.depth_boxes = (drm_radeon_clear_rect_t *)(unsigned long)clr32->depth_boxes;
 120
 121         return radeon_ioctls[DRM_IOCTL_RADEON_CLEAR].func(dev, &clr, file_priv);
 122 }
 123
 124 typedef struct drm_radeon_stipple32 {
 125         u32 mask;
 126 } drm_radeon_stipple32_t;
 127
 128 static int compat_radeon_cp_stipple(struct drm_device *dev, void *arg,
 129                                     struct drm_file *file_priv)
 130 {
 131         drm_radeon_stipple32_t __user *argp = (void __user *)arg;
 132         drm_radeon_stipple_t __user request;
 133
 134         request.mask = (unsigned int *)(unsigned long)argp->mask;
 135
 136         return radeon_ioctls[DRM_IOCTL_RADEON_STIPPLE].func(dev, &request, file_priv);
 137 }
 138
 139 typedef struct drm_radeon_tex_image32 {
 140         unsigned int x, y;      /* Blit coordinates */
 141         unsigned int width, height;
 142         u32 data;
 143 } drm_radeon_tex_image32_t;
 144
 145 typedef struct drm_radeon_texture32 {
 146         unsigned int offset;
 147         int pitch;
 148         int format;
 149         int width;              /* Texture image coordinates */
 150         int height;
 151         u32 image;
 152 } drm_radeon_texture32_t;
 153
 154 static int compat_radeon_cp_texture(struct drm_device *dev, void *arg,
 155                                     struct drm_file *file_priv)
 156 {
 157         drm_radeon_texture32_t *req32;
 158         drm_radeon_texture_t __user request;
 159         drm_radeon_tex_image32_t *img32;
 160         drm_radeon_tex_image_t __user image;
 161
 162         req32 = arg;
 163         if (req32->image == 0)
 164                 return -EINVAL;
 165         img32 = (drm_radeon_tex_image32_t *)(unsigned long)req32->image;
 166
 167         request.offset = req32->offset;
 168         request.pitch = req32->pitch;
 169         request.format = req32->format;
 170         request.width = req32->width;
 171         request.height = req32->height;
 172         request.image = &image;
 173         image.x = img32->x;
 174         image.y = img32->y;
 175         image.width = img32->width;
 176         image.height = img32->height;
 177         image.data = (void *)(unsigned long)img32->data;
 178
 179         return radeon_ioctls[DRM_IOCTL_RADEON_TEXTURE].func(dev, &request, file_priv);
 180 }
 181
 182 typedef struct drm_radeon_vertex2_32 {
 183         int idx;                /* Index of vertex buffer */
 184         int discard;            /* Client finished with buffer? */
 185         int nr_states;
 186         u32 state;
 187         int nr_prims;
 188         u32 prim;
 189 } drm_radeon_vertex2_32_t;
 190
 191 static int compat_radeon_cp_vertex2(struct drm_device *dev, void *arg,
 192                                     struct drm_file *file_priv)
 193 {
 194         drm_radeon_vertex2_32_t *req32;
 195         drm_radeon_vertex2_t __user request;
 196
 197         req32 = arg;
 198
 199         request.idx = req32->idx;
 200         request.discard = req32->discard;
 201         request.nr_states = req32->nr_states;
 202         request.state = (drm_radeon_state_t *)(unsigned long)req32->state;
 203         request.nr_prims = req32->nr_prims;
 204         request.prim = (drm_radeon_prim_t *)(unsigned long)req32->prim;
 205
 206         return radeon_ioctls[DRM_IOCTL_RADEON_VERTEX2].func(dev, &request, file_priv);
 207 }
 208
 209 typedef struct drm_radeon_cmd_buffer32 {
 210         int bufsz;
 211         u32 buf;
 212         int nbox;
 213         u32 boxes;
 214 } drm_radeon_cmd_buffer32_t;
 215
 216 static int compat_radeon_cp_cmdbuf(struct drm_device *dev, void *arg,
 217                                    struct drm_file *file_priv)
 218 {
 219         drm_radeon_cmd_buffer32_t *req32;
 220         drm_radeon_cmd_buffer_t __user request;
 221
 222         req32 = arg;
 223
 224         request.bufsz = req32->bufsz;
 225         request.buf = (char *)(unsigned long)req32->buf;
 226         request.nbox = req32->nbox;
 227         request.boxes = (struct drm_clip_rect *)(unsigned long)req32->boxes;
 228
 229         return radeon_ioctls[DRM_IOCTL_RADEON_CMDBUF].func(dev, &request, file_priv);
 230 }
 231
 232 typedef struct drm_radeon_getparam32 {
 233         int param;
 234         u32 value;
 235 } drm_radeon_getparam32_t;
 236
 237 static int compat_radeon_cp_getparam(struct drm_device *dev, void *arg,
 238                                      struct drm_file *file_priv)
 239 {
 240         drm_radeon_getparam32_t *req32;
 241         drm_radeon_getparam_t __user request;
 242
 243         req32 = arg;
 244
 245         request.param = req32->param;
 246         request.value = (void *)(unsigned long)req32->value;
 247
 248         return radeon_ioctls[DRM_IOCTL_RADEON_GETPARAM].func(dev, &request, file_priv);
 249 }
 250
 251 typedef struct drm_radeon_mem_alloc32 {
 252         int region;
 253         int alignment;
 254         int size;
 255         u32 region_offset;      /* offset from start of fb or GART */
 256 } drm_radeon_mem_alloc32_t;
 257
 258 static int compat_radeon_mem_alloc(struct drm_device *dev, void *arg,
 259                                    struct drm_file *file_priv)
 260 {
 261         drm_radeon_mem_alloc32_t *req32;
 262         drm_radeon_mem_alloc_t __user request;
 263
 264         req32 = arg;
 265
 266         request.region = req32->region;
 267         request.alignment = req32->alignment;
 268         request.size = req32->size;
 269         request.region_offset = (int *)(unsigned long)req32->region_offset;
 270
 271         return radeon_mem_alloc(dev, &request, file_priv);
 272 }
 273
 274 typedef struct drm_radeon_irq_emit32 {
 275         u32 irq_seq;
 276 } drm_radeon_irq_emit32_t;
 277
 278 static int compat_radeon_irq_emit(struct drm_device *dev, void *arg,
 279                                   struct drm_file *file_priv)
 280 {
 281         drm_radeon_irq_emit32_t *req32;
 282         drm_radeon_irq_emit_t __user request;
 283
 284         req32 = arg;
 285
 286         request.irq_seq = (int *)(unsigned long)req32->irq_seq;
 287
 288         return radeon_irq_emit(dev, &request, file_priv);
 289 }
 290
 291 /* The two 64-bit arches where alignof(u64)==4 in 32-bit code */
 292 #if defined (CONFIG_X86_64) || defined(CONFIG_IA64)
 293 typedef struct drm_radeon_setparam32 {
 294         int param;
 295         u64 value;
 296 } __attribute__((packed)) drm_radeon_setparam32_t;
 297
 298 static int compat_radeon_cp_setparam(struct drm_device *dev, void *arg,
 299                                      struct drm_file *file_priv)
 300 {
 301         drm_radeon_setparam32_t *req32;
 302         drm_radeon_setparam_t __user request;
 303
 304         req32 = arg;
 305
 306         request.param = req32->param;
 307         request.value = req32->value;
 308
 309         return radeon_ioctls[DRM_IOCTL_RADEON_SETPARAM].func(dev, &request, file_priv);
 310 }
 311 #else
 312 #define compat_radeon_cp_setparam NULL
 313 #endif /* X86_64 || IA64 */
 314
 315 struct drm_ioctl_desc radeon_compat_ioctls[] = {
 316         DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, compat_radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 317         DRM_IOCTL_DEF(DRM_RADEON_CLEAR, compat_radeon_cp_clear, DRM_AUTH),
 318         DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, compat_radeon_cp_stipple, DRM_AUTH),
 319         DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, compat_radeon_cp_texture, DRM_AUTH),
 320         DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, compat_radeon_cp_vertex2, DRM_AUTH),
 321         DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, compat_radeon_cp_cmdbuf, DRM_AUTH),
 322         DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, compat_radeon_cp_getparam, DRM_AUTH),
 323         DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, compat_radeon_cp_setparam, DRM_AUTH),
 324         DRM_IOCTL_DEF(DRM_RADEON_ALLOC, compat_radeon_mem_alloc, DRM_AUTH),
 325         DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, compat_radeon_irq_emit, DRM_AUTH)
 326 };
 327 int radeon_num_compat_ioctls = ARRAY_SIZE(radeon_compat_ioctls);
 328
 329 #endif