4 * 32-bit ioctl compatibility routines for the Radeon DRM.
6 * \author Paul Mackerras <paulus@samba.org>
8 * Copyright (C) Paul Mackerras 2005
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include "opt_compat.h"
36 #ifdef COMPAT_FREEBSD32
38 #include <dev/drm2/drmP.h>
39 #include <dev/drm2/drm.h>
40 #include <dev/drm2/radeon/radeon_drm.h>
41 #include "radeon_drv.h"
43 typedef struct drm_radeon_init32 {
45 u32 sarea_priv_offset;
53 unsigned int front_offset, front_pitch;
54 unsigned int back_offset, back_pitch;
55 unsigned int depth_bpp;
56 unsigned int depth_offset, depth_pitch;
63 u32 gart_textures_offset;
64 } drm_radeon_init32_t;
66 static int compat_radeon_cp_init(struct drm_device *dev, void *arg,
67 struct drm_file *file_priv)
69 drm_radeon_init32_t *init32;
70 drm_radeon_init_t __user init;
74 init.func = init32->func;
75 init.sarea_priv_offset = (unsigned long)init32->sarea_priv_offset;
76 init.is_pci = init32->is_pci;
77 init.cp_mode = init32->cp_mode;
78 init.gart_size = init32->gart_size;
79 init.ring_size = init32->ring_size;
80 init.usec_timeout = init32->usec_timeout;
81 init.fb_bpp = init32->fb_bpp;
82 init.front_offset = init32->front_offset;
83 init.front_pitch = init32->front_pitch;
84 init.back_offset = init32->back_offset;
85 init.back_pitch = init32->back_pitch;
86 init.depth_bpp = init32->depth_bpp;
87 init.depth_offset = init32->depth_offset;
88 init.depth_pitch = init32->depth_pitch;
89 init.fb_offset = (unsigned long)init32->fb_offset;
90 init.mmio_offset = (unsigned long)init32->mmio_offset;
91 init.ring_offset = (unsigned long)init32->ring_offset;
92 init.ring_rptr_offset = (unsigned long)init32->ring_rptr_offset;
93 init.buffers_offset = (unsigned long)init32->buffers_offset;
94 init.gart_textures_offset = (unsigned long)init32->gart_textures_offset;
96 return radeon_cp_init(dev, &init, file_priv);
99 typedef struct drm_radeon_clear32 {
101 unsigned int clear_color;
102 unsigned int clear_depth;
103 unsigned int color_mask;
104 unsigned int depth_mask; /* misnamed field: should be stencil */
106 } drm_radeon_clear32_t;
108 static int compat_radeon_cp_clear(struct drm_device *dev, void *arg,
109 struct drm_file *file_priv)
111 drm_radeon_clear32_t *clr32;
112 drm_radeon_clear_t __user clr;
116 clr.flags = clr32->flags;
117 clr.clear_color = clr32->clear_color;
118 clr.clear_depth = clr32->clear_depth;
119 clr.color_mask = clr32->color_mask;
120 clr.depth_mask = clr32->depth_mask;
121 clr.depth_boxes = (drm_radeon_clear_rect_t *)(unsigned long)clr32->depth_boxes;
123 return radeon_ioctls[DRM_IOCTL_RADEON_CLEAR].func(dev, &clr, file_priv);
126 typedef struct drm_radeon_stipple32 {
128 } drm_radeon_stipple32_t;
130 static int compat_radeon_cp_stipple(struct drm_device *dev, void *arg,
131 struct drm_file *file_priv)
133 drm_radeon_stipple32_t __user *argp = (void __user *)arg;
134 drm_radeon_stipple_t __user request;
136 request.mask = (unsigned int *)(unsigned long)argp->mask;
138 return radeon_ioctls[DRM_IOCTL_RADEON_STIPPLE].func(dev, &request, file_priv);
141 typedef struct drm_radeon_tex_image32 {
142 unsigned int x, y; /* Blit coordinates */
143 unsigned int width, height;
145 } drm_radeon_tex_image32_t;
147 typedef struct drm_radeon_texture32 {
151 int width; /* Texture image coordinates */
154 } drm_radeon_texture32_t;
156 static int compat_radeon_cp_texture(struct drm_device *dev, void *arg,
157 struct drm_file *file_priv)
159 drm_radeon_texture32_t *req32;
160 drm_radeon_texture_t __user request;
161 drm_radeon_tex_image32_t *img32;
162 drm_radeon_tex_image_t __user image;
165 if (req32->image == 0)
167 img32 = (drm_radeon_tex_image32_t *)(unsigned long)req32->image;
169 request.offset = req32->offset;
170 request.pitch = req32->pitch;
171 request.format = req32->format;
172 request.width = req32->width;
173 request.height = req32->height;
174 request.image = ℑ
177 image.width = img32->width;
178 image.height = img32->height;
179 image.data = (void *)(unsigned long)img32->data;
181 return radeon_ioctls[DRM_IOCTL_RADEON_TEXTURE].func(dev, &request, file_priv);
184 typedef struct drm_radeon_vertex2_32 {
185 int idx; /* Index of vertex buffer */
186 int discard; /* Client finished with buffer? */
191 } drm_radeon_vertex2_32_t;
193 static int compat_radeon_cp_vertex2(struct drm_device *dev, void *arg,
194 struct drm_file *file_priv)
196 drm_radeon_vertex2_32_t *req32;
197 drm_radeon_vertex2_t __user request;
201 request.idx = req32->idx;
202 request.discard = req32->discard;
203 request.nr_states = req32->nr_states;
204 request.state = (drm_radeon_state_t *)(unsigned long)req32->state;
205 request.nr_prims = req32->nr_prims;
206 request.prim = (drm_radeon_prim_t *)(unsigned long)req32->prim;
208 return radeon_ioctls[DRM_IOCTL_RADEON_VERTEX2].func(dev, &request, file_priv);
211 typedef struct drm_radeon_cmd_buffer32 {
216 } drm_radeon_cmd_buffer32_t;
218 static int compat_radeon_cp_cmdbuf(struct drm_device *dev, void *arg,
219 struct drm_file *file_priv)
221 drm_radeon_cmd_buffer32_t *req32;
222 drm_radeon_cmd_buffer_t __user request;
226 request.bufsz = req32->bufsz;
227 request.buf = (char *)(unsigned long)req32->buf;
228 request.nbox = req32->nbox;
229 request.boxes = (struct drm_clip_rect *)(unsigned long)req32->boxes;
231 return radeon_ioctls[DRM_IOCTL_RADEON_CMDBUF].func(dev, &request, file_priv);
234 typedef struct drm_radeon_getparam32 {
237 } drm_radeon_getparam32_t;
239 static int compat_radeon_cp_getparam(struct drm_device *dev, void *arg,
240 struct drm_file *file_priv)
242 drm_radeon_getparam32_t *req32;
243 drm_radeon_getparam_t __user request;
247 request.param = req32->param;
248 request.value = (void *)(unsigned long)req32->value;
250 return radeon_ioctls[DRM_IOCTL_RADEON_GETPARAM].func(dev, &request, file_priv);
253 typedef struct drm_radeon_mem_alloc32 {
257 u32 region_offset; /* offset from start of fb or GART */
258 } drm_radeon_mem_alloc32_t;
260 static int compat_radeon_mem_alloc(struct drm_device *dev, void *arg,
261 struct drm_file *file_priv)
263 drm_radeon_mem_alloc32_t *req32;
264 drm_radeon_mem_alloc_t __user request;
268 request.region = req32->region;
269 request.alignment = req32->alignment;
270 request.size = req32->size;
271 request.region_offset = (int *)(unsigned long)req32->region_offset;
273 return radeon_mem_alloc(dev, &request, file_priv);
276 typedef struct drm_radeon_irq_emit32 {
278 } drm_radeon_irq_emit32_t;
280 static int compat_radeon_irq_emit(struct drm_device *dev, void *arg,
281 struct drm_file *file_priv)
283 drm_radeon_irq_emit32_t *req32;
284 drm_radeon_irq_emit_t __user request;
288 request.irq_seq = (int *)(unsigned long)req32->irq_seq;
290 return radeon_irq_emit(dev, &request, file_priv);
293 /* The two 64-bit arches where alignof(u64)==4 in 32-bit code */
294 #if defined (CONFIG_X86_64) || defined(CONFIG_IA64)
295 typedef struct drm_radeon_setparam32 {
298 } __attribute__((packed)) drm_radeon_setparam32_t;
300 static int compat_radeon_cp_setparam(struct drm_device *dev, void *arg,
301 struct drm_file *file_priv)
303 drm_radeon_setparam32_t *req32;
304 drm_radeon_setparam_t __user request;
308 request.param = req32->param;
309 request.value = req32->value;
311 return radeon_ioctls[DRM_IOCTL_RADEON_SETPARAM].func(dev, &request, file_priv);
314 #define compat_radeon_cp_setparam NULL
315 #endif /* X86_64 || IA64 */
317 struct drm_ioctl_desc radeon_compat_ioctls[] = {
318 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, compat_radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
319 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, compat_radeon_cp_clear, DRM_AUTH),
320 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, compat_radeon_cp_stipple, DRM_AUTH),
321 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, compat_radeon_cp_texture, DRM_AUTH),
322 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, compat_radeon_cp_vertex2, DRM_AUTH),
323 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, compat_radeon_cp_cmdbuf, DRM_AUTH),
324 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, compat_radeon_cp_getparam, DRM_AUTH),
325 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, compat_radeon_cp_setparam, DRM_AUTH),
326 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, compat_radeon_mem_alloc, DRM_AUTH),
327 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, compat_radeon_irq_emit, DRM_AUTH)
329 int radeon_num_compat_ioctls = ARRAY_SIZE(radeon_compat_ioctls);