1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <dev/drm2/drmP.h>
37 #include <dev/drm2/radeon/radeon_drm.h>
38 #include "radeon_drv.h"
40 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
42 drm_radeon_private_t *dev_priv = dev->dev_private;
45 dev_priv->irq_enable_reg |= mask;
47 dev_priv->irq_enable_reg &= ~mask;
50 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
53 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
55 drm_radeon_private_t *dev_priv = dev->dev_private;
58 dev_priv->r500_disp_irq_reg |= mask;
60 dev_priv->r500_disp_irq_reg &= ~mask;
63 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
66 int radeon_enable_vblank(struct drm_device *dev, int crtc)
68 drm_radeon_private_t *dev_priv = dev->dev_private;
70 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
73 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
76 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
79 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
86 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
89 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
92 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
101 void radeon_disable_vblank(struct drm_device *dev, int crtc)
103 drm_radeon_private_t *dev_priv = dev->dev_private;
105 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
108 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
111 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
114 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
121 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
124 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
127 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
134 static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
136 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
137 u32 irq_mask = RADEON_SW_INT_TEST;
140 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
141 /* vbl interrupts in a different place */
143 if (irqs & R500_DISPLAY_INT_STATUS) {
144 /* if a display interrupt */
147 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
149 *r500_disp_int = disp_irq;
150 if (disp_irq & R500_D1_VBLANK_INTERRUPT)
151 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
152 if (disp_irq & R500_D2_VBLANK_INTERRUPT)
153 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
155 irq_mask |= R500_DISPLAY_INT_STATUS;
157 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
162 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
167 /* Interrupts - Used for device synchronization and flushing in the
168 * following circumstances:
170 * - Exclusive FB access with hw idle:
171 * - Wait for GUI Idle (?) interrupt, then do normal flush.
173 * - Frame throttling, NV_fence:
174 * - Drop marker irq's into command stream ahead of time.
175 * - Wait on irq's with lock *not held*
176 * - Check each for termination condition
178 * - Internally in cp_getbuffer, etc:
179 * - as above, but wait with lock held???
181 * NOTE: These functions are misleadingly named -- the irq's aren't
182 * tied to dma at all, this is just a hangover from dri prehistory.
185 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
187 struct drm_device *dev = (struct drm_device *) arg;
188 drm_radeon_private_t *dev_priv =
189 (drm_radeon_private_t *) dev->dev_private;
193 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
196 /* Only consider the bits we're interested in - others could be used
199 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
203 stat &= dev_priv->irq_enable_reg;
206 if (stat & RADEON_SW_INT_TEST)
207 DRM_WAKEUP(&dev_priv->swi_queue);
209 /* VBLANK interrupt */
210 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
211 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
212 drm_handle_vblank(dev, 0);
213 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
214 drm_handle_vblank(dev, 1);
216 if (stat & RADEON_CRTC_VBLANK_STAT)
217 drm_handle_vblank(dev, 0);
218 if (stat & RADEON_CRTC2_VBLANK_STAT)
219 drm_handle_vblank(dev, 1);
224 static int radeon_emit_irq(struct drm_device * dev)
226 drm_radeon_private_t *dev_priv = dev->dev_private;
230 atomic_inc(&dev_priv->swi_emitted);
231 ret = atomic_read(&dev_priv->swi_emitted);
234 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
235 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
242 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
244 drm_radeon_private_t *dev_priv =
245 (drm_radeon_private_t *) dev->dev_private;
248 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
251 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
253 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
254 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
259 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
261 drm_radeon_private_t *dev_priv = dev->dev_private;
264 DRM_ERROR("called with no initialization\n");
268 if (crtc < 0 || crtc > 1) {
269 DRM_ERROR("Invalid crtc %d\n", crtc);
273 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
275 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
277 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
280 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
282 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
286 /* Needs the lock as it touches the ring.
288 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
290 drm_radeon_private_t *dev_priv = dev->dev_private;
291 drm_radeon_irq_emit_t *emit = data;
295 DRM_ERROR("called with no initialization\n");
299 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
302 LOCK_TEST_WITH_RETURN(dev, file_priv);
304 result = radeon_emit_irq(dev);
306 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
307 DRM_ERROR("copy_to_user\n");
314 /* Doesn't need the hardware lock.
316 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
318 drm_radeon_private_t *dev_priv = dev->dev_private;
319 drm_radeon_irq_wait_t *irqwait = data;
322 DRM_ERROR("called with no initialization\n");
326 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
329 return radeon_wait_irq(dev, irqwait->irq_seq);
334 void radeon_driver_irq_preinstall(struct drm_device * dev)
336 drm_radeon_private_t *dev_priv =
337 (drm_radeon_private_t *) dev->dev_private;
340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
343 /* Disable *all* interrupts */
344 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
345 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
346 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
348 /* Clear bits if they're already high */
349 radeon_acknowledge_irqs(dev_priv, &dummy);
352 int radeon_driver_irq_postinstall(struct drm_device *dev)
354 drm_radeon_private_t *dev_priv =
355 (drm_radeon_private_t *) dev->dev_private;
357 atomic_set(&dev_priv->swi_emitted, 0);
358 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
360 dev->max_vblank_count = 0x001fffff;
362 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
365 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
370 void radeon_driver_irq_uninstall(struct drm_device * dev)
372 drm_radeon_private_t *dev_priv =
373 (drm_radeon_private_t *) dev->dev_private;
377 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
380 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
381 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
382 /* Disable *all* interrupts */
383 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
387 int radeon_vblank_crtc_get(struct drm_device *dev)
389 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
391 return dev_priv->vblank_crtc;
394 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
396 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
397 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
398 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
401 dev_priv->vblank_crtc = (unsigned int)value;