2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
34 #include <dev/drm2/radeon/radeon_drm.h>
35 #include "radeon_asic.h"
36 #include "radeon_kms.h"
39 * radeon_driver_unload_kms - Main unload function for KMS.
41 * @dev: drm dev pointer
43 * This is the main unload function for KMS (all asics).
44 * It calls radeon_modeset_fini() to tear down the
45 * displays, and radeon_device_fini() to tear down
46 * the rest of the device (CP, writeback, etc.).
47 * Returns 0 on success.
49 int radeon_driver_unload_kms(struct drm_device *dev)
51 struct radeon_device *rdev = dev->dev_private;
55 radeon_acpi_fini(rdev);
56 radeon_modeset_fini(rdev);
57 radeon_device_fini(rdev);
58 free(rdev, DRM_MEM_DRIVER);
59 dev->dev_private = NULL;
64 * radeon_driver_load_kms - Main load function for KMS.
66 * @dev: drm dev pointer
67 * @flags: device flags
69 * This is the main load function for KMS (all asics).
70 * It calls radeon_device_init() to set up the non-display
71 * parts of the chip (asic init, CP, writeback, etc.), and
72 * radeon_modeset_init() to set up the display parts
73 * (crtcs, encoders, hotplug detect, etc.).
74 * Returns 0 on success, error on failure.
76 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
78 struct radeon_device *rdev;
81 rdev = malloc(sizeof(struct radeon_device), DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
85 dev->dev_private = (void *)rdev;
88 if (drm_device_is_agp(dev)) {
89 DRM_INFO("RADEON_IS_AGP\n");
90 flags |= RADEON_IS_AGP;
91 } else if (drm_device_is_pcie(dev)) {
92 DRM_INFO("RADEON_IS_PCIE\n");
93 flags |= RADEON_IS_PCIE;
95 DRM_INFO("RADEON_IS_PCI\n");
96 flags |= RADEON_IS_PCI;
99 /* radeon_device_init should report only fatal error
100 * like memory allocation failure or iomapping failure,
101 * or memory manager initialization failure, it must
102 * properly initialize the GPU MC controller and permit
105 r = radeon_device_init(rdev, dev, flags);
107 dev_err(dev->device, "Fatal error during GPU init\n");
111 /* Again modeset_init should fail only on fatal error
112 * otherwise it should provide enough functionalities
113 * for shadowfb to run
115 r = radeon_modeset_init(rdev);
117 dev_err(dev->device, "Fatal error during modeset init\n");
119 /* Call ACPI methods: require modeset init
120 * but failure is not fatal
123 acpi_status = radeon_acpi_init(rdev);
126 "Error during ACPI methods call\n");
131 radeon_driver_unload_kms(dev);
136 * radeon_set_filp_rights - Set filp right.
138 * @dev: drm dev pointer
143 * Sets the filp rights for the device (all asics).
145 static void radeon_set_filp_rights(struct drm_device *dev,
146 struct drm_file **owner,
147 struct drm_file *applier,
155 } else if (*value == 0) {
157 if (*owner == applier)
160 *value = *owner == applier ? 1 : 0;
165 * Userspace get information ioctl
168 * radeon_info_ioctl - answer a device specific request.
170 * @rdev: radeon device pointer
171 * @data: request object
174 * This function is used to pass device specific parameters to the userspace
175 * drivers. Examples include: pci device id, pipeline parms, tiling params,
177 * Returns 0 on success, -EINVAL on failure.
179 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
181 struct radeon_device *rdev = dev->dev_private;
182 struct drm_radeon_info *info = data;
183 struct radeon_mode_info *minfo = &rdev->mode_info;
184 uint32_t value, *value_ptr;
185 uint64_t value64, *value_ptr64;
186 struct drm_crtc *crtc;
189 /* TIMESTAMP is a 64-bit value, needs special handling. */
190 if (info->request == RADEON_INFO_TIMESTAMP) {
191 if (rdev->family >= CHIP_R600) {
192 value_ptr64 = (uint64_t*)((unsigned long)info->value);
193 if (rdev->family >= CHIP_TAHITI) {
194 value64 = si_get_gpu_clock(rdev);
196 value64 = r600_get_gpu_clock(rdev);
199 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
200 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
205 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
210 value_ptr = (uint32_t *)((unsigned long)info->value);
211 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) {
212 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
216 switch (info->request) {
217 case RADEON_INFO_DEVICE_ID:
218 value = dev->pci_device;
220 case RADEON_INFO_NUM_GB_PIPES:
221 value = rdev->num_gb_pipes;
223 case RADEON_INFO_NUM_Z_PIPES:
224 value = rdev->num_z_pipes;
226 case RADEON_INFO_ACCEL_WORKING:
227 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
228 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
231 value = rdev->accel_working;
233 case RADEON_INFO_CRTC_FROM_ID:
234 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
235 crtc = (struct drm_crtc *)minfo->crtcs[i];
236 if (crtc && crtc->base.id == value) {
237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
238 value = radeon_crtc->crtc_id;
244 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
248 case RADEON_INFO_ACCEL_WORKING2:
249 value = rdev->accel_working;
251 case RADEON_INFO_TILING_CONFIG:
252 if (rdev->family >= CHIP_TAHITI)
253 value = rdev->config.si.tile_config;
254 else if (rdev->family >= CHIP_CAYMAN)
255 value = rdev->config.cayman.tile_config;
256 else if (rdev->family >= CHIP_CEDAR)
257 value = rdev->config.evergreen.tile_config;
258 else if (rdev->family >= CHIP_RV770)
259 value = rdev->config.rv770.tile_config;
260 else if (rdev->family >= CHIP_R600)
261 value = rdev->config.r600.tile_config;
263 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
267 case RADEON_INFO_WANT_HYPERZ:
268 /* The "value" here is both an input and output parameter.
269 * If the input value is 1, filp requests hyper-z access.
270 * If the input value is 0, filp revokes its hyper-z access.
272 * When returning, the value is 1 if filp owns hyper-z access,
275 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
278 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
280 case RADEON_INFO_WANT_CMASK:
281 /* The same logic as Hyper-Z. */
283 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
286 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
288 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
289 /* return clock value in KHz */
290 value = rdev->clock.spll.reference_freq * 10;
292 case RADEON_INFO_NUM_BACKENDS:
293 if (rdev->family >= CHIP_TAHITI)
294 value = rdev->config.si.max_backends_per_se *
295 rdev->config.si.max_shader_engines;
296 else if (rdev->family >= CHIP_CAYMAN)
297 value = rdev->config.cayman.max_backends_per_se *
298 rdev->config.cayman.max_shader_engines;
299 else if (rdev->family >= CHIP_CEDAR)
300 value = rdev->config.evergreen.max_backends;
301 else if (rdev->family >= CHIP_RV770)
302 value = rdev->config.rv770.max_backends;
303 else if (rdev->family >= CHIP_R600)
304 value = rdev->config.r600.max_backends;
309 case RADEON_INFO_NUM_TILE_PIPES:
310 if (rdev->family >= CHIP_TAHITI)
311 value = rdev->config.si.max_tile_pipes;
312 else if (rdev->family >= CHIP_CAYMAN)
313 value = rdev->config.cayman.max_tile_pipes;
314 else if (rdev->family >= CHIP_CEDAR)
315 value = rdev->config.evergreen.max_tile_pipes;
316 else if (rdev->family >= CHIP_RV770)
317 value = rdev->config.rv770.max_tile_pipes;
318 else if (rdev->family >= CHIP_R600)
319 value = rdev->config.r600.max_tile_pipes;
324 case RADEON_INFO_FUSION_GART_WORKING:
327 case RADEON_INFO_BACKEND_MAP:
328 if (rdev->family >= CHIP_TAHITI)
329 value = rdev->config.si.backend_map;
330 else if (rdev->family >= CHIP_CAYMAN)
331 value = rdev->config.cayman.backend_map;
332 else if (rdev->family >= CHIP_CEDAR)
333 value = rdev->config.evergreen.backend_map;
334 else if (rdev->family >= CHIP_RV770)
335 value = rdev->config.rv770.backend_map;
336 else if (rdev->family >= CHIP_R600)
337 value = rdev->config.r600.backend_map;
342 case RADEON_INFO_VA_START:
343 /* this is where we report if vm is supported or not */
344 if (rdev->family < CHIP_CAYMAN)
346 value = RADEON_VA_RESERVED_SIZE;
348 case RADEON_INFO_IB_VM_MAX_SIZE:
349 /* this is where we report if vm is supported or not */
350 if (rdev->family < CHIP_CAYMAN)
352 value = RADEON_IB_VM_MAX_SIZE;
354 case RADEON_INFO_MAX_PIPES:
355 if (rdev->family >= CHIP_TAHITI)
356 value = rdev->config.si.max_cu_per_sh;
357 else if (rdev->family >= CHIP_CAYMAN)
358 value = rdev->config.cayman.max_pipes_per_simd;
359 else if (rdev->family >= CHIP_CEDAR)
360 value = rdev->config.evergreen.max_pipes;
361 else if (rdev->family >= CHIP_RV770)
362 value = rdev->config.rv770.max_pipes;
363 else if (rdev->family >= CHIP_R600)
364 value = rdev->config.r600.max_pipes;
369 case RADEON_INFO_MAX_SE:
370 if (rdev->family >= CHIP_TAHITI)
371 value = rdev->config.si.max_shader_engines;
372 else if (rdev->family >= CHIP_CAYMAN)
373 value = rdev->config.cayman.max_shader_engines;
374 else if (rdev->family >= CHIP_CEDAR)
375 value = rdev->config.evergreen.num_ses;
379 case RADEON_INFO_MAX_SH_PER_SE:
380 if (rdev->family >= CHIP_TAHITI)
381 value = rdev->config.si.max_sh_per_se;
386 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
389 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
390 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
398 * Outdated mess for old drm with Xorg being in charge (void function now).
401 * radeon_driver_firstopen_kms - drm callback for first open
403 * @dev: drm dev pointer
405 * Nothing to be done for KMS (all asics).
406 * Returns 0 on success.
408 int radeon_driver_firstopen_kms(struct drm_device *dev)
414 * radeon_driver_firstopen_kms - drm callback for last close
416 * @dev: drm dev pointer
418 * Switch vga switcheroo state after last close (all asics).
420 void radeon_driver_lastclose_kms(struct drm_device *dev)
423 vga_switcheroo_process_delayed_switch();
424 #endif /* DUMBBELL_WIP */
428 * radeon_driver_open_kms - drm callback for open
430 * @dev: drm dev pointer
431 * @file_priv: drm file
433 * On device open, init vm on cayman+ (all asics).
434 * Returns 0 on success, error on failure.
436 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
438 struct radeon_device *rdev = dev->dev_private;
440 file_priv->driver_priv = NULL;
442 /* new gpu have virtual address space support */
443 if (rdev->family >= CHIP_CAYMAN) {
444 struct radeon_fpriv *fpriv;
445 struct radeon_bo_va *bo_va;
448 fpriv = malloc(sizeof(*fpriv), DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
449 if (unlikely(!fpriv)) {
453 radeon_vm_init(rdev, &fpriv->vm);
455 /* map the ib pool buffer read only into
456 * virtual address space */
457 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
458 rdev->ring_tmp_bo.bo);
459 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
460 RADEON_VM_PAGE_READABLE |
461 RADEON_VM_PAGE_SNOOPED);
463 radeon_vm_fini(rdev, &fpriv->vm);
464 free(fpriv, DRM_MEM_DRIVER);
468 file_priv->driver_priv = fpriv;
474 * radeon_driver_postclose_kms - drm callback for post close
476 * @dev: drm dev pointer
477 * @file_priv: drm file
479 * On device post close, tear down vm on cayman+ (all asics).
481 void radeon_driver_postclose_kms(struct drm_device *dev,
482 struct drm_file *file_priv)
484 struct radeon_device *rdev = dev->dev_private;
486 /* new gpu have virtual address space support */
487 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
488 struct radeon_fpriv *fpriv = file_priv->driver_priv;
489 struct radeon_bo_va *bo_va;
492 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
494 bo_va = radeon_vm_bo_find(&fpriv->vm,
495 rdev->ring_tmp_bo.bo);
497 radeon_vm_bo_rmv(rdev, bo_va);
498 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
501 radeon_vm_fini(rdev, &fpriv->vm);
502 free(fpriv, DRM_MEM_DRIVER);
503 file_priv->driver_priv = NULL;
508 * radeon_driver_preclose_kms - drm callback for pre close
510 * @dev: drm dev pointer
511 * @file_priv: drm file
513 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
516 void radeon_driver_preclose_kms(struct drm_device *dev,
517 struct drm_file *file_priv)
519 struct radeon_device *rdev = dev->dev_private;
520 if (rdev->hyperz_filp == file_priv)
521 rdev->hyperz_filp = NULL;
522 if (rdev->cmask_filp == file_priv)
523 rdev->cmask_filp = NULL;
527 * VBlank related functions.
530 * radeon_get_vblank_counter_kms - get frame count
532 * @dev: drm dev pointer
533 * @crtc: crtc to get the frame count from
535 * Gets the frame count on the requested crtc (all asics).
536 * Returns frame count on success, -EINVAL on failure.
538 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
540 struct radeon_device *rdev = dev->dev_private;
542 if (crtc < 0 || crtc >= rdev->num_crtc) {
543 DRM_ERROR("Invalid crtc %d\n", crtc);
547 return radeon_get_vblank_counter(rdev, crtc);
551 * radeon_enable_vblank_kms - enable vblank interrupt
553 * @dev: drm dev pointer
554 * @crtc: crtc to enable vblank interrupt for
556 * Enable the interrupt on the requested crtc (all asics).
557 * Returns 0 on success, -EINVAL on failure.
559 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
561 struct radeon_device *rdev = dev->dev_private;
564 if (crtc < 0 || crtc >= rdev->num_crtc) {
565 DRM_ERROR("Invalid crtc %d\n", crtc);
569 mtx_lock(&rdev->irq.lock);
570 rdev->irq.crtc_vblank_int[crtc] = true;
571 r = radeon_irq_set(rdev);
572 mtx_unlock(&rdev->irq.lock);
577 * radeon_disable_vblank_kms - disable vblank interrupt
579 * @dev: drm dev pointer
580 * @crtc: crtc to disable vblank interrupt for
582 * Disable the interrupt on the requested crtc (all asics).
584 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
586 struct radeon_device *rdev = dev->dev_private;
588 if (crtc < 0 || crtc >= rdev->num_crtc) {
589 DRM_ERROR("Invalid crtc %d\n", crtc);
593 mtx_lock(&rdev->irq.lock);
594 rdev->irq.crtc_vblank_int[crtc] = false;
595 radeon_irq_set(rdev);
596 mtx_unlock(&rdev->irq.lock);
600 * radeon_get_vblank_timestamp_kms - get vblank timestamp
602 * @dev: drm dev pointer
603 * @crtc: crtc to get the timestamp for
604 * @max_error: max error
605 * @vblank_time: time value
606 * @flags: flags passed to the driver
608 * Gets the timestamp on the requested crtc based on the
609 * scanout position. (all asics).
610 * Returns postive status flags on success, negative error on failure.
612 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
614 struct timeval *vblank_time,
617 struct drm_crtc *drmcrtc;
618 struct radeon_device *rdev = dev->dev_private;
620 if (crtc < 0 || crtc >= dev->num_crtcs) {
621 DRM_ERROR("Invalid crtc %d\n", crtc);
625 /* Get associated drm_crtc: */
626 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
628 /* Helper routine in DRM core does all the work: */
629 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
637 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
638 struct drm_file *file_priv)
640 /* Not valid in KMS. */
644 #define KMS_INVALID_IOCTL(name) \
646 name(struct drm_device *dev, void *data, struct drm_file *file_priv) \
648 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
653 * All these ioctls are invalid in kms world.
655 KMS_INVALID_IOCTL(radeon_cp_init_kms)
656 KMS_INVALID_IOCTL(radeon_cp_start_kms)
657 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
658 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
659 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
660 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
661 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
662 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
663 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
664 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
665 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
666 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
667 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
668 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
669 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
670 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
671 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
672 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
673 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
674 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
675 KMS_INVALID_IOCTL(radeon_mem_free_kms)
676 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
677 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
678 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
679 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
680 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
681 KMS_INVALID_IOCTL(radeon_surface_free_kms)
684 struct drm_ioctl_desc radeon_ioctls_kms[] = {
685 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
686 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
687 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
688 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
689 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
690 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
691 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
692 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
693 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
694 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
695 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
696 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
697 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
698 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
699 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
700 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
701 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
702 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
703 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
704 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
705 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
706 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
707 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
708 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
709 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
710 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
711 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
713 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
714 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
715 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
716 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
717 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
718 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
719 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
720 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
721 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
722 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
723 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
724 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
725 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
727 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);