2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <dev/drm2/drmP.h>
37 #include <dev/drm2/radeon/radeon_drm.h>
40 #include "radeon_trace.h"
41 #endif /* FREEBSD_WIP */
44 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
45 int radeon_ttm_init(struct radeon_device *rdev);
46 void radeon_ttm_fini(struct radeon_device *rdev);
48 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
51 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
52 * function are calling it.
55 static void radeon_bo_clear_va(struct radeon_bo *bo)
57 struct radeon_bo_va *bo_va, *tmp;
59 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
60 /* remove from all vm address space */
61 radeon_vm_bo_rmv(bo->rdev, bo_va);
65 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
69 bo = container_of(tbo, struct radeon_bo, tbo);
70 sx_xlock(&bo->rdev->gem.mutex);
71 list_del_init(&bo->list);
72 sx_xunlock(&bo->rdev->gem.mutex);
73 radeon_bo_clear_surface_reg(bo);
74 radeon_bo_clear_va(bo);
75 drm_gem_object_release(&bo->gem_base);
76 free(bo, DRM_MEM_DRIVER);
79 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
81 if (bo->destroy == &radeon_ttm_bo_destroy)
86 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
90 rbo->placement.fpfn = 0;
91 rbo->placement.lpfn = 0;
92 rbo->placement.placement = rbo->placements;
93 rbo->placement.busy_placement = rbo->placements;
94 if (domain & RADEON_GEM_DOMAIN_VRAM)
95 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
97 if (domain & RADEON_GEM_DOMAIN_GTT) {
98 if (rbo->rdev->flags & RADEON_IS_AGP) {
99 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
101 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
104 if (domain & RADEON_GEM_DOMAIN_CPU) {
105 if (rbo->rdev->flags & RADEON_IS_AGP) {
106 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
108 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
112 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
113 rbo->placement.num_placement = c;
114 rbo->placement.num_busy_placement = c;
117 int radeon_bo_create(struct radeon_device *rdev,
118 unsigned long size, int byte_align, bool kernel, u32 domain,
119 struct sg_table *sg, struct radeon_bo **bo_ptr)
121 struct radeon_bo *bo;
122 enum ttm_bo_type type;
123 unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
127 size = roundup2(size, PAGE_SIZE);
130 type = ttm_bo_type_kernel;
132 type = ttm_bo_type_sg;
134 type = ttm_bo_type_device;
138 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
139 sizeof(struct radeon_bo));
141 bo = malloc(sizeof(struct radeon_bo),
142 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
145 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
147 free(bo, DRM_MEM_DRIVER);
151 bo->gem_base.driver_private = NULL;
152 bo->surface_reg = -1;
153 INIT_LIST_HEAD(&bo->list);
154 INIT_LIST_HEAD(&bo->va);
155 radeon_ttm_placement_from_domain(bo, domain);
156 /* Kernel allocation are uninterruptible */
157 sx_slock(&rdev->pm.mclk_lock);
158 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
159 &bo->placement, page_align, !kernel, NULL,
160 acc_size, sg, &radeon_ttm_bo_destroy);
161 sx_sunlock(&rdev->pm.mclk_lock);
162 if (unlikely(r != 0)) {
168 trace_radeon_bo_create(bo);
169 #endif /* FREEBSD_WIP */
174 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
185 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
189 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
193 radeon_bo_check_tiling(bo, 0, 0);
197 void radeon_bo_kunmap(struct radeon_bo *bo)
199 if (bo->kptr == NULL)
202 radeon_bo_check_tiling(bo, 0, 0);
203 ttm_bo_kunmap(&bo->kmap);
206 void radeon_bo_unref(struct radeon_bo **bo)
208 struct ttm_buffer_object *tbo;
209 struct radeon_device *rdev;
215 sx_slock(&rdev->pm.mclk_lock);
217 sx_sunlock(&rdev->pm.mclk_lock);
222 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
230 *gpu_addr = radeon_bo_gpu_offset(bo);
232 if (max_offset != 0) {
235 if (domain == RADEON_GEM_DOMAIN_VRAM)
236 domain_start = bo->rdev->mc.vram_start;
238 domain_start = bo->rdev->mc.gtt_start;
239 if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) {
240 DRM_ERROR("radeon_bo_pin_restricted: "
242 "(radeon_bo_gpu_offset(%ju) - "
244 (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo),
245 (uintmax_t)domain_start);
251 radeon_ttm_placement_from_domain(bo, domain);
252 if (domain == RADEON_GEM_DOMAIN_VRAM) {
253 /* force to pin into visible video ram */
254 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
257 u64 lpfn = max_offset >> PAGE_SHIFT;
259 if (!bo->placement.lpfn)
260 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
262 if (lpfn < bo->placement.lpfn)
263 bo->placement.lpfn = lpfn;
265 for (i = 0; i < bo->placement.num_placement; i++)
266 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
267 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
268 if (likely(r == 0)) {
270 if (gpu_addr != NULL)
271 *gpu_addr = radeon_bo_gpu_offset(bo);
273 if (unlikely(r != 0))
274 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
278 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
280 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
283 int radeon_bo_unpin(struct radeon_bo *bo)
287 if (!bo->pin_count) {
288 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
294 for (i = 0; i < bo->placement.num_placement; i++)
295 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
296 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
297 if (unlikely(r != 0))
298 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
302 int radeon_bo_evict_vram(struct radeon_device *rdev)
304 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
305 if (0 && (rdev->flags & RADEON_IS_IGP)) {
306 if (rdev->mc.igp_sideport_enabled == false)
307 /* Useless to evict on IGP chips */
310 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
313 void radeon_bo_force_delete(struct radeon_device *rdev)
315 struct radeon_bo *bo, *n;
317 if (list_empty(&rdev->gem.objects)) {
320 dev_err(rdev->dev, "Userspace still has active objects !\n");
321 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
322 DRM_LOCK(rdev->ddev);
323 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
324 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
325 *((unsigned long *)&bo->gem_base.refcount));
326 sx_xlock(&bo->rdev->gem.mutex);
327 list_del_init(&bo->list);
328 sx_xunlock(&bo->rdev->gem.mutex);
329 /* this should unref the ttm bo */
330 drm_gem_object_unreference(&bo->gem_base);
331 DRM_UNLOCK(rdev->ddev);
335 int radeon_bo_init(struct radeon_device *rdev)
337 /* Add an MTRR for the VRAM */
338 rdev->mc.vram_mtrr = drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
340 DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n",
341 (uintmax_t)rdev->mc.mc_vram_size >> 20,
342 (uintmax_t)rdev->mc.aper_size >> 20);
343 DRM_INFO("RAM width %dbits %cDR\n",
344 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
345 return radeon_ttm_init(rdev);
348 void radeon_bo_fini(struct radeon_device *rdev)
350 radeon_ttm_fini(rdev);
353 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
354 struct list_head *head)
357 list_add(&lobj->tv.head, head);
359 list_add_tail(&lobj->tv.head, head);
363 int radeon_bo_list_validate(struct list_head *head)
365 struct radeon_bo_list *lobj;
366 struct radeon_bo *bo;
370 r = ttm_eu_reserve_buffers(head);
371 if (unlikely(r != 0)) {
374 list_for_each_entry(lobj, head, tv.head) {
376 if (!bo->pin_count) {
377 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
380 radeon_ttm_placement_from_domain(bo, domain);
381 r = ttm_bo_validate(&bo->tbo, &bo->placement,
384 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
385 domain |= RADEON_GEM_DOMAIN_GTT;
391 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
392 lobj->tiling_flags = bo->tiling_flags;
398 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
399 struct vm_area_struct *vma)
401 return ttm_fbdev_mmap(vma, &bo->tbo);
403 #endif /* FREEBSD_WIP */
405 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
407 struct radeon_device *rdev = bo->rdev;
408 struct radeon_surface_reg *reg;
409 struct radeon_bo *old_object;
413 KASSERT(radeon_bo_is_reserved(bo),
414 ("radeon_bo_get_surface_reg: radeon_bo is not reserved"));
416 if (!bo->tiling_flags)
419 if (bo->surface_reg >= 0) {
420 reg = &rdev->surface_regs[bo->surface_reg];
426 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
428 reg = &rdev->surface_regs[i];
432 old_object = reg->bo;
433 if (old_object->pin_count == 0)
437 /* if we are all out */
438 if (i == RADEON_GEM_MAX_SURFACES) {
441 /* find someone with a surface reg and nuke their BO */
442 reg = &rdev->surface_regs[steal];
443 old_object = reg->bo;
444 /* blow away the mapping */
445 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
446 ttm_bo_unmap_virtual(&old_object->tbo);
447 old_object->surface_reg = -1;
455 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
456 bo->tbo.mem.start << PAGE_SHIFT,
457 bo->tbo.num_pages << PAGE_SHIFT);
461 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
463 struct radeon_device *rdev = bo->rdev;
464 struct radeon_surface_reg *reg;
466 if (bo->surface_reg == -1)
469 reg = &rdev->surface_regs[bo->surface_reg];
470 radeon_clear_surface_reg(rdev, bo->surface_reg);
473 bo->surface_reg = -1;
476 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
477 uint32_t tiling_flags, uint32_t pitch)
479 struct radeon_device *rdev = bo->rdev;
482 if (rdev->family >= CHIP_CEDAR) {
483 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
485 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
486 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
487 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
488 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
489 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
523 if (stilesplit > 6) {
527 r = radeon_bo_reserve(bo, false);
528 if (unlikely(r != 0))
530 bo->tiling_flags = tiling_flags;
532 radeon_bo_unreserve(bo);
536 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
537 uint32_t *tiling_flags,
540 KASSERT(radeon_bo_is_reserved(bo),
541 ("radeon_bo_get_tiling_flags: radeon_bo is not reserved"));
543 *tiling_flags = bo->tiling_flags;
548 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
551 KASSERT((radeon_bo_is_reserved(bo) || force_drop),
552 ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop"));
554 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
558 radeon_bo_clear_surface_reg(bo);
562 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
566 if (bo->surface_reg >= 0)
567 radeon_bo_clear_surface_reg(bo);
571 if ((bo->surface_reg >= 0) && !has_moved)
574 return radeon_bo_get_surface_reg(bo);
577 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
578 struct ttm_mem_reg *mem)
580 struct radeon_bo *rbo;
581 if (!radeon_ttm_bo_is_radeon_bo(bo))
583 rbo = container_of(bo, struct radeon_bo, tbo);
584 radeon_bo_check_tiling(rbo, 0, 1);
585 radeon_vm_bo_invalidate(rbo->rdev, rbo);
588 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
590 struct radeon_device *rdev;
591 struct radeon_bo *rbo;
592 unsigned long offset, size;
595 if (!radeon_ttm_bo_is_radeon_bo(bo))
597 rbo = container_of(bo, struct radeon_bo, tbo);
598 radeon_bo_check_tiling(rbo, 0, 0);
600 if (bo->mem.mem_type == TTM_PL_VRAM) {
601 size = bo->mem.num_pages << PAGE_SHIFT;
602 offset = bo->mem.start << PAGE_SHIFT;
603 if ((offset + size) > rdev->mc.visible_vram_size) {
604 /* hurrah the memory is not visible ! */
605 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
606 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
607 r = ttm_bo_validate(bo, &rbo->placement, false, false);
608 if (unlikely(r != 0))
610 offset = bo->mem.start << PAGE_SHIFT;
611 /* this should not happen */
612 if ((offset + size) > rdev->mc.visible_vram_size)
619 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
623 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
624 if (unlikely(r != 0))
626 mtx_lock(&bo->tbo.bdev->fence_lock);
628 *mem_type = bo->tbo.mem.mem_type;
629 if (bo->tbo.sync_obj)
630 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
631 mtx_unlock(&bo->tbo.bdev->fence_lock);
632 ttm_bo_unreserve(&bo->tbo);
638 * radeon_bo_reserve - reserve bo
640 * @no_intr: don't return -ERESTARTSYS on pending signal
643 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
644 * a signal. Release all buffer reservations and return to user-space.
646 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
650 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
651 if (unlikely(r != 0)) {
652 if (r != -ERESTARTSYS)
653 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);