2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <dev/drm2/drmP.h>
34 #include <dev/drm2/radeon/radeon_drm.h>
35 #include "radeon_reg.h"
42 * IBs (Indirect Buffers) and areas of GPU accessible memory where
43 * commands are stored. You can put a pointer to the IB in the
44 * command ring and the hw will fetch the commands from the IB
45 * and execute them. Generally userspace acceleration drivers
46 * produce command buffers which are send to the kernel and
47 * put in IBs for execution by the requested ring.
49 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
50 #endif /* DUMBBELL_WIP */
53 * radeon_ib_get - request an IB (Indirect Buffer)
55 * @rdev: radeon_device pointer
56 * @ring: ring index the IB is associated with
57 * @ib: IB object returned
58 * @size: requested IB size
60 * Request an IB (all asics). IBs are allocated using the
62 * Returns 0 on success, error on failure.
64 int radeon_ib_get(struct radeon_device *rdev, int ring,
65 struct radeon_ib *ib, struct radeon_vm *vm,
70 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
72 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
76 r = radeon_semaphore_create(rdev, &ib->semaphore);
83 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
86 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
87 * space and soffset is the offset inside the pool bo
89 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
91 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
93 ib->is_const_ib = false;
94 for (i = 0; i < RADEON_NUM_RINGS; ++i)
95 ib->sync_to[i] = NULL;
101 * radeon_ib_free - free an IB (Indirect Buffer)
103 * @rdev: radeon_device pointer
104 * @ib: IB object to free
106 * Free an IB (all asics).
108 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
110 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
111 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
112 radeon_fence_unref(&ib->fence);
116 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
118 * @rdev: radeon_device pointer
119 * @ib: IB object to schedule
120 * @const_ib: Const IB to schedule (SI only)
122 * Schedule an IB on the associated ring (all asics).
123 * Returns 0 on success, error on failure.
125 * On SI, there are two parallel engines fed from the primary ring,
126 * the CE (Constant Engine) and the DE (Drawing Engine). Since
127 * resource descriptors have moved to memory, the CE allows you to
128 * prime the caches while the DE is updating register state so that
129 * the resource descriptors will be already in cache when the draw is
130 * processed. To accomplish this, the userspace driver submits two
131 * IBs, one for the CE and one for the DE. If there is a CE IB (called
132 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
133 * to SI there was just a DE IB.
135 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
136 struct radeon_ib *const_ib)
138 struct radeon_ring *ring = &rdev->ring[ib->ring];
139 bool need_sync = false;
142 if (!ib->length_dw || !ring->ready) {
143 /* TODO: Nothings in the ib we should report. */
144 dev_err(rdev->dev, "couldn't schedule ib\n");
148 /* 64 dwords should be enough for fence too */
149 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
151 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
154 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
155 struct radeon_fence *fence = ib->sync_to[i];
156 if (radeon_fence_need_sync(fence, ib->ring)) {
158 radeon_semaphore_sync_rings(rdev, ib->semaphore,
159 fence->ring, ib->ring);
160 radeon_fence_note_sync(fence, ib->ring);
163 /* immediately free semaphore when we don't need to sync */
165 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
167 /* if we can't remember our last VM flush then flush now! */
168 if (ib->vm && !ib->vm->last_flush) {
169 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
172 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
173 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
175 radeon_ring_ib_execute(rdev, ib->ring, ib);
176 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
178 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
179 radeon_ring_unlock_undo(rdev, ring);
183 const_ib->fence = radeon_fence_ref(ib->fence);
185 /* we just flushed the VM, remember that */
186 if (ib->vm && !ib->vm->last_flush) {
187 ib->vm->last_flush = radeon_fence_ref(ib->fence);
189 radeon_ring_unlock_commit(rdev, ring);
194 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
196 * @rdev: radeon_device pointer
198 * Initialize the suballocator to manage a pool of memory
199 * for use as IBs (all asics).
200 * Returns 0 on success, error on failure.
202 int radeon_ib_pool_init(struct radeon_device *rdev)
206 if (rdev->ib_pool_ready) {
209 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
210 RADEON_IB_POOL_SIZE*64*1024,
211 RADEON_GEM_DOMAIN_GTT);
216 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
221 rdev->ib_pool_ready = true;
223 if (radeon_debugfs_sa_init(rdev)) {
224 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
226 #endif /* DUMBBELL_WIP */
231 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
233 * @rdev: radeon_device pointer
235 * Tear down the suballocator managing the pool of memory
236 * for use as IBs (all asics).
238 void radeon_ib_pool_fini(struct radeon_device *rdev)
240 if (rdev->ib_pool_ready) {
241 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
242 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
243 rdev->ib_pool_ready = false;
248 * radeon_ib_ring_tests - test IBs on the rings
250 * @rdev: radeon_device pointer
252 * Test an IB (Indirect Buffer) on each ring.
253 * If the test fails, disable the ring.
254 * Returns 0 on success, error if the primary GFX ring
257 int radeon_ib_ring_tests(struct radeon_device *rdev)
262 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
263 struct radeon_ring *ring = &rdev->ring[i];
268 r = radeon_ib_test(rdev, i, ring);
272 if (i == RADEON_RING_TYPE_GFX_INDEX) {
273 /* oh, oh, that's really bad */
274 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
275 rdev->accel_working = false;
279 /* still not good, but we can live with it */
280 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
290 * Most engines on the GPU are fed via ring buffers. Ring
291 * buffers are areas of GPU accessible memory that the host
292 * writes commands into and the GPU reads commands out of.
293 * There is a rptr (read pointer) that determines where the
294 * GPU is currently reading, and a wptr (write pointer)
295 * which determines where the host has written. When the
296 * pointers are equal, the ring is idle. When the host
297 * writes commands to the ring buffer, it increments the
298 * wptr. The GPU then starts fetching commands and executes
299 * them until the pointers are equal again.
301 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
302 #endif /* DUMBBELL_WIP */
304 #if defined(DRM_DEBUG_CODE) && DRM_DEBUG_CODE != 0
306 * radeon_ring_write - write a value to the ring
308 * @ring: radeon_ring structure holding ring information
309 * @v: dword (dw) value to write
311 * Write a value to the requested ring buffer (all asics).
313 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
316 if (ring->count_dw <= 0) {
317 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
320 ring->ring[ring->wptr++] = v;
321 ring->wptr &= ring->ptr_mask;
323 ring->ring_free_dw--;
328 * radeon_ring_supports_scratch_reg - check if the ring supports
329 * writing to scratch registers
331 * @rdev: radeon_device pointer
332 * @ring: radeon_ring structure holding ring information
334 * Check if a specific ring supports writing to scratch registers (all asics).
335 * Returns true if the ring supports writing to scratch regs, false if not.
337 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
338 struct radeon_ring *ring)
341 case RADEON_RING_TYPE_GFX_INDEX:
342 case CAYMAN_RING_TYPE_CP1_INDEX:
343 case CAYMAN_RING_TYPE_CP2_INDEX:
351 * radeon_ring_free_size - update the free size
353 * @rdev: radeon_device pointer
354 * @ring: radeon_ring structure holding ring information
356 * Update the free dw slots in the ring buffer (all asics).
358 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
362 if (rdev->wb.enabled)
363 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
365 rptr = RREG32(ring->rptr_reg);
366 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
367 /* This works because ring_size is a power of 2 */
368 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
369 ring->ring_free_dw -= ring->wptr;
370 ring->ring_free_dw &= ring->ptr_mask;
371 if (!ring->ring_free_dw) {
372 ring->ring_free_dw = ring->ring_size / 4;
377 * radeon_ring_alloc - allocate space on the ring buffer
379 * @rdev: radeon_device pointer
380 * @ring: radeon_ring structure holding ring information
381 * @ndw: number of dwords to allocate in the ring buffer
383 * Allocate @ndw dwords in the ring buffer (all asics).
384 * Returns 0 on success, error on failure.
386 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
390 /* make sure we aren't trying to allocate more space than there is on the ring */
391 if (ndw > (ring->ring_size / 4))
393 /* Align requested size with padding so unlock_commit can
395 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
396 while (ndw > (ring->ring_free_dw - 1)) {
397 radeon_ring_free_size(rdev, ring);
398 if (ndw < ring->ring_free_dw) {
401 r = radeon_fence_wait_next_locked(rdev, ring->idx);
405 ring->count_dw = ndw;
406 ring->wptr_old = ring->wptr;
411 * radeon_ring_lock - lock the ring and allocate space on it
413 * @rdev: radeon_device pointer
414 * @ring: radeon_ring structure holding ring information
415 * @ndw: number of dwords to allocate in the ring buffer
417 * Lock the ring and allocate @ndw dwords in the ring buffer
419 * Returns 0 on success, error on failure.
421 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
425 sx_xlock(&rdev->ring_lock);
426 r = radeon_ring_alloc(rdev, ring, ndw);
428 sx_xunlock(&rdev->ring_lock);
435 * radeon_ring_commit - tell the GPU to execute the new
436 * commands on the ring buffer
438 * @rdev: radeon_device pointer
439 * @ring: radeon_ring structure holding ring information
441 * Update the wptr (write pointer) to tell the GPU to
442 * execute new commands on the ring buffer (all asics).
444 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
446 /* We pad to match fetch size */
447 while (ring->wptr & ring->align_mask) {
448 radeon_ring_write(ring, ring->nop);
451 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
452 (void)RREG32(ring->wptr_reg);
456 * radeon_ring_unlock_commit - tell the GPU to execute the new
457 * commands on the ring buffer and unlock it
459 * @rdev: radeon_device pointer
460 * @ring: radeon_ring structure holding ring information
462 * Call radeon_ring_commit() then unlock the ring (all asics).
464 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
466 radeon_ring_commit(rdev, ring);
467 sx_xunlock(&rdev->ring_lock);
471 * radeon_ring_undo - reset the wptr
473 * @ring: radeon_ring structure holding ring information
475 * Reset the driver's copy of the wptr (all asics).
477 void radeon_ring_undo(struct radeon_ring *ring)
479 ring->wptr = ring->wptr_old;
483 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
485 * @ring: radeon_ring structure holding ring information
487 * Call radeon_ring_undo() then unlock the ring (all asics).
489 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
491 radeon_ring_undo(ring);
492 sx_xunlock(&rdev->ring_lock);
496 * radeon_ring_force_activity - add some nop packets to the ring
498 * @rdev: radeon_device pointer
499 * @ring: radeon_ring structure holding ring information
501 * Add some nop packets to the ring to force activity (all asics).
502 * Used for lockup detection to see if the rptr is advancing.
504 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
508 radeon_ring_free_size(rdev, ring);
509 if (ring->rptr == ring->wptr) {
510 r = radeon_ring_alloc(rdev, ring, 1);
512 radeon_ring_write(ring, ring->nop);
513 radeon_ring_commit(rdev, ring);
519 * radeon_ring_lockup_update - update lockup variables
521 * @ring: radeon_ring structure holding ring information
523 * Update the last rptr value and timestamp (all asics).
525 void radeon_ring_lockup_update(struct radeon_ring *ring)
527 ring->last_rptr = ring->rptr;
528 ring->last_activity = jiffies;
532 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
533 * @rdev: radeon device structure
534 * @ring: radeon_ring structure holding ring information
536 * We don't need to initialize the lockup tracking information as we will either
537 * have CP rptr to a different value of jiffies wrap around which will force
538 * initialization of the lockup tracking informations.
540 * A possible false positivie is if we get call after while and last_cp_rptr ==
541 * the current CP rptr, even if it's unlikely it might happen. To avoid this
542 * if the elapsed time since last call is bigger than 2 second than we return
543 * false and update the tracking information. Due to this the caller must call
544 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
545 * the fencing code should be cautious about that.
547 * Caller should write to the ring to force CP to do something so we don't get
548 * false positive when CP is just gived nothing to do.
551 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
553 unsigned long cjiffies, elapsed;
557 if (!time_after(cjiffies, ring->last_activity)) {
558 /* likely a wrap around */
559 radeon_ring_lockup_update(ring);
562 rptr = RREG32(ring->rptr_reg);
563 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
564 if (ring->rptr != ring->last_rptr) {
565 /* CP is still working no lockup */
566 radeon_ring_lockup_update(ring);
569 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
570 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
571 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
574 /* give a chance to the GPU ... */
579 * radeon_ring_backup - Back up the content of a ring
581 * @rdev: radeon_device pointer
582 * @ring: the ring we want to back up
584 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
586 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
589 unsigned size, ptr, i;
591 /* just in case lock the ring */
592 sx_xlock(&rdev->ring_lock);
595 if (ring->ring_obj == NULL) {
596 sx_xunlock(&rdev->ring_lock);
600 /* it doesn't make sense to save anything if all fences are signaled */
601 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
602 sx_xunlock(&rdev->ring_lock);
606 /* calculate the number of dw on the ring */
607 if (ring->rptr_save_reg)
608 ptr = RREG32(ring->rptr_save_reg);
609 else if (rdev->wb.enabled)
610 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
612 /* no way to read back the next rptr */
613 sx_xunlock(&rdev->ring_lock);
617 size = ring->wptr + (ring->ring_size / 4);
619 size &= ring->ptr_mask;
621 sx_xunlock(&rdev->ring_lock);
625 /* and then save the content of the ring */
626 *data = malloc(size * sizeof(uint32_t), DRM_MEM_DRIVER, M_WAITOK);
628 sx_xunlock(&rdev->ring_lock);
631 for (i = 0; i < size; ++i) {
632 (*data)[i] = ring->ring[ptr++];
633 ptr &= ring->ptr_mask;
636 sx_xunlock(&rdev->ring_lock);
641 * radeon_ring_restore - append saved commands to the ring again
643 * @rdev: radeon_device pointer
644 * @ring: ring to append commands to
645 * @size: number of dwords we want to write
646 * @data: saved commands
648 * Allocates space on the ring and restore the previously saved commands.
650 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
651 unsigned size, uint32_t *data)
658 /* restore the saved ring content */
659 r = radeon_ring_lock(rdev, ring, size);
663 for (i = 0; i < size; ++i) {
664 radeon_ring_write(ring, data[i]);
667 radeon_ring_unlock_commit(rdev, ring);
668 free(data, DRM_MEM_DRIVER);
673 * radeon_ring_init - init driver ring struct.
675 * @rdev: radeon_device pointer
676 * @ring: radeon_ring structure holding ring information
677 * @ring_size: size of the ring
678 * @rptr_offs: offset of the rptr writeback location in the WB buffer
679 * @rptr_reg: MMIO offset of the rptr register
680 * @wptr_reg: MMIO offset of the wptr register
681 * @ptr_reg_shift: bit offset of the rptr/wptr values
682 * @ptr_reg_mask: bit mask of the rptr/wptr values
683 * @nop: nop packet for this ring
685 * Initialize the driver information for the selected ring (all asics).
686 * Returns 0 on success, error on failure.
688 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
689 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
690 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
695 ring->ring_size = ring_size;
696 ring->rptr_offs = rptr_offs;
697 ring->rptr_reg = rptr_reg;
698 ring->wptr_reg = wptr_reg;
699 ring->ptr_reg_shift = ptr_reg_shift;
700 ring->ptr_reg_mask = ptr_reg_mask;
702 /* Allocate ring buffer */
703 if (ring->ring_obj == NULL) {
704 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
705 RADEON_GEM_DOMAIN_GTT,
706 NULL, &ring->ring_obj);
708 dev_err(rdev->dev, "(%d) ring create failed\n", r);
711 r = radeon_bo_reserve(ring->ring_obj, false);
712 if (unlikely(r != 0)) {
713 radeon_bo_unref(&ring->ring_obj);
716 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
719 radeon_bo_unreserve(ring->ring_obj);
720 radeon_bo_unref(&ring->ring_obj);
721 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
724 ring_ptr = &ring->ring;
725 r = radeon_bo_kmap(ring->ring_obj,
727 radeon_bo_unreserve(ring->ring_obj);
729 dev_err(rdev->dev, "(%d) ring map failed\n", r);
730 radeon_bo_unref(&ring->ring_obj);
734 ring->ptr_mask = (ring->ring_size / 4) - 1;
735 ring->ring_free_dw = ring->ring_size / 4;
736 if (rdev->wb.enabled) {
737 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
738 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
739 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
742 if (radeon_debugfs_ring_init(rdev, ring)) {
743 DRM_ERROR("Failed to register debugfs file for rings !\n");
745 #endif /* DUMBBELL_WIP */
746 radeon_ring_lockup_update(ring);
751 * radeon_ring_fini - tear down the driver ring struct.
753 * @rdev: radeon_device pointer
754 * @ring: radeon_ring structure holding ring information
756 * Tear down the driver information for the selected ring (all asics).
758 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
761 struct radeon_bo *ring_obj;
763 sx_xlock(&rdev->ring_lock);
764 ring_obj = ring->ring_obj;
767 ring->ring_obj = NULL;
768 sx_xunlock(&rdev->ring_lock);
771 r = radeon_bo_reserve(ring_obj, false);
772 if (likely(r == 0)) {
773 radeon_bo_kunmap(ring_obj);
774 radeon_bo_unpin(ring_obj);
775 radeon_bo_unreserve(ring_obj);
777 radeon_bo_unref(&ring_obj);
784 #if defined(CONFIG_DEBUG_FS)
786 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
788 struct drm_info_node *node = (struct drm_info_node *) m->private;
789 struct drm_device *dev = node->minor->dev;
790 struct radeon_device *rdev = dev->dev_private;
791 int ridx = *(int*)node->info_ent->data;
792 struct radeon_ring *ring = &rdev->ring[ridx];
793 unsigned count, i, j;
796 radeon_ring_free_size(rdev, ring);
797 count = (ring->ring_size / 4) - ring->ring_free_dw;
798 tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift;
799 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
800 tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift;
801 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
802 if (ring->rptr_save_reg) {
803 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
804 RREG32(ring->rptr_save_reg));
806 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
807 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
808 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
809 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr);
810 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
811 seq_printf(m, "%u dwords in ring\n", count);
812 /* print 8 dw before current rptr as often it's the last executed
813 * packet that is the root issue
815 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
816 for (j = 0; j <= (count + 32); j++) {
817 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
818 i = (i + 1) & ring->ptr_mask;
823 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
824 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
825 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
826 static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX;
827 static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
829 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
830 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
831 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
832 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
833 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index},
834 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index},
837 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
839 struct drm_info_node *node = (struct drm_info_node *) m->private;
840 struct drm_device *dev = node->minor->dev;
841 struct radeon_device *rdev = dev->dev_private;
843 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
849 static struct drm_info_list radeon_debugfs_sa_list[] = {
850 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
856 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
858 #if defined(CONFIG_DEBUG_FS)
860 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
861 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
862 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
865 if (&rdev->ring[ridx] != ring)
868 r = radeon_debugfs_add_files(rdev, info, 1);
876 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
878 #if defined(CONFIG_DEBUG_FS)
879 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
884 #endif /* DUMBBELL_WIP */