1 /* radeon_state.c -- State support for Radeon -*- linux-c -*- */
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <dev/drm2/drmP.h>
34 #include <dev/drm2/drm_buffer.h>
35 #include <dev/drm2/radeon/radeon_drm.h>
36 #include "radeon_drv.h"
38 /* ================================================================
39 * Helper functions for client state checking and fixup
42 static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
44 struct drm_file * file_priv,
48 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
49 struct drm_radeon_driver_file_fields *radeon_priv;
51 /* Hrm ... the story of the offset ... So this function converts
52 * the various ideas of what userland clients might have for an
53 * offset in the card address space into an offset into the card
54 * address space :) So with a sane client, it should just keep
55 * the value intact and just do some boundary checking. However,
56 * not all clients are sane. Some older clients pass us 0 based
57 * offsets relative to the start of the framebuffer and some may
58 * assume the AGP aperture it appended to the framebuffer, so we
59 * try to detect those cases and fix them up.
61 * Note: It might be a good idea here to make sure the offset lands
62 * in some "allowed" area to protect things like the PCIE GART...
65 /* First, the best case, the offset already lands in either the
66 * framebuffer or the GART mapped space
68 if (radeon_check_offset(dev_priv, off))
71 /* Ok, that didn't happen... now check if we have a zero based
72 * offset that fits in the framebuffer + gart space, apply the
73 * magic offset we get from SETPARAM or calculated from fb_location
75 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
76 radeon_priv = file_priv->driver_priv;
77 off += radeon_priv->radeon_fb_delta;
80 /* Finally, assume we aimed at a GART offset if beyond the fb */
82 off = off - fb_end - 1 + dev_priv->gart_vm_start;
84 /* Now recheck and fail if out of bounds */
85 if (radeon_check_offset(dev_priv, off)) {
86 DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
93 static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
95 struct drm_file *file_priv,
96 int id, struct drm_buffer *buf)
101 case RADEON_EMIT_PP_MISC:
102 data = drm_buffer_pointer_to_dword(buf,
103 (RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4);
105 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
106 DRM_ERROR("Invalid depth buffer offset\n");
109 dev_priv->have_z_offset = 1;
112 case RADEON_EMIT_PP_CNTL:
113 data = drm_buffer_pointer_to_dword(buf,
114 (RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4);
116 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
117 DRM_ERROR("Invalid colour buffer offset\n");
122 case R200_EMIT_PP_TXOFFSET_0:
123 case R200_EMIT_PP_TXOFFSET_1:
124 case R200_EMIT_PP_TXOFFSET_2:
125 case R200_EMIT_PP_TXOFFSET_3:
126 case R200_EMIT_PP_TXOFFSET_4:
127 case R200_EMIT_PP_TXOFFSET_5:
128 data = drm_buffer_pointer_to_dword(buf, 0);
129 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
130 DRM_ERROR("Invalid R200 texture offset\n");
135 case RADEON_EMIT_PP_TXFILTER_0:
136 case RADEON_EMIT_PP_TXFILTER_1:
137 case RADEON_EMIT_PP_TXFILTER_2:
138 data = drm_buffer_pointer_to_dword(buf,
139 (RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4);
140 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
141 DRM_ERROR("Invalid R100 texture offset\n");
146 case R200_EMIT_PP_CUBIC_OFFSETS_0:
147 case R200_EMIT_PP_CUBIC_OFFSETS_1:
148 case R200_EMIT_PP_CUBIC_OFFSETS_2:
149 case R200_EMIT_PP_CUBIC_OFFSETS_3:
150 case R200_EMIT_PP_CUBIC_OFFSETS_4:
151 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
153 for (i = 0; i < 5; i++) {
154 data = drm_buffer_pointer_to_dword(buf, i);
155 if (radeon_check_and_fixup_offset(dev_priv,
159 ("Invalid R200 cubic texture offset\n");
166 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
167 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
168 case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
170 for (i = 0; i < 5; i++) {
171 data = drm_buffer_pointer_to_dword(buf, i);
172 if (radeon_check_and_fixup_offset(dev_priv,
176 ("Invalid R100 cubic texture offset\n");
183 case R200_EMIT_VAP_CTL:{
186 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
191 case RADEON_EMIT_RB3D_COLORPITCH:
192 case RADEON_EMIT_RE_LINE_PATTERN:
193 case RADEON_EMIT_SE_LINE_WIDTH:
194 case RADEON_EMIT_PP_LUM_MATRIX:
195 case RADEON_EMIT_PP_ROT_MATRIX_0:
196 case RADEON_EMIT_RB3D_STENCILREFMASK:
197 case RADEON_EMIT_SE_VPORT_XSCALE:
198 case RADEON_EMIT_SE_CNTL:
199 case RADEON_EMIT_SE_CNTL_STATUS:
200 case RADEON_EMIT_RE_MISC:
201 case RADEON_EMIT_PP_BORDER_COLOR_0:
202 case RADEON_EMIT_PP_BORDER_COLOR_1:
203 case RADEON_EMIT_PP_BORDER_COLOR_2:
204 case RADEON_EMIT_SE_ZBIAS_FACTOR:
205 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
206 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
207 case R200_EMIT_PP_TXCBLEND_0:
208 case R200_EMIT_PP_TXCBLEND_1:
209 case R200_EMIT_PP_TXCBLEND_2:
210 case R200_EMIT_PP_TXCBLEND_3:
211 case R200_EMIT_PP_TXCBLEND_4:
212 case R200_EMIT_PP_TXCBLEND_5:
213 case R200_EMIT_PP_TXCBLEND_6:
214 case R200_EMIT_PP_TXCBLEND_7:
215 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
216 case R200_EMIT_TFACTOR_0:
217 case R200_EMIT_VTX_FMT_0:
218 case R200_EMIT_MATRIX_SELECT_0:
219 case R200_EMIT_TEX_PROC_CTL_2:
220 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
221 case R200_EMIT_PP_TXFILTER_0:
222 case R200_EMIT_PP_TXFILTER_1:
223 case R200_EMIT_PP_TXFILTER_2:
224 case R200_EMIT_PP_TXFILTER_3:
225 case R200_EMIT_PP_TXFILTER_4:
226 case R200_EMIT_PP_TXFILTER_5:
227 case R200_EMIT_VTE_CNTL:
228 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
229 case R200_EMIT_PP_TAM_DEBUG3:
230 case R200_EMIT_PP_CNTL_X:
231 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
232 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
233 case R200_EMIT_RE_SCISSOR_TL_0:
234 case R200_EMIT_RE_SCISSOR_TL_1:
235 case R200_EMIT_RE_SCISSOR_TL_2:
236 case R200_EMIT_SE_VAP_CNTL_STATUS:
237 case R200_EMIT_SE_VTX_STATE_CNTL:
238 case R200_EMIT_RE_POINTSIZE:
239 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
240 case R200_EMIT_PP_CUBIC_FACES_0:
241 case R200_EMIT_PP_CUBIC_FACES_1:
242 case R200_EMIT_PP_CUBIC_FACES_2:
243 case R200_EMIT_PP_CUBIC_FACES_3:
244 case R200_EMIT_PP_CUBIC_FACES_4:
245 case R200_EMIT_PP_CUBIC_FACES_5:
246 case RADEON_EMIT_PP_TEX_SIZE_0:
247 case RADEON_EMIT_PP_TEX_SIZE_1:
248 case RADEON_EMIT_PP_TEX_SIZE_2:
249 case R200_EMIT_RB3D_BLENDCOLOR:
250 case R200_EMIT_TCL_POINT_SPRITE_CNTL:
251 case RADEON_EMIT_PP_CUBIC_FACES_0:
252 case RADEON_EMIT_PP_CUBIC_FACES_1:
253 case RADEON_EMIT_PP_CUBIC_FACES_2:
254 case R200_EMIT_PP_TRI_PERF_CNTL:
255 case R200_EMIT_PP_AFS_0:
256 case R200_EMIT_PP_AFS_1:
257 case R200_EMIT_ATF_TFACTOR:
258 case R200_EMIT_PP_TXCTLALL_0:
259 case R200_EMIT_PP_TXCTLALL_1:
260 case R200_EMIT_PP_TXCTLALL_2:
261 case R200_EMIT_PP_TXCTLALL_3:
262 case R200_EMIT_PP_TXCTLALL_4:
263 case R200_EMIT_PP_TXCTLALL_5:
264 case R200_EMIT_VAP_PVS_CNTL:
265 /* These packets don't contain memory offsets */
269 DRM_ERROR("Unknown state packet ID %d\n", id);
276 static int radeon_check_and_fixup_packet3(drm_radeon_private_t *
278 struct drm_file *file_priv,
279 drm_radeon_kcmd_buffer_t *
283 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
287 count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16);
290 if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) {
291 DRM_ERROR("Not a type 3 packet\n");
295 if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) {
296 DRM_ERROR("Packet size larger than size of data provided\n");
300 switch (*cmd & 0xff00) {
301 /* XXX Are there old drivers needing other packets? */
303 case RADEON_3D_DRAW_IMMD:
304 case RADEON_3D_DRAW_VBUF:
305 case RADEON_3D_DRAW_INDX:
306 case RADEON_WAIT_FOR_IDLE:
308 case RADEON_3D_CLEAR_ZMASK:
309 /* case RADEON_CP_NEXT_CHAR:
310 case RADEON_CP_PLY_NEXTSCAN:
311 case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
312 /* these packets are safe */
315 case RADEON_CP_3D_DRAW_IMMD_2:
316 case RADEON_CP_3D_DRAW_VBUF_2:
317 case RADEON_CP_3D_DRAW_INDX_2:
318 case RADEON_3D_CLEAR_HIZ:
319 /* safe but r200 only */
320 if (dev_priv->microcode_version != UCODE_R200) {
321 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
326 case RADEON_3D_LOAD_VBPNTR:
328 if (count > 18) { /* 12 arrays max */
329 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
334 /* carefully check packet contents */
335 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
337 narrays = *cmd & ~0xc000;
340 while ((k < narrays) && (i < (count + 2))) {
341 i++; /* skip attribute field */
342 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
343 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
346 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
354 /* have one more to process, they come in pairs */
355 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
357 if (radeon_check_and_fixup_offset(dev_priv,
361 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
368 /* do the counts match what we expect ? */
369 if ((k != narrays) || (i != (count + 2))) {
371 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
372 k, i, narrays, count + 1);
377 case RADEON_3D_RNDR_GEN_INDX_PRIM:
378 if (dev_priv->microcode_version != UCODE_R100) {
379 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
383 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
384 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
385 DRM_ERROR("Invalid rndr_gen_indx offset\n");
390 case RADEON_CP_INDX_BUFFER:
391 if (dev_priv->microcode_version != UCODE_R200) {
392 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
396 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
397 if ((*cmd & 0x8000ffff) != 0x80000810) {
398 DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd);
401 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
402 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
403 DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd);
408 case RADEON_CNTL_HOSTDATA_BLT:
409 case RADEON_CNTL_PAINT_MULTI:
410 case RADEON_CNTL_BITBLT_MULTI:
411 /* MSB of opcode: next DWORD GUI_CNTL */
412 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
413 if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
414 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
415 u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
416 offset = *cmd2 << 10;
417 if (radeon_check_and_fixup_offset
418 (dev_priv, file_priv, &offset)) {
419 DRM_ERROR("Invalid first packet offset\n");
422 *cmd2 = (*cmd2 & 0xffc00000) | offset >> 10;
425 if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
426 (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
427 u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
428 offset = *cmd3 << 10;
429 if (radeon_check_and_fixup_offset
430 (dev_priv, file_priv, &offset)) {
431 DRM_ERROR("Invalid second packet offset\n");
434 *cmd3 = (*cmd3 & 0xffc00000) | offset >> 10;
439 DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00);
446 /* ================================================================
447 * CP hardware state programming functions
450 static void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
451 struct drm_clip_rect * box)
455 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
456 box->x1, box->y1, box->x2, box->y2);
459 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
460 OUT_RING((box->y1 << 16) | box->x1);
461 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
462 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
468 static int radeon_emit_state(drm_radeon_private_t * dev_priv,
469 struct drm_file *file_priv,
470 drm_radeon_context_regs_t * ctx,
471 drm_radeon_texture_regs_t * tex,
475 DRM_DEBUG("dirty=0x%08x\n", dirty);
477 if (dirty & RADEON_UPLOAD_CONTEXT) {
478 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
479 &ctx->rb3d_depthoffset)) {
480 DRM_ERROR("Invalid depth buffer offset\n");
484 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
485 &ctx->rb3d_coloroffset)) {
486 DRM_ERROR("Invalid depth buffer offset\n");
491 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
492 OUT_RING(ctx->pp_misc);
493 OUT_RING(ctx->pp_fog_color);
494 OUT_RING(ctx->re_solid_color);
495 OUT_RING(ctx->rb3d_blendcntl);
496 OUT_RING(ctx->rb3d_depthoffset);
497 OUT_RING(ctx->rb3d_depthpitch);
498 OUT_RING(ctx->rb3d_zstencilcntl);
499 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
500 OUT_RING(ctx->pp_cntl);
501 OUT_RING(ctx->rb3d_cntl);
502 OUT_RING(ctx->rb3d_coloroffset);
503 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
504 OUT_RING(ctx->rb3d_colorpitch);
508 if (dirty & RADEON_UPLOAD_VERTFMT) {
510 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
511 OUT_RING(ctx->se_coord_fmt);
515 if (dirty & RADEON_UPLOAD_LINE) {
517 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
518 OUT_RING(ctx->re_line_pattern);
519 OUT_RING(ctx->re_line_state);
520 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
521 OUT_RING(ctx->se_line_width);
525 if (dirty & RADEON_UPLOAD_BUMPMAP) {
527 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
528 OUT_RING(ctx->pp_lum_matrix);
529 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
530 OUT_RING(ctx->pp_rot_matrix_0);
531 OUT_RING(ctx->pp_rot_matrix_1);
535 if (dirty & RADEON_UPLOAD_MASKS) {
537 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
538 OUT_RING(ctx->rb3d_stencilrefmask);
539 OUT_RING(ctx->rb3d_ropcntl);
540 OUT_RING(ctx->rb3d_planemask);
544 if (dirty & RADEON_UPLOAD_VIEWPORT) {
546 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
547 OUT_RING(ctx->se_vport_xscale);
548 OUT_RING(ctx->se_vport_xoffset);
549 OUT_RING(ctx->se_vport_yscale);
550 OUT_RING(ctx->se_vport_yoffset);
551 OUT_RING(ctx->se_vport_zscale);
552 OUT_RING(ctx->se_vport_zoffset);
556 if (dirty & RADEON_UPLOAD_SETUP) {
558 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
559 OUT_RING(ctx->se_cntl);
560 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
561 OUT_RING(ctx->se_cntl_status);
565 if (dirty & RADEON_UPLOAD_MISC) {
567 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
568 OUT_RING(ctx->re_misc);
572 if (dirty & RADEON_UPLOAD_TEX0) {
573 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
574 &tex[0].pp_txoffset)) {
575 DRM_ERROR("Invalid texture offset for unit 0\n");
580 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
581 OUT_RING(tex[0].pp_txfilter);
582 OUT_RING(tex[0].pp_txformat);
583 OUT_RING(tex[0].pp_txoffset);
584 OUT_RING(tex[0].pp_txcblend);
585 OUT_RING(tex[0].pp_txablend);
586 OUT_RING(tex[0].pp_tfactor);
587 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
588 OUT_RING(tex[0].pp_border_color);
592 if (dirty & RADEON_UPLOAD_TEX1) {
593 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
594 &tex[1].pp_txoffset)) {
595 DRM_ERROR("Invalid texture offset for unit 1\n");
600 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
601 OUT_RING(tex[1].pp_txfilter);
602 OUT_RING(tex[1].pp_txformat);
603 OUT_RING(tex[1].pp_txoffset);
604 OUT_RING(tex[1].pp_txcblend);
605 OUT_RING(tex[1].pp_txablend);
606 OUT_RING(tex[1].pp_tfactor);
607 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
608 OUT_RING(tex[1].pp_border_color);
612 if (dirty & RADEON_UPLOAD_TEX2) {
613 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
614 &tex[2].pp_txoffset)) {
615 DRM_ERROR("Invalid texture offset for unit 2\n");
620 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
621 OUT_RING(tex[2].pp_txfilter);
622 OUT_RING(tex[2].pp_txformat);
623 OUT_RING(tex[2].pp_txoffset);
624 OUT_RING(tex[2].pp_txcblend);
625 OUT_RING(tex[2].pp_txablend);
626 OUT_RING(tex[2].pp_tfactor);
627 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
628 OUT_RING(tex[2].pp_border_color);
637 static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
638 struct drm_file *file_priv,
639 drm_radeon_state_t * state)
643 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
645 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
646 OUT_RING(state->context2.se_zbias_factor);
647 OUT_RING(state->context2.se_zbias_constant);
651 return radeon_emit_state(dev_priv, file_priv, &state->context,
652 state->tex, state->dirty);
655 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
656 * 1.3 cmdbuffers allow all previous state to be updated as well as
657 * the tcl scalar and vector areas.
663 } packet[RADEON_MAX_STATE_PACKETS] = {
664 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
665 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
666 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
667 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
668 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
669 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
670 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
671 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
672 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
673 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
674 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
675 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
676 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
677 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
678 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
679 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
680 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
681 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
682 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
683 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
684 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
685 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
686 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
687 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
688 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
689 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
690 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
691 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
692 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
693 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
694 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
695 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
696 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
697 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
698 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
699 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
700 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
701 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
702 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
703 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
704 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
705 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
706 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
707 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
708 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
709 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
710 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
711 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
712 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
713 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
714 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
715 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
716 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
717 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
718 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
719 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
720 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
721 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
722 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
723 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
724 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
725 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
726 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
727 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
728 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
729 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
730 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
731 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
732 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
733 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
734 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
735 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
736 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
737 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
738 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
739 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
740 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
741 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
742 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
743 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
744 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
745 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
746 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
747 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
748 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
749 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
750 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
751 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
752 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
753 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
754 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
755 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
756 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
757 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
758 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
759 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
760 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
761 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
764 /* ================================================================
765 * Performance monitoring functions
768 static void radeon_clear_box(drm_radeon_private_t * dev_priv,
769 struct drm_radeon_master_private *master_priv,
770 int x, int y, int w, int h, int r, int g, int b)
775 x += master_priv->sarea_priv->boxes[0].x1;
776 y += master_priv->sarea_priv->boxes[0].y1;
778 switch (dev_priv->color_fmt) {
779 case RADEON_COLOR_FORMAT_RGB565:
780 color = (((r & 0xf8) << 8) |
781 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
783 case RADEON_COLOR_FORMAT_ARGB8888:
785 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
790 RADEON_WAIT_UNTIL_3D_IDLE();
791 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
792 OUT_RING(0xffffffff);
797 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
798 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
799 RADEON_GMC_BRUSH_SOLID_COLOR |
800 (dev_priv->color_fmt << 8) |
801 RADEON_GMC_SRC_DATATYPE_COLOR |
802 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
804 if (master_priv->sarea_priv->pfCurrentPage == 1) {
805 OUT_RING(dev_priv->front_pitch_offset);
807 OUT_RING(dev_priv->back_pitch_offset);
812 OUT_RING((x << 16) | y);
813 OUT_RING((w << 16) | h);
818 static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
820 /* Collapse various things into a wait flag -- trying to
821 * guess if userspase slept -- better just to have them tell us.
823 if (dev_priv->stats.last_frame_reads > 1 ||
824 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
825 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
828 if (dev_priv->stats.freelist_loops) {
829 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
832 /* Purple box for page flipping
834 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
835 radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
837 /* Red box if we have to wait for idle at any point
839 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
840 radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
842 /* Blue box: lost context?
845 /* Yellow box for texture swaps
847 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
848 radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
850 /* Green box if hardware never idles (as far as we can tell)
852 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
853 radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
855 /* Draw bars indicating number of buffers allocated
856 * (not a great measure, easily confused)
858 if (dev_priv->stats.requested_bufs) {
859 if (dev_priv->stats.requested_bufs > 100)
860 dev_priv->stats.requested_bufs = 100;
862 radeon_clear_box(dev_priv, master_priv, 4, 16,
863 dev_priv->stats.requested_bufs, 4,
867 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
871 /* ================================================================
872 * CP command dispatch functions
875 static void radeon_cp_dispatch_clear(struct drm_device * dev,
876 struct drm_master *master,
877 drm_radeon_clear_t * clear,
878 drm_radeon_clear_rect_t * depth_boxes)
880 drm_radeon_private_t *dev_priv = dev->dev_private;
881 struct drm_radeon_master_private *master_priv = master->driver_priv;
882 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
883 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
884 int nbox = sarea_priv->nbox;
885 struct drm_clip_rect *pbox = sarea_priv->boxes;
886 unsigned int flags = clear->flags;
887 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
890 DRM_DEBUG("flags = 0x%x\n", flags);
892 dev_priv->stats.clears++;
894 if (sarea_priv->pfCurrentPage == 1) {
895 unsigned int tmp = flags;
897 flags &= ~(RADEON_FRONT | RADEON_BACK);
898 if (tmp & RADEON_FRONT)
899 flags |= RADEON_BACK;
900 if (tmp & RADEON_BACK)
901 flags |= RADEON_FRONT;
903 if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
904 if (!dev_priv->have_z_offset) {
905 DRM_ERROR("radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
906 flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
910 if (flags & (RADEON_FRONT | RADEON_BACK)) {
914 /* Ensure the 3D stream is idle before doing a
915 * 2D fill to clear the front or back buffer.
917 RADEON_WAIT_UNTIL_3D_IDLE();
919 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
920 OUT_RING(clear->color_mask);
924 /* Make sure we restore the 3D state next time.
926 sarea_priv->ctx_owner = 0;
928 for (i = 0; i < nbox; i++) {
931 int w = pbox[i].x2 - x;
932 int h = pbox[i].y2 - y;
934 DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
937 if (flags & RADEON_FRONT) {
941 (RADEON_CNTL_PAINT_MULTI, 4));
942 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
943 RADEON_GMC_BRUSH_SOLID_COLOR |
946 RADEON_GMC_SRC_DATATYPE_COLOR |
948 RADEON_GMC_CLR_CMP_CNTL_DIS);
950 OUT_RING(dev_priv->front_pitch_offset);
951 OUT_RING(clear->clear_color);
953 OUT_RING((x << 16) | y);
954 OUT_RING((w << 16) | h);
959 if (flags & RADEON_BACK) {
963 (RADEON_CNTL_PAINT_MULTI, 4));
964 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
965 RADEON_GMC_BRUSH_SOLID_COLOR |
968 RADEON_GMC_SRC_DATATYPE_COLOR |
970 RADEON_GMC_CLR_CMP_CNTL_DIS);
972 OUT_RING(dev_priv->back_pitch_offset);
973 OUT_RING(clear->clear_color);
975 OUT_RING((x << 16) | y);
976 OUT_RING((w << 16) | h);
984 /* no docs available, based on reverse engineering by Stephane Marchesin */
985 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
986 && (flags & RADEON_CLEAR_FASTZ)) {
989 int depthpixperline =
990 dev_priv->depth_fmt ==
991 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
997 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
998 ((clear->depth_mask & 0xff) << 24);
1000 /* Make sure we restore the 3D state next time.
1001 * we haven't touched any "normal" state - still need this?
1003 sarea_priv->ctx_owner = 0;
1005 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1006 && (flags & RADEON_USE_HIERZ)) {
1007 /* FIXME : reverse engineer that for Rx00 cards */
1008 /* FIXME : the mask supposedly contains low-res z values. So can't set
1009 just to the max (0xff? or actually 0x3fff?), need to take z clear
1010 value into account? */
1011 /* pattern seems to work for r100, though get slight
1012 rendering errors with glxgears. If hierz is not enabled for r100,
1013 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
1014 other ones are ignored, and the same clear mask can be used. That's
1015 very different behaviour than R200 which needs different clear mask
1016 and different number of tiles to clear if hierz is enabled or not !?!
1018 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
1020 /* clear mask : chooses the clearing pattern.
1021 rv250: could be used to clear only parts of macrotiles
1022 (but that would get really complicated...)?
1023 bit 0 and 1 (either or both of them ?!?!) are used to
1024 not clear tile (or maybe one of the bits indicates if the tile is
1025 compressed or not), bit 2 and 3 to not clear tile 1,...,.
1026 Pattern is as follows:
1027 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
1028 bits -------------------------------------------------
1029 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
1030 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1031 covers 256 pixels ?!?
1037 RADEON_WAIT_UNTIL_2D_IDLE();
1038 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1039 tempRB3D_DEPTHCLEARVALUE);
1040 /* what offset is this exactly ? */
1041 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
1042 /* need ctlstat, otherwise get some strange black flickering */
1043 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1044 RADEON_RB3D_ZC_FLUSH_ALL);
1047 for (i = 0; i < nbox; i++) {
1048 int tileoffset, nrtilesx, nrtilesy, j;
1049 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
1050 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1051 && !(dev_priv->microcode_version == UCODE_R200)) {
1052 /* FIXME : figure this out for r200 (when hierz is enabled). Or
1053 maybe r200 actually doesn't need to put the low-res z value into
1054 the tile cache like r100, but just needs to clear the hi-level z-buffer?
1055 Works for R100, both with hierz and without.
1056 R100 seems to operate on 2x1 8x8 tiles, but...
1057 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
1058 problematic with resolutions which are not 64 pix aligned? */
1060 ((pbox[i].y1 >> 3) * depthpixperline +
1063 ((pbox[i].x2 & ~63) -
1064 (pbox[i].x1 & ~63)) >> 4;
1066 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1067 for (j = 0; j <= nrtilesy; j++) {
1070 (RADEON_3D_CLEAR_ZMASK, 2));
1072 OUT_RING(tileoffset * 8);
1073 /* the number of tiles to clear */
1074 OUT_RING(nrtilesx + 4);
1075 /* clear mask : chooses the clearing pattern. */
1076 OUT_RING(clearmask);
1078 tileoffset += depthpixperline >> 6;
1080 } else if (dev_priv->microcode_version == UCODE_R200) {
1081 /* works for rv250. */
1082 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
1084 ((pbox[i].y1 >> 3) * depthpixperline +
1087 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
1089 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1090 for (j = 0; j <= nrtilesy; j++) {
1093 (RADEON_3D_CLEAR_ZMASK, 2));
1095 /* judging by the first tile offset needed, could possibly
1096 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1097 macro tiles, though would still need clear mask for
1098 right/bottom if truly 4x4 granularity is desired ? */
1099 OUT_RING(tileoffset * 16);
1100 /* the number of tiles to clear */
1101 OUT_RING(nrtilesx + 1);
1102 /* clear mask : chooses the clearing pattern. */
1103 OUT_RING(clearmask);
1105 tileoffset += depthpixperline >> 5;
1107 } else { /* rv 100 */
1108 /* rv100 might not need 64 pix alignment, who knows */
1109 /* offsets are, hmm, weird */
1111 ((pbox[i].y1 >> 4) * depthpixperline +
1114 ((pbox[i].x2 & ~63) -
1115 (pbox[i].x1 & ~63)) >> 4;
1117 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
1118 for (j = 0; j <= nrtilesy; j++) {
1121 (RADEON_3D_CLEAR_ZMASK, 2));
1122 OUT_RING(tileoffset * 128);
1123 /* the number of tiles to clear */
1124 OUT_RING(nrtilesx + 4);
1125 /* clear mask : chooses the clearing pattern. */
1126 OUT_RING(clearmask);
1128 tileoffset += depthpixperline >> 6;
1133 /* TODO don't always clear all hi-level z tiles */
1134 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1135 && (dev_priv->microcode_version == UCODE_R200)
1136 && (flags & RADEON_USE_HIERZ))
1137 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
1138 /* FIXME : the mask supposedly contains low-res z values. So can't set
1139 just to the max (0xff? or actually 0x3fff?), need to take z clear
1140 value into account? */
1143 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1144 OUT_RING(0x0); /* First tile */
1146 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
1151 /* We have to clear the depth and/or stencil buffers by
1152 * rendering a quad into just those buffers. Thus, we have to
1153 * make sure the 3D engine is configured correctly.
1155 else if ((dev_priv->microcode_version == UCODE_R200) &&
1156 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1161 int tempRB3D_ZSTENCILCNTL;
1162 int tempRB3D_STENCILREFMASK;
1163 int tempRB3D_PLANEMASK;
1165 int tempSE_VTE_CNTL;
1166 int tempSE_VTX_FMT_0;
1167 int tempSE_VTX_FMT_1;
1168 int tempSE_VAP_CNTL;
1169 int tempRE_AUX_SCISSOR_CNTL;
1174 tempRB3D_CNTL = depth_clear->rb3d_cntl;
1176 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1177 tempRB3D_STENCILREFMASK = 0x0;
1179 tempSE_CNTL = depth_clear->se_cntl;
1183 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
1185 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
1187 tempRB3D_PLANEMASK = 0x0;
1189 tempRE_AUX_SCISSOR_CNTL = 0x0;
1192 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
1194 /* Vertex format (X, Y, Z, W) */
1196 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
1197 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
1198 tempSE_VTX_FMT_1 = 0x0;
1201 * Depth buffer specific enables
1203 if (flags & RADEON_DEPTH) {
1204 /* Enable depth buffer */
1205 tempRB3D_CNTL |= RADEON_Z_ENABLE;
1207 /* Disable depth buffer */
1208 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1212 * Stencil buffer specific enables
1214 if (flags & RADEON_STENCIL) {
1215 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1216 tempRB3D_STENCILREFMASK = clear->depth_mask;
1218 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1219 tempRB3D_STENCILREFMASK = 0x00000000;
1222 if (flags & RADEON_USE_COMP_ZBUF) {
1223 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1224 RADEON_Z_DECOMPRESSION_ENABLE;
1226 if (flags & RADEON_USE_HIERZ) {
1227 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1231 RADEON_WAIT_UNTIL_2D_IDLE();
1233 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1234 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1235 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1236 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1237 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1238 tempRB3D_STENCILREFMASK);
1239 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1240 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1241 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1242 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1243 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1244 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1245 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1248 /* Make sure we restore the 3D state next time.
1250 sarea_priv->ctx_owner = 0;
1252 for (i = 0; i < nbox; i++) {
1254 /* Funny that this should be required --
1257 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1260 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1261 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1262 RADEON_PRIM_WALK_RING |
1263 (3 << RADEON_NUM_VERTICES_SHIFT)));
1264 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1265 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1266 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1267 OUT_RING(0x3f800000);
1268 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1269 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1270 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1271 OUT_RING(0x3f800000);
1272 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1273 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1274 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1275 OUT_RING(0x3f800000);
1278 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1280 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1282 rb3d_cntl = depth_clear->rb3d_cntl;
1284 if (flags & RADEON_DEPTH) {
1285 rb3d_cntl |= RADEON_Z_ENABLE;
1287 rb3d_cntl &= ~RADEON_Z_ENABLE;
1290 if (flags & RADEON_STENCIL) {
1291 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1292 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1294 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1295 rb3d_stencilrefmask = 0x00000000;
1298 if (flags & RADEON_USE_COMP_ZBUF) {
1299 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1300 RADEON_Z_DECOMPRESSION_ENABLE;
1302 if (flags & RADEON_USE_HIERZ) {
1303 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1307 RADEON_WAIT_UNTIL_2D_IDLE();
1309 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1310 OUT_RING(0x00000000);
1311 OUT_RING(rb3d_cntl);
1313 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1314 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1315 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1316 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1319 /* Make sure we restore the 3D state next time.
1321 sarea_priv->ctx_owner = 0;
1323 for (i = 0; i < nbox; i++) {
1325 /* Funny that this should be required --
1328 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1332 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1333 OUT_RING(RADEON_VTX_Z_PRESENT |
1334 RADEON_VTX_PKCOLOR_PRESENT);
1335 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1336 RADEON_PRIM_WALK_RING |
1337 RADEON_MAOS_ENABLE |
1338 RADEON_VTX_FMT_RADEON_MODE |
1339 (3 << RADEON_NUM_VERTICES_SHIFT)));
1341 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1342 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1343 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1346 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1347 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1348 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1351 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1352 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1353 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1360 /* Increment the clear counter. The client-side 3D driver must
1361 * wait on this value before performing the clear ioctl. We
1362 * need this because the card's so damned fast...
1364 sarea_priv->last_clear++;
1368 RADEON_CLEAR_AGE(sarea_priv->last_clear);
1369 RADEON_WAIT_UNTIL_IDLE();
1374 static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
1376 drm_radeon_private_t *dev_priv = dev->dev_private;
1377 struct drm_radeon_master_private *master_priv = master->driver_priv;
1378 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1379 int nbox = sarea_priv->nbox;
1380 struct drm_clip_rect *pbox = sarea_priv->boxes;
1385 /* Do some trivial performance monitoring...
1387 if (dev_priv->do_boxes)
1388 radeon_cp_performance_boxes(dev_priv, master_priv);
1390 /* Wait for the 3D stream to idle before dispatching the bitblt.
1391 * This will prevent data corruption between the two streams.
1395 RADEON_WAIT_UNTIL_3D_IDLE();
1399 for (i = 0; i < nbox; i++) {
1402 int w = pbox[i].x2 - x;
1403 int h = pbox[i].y2 - y;
1405 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
1409 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
1410 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1411 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1412 RADEON_GMC_BRUSH_NONE |
1413 (dev_priv->color_fmt << 8) |
1414 RADEON_GMC_SRC_DATATYPE_COLOR |
1416 RADEON_DP_SRC_SOURCE_MEMORY |
1417 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1419 /* Make this work even if front & back are flipped:
1421 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
1422 if (sarea_priv->pfCurrentPage == 0) {
1423 OUT_RING(dev_priv->back_pitch_offset);
1424 OUT_RING(dev_priv->front_pitch_offset);
1426 OUT_RING(dev_priv->front_pitch_offset);
1427 OUT_RING(dev_priv->back_pitch_offset);
1430 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
1431 OUT_RING((x << 16) | y);
1432 OUT_RING((x << 16) | y);
1433 OUT_RING((w << 16) | h);
1438 /* Increment the frame counter. The client-side 3D driver must
1439 * throttle the framerate by waiting for this value before
1440 * performing the swapbuffer ioctl.
1442 sarea_priv->last_frame++;
1446 RADEON_FRAME_AGE(sarea_priv->last_frame);
1447 RADEON_WAIT_UNTIL_2D_IDLE();
1452 void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
1454 drm_radeon_private_t *dev_priv = dev->dev_private;
1455 struct drm_radeon_master_private *master_priv = master->driver_priv;
1456 struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
1457 int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
1458 ? dev_priv->front_offset : dev_priv->back_offset;
1460 DRM_DEBUG("pfCurrentPage=%d\n",
1461 master_priv->sarea_priv->pfCurrentPage);
1463 /* Do some trivial performance monitoring...
1465 if (dev_priv->do_boxes) {
1466 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1467 radeon_cp_performance_boxes(dev_priv, master_priv);
1470 /* Update the frame offsets for both CRTCs
1474 RADEON_WAIT_UNTIL_3D_IDLE();
1475 OUT_RING_REG(RADEON_CRTC_OFFSET,
1476 ((sarea->frame.y * dev_priv->front_pitch +
1477 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1479 OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
1484 /* Increment the frame counter. The client-side 3D driver must
1485 * throttle the framerate by waiting for this value before
1486 * performing the swapbuffer ioctl.
1488 master_priv->sarea_priv->last_frame++;
1489 master_priv->sarea_priv->pfCurrentPage =
1490 1 - master_priv->sarea_priv->pfCurrentPage;
1494 RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
1499 static int bad_prim_vertex_nr(int primitive, int nr)
1501 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1502 case RADEON_PRIM_TYPE_NONE:
1503 case RADEON_PRIM_TYPE_POINT:
1505 case RADEON_PRIM_TYPE_LINE:
1506 return (nr & 1) || nr == 0;
1507 case RADEON_PRIM_TYPE_LINE_STRIP:
1509 case RADEON_PRIM_TYPE_TRI_LIST:
1510 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1511 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1512 case RADEON_PRIM_TYPE_RECT_LIST:
1513 return nr % 3 || nr == 0;
1514 case RADEON_PRIM_TYPE_TRI_FAN:
1515 case RADEON_PRIM_TYPE_TRI_STRIP:
1524 unsigned int finish;
1526 unsigned int numverts;
1527 unsigned int offset;
1528 unsigned int vc_format;
1529 } drm_radeon_tcl_prim_t;
1531 static void radeon_cp_dispatch_vertex(struct drm_device * dev,
1532 struct drm_file *file_priv,
1533 struct drm_buf * buf,
1534 drm_radeon_tcl_prim_t * prim)
1536 drm_radeon_private_t *dev_priv = dev->dev_private;
1537 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1538 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1539 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1540 int numverts = (int)prim->numverts;
1541 int nbox = sarea_priv->nbox;
1545 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1547 prim->vc_format, prim->start, prim->finish, prim->numverts);
1549 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1550 DRM_ERROR("bad prim %x numverts %d\n",
1551 prim->prim, prim->numverts);
1556 /* Emit the next cliprect */
1558 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1561 /* Emit the vertex buffer rendering commands */
1564 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1567 OUT_RING(prim->vc_format);
1568 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1569 RADEON_COLOR_ORDER_RGBA |
1570 RADEON_VTX_FMT_RADEON_MODE |
1571 (numverts << RADEON_NUM_VERTICES_SHIFT));
1579 void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
1581 drm_radeon_private_t *dev_priv = dev->dev_private;
1582 struct drm_radeon_master_private *master_priv = master->driver_priv;
1583 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1586 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
1588 /* Emit the vertex buffer age */
1589 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1591 R600_DISPATCH_AGE(buf_priv->age);
1595 RADEON_DISPATCH_AGE(buf_priv->age);
1603 static void radeon_cp_dispatch_indirect(struct drm_device * dev,
1604 struct drm_buf * buf, int start, int end)
1606 drm_radeon_private_t *dev_priv = dev->dev_private;
1608 DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1611 int offset = (dev_priv->gart_buffers_offset
1612 + buf->offset + start);
1613 int dwords = (end - start + 3) / sizeof(u32);
1615 /* Indirect buffer data must be an even number of
1616 * dwords, so if we've been given an odd number we must
1617 * pad the data with a Type-2 CP packet.
1621 ((char *)dev->agp_buffer_map->handle
1622 + buf->offset + start);
1623 data[dwords++] = RADEON_CP_PACKET2;
1626 /* Fire off the indirect buffer */
1629 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1637 static void radeon_cp_dispatch_indices(struct drm_device *dev,
1638 struct drm_master *master,
1639 struct drm_buf * elt_buf,
1640 drm_radeon_tcl_prim_t * prim)
1642 drm_radeon_private_t *dev_priv = dev->dev_private;
1643 struct drm_radeon_master_private *master_priv = master->driver_priv;
1644 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1645 int offset = dev_priv->gart_buffers_offset + prim->offset;
1649 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1650 int count = (prim->finish - start) / sizeof(u16);
1651 int nbox = sarea_priv->nbox;
1653 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1656 prim->start, prim->finish, prim->offset, prim->numverts);
1658 if (bad_prim_vertex_nr(prim->prim, count)) {
1659 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1663 if (start >= prim->finish || (prim->start & 0x7)) {
1664 DRM_ERROR("buffer prim %d\n", prim->prim);
1668 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1670 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1671 elt_buf->offset + prim->start);
1673 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1675 data[2] = prim->numverts;
1676 data[3] = prim->vc_format;
1677 data[4] = (prim->prim |
1678 RADEON_PRIM_WALK_IND |
1679 RADEON_COLOR_ORDER_RGBA |
1680 RADEON_VTX_FMT_RADEON_MODE |
1681 (count << RADEON_NUM_VERTICES_SHIFT));
1685 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1687 radeon_cp_dispatch_indirect(dev, elt_buf,
1688 prim->start, prim->finish);
1695 #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1697 static int radeon_cp_dispatch_texture(struct drm_device * dev,
1698 struct drm_file *file_priv,
1699 drm_radeon_texture_t * tex,
1700 drm_radeon_tex_image_t * image)
1702 drm_radeon_private_t *dev_priv = dev->dev_private;
1703 struct drm_buf *buf;
1706 const u8 __user *data;
1707 int size, dwords, tex_width, blit_width, spitch;
1710 u32 texpitch, microtile;
1711 u32 offset, byte_offset;
1714 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
1715 DRM_ERROR("Invalid destination offset\n");
1719 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1721 /* Flush the pixel cache. This ensures no pixel data gets mixed
1722 * up with the texture data from the host data blit, otherwise
1723 * part of the texture image may be corrupted.
1726 RADEON_FLUSH_CACHE();
1727 RADEON_WAIT_UNTIL_IDLE();
1730 /* The compiler won't optimize away a division by a variable,
1731 * even if the only legal values are powers of two. Thus, we'll
1732 * use a shift instead.
1734 switch (tex->format) {
1735 case RADEON_TXFORMAT_ARGB8888:
1736 case RADEON_TXFORMAT_RGBA8888:
1737 format = RADEON_COLOR_FORMAT_ARGB8888;
1738 tex_width = tex->width * 4;
1739 blit_width = image->width * 4;
1741 case RADEON_TXFORMAT_AI88:
1742 case RADEON_TXFORMAT_ARGB1555:
1743 case RADEON_TXFORMAT_RGB565:
1744 case RADEON_TXFORMAT_ARGB4444:
1745 case RADEON_TXFORMAT_VYUY422:
1746 case RADEON_TXFORMAT_YVYU422:
1747 format = RADEON_COLOR_FORMAT_RGB565;
1748 tex_width = tex->width * 2;
1749 blit_width = image->width * 2;
1751 case RADEON_TXFORMAT_I8:
1752 case RADEON_TXFORMAT_RGB332:
1753 format = RADEON_COLOR_FORMAT_CI8;
1754 tex_width = tex->width * 1;
1755 blit_width = image->width * 1;
1758 DRM_ERROR("invalid texture format %d\n", tex->format);
1761 spitch = blit_width >> 6;
1762 if (spitch == 0 && image->height > 1)
1765 texpitch = tex->pitch;
1766 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1768 if (tex_width < 64) {
1769 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1770 /* we got tiled coordinates, untile them */
1776 /* this might fail for zero-sized uploads - are those illegal? */
1777 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1779 DRM_ERROR("Invalid final destination offset\n");
1783 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1786 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%u y=%u w=%u h=%u\n",
1787 tex->offset >> 10, tex->pitch, tex->format,
1788 image->x, image->y, image->width, image->height);
1790 /* Make a copy of some parameters in case we have to
1791 * update them for a multi-pass texture blit.
1793 height = image->height;
1794 data = (const u8 __user *)image->data;
1796 size = height * blit_width;
1798 if (size > RADEON_MAX_TEXTURE_SIZE) {
1799 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1800 size = height * blit_width;
1801 } else if (size < 4 && size > 0) {
1803 } else if (size == 0) {
1807 buf = radeon_freelist_get(dev);
1809 radeon_do_cp_idle(dev_priv);
1810 buf = radeon_freelist_get(dev);
1813 DRM_DEBUG("EAGAIN\n");
1814 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
1819 /* Dispatch the indirect buffer.
1822 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1825 #define RADEON_COPY_MT(_buf, _data, _width) \
1827 if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
1828 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1834 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1835 however, we cannot use blitter directly for texture width < 64 bytes,
1836 since minimum tex pitch is 64 bytes and we need this to match
1837 the texture width, otherwise the blitter will tile it wrong.
1838 Thus, tiling manually in this case. Additionally, need to special
1839 case tex height = 1, since our actual image will have height 2
1840 and we need to ensure we don't read beyond the texture size
1842 if (tex->height == 1) {
1843 if (tex_width >= 64 || tex_width <= 16) {
1844 RADEON_COPY_MT(buffer, data,
1845 (int)(tex_width * sizeof(u32)));
1846 } else if (tex_width == 32) {
1847 RADEON_COPY_MT(buffer, data, 16);
1848 RADEON_COPY_MT(buffer + 8,
1851 } else if (tex_width >= 64 || tex_width == 16) {
1852 RADEON_COPY_MT(buffer, data,
1853 (int)(dwords * sizeof(u32)));
1854 } else if (tex_width < 16) {
1855 for (i = 0; i < tex->height; i++) {
1856 RADEON_COPY_MT(buffer, data, tex_width);
1860 } else if (tex_width == 32) {
1861 /* TODO: make sure this works when not fitting in one buffer
1862 (i.e. 32bytes x 2048...) */
1863 for (i = 0; i < tex->height; i += 2) {
1864 RADEON_COPY_MT(buffer, data, 16);
1866 RADEON_COPY_MT(buffer + 8, data, 16);
1868 RADEON_COPY_MT(buffer + 4, data, 16);
1870 RADEON_COPY_MT(buffer + 12, data, 16);
1876 if (tex_width >= 32) {
1877 /* Texture image width is larger than the minimum, so we
1878 * can upload it directly.
1880 RADEON_COPY_MT(buffer, data,
1881 (int)(dwords * sizeof(u32)));
1883 /* Texture image width is less than the minimum, so we
1884 * need to pad out each image scanline to the minimum
1887 for (i = 0; i < tex->height; i++) {
1888 RADEON_COPY_MT(buffer, data, tex_width);
1895 #undef RADEON_COPY_MT
1896 byte_offset = (image->y & ~2047) * blit_width;
1897 buf->file_priv = file_priv;
1899 offset = dev_priv->gart_buffers_offset + buf->offset;
1901 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1902 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1903 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1904 RADEON_GMC_BRUSH_NONE |
1906 RADEON_GMC_SRC_DATATYPE_COLOR |
1908 RADEON_DP_SRC_SOURCE_MEMORY |
1909 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1910 OUT_RING((spitch << 22) | (offset >> 10));
1911 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1913 OUT_RING((image->x << 16) | (image->y % 2048));
1914 OUT_RING((image->width << 16) | height);
1915 RADEON_WAIT_UNTIL_2D_IDLE();
1919 radeon_cp_discard_buffer(dev, file_priv->master, buf);
1921 /* Update the input parameters for next time */
1923 image->height -= height;
1924 image->data = (const u8 __user *)image->data + size;
1925 } while (image->height > 0);
1927 /* Flush the pixel cache after the blit completes. This ensures
1928 * the texture data is written out to memory before rendering
1932 RADEON_FLUSH_CACHE();
1933 RADEON_WAIT_UNTIL_2D_IDLE();
1940 static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1942 drm_radeon_private_t *dev_priv = dev->dev_private;
1949 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1950 OUT_RING(0x00000000);
1952 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1953 for (i = 0; i < 32; i++) {
1954 OUT_RING(stipple[i]);
1960 static void radeon_apply_surface_regs(int surf_index,
1961 drm_radeon_private_t *dev_priv)
1963 if (!dev_priv->mmio)
1966 radeon_do_cp_idle(dev_priv);
1968 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1969 dev_priv->surfaces[surf_index].flags);
1970 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1971 dev_priv->surfaces[surf_index].lower);
1972 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1973 dev_priv->surfaces[surf_index].upper);
1976 /* Allocates a virtual surface
1977 * doesn't always allocate a real surface, will stretch an existing
1978 * surface when possible.
1980 * Note that refcount can be at most 2, since during a free refcount=3
1981 * might mean we have to allocate a new surface which might not always
1983 * For example : we allocate three contiguous surfaces ABC. If B is
1984 * freed, we suddenly need two surfaces to store A and C, which might
1985 * not always be available.
1987 static int alloc_surface(drm_radeon_surface_alloc_t *new,
1988 drm_radeon_private_t *dev_priv,
1989 struct drm_file *file_priv)
1991 struct radeon_virt_surface *s;
1993 int virt_surface_index;
1994 uint32_t new_upper, new_lower;
1996 new_lower = new->address;
1997 new_upper = new_lower + new->size - 1;
2000 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
2001 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
2002 RADEON_SURF_ADDRESS_FIXED_MASK)
2003 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
2006 /* make sure there is no overlap with existing surfaces */
2007 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2008 if ((dev_priv->surfaces[i].refcount != 0) &&
2009 (((new_lower >= dev_priv->surfaces[i].lower) &&
2010 (new_lower < dev_priv->surfaces[i].upper)) ||
2011 ((new_lower < dev_priv->surfaces[i].lower) &&
2012 (new_upper > dev_priv->surfaces[i].lower)))) {
2017 /* find a virtual surface */
2018 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
2019 if (dev_priv->virt_surfaces[i].file_priv == NULL)
2021 if (i == 2 * RADEON_MAX_SURFACES) {
2024 virt_surface_index = i;
2026 /* try to reuse an existing surface */
2027 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2029 if ((dev_priv->surfaces[i].refcount == 1) &&
2030 (new->flags == dev_priv->surfaces[i].flags) &&
2031 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
2032 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2033 s->surface_index = i;
2034 s->lower = new_lower;
2035 s->upper = new_upper;
2036 s->flags = new->flags;
2037 s->file_priv = file_priv;
2038 dev_priv->surfaces[i].refcount++;
2039 dev_priv->surfaces[i].lower = s->lower;
2040 radeon_apply_surface_regs(s->surface_index, dev_priv);
2041 return virt_surface_index;
2045 if ((dev_priv->surfaces[i].refcount == 1) &&
2046 (new->flags == dev_priv->surfaces[i].flags) &&
2047 (new_lower == dev_priv->surfaces[i].upper + 1)) {
2048 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2049 s->surface_index = i;
2050 s->lower = new_lower;
2051 s->upper = new_upper;
2052 s->flags = new->flags;
2053 s->file_priv = file_priv;
2054 dev_priv->surfaces[i].refcount++;
2055 dev_priv->surfaces[i].upper = s->upper;
2056 radeon_apply_surface_regs(s->surface_index, dev_priv);
2057 return virt_surface_index;
2061 /* okay, we need a new one */
2062 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2063 if (dev_priv->surfaces[i].refcount == 0) {
2064 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2065 s->surface_index = i;
2066 s->lower = new_lower;
2067 s->upper = new_upper;
2068 s->flags = new->flags;
2069 s->file_priv = file_priv;
2070 dev_priv->surfaces[i].refcount = 1;
2071 dev_priv->surfaces[i].lower = s->lower;
2072 dev_priv->surfaces[i].upper = s->upper;
2073 dev_priv->surfaces[i].flags = s->flags;
2074 radeon_apply_surface_regs(s->surface_index, dev_priv);
2075 return virt_surface_index;
2079 /* we didn't find anything */
2083 static int free_surface(struct drm_file *file_priv,
2084 drm_radeon_private_t * dev_priv,
2087 struct radeon_virt_surface *s;
2089 /* find the virtual surface */
2090 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2091 s = &(dev_priv->virt_surfaces[i]);
2093 if ((lower == s->lower) && (file_priv == s->file_priv))
2095 if (dev_priv->surfaces[s->surface_index].
2097 dev_priv->surfaces[s->surface_index].
2100 if (dev_priv->surfaces[s->surface_index].
2102 dev_priv->surfaces[s->surface_index].
2105 dev_priv->surfaces[s->surface_index].refcount--;
2106 if (dev_priv->surfaces[s->surface_index].
2108 dev_priv->surfaces[s->surface_index].
2110 s->file_priv = NULL;
2111 radeon_apply_surface_regs(s->surface_index,
2120 static void radeon_surfaces_release(struct drm_file *file_priv,
2121 drm_radeon_private_t * dev_priv)
2124 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2125 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2126 free_surface(file_priv, dev_priv,
2127 dev_priv->virt_surfaces[i].lower);
2131 /* ================================================================
2134 static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
2136 drm_radeon_private_t *dev_priv = dev->dev_private;
2137 drm_radeon_surface_alloc_t *alloc = data;
2139 if (alloc_surface(alloc, dev_priv, file_priv) == -1)
2145 static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
2147 drm_radeon_private_t *dev_priv = dev->dev_private;
2148 drm_radeon_surface_free_t *memfree = data;
2150 if (free_surface(file_priv, dev_priv, memfree->address))
2156 static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
2158 drm_radeon_private_t *dev_priv = dev->dev_private;
2159 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2160 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2161 drm_radeon_clear_t *clear = data;
2162 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2165 LOCK_TEST_WITH_RETURN(dev, file_priv);
2167 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2169 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2170 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2172 if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
2173 sarea_priv->nbox * sizeof(depth_boxes[0])))
2176 radeon_cp_dispatch_clear(dev, file_priv->master, clear, depth_boxes);
2182 /* Not sure why this isn't set all the time:
2184 static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
2186 drm_radeon_private_t *dev_priv = dev->dev_private;
2187 struct drm_radeon_master_private *master_priv = master->driver_priv;
2193 RADEON_WAIT_UNTIL_3D_IDLE();
2194 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2195 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2196 RADEON_CRTC_OFFSET_FLIP_CNTL);
2197 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2198 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2199 RADEON_CRTC_OFFSET_FLIP_CNTL);
2202 dev_priv->page_flipping = 1;
2204 if (master_priv->sarea_priv->pfCurrentPage != 1)
2205 master_priv->sarea_priv->pfCurrentPage = 0;
2210 /* Swapping and flipping are different operations, need different ioctls.
2211 * They can & should be intermixed to support multiple 3d windows.
2213 static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
2215 drm_radeon_private_t *dev_priv = dev->dev_private;
2218 LOCK_TEST_WITH_RETURN(dev, file_priv);
2220 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2222 if (!dev_priv->page_flipping)
2223 radeon_do_init_pageflip(dev, file_priv->master);
2225 radeon_cp_dispatch_flip(dev, file_priv->master);
2231 static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
2233 drm_radeon_private_t *dev_priv = dev->dev_private;
2234 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2235 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2239 LOCK_TEST_WITH_RETURN(dev, file_priv);
2241 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2243 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2244 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2246 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2247 r600_cp_dispatch_swap(dev, file_priv);
2249 radeon_cp_dispatch_swap(dev, file_priv->master);
2250 sarea_priv->ctx_owner = 0;
2256 static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
2258 drm_radeon_private_t *dev_priv = dev->dev_private;
2259 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2260 drm_radeon_sarea_t *sarea_priv;
2261 struct drm_device_dma *dma = dev->dma;
2262 struct drm_buf *buf;
2263 drm_radeon_vertex_t *vertex = data;
2264 drm_radeon_tcl_prim_t prim;
2266 LOCK_TEST_WITH_RETURN(dev, file_priv);
2268 sarea_priv = master_priv->sarea_priv;
2270 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2271 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
2273 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2274 DRM_ERROR("buffer index %d (of %d max)\n",
2275 vertex->idx, dma->buf_count - 1);
2278 if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2279 DRM_ERROR("buffer prim %d\n", vertex->prim);
2283 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2284 VB_AGE_TEST_WITH_RETURN(dev_priv);
2286 buf = dma->buflist[vertex->idx];
2288 if (buf->file_priv != file_priv) {
2289 DRM_ERROR("process %d using buffer owned by %p\n",
2290 DRM_CURRENTPID, buf->file_priv);
2294 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2298 /* Build up a prim_t record:
2300 if (vertex->count) {
2301 buf->used = vertex->count; /* not used? */
2303 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2304 if (radeon_emit_state(dev_priv, file_priv,
2305 &sarea_priv->context_state,
2306 sarea_priv->tex_state,
2307 sarea_priv->dirty)) {
2308 DRM_ERROR("radeon_emit_state failed\n");
2312 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2313 RADEON_UPLOAD_TEX1IMAGES |
2314 RADEON_UPLOAD_TEX2IMAGES |
2315 RADEON_REQUIRE_QUIESCENCE);
2319 prim.finish = vertex->count; /* unused */
2320 prim.prim = vertex->prim;
2321 prim.numverts = vertex->count;
2322 prim.vc_format = sarea_priv->vc_format;
2324 radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
2327 if (vertex->discard) {
2328 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2335 static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
2337 drm_radeon_private_t *dev_priv = dev->dev_private;
2338 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2339 drm_radeon_sarea_t *sarea_priv;
2340 struct drm_device_dma *dma = dev->dma;
2341 struct drm_buf *buf;
2342 drm_radeon_indices_t *elts = data;
2343 drm_radeon_tcl_prim_t prim;
2346 LOCK_TEST_WITH_RETURN(dev, file_priv);
2348 sarea_priv = master_priv->sarea_priv;
2350 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2351 DRM_CURRENTPID, elts->idx, elts->start, elts->end,
2354 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
2355 DRM_ERROR("buffer index %d (of %d max)\n",
2356 elts->idx, dma->buf_count - 1);
2359 if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2360 DRM_ERROR("buffer prim %d\n", elts->prim);
2364 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2365 VB_AGE_TEST_WITH_RETURN(dev_priv);
2367 buf = dma->buflist[elts->idx];
2369 if (buf->file_priv != file_priv) {
2370 DRM_ERROR("process %d using buffer owned by %p\n",
2371 DRM_CURRENTPID, buf->file_priv);
2375 DRM_ERROR("sending pending buffer %d\n", elts->idx);
2379 count = (elts->end - elts->start) / sizeof(u16);
2380 elts->start -= RADEON_INDEX_PRIM_OFFSET;
2382 if (elts->start & 0x7) {
2383 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
2386 if (elts->start < buf->used) {
2387 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
2391 buf->used = elts->end;
2393 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2394 if (radeon_emit_state(dev_priv, file_priv,
2395 &sarea_priv->context_state,
2396 sarea_priv->tex_state,
2397 sarea_priv->dirty)) {
2398 DRM_ERROR("radeon_emit_state failed\n");
2402 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2403 RADEON_UPLOAD_TEX1IMAGES |
2404 RADEON_UPLOAD_TEX2IMAGES |
2405 RADEON_REQUIRE_QUIESCENCE);
2408 /* Build up a prim_t record:
2410 prim.start = elts->start;
2411 prim.finish = elts->end;
2412 prim.prim = elts->prim;
2413 prim.offset = 0; /* offset from start of dma buffers */
2414 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2415 prim.vc_format = sarea_priv->vc_format;
2417 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &prim);
2418 if (elts->discard) {
2419 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2426 static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
2428 drm_radeon_private_t *dev_priv = dev->dev_private;
2429 drm_radeon_texture_t *tex = data;
2430 drm_radeon_tex_image_t image;
2433 LOCK_TEST_WITH_RETURN(dev, file_priv);
2435 if (tex->image == NULL) {
2436 DRM_ERROR("null texture image!\n");
2440 if (DRM_COPY_FROM_USER(&image,
2441 (drm_radeon_tex_image_t __user *) tex->image,
2445 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2446 VB_AGE_TEST_WITH_RETURN(dev_priv);
2448 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2449 ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
2451 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
2456 static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
2458 drm_radeon_private_t *dev_priv = dev->dev_private;
2459 drm_radeon_stipple_t *stipple = data;
2462 LOCK_TEST_WITH_RETURN(dev, file_priv);
2464 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
2467 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2469 radeon_cp_dispatch_stipple(dev, mask);
2475 static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
2477 drm_radeon_private_t *dev_priv = dev->dev_private;
2478 struct drm_device_dma *dma = dev->dma;
2479 struct drm_buf *buf;
2480 drm_radeon_indirect_t *indirect = data;
2483 LOCK_TEST_WITH_RETURN(dev, file_priv);
2485 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
2486 indirect->idx, indirect->start, indirect->end,
2489 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
2490 DRM_ERROR("buffer index %d (of %d max)\n",
2491 indirect->idx, dma->buf_count - 1);
2495 buf = dma->buflist[indirect->idx];
2497 if (buf->file_priv != file_priv) {
2498 DRM_ERROR("process %d using buffer owned by %p\n",
2499 DRM_CURRENTPID, buf->file_priv);
2503 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
2507 if (indirect->start < buf->used) {
2508 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2509 indirect->start, buf->used);
2513 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2514 VB_AGE_TEST_WITH_RETURN(dev_priv);
2516 buf->used = indirect->end;
2518 /* Dispatch the indirect buffer full of commands from the
2519 * X server. This is insecure and is thus only available to
2520 * privileged clients.
2522 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2523 r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2525 /* Wait for the 3D stream to idle before the indirect buffer
2526 * containing 2D acceleration commands is processed.
2529 RADEON_WAIT_UNTIL_3D_IDLE();
2531 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2534 if (indirect->discard) {
2535 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2542 static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
2544 drm_radeon_private_t *dev_priv = dev->dev_private;
2545 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2546 drm_radeon_sarea_t *sarea_priv;
2547 struct drm_device_dma *dma = dev->dma;
2548 struct drm_buf *buf;
2549 drm_radeon_vertex2_t *vertex = data;
2551 unsigned char laststate;
2553 LOCK_TEST_WITH_RETURN(dev, file_priv);
2555 sarea_priv = master_priv->sarea_priv;
2557 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2558 DRM_CURRENTPID, vertex->idx, vertex->discard);
2560 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2561 DRM_ERROR("buffer index %d (of %d max)\n",
2562 vertex->idx, dma->buf_count - 1);
2566 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2567 VB_AGE_TEST_WITH_RETURN(dev_priv);
2569 buf = dma->buflist[vertex->idx];
2571 if (buf->file_priv != file_priv) {
2572 DRM_ERROR("process %d using buffer owned by %p\n",
2573 DRM_CURRENTPID, buf->file_priv);
2578 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2582 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2585 for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
2586 drm_radeon_prim_t prim;
2587 drm_radeon_tcl_prim_t tclprim;
2589 if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
2592 if (prim.stateidx != laststate) {
2593 drm_radeon_state_t state;
2595 if (DRM_COPY_FROM_USER(&state,
2596 &vertex->state[prim.stateidx],
2600 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
2601 DRM_ERROR("radeon_emit_state2 failed\n");
2605 laststate = prim.stateidx;
2608 tclprim.start = prim.start;
2609 tclprim.finish = prim.finish;
2610 tclprim.prim = prim.prim;
2611 tclprim.vc_format = prim.vc_format;
2613 if (prim.prim & RADEON_PRIM_WALK_IND) {
2614 tclprim.offset = prim.numverts * 64;
2615 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2617 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &tclprim);
2619 tclprim.numverts = prim.numverts;
2620 tclprim.offset = 0; /* not used */
2622 radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
2625 if (sarea_priv->nbox == 1)
2626 sarea_priv->nbox = 0;
2629 if (vertex->discard) {
2630 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2637 static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2638 struct drm_file *file_priv,
2639 drm_radeon_cmd_header_t header,
2640 drm_radeon_kcmd_buffer_t *cmdbuf)
2642 int id = (int)header.packet.packet_id;
2646 if (id >= RADEON_MAX_STATE_PACKETS)
2649 sz = packet[id].len;
2650 reg = packet[id].start;
2652 if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) {
2653 DRM_ERROR("Packet size provided larger than data provided\n");
2657 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id,
2659 DRM_ERROR("Packet verification failed\n");
2664 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2665 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2671 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2672 drm_radeon_cmd_header_t header,
2673 drm_radeon_kcmd_buffer_t *cmdbuf)
2675 int sz = header.scalars.count;
2676 int start = header.scalars.offset;
2677 int stride = header.scalars.stride;
2681 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2682 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2683 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2684 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2691 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2692 drm_radeon_cmd_header_t header,
2693 drm_radeon_kcmd_buffer_t *cmdbuf)
2695 int sz = header.scalars.count;
2696 int start = ((unsigned int)header.scalars.offset) + 0x100;
2697 int stride = header.scalars.stride;
2701 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2702 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2703 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2704 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2709 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2710 drm_radeon_cmd_header_t header,
2711 drm_radeon_kcmd_buffer_t *cmdbuf)
2713 int sz = header.vectors.count;
2714 int start = header.vectors.offset;
2715 int stride = header.vectors.stride;
2719 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2720 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2721 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2722 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2723 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2729 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2730 drm_radeon_cmd_header_t header,
2731 drm_radeon_kcmd_buffer_t *cmdbuf)
2733 int sz = header.veclinear.count * 4;
2734 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2739 if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
2743 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2744 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2745 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2746 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2747 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2753 static int radeon_emit_packet3(struct drm_device * dev,
2754 struct drm_file *file_priv,
2755 drm_radeon_kcmd_buffer_t *cmdbuf)
2757 drm_radeon_private_t *dev_priv = dev->dev_private;
2764 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2766 DRM_ERROR("Packet verification failed\n");
2771 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2777 static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2778 struct drm_file *file_priv,
2779 drm_radeon_kcmd_buffer_t *cmdbuf,
2782 drm_radeon_private_t *dev_priv = dev->dev_private;
2783 struct drm_clip_rect box;
2786 struct drm_clip_rect __user *boxes = cmdbuf->boxes;
2792 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2794 DRM_ERROR("Packet verification failed\n");
2802 if (i < cmdbuf->nbox) {
2803 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
2805 /* FIXME The second and subsequent times round
2806 * this loop, send a WAIT_UNTIL_3D_IDLE before
2807 * calling emit_clip_rect(). This fixes a
2808 * lockup on fast machines when sending
2809 * several cliprects with a cmdbuf, as when
2810 * waving a 2D window over a 3D
2811 * window. Something in the commands from user
2812 * space seems to hang the card when they're
2813 * sent several times in a row. That would be
2814 * the correct place to fix it but this works
2815 * around it until I can figure that out - Tim
2819 RADEON_WAIT_UNTIL_3D_IDLE();
2822 radeon_emit_clip_rect(dev_priv, &box);
2826 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2829 } while (++i < cmdbuf->nbox);
2830 if (cmdbuf->nbox == 1)
2835 drm_buffer_advance(cmdbuf->buffer, cmdsz * 4);
2839 static int radeon_emit_wait(struct drm_device * dev, int flags)
2841 drm_radeon_private_t *dev_priv = dev->dev_private;
2844 DRM_DEBUG("%x\n", flags);
2846 case RADEON_WAIT_2D:
2848 RADEON_WAIT_UNTIL_2D_IDLE();
2851 case RADEON_WAIT_3D:
2853 RADEON_WAIT_UNTIL_3D_IDLE();
2856 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2858 RADEON_WAIT_UNTIL_IDLE();
2868 static int radeon_cp_cmdbuf(struct drm_device *dev, void *data,
2869 struct drm_file *file_priv)
2871 drm_radeon_private_t *dev_priv = dev->dev_private;
2872 struct drm_device_dma *dma = dev->dma;
2873 struct drm_buf *buf = NULL;
2874 drm_radeon_cmd_header_t stack_header;
2876 drm_radeon_kcmd_buffer_t *cmdbuf = data;
2879 LOCK_TEST_WITH_RETURN(dev, file_priv);
2881 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2882 VB_AGE_TEST_WITH_RETURN(dev_priv);
2884 if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
2888 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2889 * races between checking values and using those values in other code,
2890 * and simply to avoid a lot of function calls to copy in data.
2892 if (cmdbuf->bufsz != 0) {
2894 void __user *buffer = cmdbuf->buffer;
2895 rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz);
2898 rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer,
2901 drm_buffer_free(cmdbuf->buffer);
2907 orig_nbox = cmdbuf->nbox;
2909 if (dev_priv->microcode_version == UCODE_R300) {
2911 temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
2913 drm_buffer_free(cmdbuf->buffer);
2918 /* microcode_version != r300 */
2919 while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) {
2921 drm_radeon_cmd_header_t *header;
2922 header = drm_buffer_read_object(cmdbuf->buffer,
2923 sizeof(stack_header), &stack_header);
2925 switch (header->header.cmd_type) {
2926 case RADEON_CMD_PACKET:
2927 DRM_DEBUG("RADEON_CMD_PACKET\n");
2928 if (radeon_emit_packets
2929 (dev_priv, file_priv, *header, cmdbuf)) {
2930 DRM_ERROR("radeon_emit_packets failed\n");
2935 case RADEON_CMD_SCALARS:
2936 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2937 if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) {
2938 DRM_ERROR("radeon_emit_scalars failed\n");
2943 case RADEON_CMD_VECTORS:
2944 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2945 if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) {
2946 DRM_ERROR("radeon_emit_vectors failed\n");
2951 case RADEON_CMD_DMA_DISCARD:
2952 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2953 idx = header->dma.buf_idx;
2954 if (idx < 0 || idx >= dma->buf_count) {
2955 DRM_ERROR("buffer index %d (of %d max)\n",
2956 idx, dma->buf_count - 1);
2960 buf = dma->buflist[idx];
2961 if (buf->file_priv != file_priv || buf->pending) {
2962 DRM_ERROR("bad buffer %p %p %d\n",
2963 buf->file_priv, file_priv,
2968 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2971 case RADEON_CMD_PACKET3:
2972 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2973 if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
2974 DRM_ERROR("radeon_emit_packet3 failed\n");
2979 case RADEON_CMD_PACKET3_CLIP:
2980 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2981 if (radeon_emit_packet3_cliprect
2982 (dev, file_priv, cmdbuf, orig_nbox)) {
2983 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2988 case RADEON_CMD_SCALARS2:
2989 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2990 if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) {
2991 DRM_ERROR("radeon_emit_scalars2 failed\n");
2996 case RADEON_CMD_WAIT:
2997 DRM_DEBUG("RADEON_CMD_WAIT\n");
2998 if (radeon_emit_wait(dev, header->wait.flags)) {
2999 DRM_ERROR("radeon_emit_wait failed\n");
3003 case RADEON_CMD_VECLINEAR:
3004 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
3005 if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) {
3006 DRM_ERROR("radeon_emit_veclinear failed\n");
3012 DRM_ERROR("bad cmd_type %d at byte %d\n",
3013 header->header.cmd_type,
3014 cmdbuf->buffer->iterator);
3019 drm_buffer_free(cmdbuf->buffer);
3022 DRM_DEBUG("DONE\n");
3027 drm_buffer_free(cmdbuf->buffer);
3031 static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3033 drm_radeon_private_t *dev_priv = dev->dev_private;
3034 drm_radeon_getparam_t *param = data;
3037 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
3039 switch (param->param) {
3040 case RADEON_PARAM_GART_BUFFER_OFFSET:
3041 value = dev_priv->gart_buffers_offset;
3043 case RADEON_PARAM_LAST_FRAME:
3044 dev_priv->stats.last_frame_reads++;
3045 value = GET_SCRATCH(dev_priv, 0);
3047 case RADEON_PARAM_LAST_DISPATCH:
3048 value = GET_SCRATCH(dev_priv, 1);
3050 case RADEON_PARAM_LAST_CLEAR:
3051 dev_priv->stats.last_clear_reads++;
3052 value = GET_SCRATCH(dev_priv, 2);
3054 case RADEON_PARAM_IRQ_NR:
3055 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3060 case RADEON_PARAM_GART_BASE:
3061 value = dev_priv->gart_vm_start;
3063 case RADEON_PARAM_REGISTER_HANDLE:
3064 value = dev_priv->mmio->offset;
3066 case RADEON_PARAM_STATUS_HANDLE:
3067 value = dev_priv->ring_rptr_offset;
3069 #if BITS_PER_LONG == 32
3071 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
3072 * pointer which can't fit into an int-sized variable. According to
3073 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
3074 * not supporting it shouldn't be a problem. If the same functionality
3075 * is needed on 64-bit platforms, a new ioctl() would have to be added,
3076 * so backwards-compatibility for the embedded platforms can be
3077 * maintained. --davidm 4-Feb-2004.
3079 case RADEON_PARAM_SAREA_HANDLE:
3080 /* The lock is the first dword in the sarea. */
3081 /* no users of this parameter */
3084 case RADEON_PARAM_GART_TEX_HANDLE:
3085 value = dev_priv->gart_textures_offset;
3087 case RADEON_PARAM_SCRATCH_OFFSET:
3088 if (!dev_priv->writeback_works)
3090 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3091 value = R600_SCRATCH_REG_OFFSET;
3093 value = RADEON_SCRATCH_REG_OFFSET;
3095 case RADEON_PARAM_CARD_TYPE:
3096 if (dev_priv->flags & RADEON_IS_PCIE)
3097 value = RADEON_CARD_PCIE;
3098 else if (dev_priv->flags & RADEON_IS_AGP)
3099 value = RADEON_CARD_AGP;
3101 value = RADEON_CARD_PCI;
3103 case RADEON_PARAM_VBLANK_CRTC:
3104 value = radeon_vblank_crtc_get(dev);
3106 case RADEON_PARAM_FB_LOCATION:
3107 value = radeon_read_fb_location(dev_priv);
3109 case RADEON_PARAM_NUM_GB_PIPES:
3110 value = dev_priv->num_gb_pipes;
3112 case RADEON_PARAM_NUM_Z_PIPES:
3113 value = dev_priv->num_z_pipes;
3116 DRM_DEBUG("Invalid parameter %d\n", param->param);
3120 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
3121 DRM_ERROR("copy_to_user\n");
3128 static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3130 drm_radeon_private_t *dev_priv = dev->dev_private;
3131 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
3132 drm_radeon_setparam_t *sp = data;
3133 struct drm_radeon_driver_file_fields *radeon_priv;
3135 switch (sp->param) {
3136 case RADEON_SETPARAM_FB_LOCATION:
3137 radeon_priv = file_priv->driver_priv;
3138 radeon_priv->radeon_fb_delta = dev_priv->fb_location -
3141 case RADEON_SETPARAM_SWITCH_TILING:
3142 if (sp->value == 0) {
3143 DRM_DEBUG("color tiling disabled\n");
3144 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3145 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3146 if (master_priv->sarea_priv)
3147 master_priv->sarea_priv->tiling_enabled = 0;
3148 } else if (sp->value == 1) {
3149 DRM_DEBUG("color tiling enabled\n");
3150 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3151 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3152 if (master_priv->sarea_priv)
3153 master_priv->sarea_priv->tiling_enabled = 1;
3156 case RADEON_SETPARAM_PCIGART_LOCATION:
3157 dev_priv->pcigart_offset = sp->value;
3158 dev_priv->pcigart_offset_set = 1;
3160 case RADEON_SETPARAM_NEW_MEMMAP:
3161 dev_priv->new_memmap = sp->value;
3163 case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
3164 dev_priv->gart_info.table_size = sp->value;
3165 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3166 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3168 case RADEON_SETPARAM_VBLANK_CRTC:
3169 return radeon_vblank_crtc_set(dev, sp->value);
3172 DRM_DEBUG("Invalid parameter %d\n", sp->param);
3179 /* When a client dies:
3180 * - Check for and clean up flipped page state
3181 * - Free any alloced GART memory.
3182 * - Free any alloced radeon surfaces.
3184 * DRM infrastructure takes care of reclaiming dma buffers.
3186 void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
3188 if (dev->dev_private) {
3189 drm_radeon_private_t *dev_priv = dev->dev_private;
3190 dev_priv->page_flipping = 0;
3191 radeon_mem_release(file_priv, dev_priv->gart_heap);
3192 radeon_mem_release(file_priv, dev_priv->fb_heap);
3193 radeon_surfaces_release(file_priv, dev_priv);
3197 void radeon_driver_lastclose(struct drm_device *dev)
3199 radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
3200 radeon_do_release(dev);
3203 int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
3205 drm_radeon_private_t *dev_priv = dev->dev_private;
3206 struct drm_radeon_driver_file_fields *radeon_priv;
3209 radeon_priv = malloc(sizeof(*radeon_priv), DRM_MEM_DRIVER, M_NOWAIT);
3214 file_priv->driver_priv = radeon_priv;
3217 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3219 radeon_priv->radeon_fb_delta = 0;
3223 void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3225 struct drm_radeon_driver_file_fields *radeon_priv =
3226 file_priv->driver_priv;
3228 free(radeon_priv, DRM_MEM_DRIVER);
3231 struct drm_ioctl_desc radeon_ioctls[] = {
3232 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3233 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3236 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3237 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3238 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3239 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3240 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3241 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3242 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3243 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3244 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3245 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3246 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3247 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3248 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3249 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3250 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3251 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3252 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3253 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3254 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3255 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3256 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3257 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3258 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3259 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3262 int radeon_max_ioctl = ARRAY_SIZE(radeon_ioctls);