2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
28 #include <dev/drm2/drmP.h>
30 #include "radeon_asic.h"
31 #include <dev/drm2/radeon/radeon_drm.h>
34 #include "si_blit_shaders.h"
36 #define SI_PFP_UCODE_SIZE 2144
37 #define SI_PM4_UCODE_SIZE 2144
38 #define SI_CE_UCODE_SIZE 2144
39 #define SI_RLC_UCODE_SIZE 2048
40 #define SI_MC_UCODE_SIZE 7769
43 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
46 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
47 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
48 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
49 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
50 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
51 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
52 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
53 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
54 MODULE_FIRMWARE("radeon/VERDE_me.bin");
55 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
56 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
57 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
60 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
61 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
62 extern void r600_ih_ring_fini(struct radeon_device *rdev);
63 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
64 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
65 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
66 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
69 /* get temperature in millidegrees */
70 int si_get_temp(struct radeon_device *rdev)
75 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
81 actual_temp = temp & 0x1ff;
83 actual_temp = (actual_temp * 1000);
88 #define TAHITI_IO_MC_REGS_SIZE 36
90 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
91 {0x0000006f, 0x03044000},
92 {0x00000070, 0x0480c018},
93 {0x00000071, 0x00000040},
94 {0x00000072, 0x01000000},
95 {0x00000074, 0x000000ff},
96 {0x00000075, 0x00143400},
97 {0x00000076, 0x08ec0800},
98 {0x00000077, 0x040000cc},
99 {0x00000079, 0x00000000},
100 {0x0000007a, 0x21000409},
101 {0x0000007c, 0x00000000},
102 {0x0000007d, 0xe8000000},
103 {0x0000007e, 0x044408a8},
104 {0x0000007f, 0x00000003},
105 {0x00000080, 0x00000000},
106 {0x00000081, 0x01000000},
107 {0x00000082, 0x02000000},
108 {0x00000083, 0x00000000},
109 {0x00000084, 0xe3f3e4f4},
110 {0x00000085, 0x00052024},
111 {0x00000087, 0x00000000},
112 {0x00000088, 0x66036603},
113 {0x00000089, 0x01000000},
114 {0x0000008b, 0x1c0a0000},
115 {0x0000008c, 0xff010000},
116 {0x0000008e, 0xffffefff},
117 {0x0000008f, 0xfff3efff},
118 {0x00000090, 0xfff3efbf},
119 {0x00000094, 0x00101101},
120 {0x00000095, 0x00000fff},
121 {0x00000096, 0x00116fff},
122 {0x00000097, 0x60010000},
123 {0x00000098, 0x10010000},
124 {0x00000099, 0x00006000},
125 {0x0000009a, 0x00001000},
126 {0x0000009f, 0x00a77400}
129 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
130 {0x0000006f, 0x03044000},
131 {0x00000070, 0x0480c018},
132 {0x00000071, 0x00000040},
133 {0x00000072, 0x01000000},
134 {0x00000074, 0x000000ff},
135 {0x00000075, 0x00143400},
136 {0x00000076, 0x08ec0800},
137 {0x00000077, 0x040000cc},
138 {0x00000079, 0x00000000},
139 {0x0000007a, 0x21000409},
140 {0x0000007c, 0x00000000},
141 {0x0000007d, 0xe8000000},
142 {0x0000007e, 0x044408a8},
143 {0x0000007f, 0x00000003},
144 {0x00000080, 0x00000000},
145 {0x00000081, 0x01000000},
146 {0x00000082, 0x02000000},
147 {0x00000083, 0x00000000},
148 {0x00000084, 0xe3f3e4f4},
149 {0x00000085, 0x00052024},
150 {0x00000087, 0x00000000},
151 {0x00000088, 0x66036603},
152 {0x00000089, 0x01000000},
153 {0x0000008b, 0x1c0a0000},
154 {0x0000008c, 0xff010000},
155 {0x0000008e, 0xffffefff},
156 {0x0000008f, 0xfff3efff},
157 {0x00000090, 0xfff3efbf},
158 {0x00000094, 0x00101101},
159 {0x00000095, 0x00000fff},
160 {0x00000096, 0x00116fff},
161 {0x00000097, 0x60010000},
162 {0x00000098, 0x10010000},
163 {0x00000099, 0x00006000},
164 {0x0000009a, 0x00001000},
165 {0x0000009f, 0x00a47400}
168 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
169 {0x0000006f, 0x03044000},
170 {0x00000070, 0x0480c018},
171 {0x00000071, 0x00000040},
172 {0x00000072, 0x01000000},
173 {0x00000074, 0x000000ff},
174 {0x00000075, 0x00143400},
175 {0x00000076, 0x08ec0800},
176 {0x00000077, 0x040000cc},
177 {0x00000079, 0x00000000},
178 {0x0000007a, 0x21000409},
179 {0x0000007c, 0x00000000},
180 {0x0000007d, 0xe8000000},
181 {0x0000007e, 0x044408a8},
182 {0x0000007f, 0x00000003},
183 {0x00000080, 0x00000000},
184 {0x00000081, 0x01000000},
185 {0x00000082, 0x02000000},
186 {0x00000083, 0x00000000},
187 {0x00000084, 0xe3f3e4f4},
188 {0x00000085, 0x00052024},
189 {0x00000087, 0x00000000},
190 {0x00000088, 0x66036603},
191 {0x00000089, 0x01000000},
192 {0x0000008b, 0x1c0a0000},
193 {0x0000008c, 0xff010000},
194 {0x0000008e, 0xffffefff},
195 {0x0000008f, 0xfff3efff},
196 {0x00000090, 0xfff3efbf},
197 {0x00000094, 0x00101101},
198 {0x00000095, 0x00000fff},
199 {0x00000096, 0x00116fff},
200 {0x00000097, 0x60010000},
201 {0x00000098, 0x10010000},
202 {0x00000099, 0x00006000},
203 {0x0000009a, 0x00001000},
204 {0x0000009f, 0x00a37400}
208 static int si_mc_load_microcode(struct radeon_device *rdev)
210 const __be32 *fw_data;
211 u32 running, blackout = 0;
212 const u32 *io_mc_regs;
213 int i, ucode_size, regs_size;
218 switch (rdev->family) {
220 io_mc_regs = &tahiti_io_mc_regs[0][0];
221 ucode_size = SI_MC_UCODE_SIZE;
222 regs_size = TAHITI_IO_MC_REGS_SIZE;
225 io_mc_regs = &pitcairn_io_mc_regs[0][0];
226 ucode_size = SI_MC_UCODE_SIZE;
227 regs_size = TAHITI_IO_MC_REGS_SIZE;
231 io_mc_regs = &verde_io_mc_regs[0][0];
232 ucode_size = SI_MC_UCODE_SIZE;
233 regs_size = TAHITI_IO_MC_REGS_SIZE;
237 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
241 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
242 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
245 /* reset the engine and set to writable */
246 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
247 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
249 /* load mc io regs */
250 for (i = 0; i < regs_size; i++) {
251 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
252 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
254 /* load the MC ucode */
255 fw_data = (const __be32 *)rdev->mc_fw->data;
256 for (i = 0; i < ucode_size; i++)
257 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
259 /* put the engine back into the active state */
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
261 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
262 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
264 /* wait for training to complete */
265 for (i = 0; i < rdev->usec_timeout; i++) {
266 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
270 for (i = 0; i < rdev->usec_timeout; i++) {
271 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
277 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
283 static int si_init_microcode(struct radeon_device *rdev)
285 const char *chip_name;
286 const char *rlc_chip_name;
287 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
293 switch (rdev->family) {
295 chip_name = "TAHITI";
296 rlc_chip_name = "TAHITI";
297 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
298 me_req_size = SI_PM4_UCODE_SIZE * 4;
299 ce_req_size = SI_CE_UCODE_SIZE * 4;
300 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
301 mc_req_size = SI_MC_UCODE_SIZE * 4;
304 chip_name = "PITCAIRN";
305 rlc_chip_name = "PITCAIRN";
306 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
307 me_req_size = SI_PM4_UCODE_SIZE * 4;
308 ce_req_size = SI_CE_UCODE_SIZE * 4;
309 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
310 mc_req_size = SI_MC_UCODE_SIZE * 4;
314 rlc_chip_name = "VERDE";
315 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
316 me_req_size = SI_PM4_UCODE_SIZE * 4;
317 ce_req_size = SI_CE_UCODE_SIZE * 4;
318 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
319 mc_req_size = SI_MC_UCODE_SIZE * 4;
321 default: panic("%s: Unsupported family %d", __func__, rdev->family);
324 DRM_INFO("Loading %s Microcode\n", chip_name);
327 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
328 rdev->pfp_fw = firmware_get(fw_name);
329 if (rdev->pfp_fw == NULL) {
333 if (rdev->pfp_fw->datasize != pfp_req_size) {
335 "si_cp: Bogus length %zu in firmware \"%s\"\n",
336 rdev->pfp_fw->datasize, fw_name);
341 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
342 rdev->me_fw = firmware_get(fw_name);
343 if (rdev->me_fw == NULL) {
347 if (rdev->me_fw->datasize != me_req_size) {
349 "si_cp: Bogus length %zu in firmware \"%s\"\n",
350 rdev->me_fw->datasize, fw_name);
354 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", chip_name);
355 rdev->ce_fw = firmware_get(fw_name);
356 if (rdev->ce_fw == NULL) {
360 if (rdev->ce_fw->datasize != ce_req_size) {
362 "si_cp: Bogus length %zu in firmware \"%s\"\n",
363 rdev->ce_fw->datasize, fw_name);
367 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name);
368 rdev->rlc_fw = firmware_get(fw_name);
369 if (rdev->rlc_fw == NULL) {
373 if (rdev->rlc_fw->datasize != rlc_req_size) {
375 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
376 rdev->rlc_fw->datasize, fw_name);
380 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name);
381 rdev->mc_fw = firmware_get(fw_name);
382 if (rdev->mc_fw == NULL) {
386 if (rdev->mc_fw->datasize != mc_req_size) {
388 "si_mc: Bogus length %zu in firmware \"%s\"\n",
389 rdev->mc_fw->datasize, fw_name);
397 "si_cp: Failed to load firmware \"%s\"\n",
399 if (rdev->pfp_fw != NULL) {
400 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
403 if (rdev->me_fw != NULL) {
404 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
407 if (rdev->ce_fw != NULL) {
408 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD);
411 if (rdev->rlc_fw != NULL) {
412 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
415 if (rdev->mc_fw != NULL) {
416 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD);
424 * si_fini_microcode - drop the firmwares image references
426 * @rdev: radeon_device pointer
428 * Drop the pfp, me, rlc, mc and ce firmware image references.
429 * Called at driver shutdown.
431 static void si_fini_microcode(struct radeon_device *rdev)
434 if (rdev->pfp_fw != NULL) {
435 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD);
439 if (rdev->me_fw != NULL) {
440 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
444 if (rdev->rlc_fw != NULL) {
445 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD);
449 if (rdev->mc_fw != NULL) {
450 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD);
454 if (rdev->ce_fw != NULL) {
455 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD);
460 /* watermark setup */
461 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
462 struct radeon_crtc *radeon_crtc,
463 struct drm_display_mode *mode,
464 struct drm_display_mode *other_mode)
469 * There are 3 line buffers, each one shared by 2 display controllers.
470 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
471 * the display controllers. The paritioning is done via one of four
472 * preset allocations specified in bits 21:20:
474 * 2 - whole lb, other crtc must be disabled
476 /* this can get tricky if we have two large displays on a paired group
477 * of crtcs. Ideally for multiple large displays we'd assign them to
478 * non-linked crtcs for maximum line buffer allocation.
480 if (radeon_crtc->base.enabled && mode) {
488 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
489 DC_LB_MEMORY_CONFIG(tmp));
491 if (radeon_crtc->base.enabled && mode) {
501 /* controller not enabled, so no lb used */
505 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
507 u32 tmp = RREG32(MC_SHARED_CHMAP);
509 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
532 struct dce6_wm_params {
533 u32 dram_channels; /* number of dram channels */
534 u32 yclk; /* bandwidth per dram data pin in kHz */
535 u32 sclk; /* engine clock in kHz */
536 u32 disp_clk; /* display clock in kHz */
537 u32 src_width; /* viewport width */
538 u32 active_time; /* active display time in ns */
539 u32 blank_time; /* blank time in ns */
540 bool interlaced; /* mode is interlaced */
541 fixed20_12 vsc; /* vertical scale ratio */
542 u32 num_heads; /* number of active crtcs */
543 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
544 u32 lb_size; /* line buffer allocated to pipe */
545 u32 vtaps; /* vertical scaler taps */
548 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
550 /* Calculate raw DRAM Bandwidth */
551 fixed20_12 dram_efficiency; /* 0.7 */
552 fixed20_12 yclk, dram_channels, bandwidth;
555 a.full = dfixed_const(1000);
556 yclk.full = dfixed_const(wm->yclk);
557 yclk.full = dfixed_div(yclk, a);
558 dram_channels.full = dfixed_const(wm->dram_channels * 4);
559 a.full = dfixed_const(10);
560 dram_efficiency.full = dfixed_const(7);
561 dram_efficiency.full = dfixed_div(dram_efficiency, a);
562 bandwidth.full = dfixed_mul(dram_channels, yclk);
563 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
565 return dfixed_trunc(bandwidth);
568 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
570 /* Calculate DRAM Bandwidth and the part allocated to display. */
571 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
572 fixed20_12 yclk, dram_channels, bandwidth;
575 a.full = dfixed_const(1000);
576 yclk.full = dfixed_const(wm->yclk);
577 yclk.full = dfixed_div(yclk, a);
578 dram_channels.full = dfixed_const(wm->dram_channels * 4);
579 a.full = dfixed_const(10);
580 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
581 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
582 bandwidth.full = dfixed_mul(dram_channels, yclk);
583 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
585 return dfixed_trunc(bandwidth);
588 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
590 /* Calculate the display Data return Bandwidth */
591 fixed20_12 return_efficiency; /* 0.8 */
592 fixed20_12 sclk, bandwidth;
595 a.full = dfixed_const(1000);
596 sclk.full = dfixed_const(wm->sclk);
597 sclk.full = dfixed_div(sclk, a);
598 a.full = dfixed_const(10);
599 return_efficiency.full = dfixed_const(8);
600 return_efficiency.full = dfixed_div(return_efficiency, a);
601 a.full = dfixed_const(32);
602 bandwidth.full = dfixed_mul(a, sclk);
603 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
605 return dfixed_trunc(bandwidth);
608 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
613 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
615 /* Calculate the DMIF Request Bandwidth */
616 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
617 fixed20_12 disp_clk, sclk, bandwidth;
618 fixed20_12 a, b1, b2;
621 a.full = dfixed_const(1000);
622 disp_clk.full = dfixed_const(wm->disp_clk);
623 disp_clk.full = dfixed_div(disp_clk, a);
624 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
625 b1.full = dfixed_mul(a, disp_clk);
627 a.full = dfixed_const(1000);
628 sclk.full = dfixed_const(wm->sclk);
629 sclk.full = dfixed_div(sclk, a);
630 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
631 b2.full = dfixed_mul(a, sclk);
633 a.full = dfixed_const(10);
634 disp_clk_request_efficiency.full = dfixed_const(8);
635 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
637 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
639 a.full = dfixed_const(min_bandwidth);
640 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
642 return dfixed_trunc(bandwidth);
645 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
647 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
648 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
649 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
650 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
652 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
655 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
657 /* Calculate the display mode Average Bandwidth
658 * DisplayMode should contain the source and destination dimensions,
662 fixed20_12 line_time;
663 fixed20_12 src_width;
664 fixed20_12 bandwidth;
667 a.full = dfixed_const(1000);
668 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
669 line_time.full = dfixed_div(line_time, a);
670 bpp.full = dfixed_const(wm->bytes_per_pixel);
671 src_width.full = dfixed_const(wm->src_width);
672 bandwidth.full = dfixed_mul(src_width, bpp);
673 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
674 bandwidth.full = dfixed_div(bandwidth, line_time);
676 return dfixed_trunc(bandwidth);
679 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
681 /* First calcualte the latency in ns */
682 u32 mc_latency = 2000; /* 2000 ns. */
683 u32 available_bandwidth = dce6_available_bandwidth(wm);
684 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
685 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
686 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
687 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
688 (wm->num_heads * cursor_line_pair_return_time);
689 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
690 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
691 u32 tmp, dmif_size = 12288;
694 if (wm->num_heads == 0)
697 a.full = dfixed_const(2);
698 b.full = dfixed_const(1);
699 if ((wm->vsc.full > a.full) ||
700 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
702 ((wm->vsc.full >= a.full) && wm->interlaced))
703 max_src_lines_per_dst_line = 4;
705 max_src_lines_per_dst_line = 2;
707 a.full = dfixed_const(available_bandwidth);
708 b.full = dfixed_const(wm->num_heads);
709 a.full = dfixed_div(a, b);
711 b.full = dfixed_const(mc_latency + 512);
712 c.full = dfixed_const(wm->disp_clk);
713 b.full = dfixed_div(b, c);
715 c.full = dfixed_const(dmif_size);
716 b.full = dfixed_div(c, b);
718 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
720 b.full = dfixed_const(1000);
721 c.full = dfixed_const(wm->disp_clk);
722 b.full = dfixed_div(c, b);
723 c.full = dfixed_const(wm->bytes_per_pixel);
724 b.full = dfixed_mul(b, c);
726 lb_fill_bw = min(tmp, dfixed_trunc(b));
728 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
729 b.full = dfixed_const(1000);
730 c.full = dfixed_const(lb_fill_bw);
731 b.full = dfixed_div(c, b);
732 a.full = dfixed_div(a, b);
733 line_fill_time = dfixed_trunc(a);
735 if (line_fill_time < wm->active_time)
738 return latency + (line_fill_time - wm->active_time);
742 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
744 if (dce6_average_bandwidth(wm) <=
745 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
751 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
753 if (dce6_average_bandwidth(wm) <=
754 (dce6_available_bandwidth(wm) / wm->num_heads))
760 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
762 u32 lb_partitions = wm->lb_size / wm->src_width;
763 u32 line_time = wm->active_time + wm->blank_time;
764 u32 latency_tolerant_lines;
768 a.full = dfixed_const(1);
769 if (wm->vsc.full > a.full)
770 latency_tolerant_lines = 1;
772 if (lb_partitions <= (wm->vtaps + 1))
773 latency_tolerant_lines = 1;
775 latency_tolerant_lines = 2;
778 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
780 if (dce6_latency_watermark(wm) <= latency_hiding)
786 static void dce6_program_watermarks(struct radeon_device *rdev,
787 struct radeon_crtc *radeon_crtc,
788 u32 lb_size, u32 num_heads)
790 struct drm_display_mode *mode = &radeon_crtc->base.mode;
791 struct dce6_wm_params wm;
794 u32 latency_watermark_a = 0, latency_watermark_b = 0;
795 u32 priority_a_mark = 0, priority_b_mark = 0;
796 u32 priority_a_cnt = PRIORITY_OFF;
797 u32 priority_b_cnt = PRIORITY_OFF;
798 u32 tmp, arb_control3;
801 if (radeon_crtc->base.enabled && num_heads && mode) {
802 pixel_period = 1000000 / (u32)mode->clock;
803 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
807 wm.yclk = rdev->pm.current_mclk * 10;
808 wm.sclk = rdev->pm.current_sclk * 10;
809 wm.disp_clk = mode->clock;
810 wm.src_width = mode->crtc_hdisplay;
811 wm.active_time = mode->crtc_hdisplay * pixel_period;
812 wm.blank_time = line_time - wm.active_time;
813 wm.interlaced = false;
814 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
815 wm.interlaced = true;
816 wm.vsc = radeon_crtc->vsc;
818 if (radeon_crtc->rmx_type != RMX_OFF)
820 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
821 wm.lb_size = lb_size;
822 if (rdev->family == CHIP_ARUBA)
823 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
825 wm.dram_channels = si_get_number_of_dram_channels(rdev);
826 wm.num_heads = num_heads;
828 /* set for high clocks */
829 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
830 /* set for low clocks */
831 /* wm.yclk = low clk; wm.sclk = low clk */
832 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
834 /* possibly force display priority to high */
835 /* should really do this at mode validation time... */
836 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
837 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
838 !dce6_check_latency_hiding(&wm) ||
839 (rdev->disp_priority == 2)) {
840 DRM_DEBUG_KMS("force priority to high\n");
841 priority_a_cnt |= PRIORITY_ALWAYS_ON;
842 priority_b_cnt |= PRIORITY_ALWAYS_ON;
845 a.full = dfixed_const(1000);
846 b.full = dfixed_const(mode->clock);
847 b.full = dfixed_div(b, a);
848 c.full = dfixed_const(latency_watermark_a);
849 c.full = dfixed_mul(c, b);
850 c.full = dfixed_mul(c, radeon_crtc->hsc);
851 c.full = dfixed_div(c, a);
852 a.full = dfixed_const(16);
853 c.full = dfixed_div(c, a);
854 priority_a_mark = dfixed_trunc(c);
855 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
857 a.full = dfixed_const(1000);
858 b.full = dfixed_const(mode->clock);
859 b.full = dfixed_div(b, a);
860 c.full = dfixed_const(latency_watermark_b);
861 c.full = dfixed_mul(c, b);
862 c.full = dfixed_mul(c, radeon_crtc->hsc);
863 c.full = dfixed_div(c, a);
864 a.full = dfixed_const(16);
865 c.full = dfixed_div(c, a);
866 priority_b_mark = dfixed_trunc(c);
867 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
871 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
873 tmp &= ~LATENCY_WATERMARK_MASK(3);
874 tmp |= LATENCY_WATERMARK_MASK(1);
875 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
876 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
877 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
878 LATENCY_HIGH_WATERMARK(line_time)));
880 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
881 tmp &= ~LATENCY_WATERMARK_MASK(3);
882 tmp |= LATENCY_WATERMARK_MASK(2);
883 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
884 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
885 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
886 LATENCY_HIGH_WATERMARK(line_time)));
887 /* restore original selection */
888 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
890 /* write the priority marks */
891 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
892 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
896 void dce6_bandwidth_update(struct radeon_device *rdev)
898 struct drm_display_mode *mode0 = NULL;
899 struct drm_display_mode *mode1 = NULL;
900 u32 num_heads = 0, lb_size;
903 radeon_update_display_priority(rdev);
905 for (i = 0; i < rdev->num_crtc; i++) {
906 if (rdev->mode_info.crtcs[i]->base.enabled)
909 for (i = 0; i < rdev->num_crtc; i += 2) {
910 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
911 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
912 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
913 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
914 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
915 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
922 static void si_tiling_mode_table_init(struct radeon_device *rdev)
924 const u32 num_tile_mode_states = 32;
925 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
927 switch (rdev->config.si.mem_row_size_in_kb) {
929 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
933 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
936 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
940 if ((rdev->family == CHIP_TAHITI) ||
941 (rdev->family == CHIP_PITCAIRN)) {
942 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
943 switch (reg_offset) {
944 case 0: /* non-AA compressed depth or any compressed stencil */
945 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
947 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
948 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
949 NUM_BANKS(ADDR_SURF_16_BANK) |
950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
954 case 1: /* 2xAA/4xAA compressed depth only */
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
957 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
958 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
964 case 2: /* 8xAA compressed depth only */
965 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
967 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
968 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
969 NUM_BANKS(ADDR_SURF_16_BANK) |
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
974 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
975 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
976 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
977 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
979 NUM_BANKS(ADDR_SURF_16_BANK) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
984 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
987 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
989 NUM_BANKS(ADDR_SURF_16_BANK) |
990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
994 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
997 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
998 TILE_SPLIT(split_equal_to_row_size) |
999 NUM_BANKS(ADDR_SURF_16_BANK) |
1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1004 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1006 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1008 TILE_SPLIT(split_equal_to_row_size) |
1009 NUM_BANKS(ADDR_SURF_16_BANK) |
1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1014 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1015 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1017 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1018 TILE_SPLIT(split_equal_to_row_size) |
1019 NUM_BANKS(ADDR_SURF_16_BANK) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1024 case 8: /* 1D and 1D Array Surfaces */
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1026 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1027 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1029 NUM_BANKS(ADDR_SURF_16_BANK) |
1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1034 case 9: /* Displayable maps. */
1035 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1036 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1037 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1039 NUM_BANKS(ADDR_SURF_16_BANK) |
1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1044 case 10: /* Display 8bpp. */
1045 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1049 NUM_BANKS(ADDR_SURF_16_BANK) |
1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1054 case 11: /* Display 16bpp. */
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1057 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1059 NUM_BANKS(ADDR_SURF_16_BANK) |
1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1064 case 12: /* Display 32bpp. */
1065 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1067 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1068 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1069 NUM_BANKS(ADDR_SURF_16_BANK) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1074 case 13: /* Thin. */
1075 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1076 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1079 NUM_BANKS(ADDR_SURF_16_BANK) |
1080 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1084 case 14: /* Thin 8 bpp. */
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1089 NUM_BANKS(ADDR_SURF_16_BANK) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1094 case 15: /* Thin 16 bpp. */
1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 NUM_BANKS(ADDR_SURF_16_BANK) |
1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1104 case 16: /* Thin 32 bpp. */
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1109 NUM_BANKS(ADDR_SURF_16_BANK) |
1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1114 case 17: /* Thin 64 bpp. */
1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(split_equal_to_row_size) |
1119 NUM_BANKS(ADDR_SURF_16_BANK) |
1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1124 case 21: /* 8 bpp PRT. */
1125 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1126 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1127 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1128 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1129 NUM_BANKS(ADDR_SURF_16_BANK) |
1130 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1134 case 22: /* 16 bpp PRT */
1135 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1136 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1137 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1138 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1139 NUM_BANKS(ADDR_SURF_16_BANK) |
1140 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1144 case 23: /* 32 bpp PRT */
1145 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1147 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1148 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1149 NUM_BANKS(ADDR_SURF_16_BANK) |
1150 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1154 case 24: /* 64 bpp PRT */
1155 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1156 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1157 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1158 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1159 NUM_BANKS(ADDR_SURF_16_BANK) |
1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1164 case 25: /* 128 bpp PRT */
1165 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1166 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1168 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1169 NUM_BANKS(ADDR_SURF_8_BANK) |
1170 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1178 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1180 } else if (rdev->family == CHIP_VERDE) {
1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1182 switch (reg_offset) {
1183 case 0: /* non-AA compressed depth or any compressed stencil */
1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1185 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1186 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1187 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1188 NUM_BANKS(ADDR_SURF_16_BANK) |
1189 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1193 case 1: /* 2xAA/4xAA compressed depth only */
1194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1196 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1203 case 2: /* 8xAA compressed depth only */
1204 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1206 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1208 NUM_BANKS(ADDR_SURF_16_BANK) |
1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1213 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1214 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1215 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1216 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1218 NUM_BANKS(ADDR_SURF_16_BANK) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1223 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1228 NUM_BANKS(ADDR_SURF_16_BANK) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1233 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1234 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237 TILE_SPLIT(split_equal_to_row_size) |
1238 NUM_BANKS(ADDR_SURF_16_BANK) |
1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1243 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1247 TILE_SPLIT(split_equal_to_row_size) |
1248 NUM_BANKS(ADDR_SURF_16_BANK) |
1249 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1253 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1255 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257 TILE_SPLIT(split_equal_to_row_size) |
1258 NUM_BANKS(ADDR_SURF_16_BANK) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1263 case 8: /* 1D and 1D Array Surfaces */
1264 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1265 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1268 NUM_BANKS(ADDR_SURF_16_BANK) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1273 case 9: /* Displayable maps. */
1274 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1275 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1278 NUM_BANKS(ADDR_SURF_16_BANK) |
1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1283 case 10: /* Display 8bpp. */
1284 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1285 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1288 NUM_BANKS(ADDR_SURF_16_BANK) |
1289 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1293 case 11: /* Display 16bpp. */
1294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1296 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1298 NUM_BANKS(ADDR_SURF_16_BANK) |
1299 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1300 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1301 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1303 case 12: /* Display 32bpp. */
1304 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1305 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1306 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1307 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1308 NUM_BANKS(ADDR_SURF_16_BANK) |
1309 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1313 case 13: /* Thin. */
1314 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1315 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1316 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1318 NUM_BANKS(ADDR_SURF_16_BANK) |
1319 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1323 case 14: /* Thin 8 bpp. */
1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1326 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1327 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1328 NUM_BANKS(ADDR_SURF_16_BANK) |
1329 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1333 case 15: /* Thin 16 bpp. */
1334 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1336 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1338 NUM_BANKS(ADDR_SURF_16_BANK) |
1339 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1343 case 16: /* Thin 32 bpp. */
1344 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1346 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1348 NUM_BANKS(ADDR_SURF_16_BANK) |
1349 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1353 case 17: /* Thin 64 bpp. */
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1356 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1357 TILE_SPLIT(split_equal_to_row_size) |
1358 NUM_BANKS(ADDR_SURF_16_BANK) |
1359 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1363 case 21: /* 8 bpp PRT. */
1364 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1365 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1366 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1367 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1368 NUM_BANKS(ADDR_SURF_16_BANK) |
1369 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1373 case 22: /* 16 bpp PRT */
1374 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1375 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1376 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1378 NUM_BANKS(ADDR_SURF_16_BANK) |
1379 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1383 case 23: /* 32 bpp PRT */
1384 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1385 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1386 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1387 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1388 NUM_BANKS(ADDR_SURF_16_BANK) |
1389 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1393 case 24: /* 64 bpp PRT */
1394 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1396 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1397 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1398 NUM_BANKS(ADDR_SURF_16_BANK) |
1399 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1403 case 25: /* 128 bpp PRT */
1404 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1405 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1406 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1408 NUM_BANKS(ADDR_SURF_8_BANK) |
1409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1417 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1420 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1423 static void si_select_se_sh(struct radeon_device *rdev,
1424 u32 se_num, u32 sh_num)
1426 u32 data = INSTANCE_BROADCAST_WRITES;
1428 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1429 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1430 else if (se_num == 0xffffffff)
1431 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1432 else if (sh_num == 0xffffffff)
1433 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1435 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1436 WREG32(GRBM_GFX_INDEX, data);
1439 static u32 si_create_bitmask(u32 bit_width)
1443 for (i = 0; i < bit_width; i++) {
1450 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1454 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1456 data &= INACTIVE_CUS_MASK;
1459 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1461 data >>= INACTIVE_CUS_SHIFT;
1463 mask = si_create_bitmask(cu_per_sh);
1465 return ~data & mask;
1468 static void si_setup_spi(struct radeon_device *rdev,
1469 u32 se_num, u32 sh_per_se,
1473 u32 data, mask, active_cu;
1475 for (i = 0; i < se_num; i++) {
1476 for (j = 0; j < sh_per_se; j++) {
1477 si_select_se_sh(rdev, i, j);
1478 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1479 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1482 for (k = 0; k < 16; k++) {
1484 if (active_cu & mask) {
1486 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1492 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1495 static u32 si_get_rb_disabled(struct radeon_device *rdev,
1496 u32 max_rb_num, u32 se_num,
1501 data = RREG32(CC_RB_BACKEND_DISABLE);
1503 data &= BACKEND_DISABLE_MASK;
1506 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1508 data >>= BACKEND_DISABLE_SHIFT;
1510 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1515 static void si_setup_rb(struct radeon_device *rdev,
1516 u32 se_num, u32 sh_per_se,
1521 u32 disabled_rbs = 0;
1522 u32 enabled_rbs = 0;
1524 for (i = 0; i < se_num; i++) {
1525 for (j = 0; j < sh_per_se; j++) {
1526 si_select_se_sh(rdev, i, j);
1527 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1528 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1531 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1534 for (i = 0; i < max_rb_num; i++) {
1535 if (!(disabled_rbs & mask))
1536 enabled_rbs |= mask;
1540 for (i = 0; i < se_num; i++) {
1541 si_select_se_sh(rdev, i, 0xffffffff);
1543 for (j = 0; j < sh_per_se; j++) {
1544 switch (enabled_rbs & 3) {
1546 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1549 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1553 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1558 WREG32(PA_SC_RASTER_CONFIG, data);
1560 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1563 static void si_gpu_init(struct radeon_device *rdev)
1565 u32 gb_addr_config = 0;
1566 u32 mc_shared_chmap, mc_arb_ramcfg;
1568 u32 hdp_host_path_cntl;
1572 switch (rdev->family) {
1574 rdev->config.si.max_shader_engines = 2;
1575 rdev->config.si.max_tile_pipes = 12;
1576 rdev->config.si.max_cu_per_sh = 8;
1577 rdev->config.si.max_sh_per_se = 2;
1578 rdev->config.si.max_backends_per_se = 4;
1579 rdev->config.si.max_texture_channel_caches = 12;
1580 rdev->config.si.max_gprs = 256;
1581 rdev->config.si.max_gs_threads = 32;
1582 rdev->config.si.max_hw_contexts = 8;
1584 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1585 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1586 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1587 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1588 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1591 rdev->config.si.max_shader_engines = 2;
1592 rdev->config.si.max_tile_pipes = 8;
1593 rdev->config.si.max_cu_per_sh = 5;
1594 rdev->config.si.max_sh_per_se = 2;
1595 rdev->config.si.max_backends_per_se = 4;
1596 rdev->config.si.max_texture_channel_caches = 8;
1597 rdev->config.si.max_gprs = 256;
1598 rdev->config.si.max_gs_threads = 32;
1599 rdev->config.si.max_hw_contexts = 8;
1601 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1602 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1603 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1604 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1605 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1609 rdev->config.si.max_shader_engines = 1;
1610 rdev->config.si.max_tile_pipes = 4;
1611 rdev->config.si.max_cu_per_sh = 2;
1612 rdev->config.si.max_sh_per_se = 2;
1613 rdev->config.si.max_backends_per_se = 4;
1614 rdev->config.si.max_texture_channel_caches = 4;
1615 rdev->config.si.max_gprs = 256;
1616 rdev->config.si.max_gs_threads = 32;
1617 rdev->config.si.max_hw_contexts = 8;
1619 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1620 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1621 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1622 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1623 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1627 /* Initialize HDP */
1628 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1629 WREG32((0x2c14 + j), 0x00000000);
1630 WREG32((0x2c18 + j), 0x00000000);
1631 WREG32((0x2c1c + j), 0x00000000);
1632 WREG32((0x2c20 + j), 0x00000000);
1633 WREG32((0x2c24 + j), 0x00000000);
1636 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1638 evergreen_fix_pci_max_read_req_size(rdev);
1640 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1642 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1643 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1645 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1646 rdev->config.si.mem_max_burst_length_bytes = 256;
1647 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1648 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1649 if (rdev->config.si.mem_row_size_in_kb > 4)
1650 rdev->config.si.mem_row_size_in_kb = 4;
1651 /* XXX use MC settings? */
1652 rdev->config.si.shader_engine_tile_size = 32;
1653 rdev->config.si.num_gpus = 1;
1654 rdev->config.si.multi_gpu_tile_size = 64;
1656 /* fix up row size */
1657 gb_addr_config &= ~ROW_SIZE_MASK;
1658 switch (rdev->config.si.mem_row_size_in_kb) {
1661 gb_addr_config |= ROW_SIZE(0);
1664 gb_addr_config |= ROW_SIZE(1);
1667 gb_addr_config |= ROW_SIZE(2);
1671 /* setup tiling info dword. gb_addr_config is not adequate since it does
1672 * not have bank info, so create a custom tiling dword.
1673 * bits 3:0 num_pipes
1674 * bits 7:4 num_banks
1675 * bits 11:8 group_size
1676 * bits 15:12 row_size
1678 rdev->config.si.tile_config = 0;
1679 switch (rdev->config.si.num_tile_pipes) {
1681 rdev->config.si.tile_config |= (0 << 0);
1684 rdev->config.si.tile_config |= (1 << 0);
1687 rdev->config.si.tile_config |= (2 << 0);
1691 /* XXX what about 12? */
1692 rdev->config.si.tile_config |= (3 << 0);
1695 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1696 case 0: /* four banks */
1697 rdev->config.si.tile_config |= 0 << 4;
1699 case 1: /* eight banks */
1700 rdev->config.si.tile_config |= 1 << 4;
1702 case 2: /* sixteen banks */
1704 rdev->config.si.tile_config |= 2 << 4;
1707 rdev->config.si.tile_config |=
1708 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1709 rdev->config.si.tile_config |=
1710 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1712 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1713 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1714 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1715 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1716 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1717 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1719 si_tiling_mode_table_init(rdev);
1721 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1722 rdev->config.si.max_sh_per_se,
1723 rdev->config.si.max_backends_per_se);
1725 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1726 rdev->config.si.max_sh_per_se,
1727 rdev->config.si.max_cu_per_sh);
1730 /* set HW defaults for 3D engine */
1731 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1732 ROQ_IB2_START(0x2b)));
1733 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1735 sx_debug_1 = RREG32(SX_DEBUG_1);
1736 WREG32(SX_DEBUG_1, sx_debug_1);
1738 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1740 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1741 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1742 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1743 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1745 WREG32(VGT_NUM_INSTANCES, 1);
1747 WREG32(CP_PERFMON_CNTL, 0);
1749 WREG32(SQ_CONFIG, 0);
1751 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1752 FORCE_EOV_MAX_REZ_CNT(255)));
1754 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1755 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1757 WREG32(VGT_GS_VERTEX_REUSE, 16);
1758 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1760 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1761 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1762 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1763 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1764 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1765 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1766 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1767 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1769 tmp = RREG32(HDP_MISC_CNTL);
1770 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1771 WREG32(HDP_MISC_CNTL, tmp);
1773 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1774 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1776 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1782 * GPU scratch registers helpers function.
1784 static void si_scratch_init(struct radeon_device *rdev)
1788 rdev->scratch.num_reg = 7;
1789 rdev->scratch.reg_base = SCRATCH_REG0;
1790 for (i = 0; i < rdev->scratch.num_reg; i++) {
1791 rdev->scratch.free[i] = true;
1792 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1796 void si_fence_ring_emit(struct radeon_device *rdev,
1797 struct radeon_fence *fence)
1799 struct radeon_ring *ring = &rdev->ring[fence->ring];
1800 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1802 /* flush read cache over gart */
1803 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1804 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1805 radeon_ring_write(ring, 0);
1806 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1807 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1808 PACKET3_TC_ACTION_ENA |
1809 PACKET3_SH_KCACHE_ACTION_ENA |
1810 PACKET3_SH_ICACHE_ACTION_ENA);
1811 radeon_ring_write(ring, 0xFFFFFFFF);
1812 radeon_ring_write(ring, 0);
1813 radeon_ring_write(ring, 10); /* poll interval */
1814 /* EVENT_WRITE_EOP - flush caches, send int */
1815 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1816 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1817 radeon_ring_write(ring, addr & 0xffffffff);
1818 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1819 radeon_ring_write(ring, fence->seq);
1820 radeon_ring_write(ring, 0);
1826 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1828 struct radeon_ring *ring = &rdev->ring[ib->ring];
1831 if (ib->is_const_ib) {
1832 /* set switch buffer packet before const IB */
1833 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1834 radeon_ring_write(ring, 0);
1836 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1839 if (ring->rptr_save_reg) {
1840 next_rptr = ring->wptr + 3 + 4 + 8;
1841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1842 radeon_ring_write(ring, ((ring->rptr_save_reg -
1843 PACKET3_SET_CONFIG_REG_START) >> 2));
1844 radeon_ring_write(ring, next_rptr);
1845 } else if (rdev->wb.enabled) {
1846 next_rptr = ring->wptr + 5 + 4 + 8;
1847 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1848 radeon_ring_write(ring, (1 << 8));
1849 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1850 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1851 radeon_ring_write(ring, next_rptr);
1854 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1857 radeon_ring_write(ring, header);
1858 radeon_ring_write(ring,
1862 (ib->gpu_addr & 0xFFFFFFFC));
1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1864 radeon_ring_write(ring, ib->length_dw |
1865 (ib->vm ? (ib->vm->id << 24) : 0));
1867 if (!ib->is_const_ib) {
1868 /* flush read cache over gart for this vmid */
1869 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1870 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1871 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1872 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1873 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1874 PACKET3_TC_ACTION_ENA |
1875 PACKET3_SH_KCACHE_ACTION_ENA |
1876 PACKET3_SH_ICACHE_ACTION_ENA);
1877 radeon_ring_write(ring, 0xFFFFFFFF);
1878 radeon_ring_write(ring, 0);
1879 radeon_ring_write(ring, 10); /* poll interval */
1886 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1889 WREG32(CP_ME_CNTL, 0);
1891 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1892 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1893 WREG32(SCRATCH_UMSK, 0);
1894 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1895 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1896 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1901 static int si_cp_load_microcode(struct radeon_device *rdev)
1903 const __be32 *fw_data;
1906 if (!rdev->me_fw || !rdev->pfp_fw)
1909 si_cp_enable(rdev, false);
1912 fw_data = (const __be32 *)rdev->pfp_fw->data;
1913 WREG32(CP_PFP_UCODE_ADDR, 0);
1914 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1915 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1916 WREG32(CP_PFP_UCODE_ADDR, 0);
1919 fw_data = (const __be32 *)rdev->ce_fw->data;
1920 WREG32(CP_CE_UCODE_ADDR, 0);
1921 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1922 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1923 WREG32(CP_CE_UCODE_ADDR, 0);
1926 fw_data = (const __be32 *)rdev->me_fw->data;
1927 WREG32(CP_ME_RAM_WADDR, 0);
1928 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1929 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1930 WREG32(CP_ME_RAM_WADDR, 0);
1932 WREG32(CP_PFP_UCODE_ADDR, 0);
1933 WREG32(CP_CE_UCODE_ADDR, 0);
1934 WREG32(CP_ME_RAM_WADDR, 0);
1935 WREG32(CP_ME_RAM_RADDR, 0);
1939 static int si_cp_start(struct radeon_device *rdev)
1941 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1944 r = radeon_ring_lock(rdev, ring, 7 + 4);
1946 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1950 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1951 radeon_ring_write(ring, 0x1);
1952 radeon_ring_write(ring, 0x0);
1953 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1954 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1955 radeon_ring_write(ring, 0);
1956 radeon_ring_write(ring, 0);
1958 /* init the CE partitions */
1959 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1960 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1961 radeon_ring_write(ring, 0xc000);
1962 radeon_ring_write(ring, 0xe000);
1963 radeon_ring_unlock_commit(rdev, ring);
1965 si_cp_enable(rdev, true);
1967 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1969 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1973 /* setup clear context state */
1974 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1975 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1977 for (i = 0; i < si_default_size; i++)
1978 radeon_ring_write(ring, si_default_state[i]);
1980 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1981 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1983 /* set clear context state */
1984 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1985 radeon_ring_write(ring, 0);
1987 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1988 radeon_ring_write(ring, 0x00000316);
1989 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1990 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1992 radeon_ring_unlock_commit(rdev, ring);
1994 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1995 ring = &rdev->ring[i];
1996 r = radeon_ring_lock(rdev, ring, 2);
1998 /* clear the compute context state */
1999 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2000 radeon_ring_write(ring, 0);
2002 radeon_ring_unlock_commit(rdev, ring);
2008 static void si_cp_fini(struct radeon_device *rdev)
2010 struct radeon_ring *ring;
2011 si_cp_enable(rdev, false);
2013 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2014 radeon_ring_fini(rdev, ring);
2015 radeon_scratch_free(rdev, ring->rptr_save_reg);
2017 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2018 radeon_ring_fini(rdev, ring);
2019 radeon_scratch_free(rdev, ring->rptr_save_reg);
2021 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2022 radeon_ring_fini(rdev, ring);
2023 radeon_scratch_free(rdev, ring->rptr_save_reg);
2026 static int si_cp_resume(struct radeon_device *rdev)
2028 struct radeon_ring *ring;
2033 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2034 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2039 RREG32(GRBM_SOFT_RESET);
2041 WREG32(GRBM_SOFT_RESET, 0);
2042 RREG32(GRBM_SOFT_RESET);
2044 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2045 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2047 /* Set the write pointer delay */
2048 WREG32(CP_RB_WPTR_DELAY, 0);
2050 WREG32(CP_DEBUG, 0);
2051 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2053 /* ring 0 - compute and gfx */
2054 /* Set ring buffer size */
2055 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2056 rb_bufsz = drm_order(ring->ring_size / 8);
2057 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2059 tmp |= BUF_SWAP_32BIT;
2061 WREG32(CP_RB0_CNTL, tmp);
2063 /* Initialize the ring buffer's read and write pointers */
2064 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2066 WREG32(CP_RB0_WPTR, ring->wptr);
2068 /* set the wb address whether it's enabled or not */
2069 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2072 if (rdev->wb.enabled)
2073 WREG32(SCRATCH_UMSK, 0xff);
2075 tmp |= RB_NO_UPDATE;
2076 WREG32(SCRATCH_UMSK, 0);
2080 WREG32(CP_RB0_CNTL, tmp);
2082 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2084 ring->rptr = RREG32(CP_RB0_RPTR);
2086 /* ring1 - compute only */
2087 /* Set ring buffer size */
2088 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2089 rb_bufsz = drm_order(ring->ring_size / 8);
2090 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2092 tmp |= BUF_SWAP_32BIT;
2094 WREG32(CP_RB1_CNTL, tmp);
2096 /* Initialize the ring buffer's read and write pointers */
2097 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2099 WREG32(CP_RB1_WPTR, ring->wptr);
2101 /* set the wb address whether it's enabled or not */
2102 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2106 WREG32(CP_RB1_CNTL, tmp);
2108 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2110 ring->rptr = RREG32(CP_RB1_RPTR);
2112 /* ring2 - compute only */
2113 /* Set ring buffer size */
2114 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2115 rb_bufsz = drm_order(ring->ring_size / 8);
2116 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2118 tmp |= BUF_SWAP_32BIT;
2120 WREG32(CP_RB2_CNTL, tmp);
2122 /* Initialize the ring buffer's read and write pointers */
2123 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2125 WREG32(CP_RB2_WPTR, ring->wptr);
2127 /* set the wb address whether it's enabled or not */
2128 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2129 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2132 WREG32(CP_RB2_CNTL, tmp);
2134 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2136 ring->rptr = RREG32(CP_RB2_RPTR);
2138 /* start the rings */
2140 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2141 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2142 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2143 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2145 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2146 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2147 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2150 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2152 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2154 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2156 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2162 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2165 u32 grbm_status, grbm_status2;
2166 u32 grbm_status_se0, grbm_status_se1;
2168 srbm_status = RREG32(SRBM_STATUS);
2169 grbm_status = RREG32(GRBM_STATUS);
2170 grbm_status2 = RREG32(GRBM_STATUS2);
2171 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2172 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2173 if (!(grbm_status & GUI_ACTIVE)) {
2174 radeon_ring_lockup_update(ring);
2177 /* force CP activities */
2178 radeon_ring_force_activity(rdev, ring);
2179 return radeon_ring_test_lockup(rdev, ring);
2182 static void si_gpu_soft_reset_gfx(struct radeon_device *rdev)
2186 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2189 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2190 RREG32(GRBM_STATUS));
2191 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2192 RREG32(GRBM_STATUS2));
2193 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2194 RREG32(GRBM_STATUS_SE0));
2195 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2196 RREG32(GRBM_STATUS_SE1));
2197 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2198 RREG32(SRBM_STATUS));
2200 /* Disable CP parsing/prefetching */
2201 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2203 /* reset all the gfx blocks */
2204 grbm_reset = (SOFT_RESET_CP |
2218 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2219 WREG32(GRBM_SOFT_RESET, grbm_reset);
2220 (void)RREG32(GRBM_SOFT_RESET);
2222 WREG32(GRBM_SOFT_RESET, 0);
2223 (void)RREG32(GRBM_SOFT_RESET);
2225 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2226 RREG32(GRBM_STATUS));
2227 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2228 RREG32(GRBM_STATUS2));
2229 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2230 RREG32(GRBM_STATUS_SE0));
2231 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2232 RREG32(GRBM_STATUS_SE1));
2233 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2234 RREG32(SRBM_STATUS));
2237 static void si_gpu_soft_reset_dma(struct radeon_device *rdev)
2241 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2244 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
2245 RREG32(DMA_STATUS_REG));
2248 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2249 tmp &= ~DMA_RB_ENABLE;
2250 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2253 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2254 tmp &= ~DMA_RB_ENABLE;
2255 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2258 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
2259 RREG32(SRBM_SOFT_RESET);
2261 WREG32(SRBM_SOFT_RESET, 0);
2263 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
2264 RREG32(DMA_STATUS_REG));
2267 static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2269 struct evergreen_mc_save save;
2271 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2272 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2274 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2275 reset_mask &= ~RADEON_RESET_DMA;
2277 if (reset_mask == 0)
2280 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2282 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2283 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2284 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2285 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2287 evergreen_mc_stop(rdev, &save);
2288 if (radeon_mc_wait_for_idle(rdev)) {
2289 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2292 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2293 si_gpu_soft_reset_gfx(rdev);
2295 if (reset_mask & RADEON_RESET_DMA)
2296 si_gpu_soft_reset_dma(rdev);
2298 /* Wait a little for things to settle down */
2301 evergreen_mc_resume(rdev, &save);
2305 int si_asic_reset(struct radeon_device *rdev)
2307 return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2308 RADEON_RESET_COMPUTE |
2313 static void si_mc_program(struct radeon_device *rdev)
2315 struct evergreen_mc_save save;
2319 /* Initialize HDP */
2320 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2321 WREG32((0x2c14 + j), 0x00000000);
2322 WREG32((0x2c18 + j), 0x00000000);
2323 WREG32((0x2c1c + j), 0x00000000);
2324 WREG32((0x2c20 + j), 0x00000000);
2325 WREG32((0x2c24 + j), 0x00000000);
2327 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2329 evergreen_mc_stop(rdev, &save);
2330 if (radeon_mc_wait_for_idle(rdev)) {
2331 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2333 /* Lockout access through VGA aperture*/
2334 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2335 /* Update configuration */
2336 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2337 rdev->mc.vram_start >> 12);
2338 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2339 rdev->mc.vram_end >> 12);
2340 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2341 rdev->vram_scratch.gpu_addr >> 12);
2342 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2343 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2344 WREG32(MC_VM_FB_LOCATION, tmp);
2345 /* XXX double check these! */
2346 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2347 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2348 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2349 WREG32(MC_VM_AGP_BASE, 0);
2350 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2351 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2352 if (radeon_mc_wait_for_idle(rdev)) {
2353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2355 evergreen_mc_resume(rdev, &save);
2356 /* we need to own VRAM, so turn off the VGA renderer here
2357 * to stop it overwriting our objects */
2358 rv515_vga_render_disable(rdev);
2361 /* SI MC address space is 40 bits */
2362 static void si_vram_location(struct radeon_device *rdev,
2363 struct radeon_mc *mc, u64 base)
2365 mc->vram_start = base;
2366 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2367 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2368 mc->real_vram_size = mc->aper_size;
2369 mc->mc_vram_size = mc->aper_size;
2371 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2372 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
2373 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
2374 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
2377 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2379 u64 size_af, size_bf;
2381 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2382 size_bf = mc->vram_start & ~mc->gtt_base_align;
2383 if (size_bf > size_af) {
2384 if (mc->gtt_size > size_bf) {
2385 dev_warn(rdev->dev, "limiting GTT\n");
2386 mc->gtt_size = size_bf;
2388 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2390 if (mc->gtt_size > size_af) {
2391 dev_warn(rdev->dev, "limiting GTT\n");
2392 mc->gtt_size = size_af;
2394 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2396 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2397 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
2398 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end);
2401 static void si_vram_gtt_location(struct radeon_device *rdev,
2402 struct radeon_mc *mc)
2404 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2405 /* leave room for at least 1024M GTT */
2406 dev_warn(rdev->dev, "limiting VRAM\n");
2407 mc->real_vram_size = 0xFFC0000000ULL;
2408 mc->mc_vram_size = 0xFFC0000000ULL;
2410 si_vram_location(rdev, &rdev->mc, 0);
2411 rdev->mc.gtt_base_align = 0;
2412 si_gtt_location(rdev, mc);
2415 static int si_mc_init(struct radeon_device *rdev)
2418 int chansize, numchan;
2420 /* Get VRAM informations */
2421 rdev->mc.vram_is_ddr = true;
2422 tmp = RREG32(MC_ARB_RAMCFG);
2423 if (tmp & CHANSIZE_OVERRIDE) {
2425 } else if (tmp & CHANSIZE_MASK) {
2430 tmp = RREG32(MC_SHARED_CHMAP);
2431 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2461 rdev->mc.vram_width = numchan * chansize;
2462 /* Could aper size report 0 ? */
2463 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2464 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2465 /* size in MB on si */
2466 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2467 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2468 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2469 si_vram_gtt_location(rdev, &rdev->mc);
2470 radeon_update_bandwidth_info(rdev);
2478 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2480 /* flush hdp cache */
2481 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2483 /* bits 0-15 are the VM contexts0-15 */
2484 WREG32(VM_INVALIDATE_REQUEST, 1);
2487 static int si_pcie_gart_enable(struct radeon_device *rdev)
2491 if (rdev->gart.robj == NULL) {
2492 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2495 r = radeon_gart_table_vram_pin(rdev);
2498 radeon_gart_restore(rdev);
2499 /* Setup TLB control */
2500 WREG32(MC_VM_MX_L1_TLB_CNTL,
2503 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2504 ENABLE_ADVANCED_DRIVER_MODEL |
2505 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2506 /* Setup L2 cache */
2507 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2508 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2509 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2510 EFFECTIVE_L2_QUEUE_SIZE(7) |
2511 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2512 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2513 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2514 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2515 /* setup context0 */
2516 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2517 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2518 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2519 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2520 (u32)(rdev->dummy_page.addr >> 12));
2521 WREG32(VM_CONTEXT0_CNTL2, 0);
2522 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2523 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2529 /* empty context1-15 */
2530 /* set vm size, must be a multiple of 4 */
2531 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2532 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2533 /* Assign the pt base to something valid for now; the pts used for
2534 * the VMs are determined by the application and setup and assigned
2535 * on the fly in the vm part of radeon_gart.c
2537 for (i = 1; i < 16; i++) {
2539 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2540 rdev->gart.table_addr >> 12);
2542 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2543 rdev->gart.table_addr >> 12);
2546 /* enable context1-15 */
2547 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2548 (u32)(rdev->dummy_page.addr >> 12));
2549 WREG32(VM_CONTEXT1_CNTL2, 4);
2550 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
2551 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2552 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2553 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2554 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2555 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2556 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2557 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2558 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2559 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2560 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2561 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2562 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
2564 si_pcie_gart_tlb_flush(rdev);
2565 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2566 (unsigned)(rdev->mc.gtt_size >> 20),
2567 (unsigned long long)rdev->gart.table_addr);
2568 rdev->gart.ready = true;
2572 static void si_pcie_gart_disable(struct radeon_device *rdev)
2574 /* Disable all tables */
2575 WREG32(VM_CONTEXT0_CNTL, 0);
2576 WREG32(VM_CONTEXT1_CNTL, 0);
2577 /* Setup TLB control */
2578 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2579 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2580 /* Setup L2 cache */
2581 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2582 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2583 EFFECTIVE_L2_QUEUE_SIZE(7) |
2584 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2585 WREG32(VM_L2_CNTL2, 0);
2586 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2587 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2588 radeon_gart_table_vram_unpin(rdev);
2591 static void si_pcie_gart_fini(struct radeon_device *rdev)
2593 si_pcie_gart_disable(rdev);
2594 radeon_gart_table_vram_free(rdev);
2595 radeon_gart_fini(rdev);
2599 static bool si_vm_reg_valid(u32 reg)
2601 /* context regs are fine */
2605 /* check config regs */
2607 case GRBM_GFX_INDEX:
2608 case CP_STRMOUT_CNTL:
2609 case VGT_VTX_VECT_EJECT_REG:
2610 case VGT_CACHE_INVALIDATION:
2611 case VGT_ESGS_RING_SIZE:
2612 case VGT_GSVS_RING_SIZE:
2613 case VGT_GS_VERTEX_REUSE:
2614 case VGT_PRIMITIVE_TYPE:
2615 case VGT_INDEX_TYPE:
2616 case VGT_NUM_INDICES:
2617 case VGT_NUM_INSTANCES:
2618 case VGT_TF_RING_SIZE:
2619 case VGT_HS_OFFCHIP_PARAM:
2620 case VGT_TF_MEMORY_BASE:
2622 case PA_SU_LINE_STIPPLE_VALUE:
2623 case PA_SC_LINE_STIPPLE_STATE:
2626 case SPI_STATIC_THREAD_MGMT_1:
2627 case SPI_STATIC_THREAD_MGMT_2:
2628 case SPI_STATIC_THREAD_MGMT_3:
2629 case SPI_PS_MAX_WAVE_ID:
2630 case SPI_CONFIG_CNTL:
2631 case SPI_CONFIG_CNTL_1:
2635 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2640 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2641 u32 *ib, struct radeon_cs_packet *pkt)
2643 switch (pkt->opcode) {
2645 case PACKET3_SET_BASE:
2646 case PACKET3_SET_CE_DE_COUNTERS:
2647 case PACKET3_LOAD_CONST_RAM:
2648 case PACKET3_WRITE_CONST_RAM:
2649 case PACKET3_WRITE_CONST_RAM_OFFSET:
2650 case PACKET3_DUMP_CONST_RAM:
2651 case PACKET3_INCREMENT_CE_COUNTER:
2652 case PACKET3_WAIT_ON_DE_COUNTER:
2653 case PACKET3_CE_WRITE:
2656 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2662 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2663 u32 *ib, struct radeon_cs_packet *pkt)
2665 u32 idx = pkt->idx + 1;
2666 u32 idx_value = ib[idx];
2667 u32 start_reg, end_reg, reg, i;
2670 switch (pkt->opcode) {
2672 case PACKET3_SET_BASE:
2673 case PACKET3_CLEAR_STATE:
2674 case PACKET3_INDEX_BUFFER_SIZE:
2675 case PACKET3_DISPATCH_DIRECT:
2676 case PACKET3_DISPATCH_INDIRECT:
2677 case PACKET3_ALLOC_GDS:
2678 case PACKET3_WRITE_GDS_RAM:
2679 case PACKET3_ATOMIC_GDS:
2680 case PACKET3_ATOMIC:
2681 case PACKET3_OCCLUSION_QUERY:
2682 case PACKET3_SET_PREDICATION:
2683 case PACKET3_COND_EXEC:
2684 case PACKET3_PRED_EXEC:
2685 case PACKET3_DRAW_INDIRECT:
2686 case PACKET3_DRAW_INDEX_INDIRECT:
2687 case PACKET3_INDEX_BASE:
2688 case PACKET3_DRAW_INDEX_2:
2689 case PACKET3_CONTEXT_CONTROL:
2690 case PACKET3_INDEX_TYPE:
2691 case PACKET3_DRAW_INDIRECT_MULTI:
2692 case PACKET3_DRAW_INDEX_AUTO:
2693 case PACKET3_DRAW_INDEX_IMMD:
2694 case PACKET3_NUM_INSTANCES:
2695 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2696 case PACKET3_STRMOUT_BUFFER_UPDATE:
2697 case PACKET3_DRAW_INDEX_OFFSET_2:
2698 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2699 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2700 case PACKET3_MPEG_INDEX:
2701 case PACKET3_WAIT_REG_MEM:
2702 case PACKET3_MEM_WRITE:
2703 case PACKET3_PFP_SYNC_ME:
2704 case PACKET3_SURFACE_SYNC:
2705 case PACKET3_EVENT_WRITE:
2706 case PACKET3_EVENT_WRITE_EOP:
2707 case PACKET3_EVENT_WRITE_EOS:
2708 case PACKET3_SET_CONTEXT_REG:
2709 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2710 case PACKET3_SET_SH_REG:
2711 case PACKET3_SET_SH_REG_OFFSET:
2712 case PACKET3_INCREMENT_DE_COUNTER:
2713 case PACKET3_WAIT_ON_CE_COUNTER:
2714 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2715 case PACKET3_ME_WRITE:
2717 case PACKET3_COPY_DATA:
2718 if ((idx_value & 0xf00) == 0) {
2719 reg = ib[idx + 3] * 4;
2720 if (!si_vm_reg_valid(reg))
2724 case PACKET3_WRITE_DATA:
2725 if ((idx_value & 0xf00) == 0) {
2726 start_reg = ib[idx + 1] * 4;
2727 if (idx_value & 0x10000) {
2728 if (!si_vm_reg_valid(start_reg))
2731 for (i = 0; i < (pkt->count - 2); i++) {
2732 reg = start_reg + (4 * i);
2733 if (!si_vm_reg_valid(reg))
2739 case PACKET3_COND_WRITE:
2740 if (idx_value & 0x100) {
2741 reg = ib[idx + 5] * 4;
2742 if (!si_vm_reg_valid(reg))
2746 case PACKET3_COPY_DW:
2747 if (idx_value & 0x2) {
2748 reg = ib[idx + 3] * 4;
2749 if (!si_vm_reg_valid(reg))
2753 case PACKET3_SET_CONFIG_REG:
2754 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2755 end_reg = 4 * pkt->count + start_reg - 4;
2756 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2757 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2758 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2759 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2762 for (i = 0; i < pkt->count; i++) {
2763 reg = start_reg + (4 * i);
2764 if (!si_vm_reg_valid(reg))
2768 case PACKET3_CP_DMA:
2769 command = ib[idx + 4];
2771 if (command & PACKET3_CP_DMA_CMD_SAS) {
2772 /* src address space is register */
2773 if (((info & 0x60000000) >> 29) == 0) {
2774 start_reg = idx_value << 2;
2775 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2777 if (!si_vm_reg_valid(reg)) {
2778 DRM_ERROR("CP DMA Bad SRC register\n");
2782 for (i = 0; i < (command & 0x1fffff); i++) {
2783 reg = start_reg + (4 * i);
2784 if (!si_vm_reg_valid(reg)) {
2785 DRM_ERROR("CP DMA Bad SRC register\n");
2792 if (command & PACKET3_CP_DMA_CMD_DAS) {
2793 /* dst address space is register */
2794 if (((info & 0x00300000) >> 20) == 0) {
2795 start_reg = ib[idx + 2];
2796 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2798 if (!si_vm_reg_valid(reg)) {
2799 DRM_ERROR("CP DMA Bad DST register\n");
2803 for (i = 0; i < (command & 0x1fffff); i++) {
2804 reg = start_reg + (4 * i);
2805 if (!si_vm_reg_valid(reg)) {
2806 DRM_ERROR("CP DMA Bad DST register\n");
2815 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2821 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2822 u32 *ib, struct radeon_cs_packet *pkt)
2824 u32 idx = pkt->idx + 1;
2825 u32 idx_value = ib[idx];
2826 u32 start_reg, reg, i;
2828 switch (pkt->opcode) {
2830 case PACKET3_SET_BASE:
2831 case PACKET3_CLEAR_STATE:
2832 case PACKET3_DISPATCH_DIRECT:
2833 case PACKET3_DISPATCH_INDIRECT:
2834 case PACKET3_ALLOC_GDS:
2835 case PACKET3_WRITE_GDS_RAM:
2836 case PACKET3_ATOMIC_GDS:
2837 case PACKET3_ATOMIC:
2838 case PACKET3_OCCLUSION_QUERY:
2839 case PACKET3_SET_PREDICATION:
2840 case PACKET3_COND_EXEC:
2841 case PACKET3_PRED_EXEC:
2842 case PACKET3_CONTEXT_CONTROL:
2843 case PACKET3_STRMOUT_BUFFER_UPDATE:
2844 case PACKET3_WAIT_REG_MEM:
2845 case PACKET3_MEM_WRITE:
2846 case PACKET3_PFP_SYNC_ME:
2847 case PACKET3_SURFACE_SYNC:
2848 case PACKET3_EVENT_WRITE:
2849 case PACKET3_EVENT_WRITE_EOP:
2850 case PACKET3_EVENT_WRITE_EOS:
2851 case PACKET3_SET_CONTEXT_REG:
2852 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2853 case PACKET3_SET_SH_REG:
2854 case PACKET3_SET_SH_REG_OFFSET:
2855 case PACKET3_INCREMENT_DE_COUNTER:
2856 case PACKET3_WAIT_ON_CE_COUNTER:
2857 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2858 case PACKET3_ME_WRITE:
2860 case PACKET3_COPY_DATA:
2861 if ((idx_value & 0xf00) == 0) {
2862 reg = ib[idx + 3] * 4;
2863 if (!si_vm_reg_valid(reg))
2867 case PACKET3_WRITE_DATA:
2868 if ((idx_value & 0xf00) == 0) {
2869 start_reg = ib[idx + 1] * 4;
2870 if (idx_value & 0x10000) {
2871 if (!si_vm_reg_valid(start_reg))
2874 for (i = 0; i < (pkt->count - 2); i++) {
2875 reg = start_reg + (4 * i);
2876 if (!si_vm_reg_valid(reg))
2882 case PACKET3_COND_WRITE:
2883 if (idx_value & 0x100) {
2884 reg = ib[idx + 5] * 4;
2885 if (!si_vm_reg_valid(reg))
2889 case PACKET3_COPY_DW:
2890 if (idx_value & 0x2) {
2891 reg = ib[idx + 3] * 4;
2892 if (!si_vm_reg_valid(reg))
2897 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2903 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2907 struct radeon_cs_packet pkt;
2911 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2912 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2916 dev_err(rdev->dev, "Packet0 not allowed!\n");
2923 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2924 if (ib->is_const_ib)
2925 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2928 case RADEON_RING_TYPE_GFX_INDEX:
2929 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2931 case CAYMAN_RING_TYPE_CP1_INDEX:
2932 case CAYMAN_RING_TYPE_CP2_INDEX:
2933 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2936 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
2941 idx += pkt.count + 2;
2944 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2950 } while (idx < ib->length_dw);
2958 int si_vm_init(struct radeon_device *rdev)
2961 rdev->vm_manager.nvm = 16;
2962 /* base offset of vram pages */
2963 rdev->vm_manager.vram_base_offset = 0;
2968 void si_vm_fini(struct radeon_device *rdev)
2973 * si_vm_set_page - update the page tables using the CP
2975 * @rdev: radeon_device pointer
2976 * @pe: addr of the page entry
2977 * @addr: dst addr to write into pe
2978 * @count: number of page entries to update
2979 * @incr: increase next addr by incr bytes
2980 * @flags: access flags
2982 * Update the page tables using the CP (cayman-si).
2984 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2985 uint64_t addr, unsigned count,
2986 uint32_t incr, uint32_t flags)
2988 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
2989 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2993 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2995 ndw = 2 + count * 2;
2999 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
3000 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3001 WRITE_DATA_DST_SEL(1)));
3002 radeon_ring_write(ring, pe);
3003 radeon_ring_write(ring, upper_32_bits(pe));
3004 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3005 if (flags & RADEON_VM_PAGE_SYSTEM) {
3006 value = radeon_vm_map_gart(rdev, addr);
3007 value &= 0xFFFFFFFFFFFFF000ULL;
3008 } else if (flags & RADEON_VM_PAGE_VALID) {
3014 value |= r600_flags;
3015 radeon_ring_write(ring, value);
3016 radeon_ring_write(ring, upper_32_bits(value));
3021 if (flags & RADEON_VM_PAGE_SYSTEM) {
3027 /* for non-physically contiguous pages (system) */
3028 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw));
3029 radeon_ring_write(ring, pe);
3030 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3031 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3032 if (flags & RADEON_VM_PAGE_SYSTEM) {
3033 value = radeon_vm_map_gart(rdev, addr);
3034 value &= 0xFFFFFFFFFFFFF000ULL;
3035 } else if (flags & RADEON_VM_PAGE_VALID) {
3041 value |= r600_flags;
3042 radeon_ring_write(ring, value);
3043 radeon_ring_write(ring, upper_32_bits(value));
3052 if (flags & RADEON_VM_PAGE_VALID)
3056 /* for physically contiguous pages (vram) */
3057 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw));
3058 radeon_ring_write(ring, pe); /* dst addr */
3059 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3060 radeon_ring_write(ring, r600_flags); /* mask */
3061 radeon_ring_write(ring, 0);
3062 radeon_ring_write(ring, value); /* value */
3063 radeon_ring_write(ring, upper_32_bits(value));
3064 radeon_ring_write(ring, incr); /* increment size */
3065 radeon_ring_write(ring, 0);
3067 addr += (ndw / 2) * incr;
3074 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3076 struct radeon_ring *ring = &rdev->ring[ridx];
3081 /* write new base address */
3082 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3083 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3084 WRITE_DATA_DST_SEL(0)));
3087 radeon_ring_write(ring,
3088 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
3090 radeon_ring_write(ring,
3091 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
3093 radeon_ring_write(ring, 0);
3094 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3096 /* flush hdp cache */
3097 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3098 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3099 WRITE_DATA_DST_SEL(0)));
3100 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3101 radeon_ring_write(ring, 0);
3102 radeon_ring_write(ring, 0x1);
3104 /* bits 0-15 are the VM contexts0-15 */
3105 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3106 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3107 WRITE_DATA_DST_SEL(0)));
3108 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3109 radeon_ring_write(ring, 0);
3110 radeon_ring_write(ring, 1 << vm->id);
3112 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3113 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3114 radeon_ring_write(ring, 0x0);
3117 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3119 struct radeon_ring *ring = &rdev->ring[ridx];
3124 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3126 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3128 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3130 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3132 /* flush hdp cache */
3133 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3134 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3135 radeon_ring_write(ring, 1);
3137 /* bits 0-7 are the VM contexts0-7 */
3138 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3139 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3140 radeon_ring_write(ring, 1 << vm->id);
3146 void si_rlc_fini(struct radeon_device *rdev)
3150 /* save restore block */
3151 if (rdev->rlc.save_restore_obj) {
3152 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3153 if (unlikely(r != 0))
3154 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3155 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3156 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3158 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3159 rdev->rlc.save_restore_obj = NULL;
3162 /* clear state block */
3163 if (rdev->rlc.clear_state_obj) {
3164 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3165 if (unlikely(r != 0))
3166 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3167 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3168 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3170 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3171 rdev->rlc.clear_state_obj = NULL;
3175 int si_rlc_init(struct radeon_device *rdev)
3179 /* save restore block */
3180 if (rdev->rlc.save_restore_obj == NULL) {
3181 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3182 RADEON_GEM_DOMAIN_VRAM, NULL,
3183 &rdev->rlc.save_restore_obj);
3185 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3190 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3191 if (unlikely(r != 0)) {
3195 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3196 &rdev->rlc.save_restore_gpu_addr);
3197 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3199 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3204 /* clear state block */
3205 if (rdev->rlc.clear_state_obj == NULL) {
3206 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3207 RADEON_GEM_DOMAIN_VRAM, NULL,
3208 &rdev->rlc.clear_state_obj);
3210 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3215 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3216 if (unlikely(r != 0)) {
3220 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3221 &rdev->rlc.clear_state_gpu_addr);
3222 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3224 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3232 static void si_rlc_stop(struct radeon_device *rdev)
3234 WREG32(RLC_CNTL, 0);
3237 static void si_rlc_start(struct radeon_device *rdev)
3239 WREG32(RLC_CNTL, RLC_ENABLE);
3242 static int si_rlc_resume(struct radeon_device *rdev)
3245 const __be32 *fw_data;
3252 WREG32(RLC_RL_BASE, 0);
3253 WREG32(RLC_RL_SIZE, 0);
3254 WREG32(RLC_LB_CNTL, 0);
3255 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3256 WREG32(RLC_LB_CNTR_INIT, 0);
3258 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3259 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3261 WREG32(RLC_MC_CNTL, 0);
3262 WREG32(RLC_UCODE_CNTL, 0);
3264 fw_data = (const __be32 *)rdev->rlc_fw->data;
3265 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3266 WREG32(RLC_UCODE_ADDR, i);
3267 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3269 WREG32(RLC_UCODE_ADDR, 0);
3276 static void si_enable_interrupts(struct radeon_device *rdev)
3278 u32 ih_cntl = RREG32(IH_CNTL);
3279 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3281 ih_cntl |= ENABLE_INTR;
3282 ih_rb_cntl |= IH_RB_ENABLE;
3283 WREG32(IH_CNTL, ih_cntl);
3284 WREG32(IH_RB_CNTL, ih_rb_cntl);
3285 rdev->ih.enabled = true;
3288 static void si_disable_interrupts(struct radeon_device *rdev)
3290 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3291 u32 ih_cntl = RREG32(IH_CNTL);
3293 ih_rb_cntl &= ~IH_RB_ENABLE;
3294 ih_cntl &= ~ENABLE_INTR;
3295 WREG32(IH_RB_CNTL, ih_rb_cntl);
3296 WREG32(IH_CNTL, ih_cntl);
3297 /* set rptr, wptr to 0 */
3298 WREG32(IH_RB_RPTR, 0);
3299 WREG32(IH_RB_WPTR, 0);
3300 rdev->ih.enabled = false;
3304 static void si_disable_interrupt_state(struct radeon_device *rdev)
3308 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3309 WREG32(CP_INT_CNTL_RING1, 0);
3310 WREG32(CP_INT_CNTL_RING2, 0);
3311 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3312 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3313 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3314 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
3315 WREG32(GRBM_INT_CNTL, 0);
3316 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3317 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3318 if (rdev->num_crtc >= 4) {
3319 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3320 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3322 if (rdev->num_crtc >= 6) {
3323 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3324 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3327 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3328 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3329 if (rdev->num_crtc >= 4) {
3330 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3331 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3333 if (rdev->num_crtc >= 6) {
3334 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3335 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3338 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3340 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3341 WREG32(DC_HPD1_INT_CONTROL, tmp);
3342 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3343 WREG32(DC_HPD2_INT_CONTROL, tmp);
3344 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3345 WREG32(DC_HPD3_INT_CONTROL, tmp);
3346 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3347 WREG32(DC_HPD4_INT_CONTROL, tmp);
3348 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3349 WREG32(DC_HPD5_INT_CONTROL, tmp);
3350 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3351 WREG32(DC_HPD6_INT_CONTROL, tmp);
3355 static int si_irq_init(struct radeon_device *rdev)
3359 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3362 ret = r600_ih_ring_alloc(rdev);
3367 si_disable_interrupts(rdev);
3370 ret = si_rlc_resume(rdev);
3372 r600_ih_ring_fini(rdev);
3376 /* setup interrupt control */
3377 /* set dummy read address to ring address */
3378 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3379 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3380 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3381 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3383 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3384 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3385 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3386 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3388 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3389 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3391 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3392 IH_WPTR_OVERFLOW_CLEAR |
3395 if (rdev->wb.enabled)
3396 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3398 /* set the writeback address whether it's enabled or not */
3399 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3400 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3402 WREG32(IH_RB_CNTL, ih_rb_cntl);
3404 /* set rptr, wptr to 0 */
3405 WREG32(IH_RB_RPTR, 0);
3406 WREG32(IH_RB_WPTR, 0);
3408 /* Default settings for IH_CNTL (disabled at first) */
3409 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3410 /* RPTR_REARM only works if msi's are enabled */
3411 if (rdev->msi_enabled)
3412 ih_cntl |= RPTR_REARM;
3413 WREG32(IH_CNTL, ih_cntl);
3415 /* force the active interrupt state to all disabled */
3416 si_disable_interrupt_state(rdev);
3418 pci_enable_busmaster(rdev->dev);
3421 si_enable_interrupts(rdev);
3426 int si_irq_set(struct radeon_device *rdev)
3428 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3429 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3430 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3431 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3432 u32 grbm_int_cntl = 0;
3433 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3434 u32 dma_cntl, dma_cntl1;
3436 if (!rdev->irq.installed) {
3437 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n");
3440 /* don't enable anything if the ih is disabled */
3441 if (!rdev->ih.enabled) {
3442 si_disable_interrupts(rdev);
3443 /* force the active interrupt state to all disabled */
3444 si_disable_interrupt_state(rdev);
3448 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3449 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3450 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3451 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3452 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3453 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3455 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3456 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3458 /* enable CP interrupts on all rings */
3459 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3460 DRM_DEBUG("si_irq_set: sw int gfx\n");
3461 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3463 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
3464 DRM_DEBUG("si_irq_set: sw int cp1\n");
3465 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3467 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
3468 DRM_DEBUG("si_irq_set: sw int cp2\n");
3469 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3471 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3472 DRM_DEBUG("si_irq_set: sw int dma\n");
3473 dma_cntl |= TRAP_ENABLE;
3476 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3477 DRM_DEBUG("si_irq_set: sw int dma1\n");
3478 dma_cntl1 |= TRAP_ENABLE;
3480 if (rdev->irq.crtc_vblank_int[0] ||
3481 atomic_read(&rdev->irq.pflip[0])) {
3482 DRM_DEBUG("si_irq_set: vblank 0\n");
3483 crtc1 |= VBLANK_INT_MASK;
3485 if (rdev->irq.crtc_vblank_int[1] ||
3486 atomic_read(&rdev->irq.pflip[1])) {
3487 DRM_DEBUG("si_irq_set: vblank 1\n");
3488 crtc2 |= VBLANK_INT_MASK;
3490 if (rdev->irq.crtc_vblank_int[2] ||
3491 atomic_read(&rdev->irq.pflip[2])) {
3492 DRM_DEBUG("si_irq_set: vblank 2\n");
3493 crtc3 |= VBLANK_INT_MASK;
3495 if (rdev->irq.crtc_vblank_int[3] ||
3496 atomic_read(&rdev->irq.pflip[3])) {
3497 DRM_DEBUG("si_irq_set: vblank 3\n");
3498 crtc4 |= VBLANK_INT_MASK;
3500 if (rdev->irq.crtc_vblank_int[4] ||
3501 atomic_read(&rdev->irq.pflip[4])) {
3502 DRM_DEBUG("si_irq_set: vblank 4\n");
3503 crtc5 |= VBLANK_INT_MASK;
3505 if (rdev->irq.crtc_vblank_int[5] ||
3506 atomic_read(&rdev->irq.pflip[5])) {
3507 DRM_DEBUG("si_irq_set: vblank 5\n");
3508 crtc6 |= VBLANK_INT_MASK;
3510 if (rdev->irq.hpd[0]) {
3511 DRM_DEBUG("si_irq_set: hpd 1\n");
3512 hpd1 |= DC_HPDx_INT_EN;
3514 if (rdev->irq.hpd[1]) {
3515 DRM_DEBUG("si_irq_set: hpd 2\n");
3516 hpd2 |= DC_HPDx_INT_EN;
3518 if (rdev->irq.hpd[2]) {
3519 DRM_DEBUG("si_irq_set: hpd 3\n");
3520 hpd3 |= DC_HPDx_INT_EN;
3522 if (rdev->irq.hpd[3]) {
3523 DRM_DEBUG("si_irq_set: hpd 4\n");
3524 hpd4 |= DC_HPDx_INT_EN;
3526 if (rdev->irq.hpd[4]) {
3527 DRM_DEBUG("si_irq_set: hpd 5\n");
3528 hpd5 |= DC_HPDx_INT_EN;
3530 if (rdev->irq.hpd[5]) {
3531 DRM_DEBUG("si_irq_set: hpd 6\n");
3532 hpd6 |= DC_HPDx_INT_EN;
3535 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3536 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3537 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3539 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3540 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3542 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3544 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3545 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3546 if (rdev->num_crtc >= 4) {
3547 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3548 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3550 if (rdev->num_crtc >= 6) {
3551 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3552 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3555 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3557 if (rdev->num_crtc >= 4) {
3558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3561 if (rdev->num_crtc >= 6) {
3562 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3563 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3566 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3567 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3568 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3569 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3570 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3571 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3576 static inline void si_irq_ack(struct radeon_device *rdev)
3580 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3581 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3582 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3583 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3584 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3585 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3586 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3587 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3588 if (rdev->num_crtc >= 4) {
3589 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3590 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3592 if (rdev->num_crtc >= 6) {
3593 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3594 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3597 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3598 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3599 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3600 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3602 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3603 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3604 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3605 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3606 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3607 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3608 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3610 if (rdev->num_crtc >= 4) {
3611 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3612 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3613 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3614 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3615 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3616 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3617 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3618 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3619 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3621 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3622 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3625 if (rdev->num_crtc >= 6) {
3626 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3627 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3628 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3630 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3631 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3632 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3633 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3634 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3635 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3636 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3637 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3640 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3641 tmp = RREG32(DC_HPD1_INT_CONTROL);
3642 tmp |= DC_HPDx_INT_ACK;
3643 WREG32(DC_HPD1_INT_CONTROL, tmp);
3645 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3646 tmp = RREG32(DC_HPD2_INT_CONTROL);
3647 tmp |= DC_HPDx_INT_ACK;
3648 WREG32(DC_HPD2_INT_CONTROL, tmp);
3650 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3651 tmp = RREG32(DC_HPD3_INT_CONTROL);
3652 tmp |= DC_HPDx_INT_ACK;
3653 WREG32(DC_HPD3_INT_CONTROL, tmp);
3655 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3656 tmp = RREG32(DC_HPD4_INT_CONTROL);
3657 tmp |= DC_HPDx_INT_ACK;
3658 WREG32(DC_HPD4_INT_CONTROL, tmp);
3660 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3661 tmp = RREG32(DC_HPD5_INT_CONTROL);
3662 tmp |= DC_HPDx_INT_ACK;
3663 WREG32(DC_HPD5_INT_CONTROL, tmp);
3665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3666 tmp = RREG32(DC_HPD5_INT_CONTROL);
3667 tmp |= DC_HPDx_INT_ACK;
3668 WREG32(DC_HPD6_INT_CONTROL, tmp);
3672 static void si_irq_disable(struct radeon_device *rdev)
3674 si_disable_interrupts(rdev);
3675 /* Wait and acknowledge irq */
3678 si_disable_interrupt_state(rdev);
3681 static void si_irq_suspend(struct radeon_device *rdev)
3683 si_irq_disable(rdev);
3687 static void si_irq_fini(struct radeon_device *rdev)
3689 si_irq_suspend(rdev);
3690 r600_ih_ring_fini(rdev);
3693 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3697 if (rdev->wb.enabled)
3698 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3700 wptr = RREG32(IH_RB_WPTR);
3702 if (wptr & RB_OVERFLOW) {
3703 /* When a ring buffer overflow happen start parsing interrupt
3704 * from the last not overwritten vector (wptr + 16). Hopefully
3705 * this should allow us to catchup.
3707 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3708 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3709 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3710 tmp = RREG32(IH_RB_CNTL);
3711 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3712 WREG32(IH_RB_CNTL, tmp);
3714 return (wptr & rdev->ih.ptr_mask);
3718 * Each IV ring entry is 128 bits:
3719 * [7:0] - interrupt source id
3721 * [59:32] - interrupt source data
3722 * [63:60] - reserved
3725 * [127:80] - reserved
3727 irqreturn_t si_irq_process(struct radeon_device *rdev)
3731 u32 src_id, src_data, ring_id;
3733 bool queue_hotplug = false;
3735 if (!rdev->ih.enabled || rdev->shutdown)
3738 wptr = si_get_ih_wptr(rdev);
3741 /* is somebody else already processing irqs? */
3742 if (atomic_xchg(&rdev->ih.lock, 1))
3745 rptr = rdev->ih.rptr;
3746 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3748 /* Order reading of wptr vs. reading of IH ring data */
3751 /* display interrupts */
3754 while (rptr != wptr) {
3755 /* wptr/rptr are in bytes! */
3756 ring_index = rptr / 4;
3757 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3758 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3759 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3762 case 1: /* D1 vblank/vline */
3764 case 0: /* D1 vblank */
3765 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3766 if (rdev->irq.crtc_vblank_int[0]) {
3767 drm_handle_vblank(rdev->ddev, 0);
3768 rdev->pm.vblank_sync = true;
3769 DRM_WAKEUP(&rdev->irq.vblank_queue);
3771 if (atomic_read(&rdev->irq.pflip[0]))
3772 radeon_crtc_handle_flip(rdev, 0);
3773 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3774 DRM_DEBUG("IH: D1 vblank\n");
3777 case 1: /* D1 vline */
3778 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3779 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3780 DRM_DEBUG("IH: D1 vline\n");
3784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3788 case 2: /* D2 vblank/vline */
3790 case 0: /* D2 vblank */
3791 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3792 if (rdev->irq.crtc_vblank_int[1]) {
3793 drm_handle_vblank(rdev->ddev, 1);
3794 rdev->pm.vblank_sync = true;
3795 DRM_WAKEUP(&rdev->irq.vblank_queue);
3797 if (atomic_read(&rdev->irq.pflip[1]))
3798 radeon_crtc_handle_flip(rdev, 1);
3799 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3800 DRM_DEBUG("IH: D2 vblank\n");
3803 case 1: /* D2 vline */
3804 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3805 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3806 DRM_DEBUG("IH: D2 vline\n");
3810 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3814 case 3: /* D3 vblank/vline */
3816 case 0: /* D3 vblank */
3817 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3818 if (rdev->irq.crtc_vblank_int[2]) {
3819 drm_handle_vblank(rdev->ddev, 2);
3820 rdev->pm.vblank_sync = true;
3821 DRM_WAKEUP(&rdev->irq.vblank_queue);
3823 if (atomic_read(&rdev->irq.pflip[2]))
3824 radeon_crtc_handle_flip(rdev, 2);
3825 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3826 DRM_DEBUG("IH: D3 vblank\n");
3829 case 1: /* D3 vline */
3830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3831 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3832 DRM_DEBUG("IH: D3 vline\n");
3836 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3840 case 4: /* D4 vblank/vline */
3842 case 0: /* D4 vblank */
3843 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3844 if (rdev->irq.crtc_vblank_int[3]) {
3845 drm_handle_vblank(rdev->ddev, 3);
3846 rdev->pm.vblank_sync = true;
3847 DRM_WAKEUP(&rdev->irq.vblank_queue);
3849 if (atomic_read(&rdev->irq.pflip[3]))
3850 radeon_crtc_handle_flip(rdev, 3);
3851 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3852 DRM_DEBUG("IH: D4 vblank\n");
3855 case 1: /* D4 vline */
3856 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3857 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3858 DRM_DEBUG("IH: D4 vline\n");
3862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3866 case 5: /* D5 vblank/vline */
3868 case 0: /* D5 vblank */
3869 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3870 if (rdev->irq.crtc_vblank_int[4]) {
3871 drm_handle_vblank(rdev->ddev, 4);
3872 rdev->pm.vblank_sync = true;
3873 DRM_WAKEUP(&rdev->irq.vblank_queue);
3875 if (atomic_read(&rdev->irq.pflip[4]))
3876 radeon_crtc_handle_flip(rdev, 4);
3877 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3878 DRM_DEBUG("IH: D5 vblank\n");
3881 case 1: /* D5 vline */
3882 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3883 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3884 DRM_DEBUG("IH: D5 vline\n");
3888 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3892 case 6: /* D6 vblank/vline */
3894 case 0: /* D6 vblank */
3895 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3896 if (rdev->irq.crtc_vblank_int[5]) {
3897 drm_handle_vblank(rdev->ddev, 5);
3898 rdev->pm.vblank_sync = true;
3899 DRM_WAKEUP(&rdev->irq.vblank_queue);
3901 if (atomic_read(&rdev->irq.pflip[5]))
3902 radeon_crtc_handle_flip(rdev, 5);
3903 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3904 DRM_DEBUG("IH: D6 vblank\n");
3907 case 1: /* D6 vline */
3908 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3909 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3910 DRM_DEBUG("IH: D6 vline\n");
3914 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3918 case 42: /* HPD hotplug */
3921 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3922 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3923 queue_hotplug = true;
3924 DRM_DEBUG("IH: HPD1\n");
3928 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3929 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3930 queue_hotplug = true;
3931 DRM_DEBUG("IH: HPD2\n");
3935 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3936 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3937 queue_hotplug = true;
3938 DRM_DEBUG("IH: HPD3\n");
3942 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3943 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3944 queue_hotplug = true;
3945 DRM_DEBUG("IH: HPD4\n");
3949 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3950 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3951 queue_hotplug = true;
3952 DRM_DEBUG("IH: HPD5\n");
3956 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3957 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3958 queue_hotplug = true;
3959 DRM_DEBUG("IH: HPD6\n");
3963 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3969 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3970 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3971 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3972 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3973 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3974 /* reset addr and status */
3975 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3977 case 176: /* RINGID0 CP_INT */
3978 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3980 case 177: /* RINGID1 CP_INT */
3981 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3983 case 178: /* RINGID2 CP_INT */
3984 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3986 case 181: /* CP EOP event */
3987 DRM_DEBUG("IH: CP EOP\n");
3990 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3993 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3996 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4000 case 224: /* DMA trap event */
4001 DRM_DEBUG("IH: DMA trap\n");
4002 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4004 case 233: /* GUI IDLE */
4005 DRM_DEBUG("IH: GUI idle\n");
4007 case 244: /* DMA trap event */
4008 DRM_DEBUG("IH: DMA1 trap\n");
4009 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4012 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4016 /* wptr/rptr are in bytes! */
4018 rptr &= rdev->ih.ptr_mask;
4021 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
4022 rdev->ih.rptr = rptr;
4023 WREG32(IH_RB_RPTR, rdev->ih.rptr);
4024 atomic_set(&rdev->ih.lock, 0);
4026 /* make sure wptr hasn't changed while processing */
4027 wptr = si_get_ih_wptr(rdev);
4035 * si_copy_dma - copy pages using the DMA engine
4037 * @rdev: radeon_device pointer
4038 * @src_offset: src GPU address
4039 * @dst_offset: dst GPU address
4040 * @num_gpu_pages: number of GPU pages to xfer
4041 * @fence: radeon fence object
4043 * Copy GPU paging using the DMA engine (SI).
4044 * Used by the radeon ttm implementation to move pages if
4045 * registered as the asic copy callback.
4047 int si_copy_dma(struct radeon_device *rdev,
4048 uint64_t src_offset, uint64_t dst_offset,
4049 unsigned num_gpu_pages,
4050 struct radeon_fence **fence)
4052 struct radeon_semaphore *sem = NULL;
4053 int ring_index = rdev->asic->copy.dma_ring_index;
4054 struct radeon_ring *ring = &rdev->ring[ring_index];
4055 u32 size_in_bytes, cur_size_in_bytes;
4059 r = radeon_semaphore_create(rdev, &sem);
4061 DRM_ERROR("radeon: moving bo (%d).\n", r);
4065 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4066 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4067 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4069 DRM_ERROR("radeon: moving bo (%d).\n", r);
4070 radeon_semaphore_free(rdev, &sem, NULL);
4074 if (radeon_fence_need_sync(*fence, ring->idx)) {
4075 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4077 radeon_fence_note_sync(*fence, ring->idx);
4079 radeon_semaphore_free(rdev, &sem, NULL);
4082 for (i = 0; i < num_loops; i++) {
4083 cur_size_in_bytes = size_in_bytes;
4084 if (cur_size_in_bytes > 0xFFFFF)
4085 cur_size_in_bytes = 0xFFFFF;
4086 size_in_bytes -= cur_size_in_bytes;
4087 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4088 radeon_ring_write(ring, dst_offset & 0xffffffff);
4089 radeon_ring_write(ring, src_offset & 0xffffffff);
4090 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4091 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4092 src_offset += cur_size_in_bytes;
4093 dst_offset += cur_size_in_bytes;
4096 r = radeon_fence_emit(rdev, fence, ring->idx);
4098 radeon_ring_unlock_undo(rdev, ring);
4102 radeon_ring_unlock_commit(rdev, ring);
4103 radeon_semaphore_free(rdev, &sem, *fence);
4109 * startup/shutdown callbacks
4111 static int si_startup(struct radeon_device *rdev)
4113 struct radeon_ring *ring;
4116 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4117 !rdev->rlc_fw || !rdev->mc_fw) {
4118 r = si_init_microcode(rdev);
4120 DRM_ERROR("Failed to load firmware!\n");
4125 r = si_mc_load_microcode(rdev);
4127 DRM_ERROR("Failed to load MC firmware!\n");
4131 r = r600_vram_scratch_init(rdev);
4135 si_mc_program(rdev);
4136 r = si_pcie_gart_enable(rdev);
4142 r = evergreen_blit_init(rdev);
4144 r600_blit_fini(rdev);
4145 rdev->asic->copy = NULL;
4146 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4149 /* allocate rlc buffers */
4150 r = si_rlc_init(rdev);
4152 DRM_ERROR("Failed to init rlc BOs!\n");
4156 /* allocate wb buffer */
4157 r = radeon_wb_init(rdev);
4161 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4163 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4167 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4169 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4173 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4175 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4179 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4181 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4185 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4187 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4192 r = si_irq_init(rdev);
4194 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4195 radeon_irq_kms_fini(rdev);
4200 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4201 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4202 CP_RB0_RPTR, CP_RB0_WPTR,
4203 0, 0xfffff, RADEON_CP_PACKET2);
4207 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4208 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4209 CP_RB1_RPTR, CP_RB1_WPTR,
4210 0, 0xfffff, RADEON_CP_PACKET2);
4214 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4215 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4216 CP_RB2_RPTR, CP_RB2_WPTR,
4217 0, 0xfffff, RADEON_CP_PACKET2);
4221 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4222 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4223 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4224 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4225 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4229 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4230 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4231 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4232 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4233 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4237 r = si_cp_load_microcode(rdev);
4240 r = si_cp_resume(rdev);
4244 r = cayman_dma_resume(rdev);
4248 r = radeon_ib_pool_init(rdev);
4250 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4254 r = radeon_vm_manager_init(rdev);
4256 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
4263 int si_resume(struct radeon_device *rdev)
4267 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4268 * posting will perform necessary task to bring back GPU into good
4272 atom_asic_init(rdev->mode_info.atom_context);
4274 rdev->accel_working = true;
4275 r = si_startup(rdev);
4277 DRM_ERROR("si startup failed on resume\n");
4278 rdev->accel_working = false;
4286 int si_suspend(struct radeon_device *rdev)
4288 radeon_vm_manager_fini(rdev);
4289 si_cp_enable(rdev, false);
4290 cayman_dma_stop(rdev);
4291 si_irq_suspend(rdev);
4292 radeon_wb_disable(rdev);
4293 si_pcie_gart_disable(rdev);
4297 /* Plan is to move initialization in that function and use
4298 * helper function so that radeon_device_init pretty much
4299 * do nothing more than calling asic specific function. This
4300 * should also allow to remove a bunch of callback function
4303 int si_init(struct radeon_device *rdev)
4305 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4309 if (!radeon_get_bios(rdev)) {
4310 if (ASIC_IS_AVIVO(rdev))
4313 /* Must be an ATOMBIOS */
4314 if (!rdev->is_atom_bios) {
4315 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4318 r = radeon_atombios_init(rdev);
4322 /* Post card if necessary */
4323 if (!radeon_card_posted(rdev)) {
4325 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4328 DRM_INFO("GPU not posted. posting now...\n");
4329 atom_asic_init(rdev->mode_info.atom_context);
4331 /* Initialize scratch registers */
4332 si_scratch_init(rdev);
4333 /* Initialize surface registers */
4334 radeon_surface_init(rdev);
4335 /* Initialize clocks */
4336 radeon_get_clock_info(rdev->ddev);
4339 r = radeon_fence_driver_init(rdev);
4343 /* initialize memory controller */
4344 r = si_mc_init(rdev);
4347 /* Memory manager */
4348 r = radeon_bo_init(rdev);
4352 r = radeon_irq_kms_init(rdev);
4356 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4357 ring->ring_obj = NULL;
4358 r600_ring_init(rdev, ring, 1024 * 1024);
4360 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4361 ring->ring_obj = NULL;
4362 r600_ring_init(rdev, ring, 1024 * 1024);
4364 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4365 ring->ring_obj = NULL;
4366 r600_ring_init(rdev, ring, 1024 * 1024);
4368 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4369 ring->ring_obj = NULL;
4370 r600_ring_init(rdev, ring, 64 * 1024);
4372 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4373 ring->ring_obj = NULL;
4374 r600_ring_init(rdev, ring, 64 * 1024);
4376 rdev->ih.ring_obj = NULL;
4377 r600_ih_ring_init(rdev, 64 * 1024);
4379 r = r600_pcie_gart_init(rdev);
4383 rdev->accel_working = true;
4384 r = si_startup(rdev);
4386 dev_err(rdev->dev, "disabling GPU acceleration\n");
4388 cayman_dma_fini(rdev);
4391 radeon_wb_fini(rdev);
4392 radeon_ib_pool_fini(rdev);
4393 radeon_vm_manager_fini(rdev);
4394 radeon_irq_kms_fini(rdev);
4395 si_pcie_gart_fini(rdev);
4396 rdev->accel_working = false;
4399 /* Don't start up if the MC ucode is missing.
4400 * The default clocks and voltages before the MC ucode
4401 * is loaded are not suffient for advanced operations.
4404 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4411 void si_fini(struct radeon_device *rdev)
4414 r600_blit_fini(rdev);
4417 cayman_dma_fini(rdev);
4420 radeon_wb_fini(rdev);
4421 radeon_vm_manager_fini(rdev);
4422 radeon_ib_pool_fini(rdev);
4423 radeon_irq_kms_fini(rdev);
4424 si_pcie_gart_fini(rdev);
4425 r600_vram_scratch_fini(rdev);
4426 radeon_gem_fini(rdev);
4427 radeon_fence_driver_fini(rdev);
4428 radeon_bo_fini(rdev);
4429 radeon_atombios_fini(rdev);
4430 si_fini_microcode(rdev);
4431 free(rdev->bios, DRM_MEM_DRIVER);
4436 * si_get_gpu_clock - return GPU clock counter snapshot
4438 * @rdev: radeon_device pointer
4440 * Fetches a GPU clock counter snapshot (SI).
4441 * Returns the 64 bit clock counter snapshot.
4443 uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4447 sx_xlock(&rdev->gpu_clock_mutex);
4448 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4449 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4450 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4451 sx_xunlock(&rdev->gpu_clock_mutex);