2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
32 const u32 si_default_state[] =
36 0x00000060, /* DB_RENDER_CONTROL */
37 0x00000000, /* DB_COUNT_CONTROL */
38 0x00000000, /* DB_DEPTH_VIEW */
39 0x0000002a, /* DB_RENDER_OVERRIDE */
40 0x00000000, /* DB_RENDER_OVERRIDE2 */
41 0x00000000, /* DB_HTILE_DATA_BASE */
45 0x00000000, /* DB_DEPTH_BOUNDS_MIN */
46 0x00000000, /* DB_DEPTH_BOUNDS_MAX */
47 0x00000000, /* DB_STENCIL_CLEAR */
48 0x00000000, /* DB_DEPTH_CLEAR */
52 0x00000000, /* DB_DEPTH_INFO */
53 0x00000000, /* DB_Z_INFO */
54 0x00000000, /* DB_STENCIL_INFO */
58 0x00000000, /* PA_SC_WINDOW_OFFSET */
62 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
63 0x00000000, /* PA_SC_CLIPRECT_0_TL */
64 0x20002000, /* PA_SC_CLIPRECT_0_BR */
71 0xaaaaaaaa, /* PA_SC_EDGERULE */
72 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
73 0x0000000f, /* CB_TARGET_MASK */
74 0x0000000f, /* CB_SHADER_MASK */
78 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
79 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
110 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
111 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
115 0x00000000, /* CP_RINGID */
116 0x00000000, /* CP_VMID */
120 0xffffffff, /* VGT_MAX_VTX_INDX */
121 0x00000000, /* VGT_MIN_VTX_INDX */
122 0x00000000, /* VGT_INDX_OFFSET */
123 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
127 0x00000000, /* CB_BLEND_RED */
128 0x00000000, /* CB_BLEND_GREEN */
129 0x00000000, /* CB_BLEND_BLUE */
130 0x00000000, /* CB_BLEND_ALPHA */
134 0x00000000, /* CB_BLEND0_CONTROL */
138 0x00000000, /* DB_DEPTH_CONTROL */
139 0x00000000, /* DB_EQAA */
140 0x00cc0010, /* CB_COLOR_CONTROL */
141 0x00000210, /* DB_SHADER_CONTROL */
142 0x00010000, /* PA_CL_CLIP_CNTL */
143 0x00000004, /* PA_SU_SC_MODE_CNTL */
144 0x00000100, /* PA_CL_VTE_CNTL */
145 0x00000000, /* PA_CL_VS_OUT_CNTL */
146 0x00000000, /* PA_CL_NANINF_CNTL */
147 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
148 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
149 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
155 0x00000000, /* PA_SU_POINT_SIZE */
156 0x00000000, /* PA_SU_POINT_MINMAX */
157 0x00000008, /* PA_SU_LINE_CNTL */
158 0x00000000, /* PA_SC_LINE_STIPPLE */
159 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
160 0x00000000, /* VGT_HOS_CNTL */
171 0x00000000, /* VGT_GS_MODE */
175 0x00000000, /* PA_SC_MODE_CNTL_0 */
176 0x00000000, /* PA_SC_MODE_CNTL_1 */
180 0x00000000, /* VGT_PRIMITIVEID_EN */
184 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
188 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
193 0x00000000, /* VGT_REUSE_OFF */
198 0x00000000, /* VGT_SHADER_STAGES_EN */
202 0x0000aa00, /* DB_ALPHA_TO_MASK */
206 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
215 0x00000000, /* VGT_STRMOUT_CONFIG */
220 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
221 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
222 0x00000000, /* PA_SC_LINE_CNTL */
223 0x00000000, /* PA_SC_AA_CONFIG */
224 0x00000005, /* PA_SU_VTX_CNTL */
225 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
226 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
227 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
228 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
229 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
245 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
250 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
254 const u32 si_default_size = DRM_ARRAY_SIZE(si_default_state);