2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Ethernet media access controller (EMAC)
33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
35 * EMAC is an instance of the Synopsys DesignWare 3504-0
36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_var.h>
64 #include <machine/bus.h>
66 #include <dev/dwc/if_dwc.h>
67 #include <dev/dwc/if_dwcvar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
74 #include <dev/extres/clk/clk.h>
75 #include <dev/extres/hwreset/hwreset.h>
78 #include "if_dwc_if.h"
80 #include "miibus_if.h"
82 #define READ4(_sc, _reg) \
83 bus_read_4((_sc)->res[0], _reg)
84 #define WRITE4(_sc, _reg, _val) \
85 bus_write_4((_sc)->res[0], _reg, _val)
87 #define MAC_RESET_TIMEOUT 100
88 #define WATCHDOG_TIMEOUT_SECS 5
89 #define STATS_HARVEST_INTERVAL 2
91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
96 #define DDESC_TDES0_OWN (1U << 31)
97 #define DDESC_TDES0_TXINT (1U << 30)
98 #define DDESC_TDES0_TXLAST (1U << 29)
99 #define DDESC_TDES0_TXFIRST (1U << 28)
100 #define DDESC_TDES0_TXCRCDIS (1U << 27)
101 #define DDESC_TDES0_TXRINGEND (1U << 21)
102 #define DDESC_TDES0_TXCHAIN (1U << 20)
104 #define DDESC_RDES0_OWN (1U << 31)
105 #define DDESC_RDES0_FL_MASK 0x3fff
106 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */
107 #define DDESC_RDES1_CHAINED (1U << 14)
109 /* Alt descriptor bits. */
110 #define DDESC_CNTL_TXINT (1U << 31)
111 #define DDESC_CNTL_TXLAST (1U << 30)
112 #define DDESC_CNTL_TXFIRST (1U << 29)
113 #define DDESC_CNTL_TXCRCDIS (1U << 26)
114 #define DDESC_CNTL_TXRINGEND (1U << 25)
115 #define DDESC_CNTL_TXCHAIN (1U << 24)
117 #define DDESC_CNTL_CHAINED (1U << 24)
120 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
121 * layout, but the bits in the fields have different meanings.
125 uint32_t tdes0; /* status for alt layout */
126 uint32_t tdes1; /* cntl for alt layout */
127 uint32_t addr; /* pointer to buffer data */
128 uint32_t addr_next; /* link to next descriptor */
132 * The hardware imposes alignment restrictions on various objects involved in
133 * DMA transfers. These values are expressed in bytes (not bits).
135 #define DWC_DESC_RING_ALIGN 2048
137 static struct resource_spec dwc_spec[] = {
138 { SYS_RES_MEMORY, 0, RF_ACTIVE },
139 { SYS_RES_IRQ, 0, RF_ACTIVE },
143 static void dwc_txfinish_locked(struct dwc_softc *sc);
144 static void dwc_rxfinish_locked(struct dwc_softc *sc);
145 static void dwc_stop_locked(struct dwc_softc *sc);
146 static void dwc_setup_rxfilter(struct dwc_softc *sc);
148 static inline uint32_t
149 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
152 return ((curidx + 1) % RX_DESC_COUNT);
155 static inline uint32_t
156 next_txidx(struct dwc_softc *sc, uint32_t curidx)
159 return ((curidx + 1) % TX_DESC_COUNT);
163 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
168 *(bus_addr_t *)arg = segs[0].ds_addr;
171 inline static uint32_t
172 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
178 nidx = next_txidx(sc, idx);
180 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
181 if (paddr == 0 || len == 0) {
185 if (sc->mactype == DWC_GMAC_ALT_DESC)
186 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST
187 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT;
189 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST
190 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT;
194 sc->txdesc_ring[idx].addr = (uint32_t)(paddr);
195 if (sc->mactype == DWC_GMAC_ALT_DESC) {
196 sc->txdesc_ring[idx].tdes0 = 0;
197 sc->txdesc_ring[idx].tdes1 = flags | len;
199 sc->txdesc_ring[idx].tdes0 = flags;
200 sc->txdesc_ring[idx].tdes1 = len;
205 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN;
213 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
215 struct bus_dma_segment seg;
219 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
223 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
229 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
231 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
232 BUS_DMASYNC_PREWRITE);
234 sc->txbuf_map[idx].mbuf = m;
236 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
242 dwc_txstart_locked(struct dwc_softc *sc)
248 DWC_ASSERT_LOCKED(sc);
255 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
262 if (sc->txcount == (TX_DESC_COUNT-1)) {
263 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
267 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
270 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
271 IFQ_DRV_PREPEND(&ifp->if_snd, m);
275 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
280 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
281 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
286 dwc_txstart(struct ifnet *ifp)
288 struct dwc_softc *sc = ifp->if_softc;
291 dwc_txstart_locked(sc);
296 dwc_stop_locked(struct dwc_softc *sc)
301 DWC_ASSERT_LOCKED(sc);
304 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
305 sc->tx_watchdog_count = 0;
306 sc->stats_harvest_count = 0;
308 callout_stop(&sc->dwc_callout);
311 reg = READ4(sc, OPERATION_MODE);
313 WRITE4(sc, OPERATION_MODE, reg);
316 reg = READ4(sc, OPERATION_MODE);
318 WRITE4(sc, OPERATION_MODE, reg);
320 /* Stop transmitters */
321 reg = READ4(sc, MAC_CONFIGURATION);
322 reg &= ~(CONF_TE | CONF_RE);
323 WRITE4(sc, MAC_CONFIGURATION, reg);
326 reg = READ4(sc, OPERATION_MODE);
328 WRITE4(sc, OPERATION_MODE, reg);
331 static void dwc_clear_stats(struct dwc_softc *sc)
335 reg = READ4(sc, MMC_CONTROL);
336 reg |= (MMC_CONTROL_CNTRST);
337 WRITE4(sc, MMC_CONTROL, reg);
341 dwc_harvest_stats(struct dwc_softc *sc)
345 /* We don't need to harvest too often. */
346 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
349 sc->stats_harvest_count = 0;
352 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
353 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
354 if_inc_counter(ifp, IFCOUNTER_IERRORS,
355 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
356 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
357 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
358 READ4(sc, RXLENGTHERROR));
360 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
361 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
362 if_inc_counter(ifp, IFCOUNTER_OERRORS,
363 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
364 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
366 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
367 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
375 struct dwc_softc *sc;
381 DWC_ASSERT_LOCKED(sc);
385 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
389 * Typical tx watchdog. If this fires it indicates that we enqueued
390 * packets for output and never got a txdone interrupt for them. Maybe
391 * it's a missed interrupt somehow, just pretend we got one.
393 if (sc->tx_watchdog_count > 0) {
394 if (--sc->tx_watchdog_count == 0) {
395 dwc_txfinish_locked(sc);
399 /* Gather stats from hardware counters. */
400 dwc_harvest_stats(sc);
402 /* Check the media status. */
403 link_was_up = sc->link_is_up;
404 mii_tick(sc->mii_softc);
405 if (sc->link_is_up && !link_was_up)
406 dwc_txstart_locked(sc);
408 /* Schedule another check one second from now. */
409 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
413 dwc_init_locked(struct dwc_softc *sc)
415 struct ifnet *ifp = sc->ifp;
418 DWC_ASSERT_LOCKED(sc);
420 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
423 ifp->if_drv_flags |= IFF_DRV_RUNNING;
425 dwc_setup_rxfilter(sc);
427 /* Initializa DMA and enable transmitters */
428 reg = READ4(sc, OPERATION_MODE);
429 reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
431 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
432 WRITE4(sc, OPERATION_MODE, reg);
434 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
437 reg = READ4(sc, OPERATION_MODE);
438 reg |= (MODE_ST | MODE_SR);
439 WRITE4(sc, OPERATION_MODE, reg);
441 /* Enable transmitters */
442 reg = READ4(sc, MAC_CONFIGURATION);
443 reg |= (CONF_JD | CONF_ACS | CONF_BE);
444 reg |= (CONF_TE | CONF_RE);
445 WRITE4(sc, MAC_CONFIGURATION, reg);
448 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
449 * to set up the remaining config registers based on current media.
451 mii_mediachg(sc->mii_softc);
452 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
456 dwc_init(void *if_softc)
458 struct dwc_softc *sc = if_softc;
465 inline static uint32_t
466 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
470 sc->rxdesc_ring[idx].addr = (uint32_t)paddr;
471 nidx = next_rxidx(sc, idx);
472 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \
473 (nidx * sizeof(struct dwc_hwdesc));
474 if (sc->mactype == DWC_GMAC_ALT_DESC)
475 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET;
477 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES;
480 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN;
487 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
489 struct bus_dma_segment seg;
492 m_adj(m, ETHER_ALIGN);
494 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
500 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
502 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
503 BUS_DMASYNC_PREREAD);
505 sc->rxbuf_map[idx].mbuf = m;
506 dwc_setup_rxdesc(sc, idx, seg.ds_addr);
512 dwc_alloc_mbufcl(struct dwc_softc *sc)
516 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
518 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
524 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
526 struct dwc_softc *sc;
527 struct mii_data *mii;
533 ifmr->ifm_active = mii->mii_media_active;
534 ifmr->ifm_status = mii->mii_media_status;
539 dwc_media_change_locked(struct dwc_softc *sc)
542 return (mii_mediachg(sc->mii_softc));
546 dwc_media_change(struct ifnet * ifp)
548 struct dwc_softc *sc;
554 error = dwc_media_change_locked(sc);
559 static const uint8_t nibbletab[] = {
560 /* 0x0 0000 -> 0000 */ 0x0,
561 /* 0x1 0001 -> 1000 */ 0x8,
562 /* 0x2 0010 -> 0100 */ 0x4,
563 /* 0x3 0011 -> 1100 */ 0xc,
564 /* 0x4 0100 -> 0010 */ 0x2,
565 /* 0x5 0101 -> 1010 */ 0xa,
566 /* 0x6 0110 -> 0110 */ 0x6,
567 /* 0x7 0111 -> 1110 */ 0xe,
568 /* 0x8 1000 -> 0001 */ 0x1,
569 /* 0x9 1001 -> 1001 */ 0x9,
570 /* 0xa 1010 -> 0101 */ 0x5,
571 /* 0xb 1011 -> 1101 */ 0xd,
572 /* 0xc 1100 -> 0011 */ 0x3,
573 /* 0xd 1101 -> 1011 */ 0xb,
574 /* 0xe 1110 -> 0111 */ 0x7,
575 /* 0xf 1111 -> 1111 */ 0xf, };
578 bitreverse(uint8_t x)
581 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
585 dwc_setup_rxfilter(struct dwc_softc *sc)
587 struct ifmultiaddr *ifma;
590 uint32_t crc, ffval, hashbit, hashreg, hi, lo, hash[8];
593 DWC_ASSERT_LOCKED(sc);
596 nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8;
599 * Set the multicast (group) filter hash.
601 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
602 ffval = (FRAME_FILTER_PM);
603 for (i = 0; i < nhash; i++)
606 ffval = (FRAME_FILTER_HMC);
607 for (i = 0; i < nhash; i++)
610 CK_STAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
611 if (ifma->ifma_addr->sa_family != AF_LINK)
613 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
614 ifma->ifma_addr), ETHER_ADDR_LEN);
616 /* Take lower 8 bits and reverse it */
617 val = bitreverse(~crc & 0xff);
618 if (sc->mactype == DWC_GMAC_ALT_DESC)
619 val >>= nhash; /* Only need lower 6 bits */
620 hashreg = (val >> 5);
621 hashbit = (val & 31);
622 hash[hashreg] |= (1 << hashbit);
624 if_maddr_runlock(ifp);
628 * Set the individual address filter hash.
630 if (ifp->if_flags & IFF_PROMISC)
631 ffval |= (FRAME_FILTER_PR);
634 * Set the primary address.
636 eaddr = IF_LLADDR(ifp);
637 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
639 hi = eaddr[4] | (eaddr[5] << 8);
640 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
641 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
642 WRITE4(sc, MAC_FRAME_FILTER, ffval);
643 if (sc->mactype == DWC_GMAC_ALT_DESC) {
644 WRITE4(sc, GMAC_MAC_HTLOW, hash[0]);
645 WRITE4(sc, GMAC_MAC_HTHIGH, hash[1]);
647 for (i = 0; i < nhash; i++)
648 WRITE4(sc, HASH_TABLE_REG(i), hash[i]);
653 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
655 struct dwc_softc *sc;
656 struct mii_data *mii;
661 ifr = (struct ifreq *)data;
667 if (ifp->if_flags & IFF_UP) {
668 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
669 if ((ifp->if_flags ^ sc->if_flags) &
670 (IFF_PROMISC | IFF_ALLMULTI))
671 dwc_setup_rxfilter(sc);
673 if (!sc->is_detaching)
677 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
680 sc->if_flags = ifp->if_flags;
685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
687 dwc_setup_rxfilter(sc);
694 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
697 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
698 if (mask & IFCAP_VLAN_MTU) {
699 /* No work to do except acknowledge the change took */
700 ifp->if_capenable ^= IFCAP_VLAN_MTU;
705 error = ether_ioctl(ifp, cmd, data);
713 dwc_txfinish_locked(struct dwc_softc *sc)
715 struct dwc_bufmap *bmap;
716 struct dwc_hwdesc *desc;
719 DWC_ASSERT_LOCKED(sc);
722 while (sc->tx_idx_tail != sc->tx_idx_head) {
723 desc = &sc->txdesc_ring[sc->tx_idx_tail];
724 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0)
726 bmap = &sc->txbuf_map[sc->tx_idx_tail];
727 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
728 BUS_DMASYNC_POSTWRITE);
729 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
732 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
733 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
734 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
735 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
738 /* If there are no buffers outstanding, muzzle the watchdog. */
739 if (sc->tx_idx_tail == sc->tx_idx_head) {
740 sc->tx_watchdog_count = 0;
745 dwc_rxfinish_locked(struct dwc_softc *sc)
758 rdes0 = sc->rxdesc_ring[idx].tdes0;
759 if ((rdes0 & DDESC_RDES0_OWN) != 0)
762 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
763 BUS_DMASYNC_POSTREAD);
764 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map);
766 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK;
768 m = sc->rxbuf_map[idx].mbuf;
769 m->m_pkthdr.rcvif = ifp;
770 m->m_pkthdr.len = len;
772 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
774 /* Remove trailing FCS */
775 m_adj(m, -ETHER_CRC_LEN);
778 (*ifp->if_input)(ifp, m);
781 /* XXX Zero-length packet ? */
784 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) {
785 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) {
788 * We've got a hole in the rx ring.
792 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
794 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
801 struct dwc_softc *sc;
808 reg = READ4(sc, INTERRUPT_STATUS);
810 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
812 reg = READ4(sc, DMA_STATUS);
813 if (reg & DMA_STATUS_NIS) {
814 if (reg & DMA_STATUS_RI)
815 dwc_rxfinish_locked(sc);
817 if (reg & DMA_STATUS_TI) {
818 dwc_txfinish_locked(sc);
819 dwc_txstart_locked(sc);
823 if (reg & DMA_STATUS_AIS) {
824 if (reg & DMA_STATUS_FBI) {
825 /* Fatal bus error */
826 device_printf(sc->dev,
827 "Ethernet DMA error, restarting controller.\n");
833 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
838 setup_dma(struct dwc_softc *sc)
846 * Set up TX descriptor ring, descriptors, and dma maps.
848 error = bus_dma_tag_create(
849 bus_get_dma_tag(sc->dev), /* Parent tag. */
850 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
851 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
852 BUS_SPACE_MAXADDR, /* highaddr */
853 NULL, NULL, /* filter, filterarg */
854 TX_DESC_SIZE, 1, /* maxsize, nsegments */
855 TX_DESC_SIZE, /* maxsegsize */
857 NULL, NULL, /* lockfunc, lockarg */
860 device_printf(sc->dev,
861 "could not create TX ring DMA tag.\n");
865 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
866 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
869 device_printf(sc->dev,
870 "could not allocate TX descriptor ring.\n");
874 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
875 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
876 &sc->txdesc_ring_paddr, 0);
878 device_printf(sc->dev,
879 "could not load TX descriptor ring map.\n");
883 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
884 nidx = next_txidx(sc, idx);
885 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr +
886 (nidx * sizeof(struct dwc_hwdesc));
889 error = bus_dma_tag_create(
890 bus_get_dma_tag(sc->dev), /* Parent tag. */
891 1, 0, /* alignment, boundary */
892 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
893 BUS_SPACE_MAXADDR, /* highaddr */
894 NULL, NULL, /* filter, filterarg */
895 MCLBYTES, 1, /* maxsize, nsegments */
896 MCLBYTES, /* maxsegsize */
898 NULL, NULL, /* lockfunc, lockarg */
901 device_printf(sc->dev,
902 "could not create TX ring DMA tag.\n");
906 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
907 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
908 &sc->txbuf_map[idx].map);
910 device_printf(sc->dev,
911 "could not create TX buffer DMA map.\n");
914 dwc_setup_txdesc(sc, idx, 0, 0);
918 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
920 error = bus_dma_tag_create(
921 bus_get_dma_tag(sc->dev), /* Parent tag. */
922 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
923 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
924 BUS_SPACE_MAXADDR, /* highaddr */
925 NULL, NULL, /* filter, filterarg */
926 RX_DESC_SIZE, 1, /* maxsize, nsegments */
927 RX_DESC_SIZE, /* maxsegsize */
929 NULL, NULL, /* lockfunc, lockarg */
932 device_printf(sc->dev,
933 "could not create RX ring DMA tag.\n");
937 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
938 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
941 device_printf(sc->dev,
942 "could not allocate RX descriptor ring.\n");
946 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
947 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
948 &sc->rxdesc_ring_paddr, 0);
950 device_printf(sc->dev,
951 "could not load RX descriptor ring map.\n");
955 error = bus_dma_tag_create(
956 bus_get_dma_tag(sc->dev), /* Parent tag. */
957 1, 0, /* alignment, boundary */
958 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
959 BUS_SPACE_MAXADDR, /* highaddr */
960 NULL, NULL, /* filter, filterarg */
961 MCLBYTES, 1, /* maxsize, nsegments */
962 MCLBYTES, /* maxsegsize */
964 NULL, NULL, /* lockfunc, lockarg */
967 device_printf(sc->dev,
968 "could not create RX buf DMA tag.\n");
972 for (idx = 0; idx < RX_DESC_COUNT; idx++) {
973 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
974 &sc->rxbuf_map[idx].map);
976 device_printf(sc->dev,
977 "could not create RX buffer DMA map.\n");
980 if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
981 device_printf(sc->dev, "Could not alloc mbuf\n");
985 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
986 device_printf(sc->dev,
987 "could not create new RX buffer.\n");
1000 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
1002 uint32_t hi, lo, rnd;
1005 * Try to recover a MAC address from the running hardware. If there's
1006 * something non-zero there, assume the bootloader did the right thing
1009 * Otherwise, set the address to a convenient locally assigned address,
1010 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
1011 * assigned bit set, and the broadcast/multicast bit clear.
1013 lo = READ4(sc, MAC_ADDRESS_LOW(0));
1014 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1015 if ((lo != 0xffffffff) || (hi != 0xffff)) {
1016 hwaddr[0] = (lo >> 0) & 0xff;
1017 hwaddr[1] = (lo >> 8) & 0xff;
1018 hwaddr[2] = (lo >> 16) & 0xff;
1019 hwaddr[3] = (lo >> 24) & 0xff;
1020 hwaddr[4] = (hi >> 0) & 0xff;
1021 hwaddr[5] = (hi >> 8) & 0xff;
1023 rnd = arc4random() & 0x00ffffff;
1027 hwaddr[3] = rnd >> 16;
1028 hwaddr[4] = rnd >> 8;
1029 hwaddr[5] = rnd >> 0;
1035 #define GPIO_ACTIVE_LOW 1
1038 dwc_reset(device_t dev)
1040 pcell_t gpio_prop[4];
1041 pcell_t delay_prop[3];
1042 phandle_t node, gpio_node;
1044 uint32_t pin, flags;
1047 node = ofw_bus_get_node(dev);
1048 if (OF_getencprop(node, "snps,reset-gpio",
1049 gpio_prop, sizeof(gpio_prop)) <= 0)
1052 if (OF_getencprop(node, "snps,reset-delays-us",
1053 delay_prop, sizeof(delay_prop)) <= 0) {
1055 "Wrong property for snps,reset-delays-us");
1059 gpio_node = OF_node_from_xref(gpio_prop[0]);
1060 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
1062 "Can't find gpio controller for phy reset\n");
1066 if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
1067 nitems(gpio_prop) - 1,
1068 gpio_prop + 1, &pin, &flags) != 0) {
1069 device_printf(dev, "Can't map gpio for phy reset\n");
1073 pin_value = GPIO_PIN_LOW;
1074 if (OF_hasprop(node, "snps,reset-active-low"))
1075 pin_value = GPIO_PIN_HIGH;
1077 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1078 GPIO_PIN_SET(gpio, pin, pin_value);
1079 DELAY(delay_prop[0] * 5);
1080 GPIO_PIN_SET(gpio, pin, !pin_value);
1081 DELAY(delay_prop[1] * 5);
1082 GPIO_PIN_SET(gpio, pin, pin_value);
1083 DELAY(delay_prop[2] * 5);
1088 #ifdef EXT_RESOURCES
1090 dwc_clock_init(device_t dev)
1097 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
1098 error = clk_enable(clk);
1100 device_printf(dev, "could not enable main clock\n");
1105 /* De-assert reset */
1106 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
1107 error = hwreset_deassert(rst);
1109 device_printf(dev, "could not de-assert reset\n");
1119 dwc_probe(device_t dev)
1122 if (!ofw_bus_status_okay(dev))
1125 if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1128 device_set_desc(dev, "Gigabit Ethernet Controller");
1129 return (BUS_PROBE_DEFAULT);
1133 dwc_attach(device_t dev)
1135 uint8_t macaddr[ETHER_ADDR_LEN];
1136 struct dwc_softc *sc;
1141 sc = device_get_softc(dev);
1144 sc->txcount = TX_DESC_COUNT;
1145 sc->mii_clk = IF_DWC_MII_CLK(dev);
1146 sc->mactype = IF_DWC_MAC_TYPE(dev);
1148 if (IF_DWC_INIT(dev) != 0)
1151 #ifdef EXT_RESOURCES
1152 if (dwc_clock_init(dev) != 0)
1156 if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1157 device_printf(dev, "could not allocate resources\n");
1161 /* Memory interface */
1162 sc->bst = rman_get_bustag(sc->res[0]);
1163 sc->bsh = rman_get_bushandle(sc->res[0]);
1165 /* Read MAC before reset */
1166 if (dwc_get_hwaddr(sc, macaddr)) {
1167 device_printf(sc->dev, "can't get mac\n");
1171 /* Reset the PHY if needed */
1172 if (dwc_reset(dev) != 0) {
1173 device_printf(dev, "Can't reset the PHY\n");
1178 reg = READ4(sc, BUS_MODE);
1179 reg |= (BUS_MODE_SWR);
1180 WRITE4(sc, BUS_MODE, reg);
1182 for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1183 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1187 if (i >= MAC_RESET_TIMEOUT) {
1188 device_printf(sc->dev, "Can't reset DWC.\n");
1192 if (sc->mactype == DWC_GMAC_ALT_DESC) {
1193 reg = BUS_MODE_FIXEDBURST;
1194 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT);
1196 reg = (BUS_MODE_EIGHTXPBL);
1197 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1198 WRITE4(sc, BUS_MODE, reg);
1201 * DMA must be stop while changing descriptor list addresses.
1203 reg = READ4(sc, OPERATION_MODE);
1204 reg &= ~(MODE_ST | MODE_SR);
1205 WRITE4(sc, OPERATION_MODE, reg);
1210 /* Setup addresses */
1211 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1212 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1214 mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1215 MTX_NETWORK_LOCK, MTX_DEF);
1217 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1219 /* Setup interrupt handler. */
1220 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1221 NULL, dwc_intr, sc, &sc->intr_cookie);
1223 device_printf(dev, "could not setup interrupt handler.\n");
1227 /* Set up the ethernet interface. */
1228 sc->ifp = ifp = if_alloc(IFT_ETHER);
1231 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1232 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1233 ifp->if_capabilities = IFCAP_VLAN_MTU;
1234 ifp->if_capenable = ifp->if_capabilities;
1235 ifp->if_start = dwc_txstart;
1236 ifp->if_ioctl = dwc_ioctl;
1237 ifp->if_init = dwc_init;
1238 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1239 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1240 IFQ_SET_READY(&ifp->if_snd);
1242 /* Attach the mii driver. */
1243 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1244 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1248 device_printf(dev, "PHY attach failed\n");
1251 sc->mii_softc = device_get_softc(sc->miibus);
1253 /* All ready to run, attach the ethernet interface. */
1254 ether_ifattach(ifp, macaddr);
1255 sc->is_attached = true;
1261 dwc_miibus_read_reg(device_t dev, int phy, int reg)
1263 struct dwc_softc *sc;
1268 sc = device_get_softc(dev);
1270 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1271 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1272 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1273 | GMII_ADDRESS_GB; /* Busy flag */
1275 WRITE4(sc, GMII_ADDRESS, mii);
1277 for (cnt = 0; cnt < 1000; cnt++) {
1278 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1279 rv = READ4(sc, GMII_DATA);
1289 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1291 struct dwc_softc *sc;
1295 sc = device_get_softc(dev);
1297 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1298 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1299 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1300 | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
1302 WRITE4(sc, GMII_DATA, val);
1303 WRITE4(sc, GMII_ADDRESS, mii);
1305 for (cnt = 0; cnt < 1000; cnt++) {
1306 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1316 dwc_miibus_statchg(device_t dev)
1318 struct dwc_softc *sc;
1319 struct mii_data *mii;
1323 * Called by the MII bus driver when the PHY establishes
1324 * link to set the MAC interface registers.
1327 sc = device_get_softc(dev);
1329 DWC_ASSERT_LOCKED(sc);
1331 mii = sc->mii_softc;
1333 if (mii->mii_media_status & IFM_ACTIVE)
1334 sc->link_is_up = true;
1336 sc->link_is_up = false;
1338 reg = READ4(sc, MAC_CONFIGURATION);
1339 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1342 reg &= ~(CONF_FES | CONF_PS);
1345 reg |= (CONF_FES | CONF_PS);
1352 sc->link_is_up = false;
1355 sc->link_is_up = false;
1356 device_printf(dev, "Unsupported media %u\n",
1357 IFM_SUBTYPE(mii->mii_media_active));
1360 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1364 WRITE4(sc, MAC_CONFIGURATION, reg);
1367 static device_method_t dwc_methods[] = {
1368 DEVMETHOD(device_probe, dwc_probe),
1369 DEVMETHOD(device_attach, dwc_attach),
1372 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg),
1373 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg),
1374 DEVMETHOD(miibus_statchg, dwc_miibus_statchg),
1379 driver_t dwc_driver = {
1382 sizeof(struct dwc_softc),
1385 static devclass_t dwc_devclass;
1387 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1388 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1390 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1391 MODULE_DEPEND(dwc, miibus, 1, 1, 1);