2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Ethernet media access controller (EMAC)
33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
35 * EMAC is an instance of the Synopsys DesignWare 3504-0
36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_var.h>
64 #include <machine/bus.h>
66 #include <dev/dwc/if_dwc.h>
67 #include <dev/dwc/if_dwcvar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
74 #include <dev/extres/clk/clk.h>
75 #include <dev/extres/hwreset/hwreset.h>
78 #include "if_dwc_if.h"
80 #include "miibus_if.h"
82 #define READ4(_sc, _reg) \
83 bus_read_4((_sc)->res[0], _reg)
84 #define WRITE4(_sc, _reg, _val) \
85 bus_write_4((_sc)->res[0], _reg, _val)
87 #define MAC_RESET_TIMEOUT 100
88 #define WATCHDOG_TIMEOUT_SECS 5
89 #define STATS_HARVEST_INTERVAL 2
91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
96 /* TX descriptors - TDESC0 is almost unified */
97 #define TDESC0_OWN (1U << 31)
98 #define TDESC0_IHE (1U << 16) /* IP Header Error */
99 #define TDESC0_ES (1U << 15) /* Error Summary */
100 #define TDESC0_JT (1U << 14) /* Jabber Timeout */
101 #define TDESC0_FF (1U << 13) /* Frame Flushed */
102 #define TDESC0_PCE (1U << 12) /* Payload Checksum Error */
103 #define TDESC0_LOC (1U << 11) /* Loss of Carrier */
104 #define TDESC0_NC (1U << 10) /* No Carrier */
105 #define TDESC0_LC (1U << 9) /* Late Collision */
106 #define TDESC0_EC (1U << 8) /* Excessive Collision */
107 #define TDESC0_VF (1U << 7) /* VLAN Frame */
108 #define TDESC0_CC_MASK 0xf
109 #define TDESC0_CC_SHIFT 3 /* Collision Count */
110 #define TDESC0_ED (1U << 2) /* Excessive Deferral */
111 #define TDESC0_UF (1U << 1) /* Underflow Error */
112 #define TDESC0_DB (1U << 0) /* Deferred Bit */
113 /* TX descriptors - TDESC0 extended format only */
114 #define ETDESC0_IC (1U << 30) /* Interrupt on Completion */
115 #define ETDESC0_LS (1U << 29) /* Last Segment */
116 #define ETDESC0_FS (1U << 28) /* First Segment */
117 #define ETDESC0_DC (1U << 27) /* Disable CRC */
118 #define ETDESC0_DP (1U << 26) /* Disable Padding */
119 #define ETDESC0_CIC_NONE (0U << 22) /* Checksum Insertion Control */
120 #define ETDESC0_CIC_HDR (1U << 22)
121 #define ETDESC0_CIC_SEG (2U << 22)
122 #define ETDESC0_CIC_FULL (3U << 22)
123 #define ETDESC0_TER (1U << 21) /* Transmit End of Ring */
124 #define ETDESC0_TCH (1U << 20) /* Second Address Chained */
126 /* TX descriptors - TDESC1 normal format */
127 #define NTDESC1_IC (1U << 31) /* Interrupt on Completion */
128 #define NTDESC1_LS (1U << 30) /* Last Segment */
129 #define NTDESC1_FS (1U << 29) /* First Segment */
130 #define NTDESC1_CIC_NONE (0U << 27) /* Checksum Insertion Control */
131 #define NTDESC1_CIC_HDR (1U << 27)
132 #define NTDESC1_CIC_SEG (2U << 27)
133 #define NTDESC1_CIC_FULL (3U << 27)
134 #define NTDESC1_DC (1U << 26) /* Disable CRC */
135 #define NTDESC1_TER (1U << 25) /* Transmit End of Ring */
136 #define NTDESC1_TCH (1U << 24) /* Second Address Chained */
137 /* TX descriptors - TDESC1 extended format */
138 #define ETDESC1_DP (1U << 23) /* Disable Padding */
139 #define ETDESC1_TBS2_MASK 0x7ff
140 #define ETDESC1_TBS2_SHIFT 11 /* Receive Buffer 2 Size */
141 #define ETDESC1_TBS1_MASK 0x7ff
142 #define ETDESC1_TBS1_SHIFT 0 /* Receive Buffer 1 Size */
144 /* RX descriptor - RDESC0 is unified */
145 #define RDESC0_OWN (1U << 31)
146 #define RDESC0_AFM (1U << 30) /* Dest. Address Filter Fail */
147 #define RDESC0_FL_MASK 0x3fff
148 #define RDESC0_FL_SHIFT 16 /* Frame Length */
149 #define RDESC0_ES (1U << 15) /* Error Summary */
150 #define RDESC0_DE (1U << 14) /* Descriptor Error */
151 #define RDESC0_SAF (1U << 13) /* Source Address Filter Fail */
152 #define RDESC0_LE (1U << 12) /* Length Error */
153 #define RDESC0_OE (1U << 11) /* Overflow Error */
154 #define RDESC0_VLAN (1U << 10) /* VLAN Tag */
155 #define RDESC0_FS (1U << 9) /* First Descriptor */
156 #define RDESC0_LS (1U << 8) /* Last Descriptor */
157 #define RDESC0_ICE (1U << 7) /* IPC Checksum Error */
158 #define RDESC0_GF (1U << 7) /* Giant Frame */
159 #define RDESC0_LC (1U << 6) /* Late Collision */
160 #define RDESC0_FT (1U << 5) /* Frame Type */
161 #define RDESC0_RWT (1U << 4) /* Receive Watchdog Timeout */
162 #define RDESC0_RE (1U << 3) /* Receive Error */
163 #define RDESC0_DBE (1U << 2) /* Dribble Bit Error */
164 #define RDESC0_CE (1U << 1) /* CRC Error */
165 #define RDESC0_PCE (1U << 0) /* Payload Checksum Error */
166 #define RDESC0_RXMA (1U << 0) /* Rx MAC Address */
168 /* RX descriptors - RDESC1 normal format */
169 #define NRDESC1_DIC (1U << 31) /* Disable Intr on Completion */
170 #define NRDESC1_RER (1U << 25) /* Receive End of Ring */
171 #define NRDESC1_RCH (1U << 24) /* Second Address Chained */
172 #define NRDESC1_RBS2_MASK 0x7ff
173 #define NRDESC1_RBS2_SHIFT 11 /* Receive Buffer 2 Size */
174 #define NRDESC1_RBS1_MASK 0x7ff
175 #define NRDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */
177 /* RX descriptors - RDESC1 enhanced format */
178 #define ERDESC1_DIC (1U << 31) /* Disable Intr on Completion */
179 #define ERDESC1_RBS2_MASK 0x7ffff
180 #define ERDESC1_RBS2_SHIFT 16 /* Receive Buffer 2 Size */
181 #define ERDESC1_RER (1U << 15) /* Receive End of Ring */
182 #define ERDESC1_RCH (1U << 14) /* Second Address Chained */
183 #define ERDESC1_RBS1_MASK 0x7ffff
184 #define ERDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */
187 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
188 * layout, but the bits in the fields have different meanings.
194 uint32_t addr1; /* ptr to first buffer data */
195 uint32_t addr2; /* ptr to next descriptor / second buffer data*/
199 * The hardware imposes alignment restrictions on various objects involved in
200 * DMA transfers. These values are expressed in bytes (not bits).
202 #define DWC_DESC_RING_ALIGN 2048
204 static struct resource_spec dwc_spec[] = {
205 { SYS_RES_MEMORY, 0, RF_ACTIVE },
206 { SYS_RES_IRQ, 0, RF_ACTIVE },
210 static void dwc_txfinish_locked(struct dwc_softc *sc);
211 static void dwc_rxfinish_locked(struct dwc_softc *sc);
212 static void dwc_stop_locked(struct dwc_softc *sc);
213 static void dwc_setup_rxfilter(struct dwc_softc *sc);
214 static void dwc_setup_core(struct dwc_softc *sc);
215 static void dwc_init_dma(struct dwc_softc *sc);
217 static inline uint32_t
218 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
221 return ((curidx + 1) % RX_DESC_COUNT);
224 static inline uint32_t
225 next_txidx(struct dwc_softc *sc, uint32_t curidx)
228 return ((curidx + 1) % TX_DESC_COUNT);
232 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
237 *(bus_addr_t *)arg = segs[0].ds_addr;
241 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
244 uint32_t desc0, desc1;
246 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
247 if (paddr == 0 || len == 0) {
252 if (sc->mactype != DWC_GMAC_EXT_DESC) {
254 desc1 = NTDESC1_TCH | NTDESC1_FS | NTDESC1_LS |
257 desc0 = ETDESC0_TCH | ETDESC0_FS | ETDESC0_LS |
264 sc->txdesc_ring[idx].addr1 = (uint32_t)(paddr);
265 sc->txdesc_ring[idx].desc0 = desc0;
266 sc->txdesc_ring[idx].desc1 = desc1;
270 sc->txdesc_ring[idx].desc0 |= TDESC0_OWN;
276 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
278 struct bus_dma_segment seg;
282 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
286 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
292 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
294 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
295 BUS_DMASYNC_PREWRITE);
297 sc->txbuf_map[idx].mbuf = m;
299 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
305 dwc_txstart_locked(struct dwc_softc *sc)
311 DWC_ASSERT_LOCKED(sc);
318 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
324 if (sc->txcount == (TX_DESC_COUNT - 1)) {
325 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
329 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
332 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
333 IFQ_DRV_PREPEND(&ifp->if_snd, m);
337 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
342 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
343 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
348 dwc_txstart(struct ifnet *ifp)
350 struct dwc_softc *sc = ifp->if_softc;
353 dwc_txstart_locked(sc);
358 dwc_stop_locked(struct dwc_softc *sc)
363 DWC_ASSERT_LOCKED(sc);
366 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
367 sc->tx_watchdog_count = 0;
368 sc->stats_harvest_count = 0;
370 callout_stop(&sc->dwc_callout);
373 reg = READ4(sc, OPERATION_MODE);
375 WRITE4(sc, OPERATION_MODE, reg);
378 reg = READ4(sc, OPERATION_MODE);
380 WRITE4(sc, OPERATION_MODE, reg);
382 /* Stop transmitters */
383 reg = READ4(sc, MAC_CONFIGURATION);
384 reg &= ~(CONF_TE | CONF_RE);
385 WRITE4(sc, MAC_CONFIGURATION, reg);
388 reg = READ4(sc, OPERATION_MODE);
390 WRITE4(sc, OPERATION_MODE, reg);
393 static void dwc_clear_stats(struct dwc_softc *sc)
397 reg = READ4(sc, MMC_CONTROL);
398 reg |= (MMC_CONTROL_CNTRST);
399 WRITE4(sc, MMC_CONTROL, reg);
403 dwc_harvest_stats(struct dwc_softc *sc)
407 /* We don't need to harvest too often. */
408 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
411 sc->stats_harvest_count = 0;
414 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
415 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
416 if_inc_counter(ifp, IFCOUNTER_IERRORS,
417 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
418 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
419 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
420 READ4(sc, RXLENGTHERROR));
422 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
423 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
424 if_inc_counter(ifp, IFCOUNTER_OERRORS,
425 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
426 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
428 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
429 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
437 struct dwc_softc *sc;
443 DWC_ASSERT_LOCKED(sc);
447 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
451 * Typical tx watchdog. If this fires it indicates that we enqueued
452 * packets for output and never got a txdone interrupt for them. Maybe
453 * it's a missed interrupt somehow, just pretend we got one.
455 if (sc->tx_watchdog_count > 0) {
456 if (--sc->tx_watchdog_count == 0) {
457 dwc_txfinish_locked(sc);
461 /* Gather stats from hardware counters. */
462 dwc_harvest_stats(sc);
464 /* Check the media status. */
465 link_was_up = sc->link_is_up;
466 mii_tick(sc->mii_softc);
467 if (sc->link_is_up && !link_was_up)
468 dwc_txstart_locked(sc);
470 /* Schedule another check one second from now. */
471 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
475 dwc_init_locked(struct dwc_softc *sc)
477 struct ifnet *ifp = sc->ifp;
479 DWC_ASSERT_LOCKED(sc);
481 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
484 ifp->if_drv_flags |= IFF_DRV_RUNNING;
486 dwc_setup_rxfilter(sc);
491 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
492 * to set up the remaining config registers based on current media.
494 mii_mediachg(sc->mii_softc);
495 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
499 dwc_init(void *if_softc)
501 struct dwc_softc *sc = if_softc;
509 inline static uint32_t
510 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
514 sc->rxdesc_ring[idx].addr1 = (uint32_t)paddr;
515 nidx = next_rxidx(sc, idx);
516 sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr +
517 (nidx * sizeof(struct dwc_hwdesc));
518 if (sc->mactype != DWC_GMAC_EXT_DESC)
519 sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH |
520 MIN(MCLBYTES, NRDESC1_RBS1_MASK);
522 sc->rxdesc_ring[idx].desc1 = ERDESC1_RCH |
523 MIN(MCLBYTES, ERDESC1_RBS1_MASK);
526 sc->rxdesc_ring[idx].desc0 = RDESC0_OWN;
532 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
534 struct bus_dma_segment seg;
537 m_adj(m, ETHER_ALIGN);
539 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
544 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
546 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
547 BUS_DMASYNC_PREREAD);
549 sc->rxbuf_map[idx].mbuf = m;
550 dwc_setup_rxdesc(sc, idx, seg.ds_addr);
556 dwc_alloc_mbufcl(struct dwc_softc *sc)
560 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
562 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
568 dwc_rxfinish_one(struct dwc_softc *sc, struct dwc_hwdesc *desc,
569 struct dwc_bufmap *map)
578 rdesc0 = desc ->desc0;
579 /* Validate descriptor. */
580 if (rdesc0 & RDESC0_ES) {
582 * Errored packet. Statistic counters are updated
583 * globally, so do nothing
588 if ((rdesc0 & (RDESC0_FS | RDESC0_LS)) !=
589 (RDESC0_FS | RDESC0_LS)) {
591 * Something very wrong happens. The whole packet should be
592 * recevied in one descriptr. Report problem.
594 device_printf(sc->dev,
595 "%s: RX descriptor without FIRST and LAST bit set: 0x%08X",
600 len = (rdesc0 >> RDESC0_FL_SHIFT) & RDESC0_FL_MASK;
603 * Lenght is invalid, recycle old mbuf
604 * Probably impossible case
609 /* Allocate new buffer */
610 m0 = dwc_alloc_mbufcl(sc);
612 /* no new mbuf available, recycle old */
613 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
616 /* Do dmasync for newly received packet */
617 bus_dmamap_sync(sc->rxbuf_tag, map->map, BUS_DMASYNC_POSTREAD);
618 bus_dmamap_unload(sc->rxbuf_tag, map->map);
620 /* Received packet is valid, process it */
621 m->m_pkthdr.rcvif = ifp;
622 m->m_pkthdr.len = len;
624 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
626 /* Remove trailing FCS */
627 m_adj(m, -ETHER_CRC_LEN);
630 (*ifp->if_input)(ifp, m);
636 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
638 struct dwc_softc *sc;
639 struct mii_data *mii;
645 ifmr->ifm_active = mii->mii_media_active;
646 ifmr->ifm_status = mii->mii_media_status;
651 dwc_media_change_locked(struct dwc_softc *sc)
654 return (mii_mediachg(sc->mii_softc));
658 dwc_media_change(struct ifnet * ifp)
660 struct dwc_softc *sc;
666 error = dwc_media_change_locked(sc);
671 static const uint8_t nibbletab[] = {
672 /* 0x0 0000 -> 0000 */ 0x0,
673 /* 0x1 0001 -> 1000 */ 0x8,
674 /* 0x2 0010 -> 0100 */ 0x4,
675 /* 0x3 0011 -> 1100 */ 0xc,
676 /* 0x4 0100 -> 0010 */ 0x2,
677 /* 0x5 0101 -> 1010 */ 0xa,
678 /* 0x6 0110 -> 0110 */ 0x6,
679 /* 0x7 0111 -> 1110 */ 0xe,
680 /* 0x8 1000 -> 0001 */ 0x1,
681 /* 0x9 1001 -> 1001 */ 0x9,
682 /* 0xa 1010 -> 0101 */ 0x5,
683 /* 0xb 1011 -> 1101 */ 0xd,
684 /* 0xc 1100 -> 0011 */ 0x3,
685 /* 0xd 1101 -> 1011 */ 0xb,
686 /* 0xe 1110 -> 0111 */ 0x7,
687 /* 0xf 1111 -> 1111 */ 0xf, };
690 bitreverse(uint8_t x)
693 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
696 struct dwc_hash_maddr_ctx {
697 struct dwc_softc *sc;
702 dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
704 struct dwc_hash_maddr_ctx *ctx = arg;
705 uint32_t crc, hashbit, hashreg;
708 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
709 /* Take lower 8 bits and reverse it */
710 val = bitreverse(~crc & 0xff);
711 if (ctx->sc->mactype != DWC_GMAC_EXT_DESC)
712 val >>= 2; /* Only need lower 6 bits */
713 hashreg = (val >> 5);
714 hashbit = (val & 31);
715 ctx->hash[hashreg] |= (1 << hashbit);
721 dwc_setup_rxfilter(struct dwc_softc *sc)
723 struct dwc_hash_maddr_ctx ctx;
726 uint32_t ffval, hi, lo;
729 DWC_ASSERT_LOCKED(sc);
732 nhash = sc->mactype != DWC_GMAC_EXT_DESC ? 2 : 8;
735 * Set the multicast (group) filter hash.
737 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
738 ffval = (FRAME_FILTER_PM);
739 for (i = 0; i < nhash; i++)
742 ffval = (FRAME_FILTER_HMC);
743 for (i = 0; i < nhash; i++)
746 if_foreach_llmaddr(ifp, dwc_hash_maddr, &ctx);
750 * Set the individual address filter hash.
752 if (ifp->if_flags & IFF_PROMISC)
753 ffval |= (FRAME_FILTER_PR);
756 * Set the primary address.
758 eaddr = IF_LLADDR(ifp);
759 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
761 hi = eaddr[4] | (eaddr[5] << 8);
762 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
763 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
764 WRITE4(sc, MAC_FRAME_FILTER, ffval);
765 if (sc->mactype != DWC_GMAC_EXT_DESC) {
766 WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);
767 WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);
769 for (i = 0; i < nhash; i++)
770 WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]);
775 dwc_setup_core(struct dwc_softc *sc)
779 DWC_ASSERT_LOCKED(sc);
781 /* Enable transmitters */
782 reg = READ4(sc, MAC_CONFIGURATION);
783 reg |= (CONF_JD | CONF_ACS | CONF_BE);
784 reg |= (CONF_TE | CONF_RE);
785 WRITE4(sc, MAC_CONFIGURATION, reg);
789 dwc_init_dma(struct dwc_softc *sc)
793 DWC_ASSERT_LOCKED(sc);
795 /* Initializa DMA and enable transmitters */
796 reg = READ4(sc, OPERATION_MODE);
797 reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
799 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
800 WRITE4(sc, OPERATION_MODE, reg);
802 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
805 reg = READ4(sc, OPERATION_MODE);
806 reg |= (MODE_ST | MODE_SR);
807 WRITE4(sc, OPERATION_MODE, reg);
811 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
813 struct dwc_softc *sc;
814 struct mii_data *mii;
819 ifr = (struct ifreq *)data;
825 if (ifp->if_flags & IFF_UP) {
826 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
827 if ((ifp->if_flags ^ sc->if_flags) &
828 (IFF_PROMISC | IFF_ALLMULTI))
829 dwc_setup_rxfilter(sc);
831 if (!sc->is_detaching)
835 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
838 sc->if_flags = ifp->if_flags;
843 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
845 dwc_setup_rxfilter(sc);
852 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
855 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
856 if (mask & IFCAP_VLAN_MTU) {
857 /* No work to do except acknowledge the change took */
858 ifp->if_capenable ^= IFCAP_VLAN_MTU;
863 error = ether_ioctl(ifp, cmd, data);
871 dwc_txfinish_locked(struct dwc_softc *sc)
873 struct dwc_bufmap *bmap;
874 struct dwc_hwdesc *desc;
877 DWC_ASSERT_LOCKED(sc);
880 while (sc->tx_idx_tail != sc->tx_idx_head) {
881 desc = &sc->txdesc_ring[sc->tx_idx_tail];
882 if ((desc->desc0 & TDESC0_OWN) != 0)
884 bmap = &sc->txbuf_map[sc->tx_idx_tail];
885 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
886 BUS_DMASYNC_POSTWRITE);
887 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
890 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
891 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
892 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
893 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
896 /* If there are no buffers outstanding, muzzle the watchdog. */
897 if (sc->tx_idx_tail == sc->tx_idx_head) {
898 sc->tx_watchdog_count = 0;
903 dwc_rxfinish_locked(struct dwc_softc *sc)
908 struct dwc_hwdesc *desc;
910 DWC_ASSERT_LOCKED(sc);
914 desc = sc->rxdesc_ring + idx;
915 if ((desc->desc0 & RDESC0_OWN) != 0)
918 m = dwc_rxfinish_one(sc, desc, sc->rxbuf_map + idx);
921 desc->desc0 = RDESC0_OWN;
924 /* We cannot create hole in RX ring */
925 error = dwc_setup_rxbuf(sc, idx, m);
927 panic("dwc_setup_rxbuf failed: error %d\n",
930 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
937 struct dwc_softc *sc;
944 reg = READ4(sc, INTERRUPT_STATUS);
946 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
948 reg = READ4(sc, DMA_STATUS);
949 if (reg & DMA_STATUS_NIS) {
950 if (reg & DMA_STATUS_RI)
951 dwc_rxfinish_locked(sc);
953 if (reg & DMA_STATUS_TI) {
954 dwc_txfinish_locked(sc);
955 dwc_txstart_locked(sc);
959 if (reg & DMA_STATUS_AIS) {
960 if (reg & DMA_STATUS_FBI) {
961 /* Fatal bus error */
962 device_printf(sc->dev,
963 "Ethernet DMA error, restarting controller.\n");
969 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
974 setup_dma(struct dwc_softc *sc)
982 * Set up TX descriptor ring, descriptors, and dma maps.
984 error = bus_dma_tag_create(
985 bus_get_dma_tag(sc->dev), /* Parent tag. */
986 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
987 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
988 BUS_SPACE_MAXADDR, /* highaddr */
989 NULL, NULL, /* filter, filterarg */
990 TX_DESC_SIZE, 1, /* maxsize, nsegments */
991 TX_DESC_SIZE, /* maxsegsize */
993 NULL, NULL, /* lockfunc, lockarg */
996 device_printf(sc->dev,
997 "could not create TX ring DMA tag.\n");
1001 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1002 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
1005 device_printf(sc->dev,
1006 "could not allocate TX descriptor ring.\n");
1010 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
1011 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
1012 &sc->txdesc_ring_paddr, 0);
1014 device_printf(sc->dev,
1015 "could not load TX descriptor ring map.\n");
1019 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
1020 nidx = next_txidx(sc, idx);
1021 sc->txdesc_ring[idx].addr2 = sc->txdesc_ring_paddr +
1022 (nidx * sizeof(struct dwc_hwdesc));
1025 error = bus_dma_tag_create(
1026 bus_get_dma_tag(sc->dev), /* Parent tag. */
1027 1, 0, /* alignment, boundary */
1028 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1029 BUS_SPACE_MAXADDR, /* highaddr */
1030 NULL, NULL, /* filter, filterarg */
1031 MCLBYTES, 1, /* maxsize, nsegments */
1032 MCLBYTES, /* maxsegsize */
1034 NULL, NULL, /* lockfunc, lockarg */
1037 device_printf(sc->dev,
1038 "could not create TX ring DMA tag.\n");
1042 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
1043 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
1044 &sc->txbuf_map[idx].map);
1046 device_printf(sc->dev,
1047 "could not create TX buffer DMA map.\n");
1050 dwc_setup_txdesc(sc, idx, 0, 0);
1054 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1056 error = bus_dma_tag_create(
1057 bus_get_dma_tag(sc->dev), /* Parent tag. */
1058 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1059 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1060 BUS_SPACE_MAXADDR, /* highaddr */
1061 NULL, NULL, /* filter, filterarg */
1062 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1063 RX_DESC_SIZE, /* maxsegsize */
1065 NULL, NULL, /* lockfunc, lockarg */
1068 device_printf(sc->dev,
1069 "could not create RX ring DMA tag.\n");
1073 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1074 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
1077 device_printf(sc->dev,
1078 "could not allocate RX descriptor ring.\n");
1082 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
1083 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
1084 &sc->rxdesc_ring_paddr, 0);
1086 device_printf(sc->dev,
1087 "could not load RX descriptor ring map.\n");
1091 error = bus_dma_tag_create(
1092 bus_get_dma_tag(sc->dev), /* Parent tag. */
1093 1, 0, /* alignment, boundary */
1094 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1095 BUS_SPACE_MAXADDR, /* highaddr */
1096 NULL, NULL, /* filter, filterarg */
1097 MCLBYTES, 1, /* maxsize, nsegments */
1098 MCLBYTES, /* maxsegsize */
1100 NULL, NULL, /* lockfunc, lockarg */
1103 device_printf(sc->dev,
1104 "could not create RX buf DMA tag.\n");
1108 for (idx = 0; idx < RX_DESC_COUNT; idx++) {
1109 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
1110 &sc->rxbuf_map[idx].map);
1112 device_printf(sc->dev,
1113 "could not create RX buffer DMA map.\n");
1116 if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
1117 device_printf(sc->dev, "Could not alloc mbuf\n");
1121 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
1122 device_printf(sc->dev,
1123 "could not create new RX buffer.\n");
1136 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
1138 uint32_t hi, lo, rnd;
1141 * Try to recover a MAC address from the running hardware. If there's
1142 * something non-zero there, assume the bootloader did the right thing
1145 * Otherwise, set the address to a convenient locally assigned address,
1146 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
1147 * assigned bit set, and the broadcast/multicast bit clear.
1149 lo = READ4(sc, MAC_ADDRESS_LOW(0));
1150 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1151 if ((lo != 0xffffffff) || (hi != 0xffff)) {
1152 hwaddr[0] = (lo >> 0) & 0xff;
1153 hwaddr[1] = (lo >> 8) & 0xff;
1154 hwaddr[2] = (lo >> 16) & 0xff;
1155 hwaddr[3] = (lo >> 24) & 0xff;
1156 hwaddr[4] = (hi >> 0) & 0xff;
1157 hwaddr[5] = (hi >> 8) & 0xff;
1159 rnd = arc4random() & 0x00ffffff;
1163 hwaddr[3] = rnd >> 16;
1164 hwaddr[4] = rnd >> 8;
1165 hwaddr[5] = rnd >> 0;
1171 #define GPIO_ACTIVE_LOW 1
1174 dwc_reset(device_t dev)
1176 pcell_t gpio_prop[4];
1177 pcell_t delay_prop[3];
1178 phandle_t node, gpio_node;
1180 uint32_t pin, flags;
1183 node = ofw_bus_get_node(dev);
1184 if (OF_getencprop(node, "snps,reset-gpio",
1185 gpio_prop, sizeof(gpio_prop)) <= 0)
1188 if (OF_getencprop(node, "snps,reset-delays-us",
1189 delay_prop, sizeof(delay_prop)) <= 0) {
1191 "Wrong property for snps,reset-delays-us");
1195 gpio_node = OF_node_from_xref(gpio_prop[0]);
1196 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
1198 "Can't find gpio controller for phy reset\n");
1202 if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
1203 nitems(gpio_prop) - 1,
1204 gpio_prop + 1, &pin, &flags) != 0) {
1205 device_printf(dev, "Can't map gpio for phy reset\n");
1209 pin_value = GPIO_PIN_LOW;
1210 if (OF_hasprop(node, "snps,reset-active-low"))
1211 pin_value = GPIO_PIN_HIGH;
1213 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1214 GPIO_PIN_SET(gpio, pin, pin_value);
1215 DELAY(delay_prop[0] * 5);
1216 GPIO_PIN_SET(gpio, pin, !pin_value);
1217 DELAY(delay_prop[1] * 5);
1218 GPIO_PIN_SET(gpio, pin, pin_value);
1219 DELAY(delay_prop[2] * 5);
1224 #ifdef EXT_RESOURCES
1226 dwc_clock_init(device_t dev)
1234 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
1235 error = clk_enable(clk);
1237 device_printf(dev, "could not enable main clock\n");
1241 clk_get_freq(clk, &freq);
1242 device_printf(dev, "MAC clock(%s) freq: %jd\n",
1243 clk_get_name(clk), (intmax_t)freq);
1247 device_printf(dev, "could not find clock stmmaceth\n");
1250 /* De-assert reset */
1251 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
1252 error = hwreset_deassert(rst);
1254 device_printf(dev, "could not de-assert reset\n");
1264 dwc_probe(device_t dev)
1267 if (!ofw_bus_status_okay(dev))
1270 if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1273 device_set_desc(dev, "Gigabit Ethernet Controller");
1274 return (BUS_PROBE_DEFAULT);
1278 dwc_attach(device_t dev)
1280 uint8_t macaddr[ETHER_ADDR_LEN];
1281 struct dwc_softc *sc;
1288 sc = device_get_softc(dev);
1291 sc->txcount = TX_DESC_COUNT;
1292 sc->mii_clk = IF_DWC_MII_CLK(dev);
1293 sc->mactype = IF_DWC_MAC_TYPE(dev);
1295 node = ofw_bus_get_node(dev);
1296 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_mode)) {
1297 if (strcmp(phy_mode, "rgmii") == 0)
1298 sc->phy_mode = PHY_MODE_RGMII;
1299 if (strcmp(phy_mode, "rmii") == 0)
1300 sc->phy_mode = PHY_MODE_RMII;
1301 OF_prop_free(phy_mode);
1304 if (IF_DWC_INIT(dev) != 0)
1307 #ifdef EXT_RESOURCES
1308 if (dwc_clock_init(dev) != 0)
1312 if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1313 device_printf(dev, "could not allocate resources\n");
1317 /* Read MAC before reset */
1318 if (dwc_get_hwaddr(sc, macaddr)) {
1319 device_printf(sc->dev, "can't get mac\n");
1323 /* Reset the PHY if needed */
1324 if (dwc_reset(dev) != 0) {
1325 device_printf(dev, "Can't reset the PHY\n");
1330 reg = READ4(sc, BUS_MODE);
1331 reg |= (BUS_MODE_SWR);
1332 WRITE4(sc, BUS_MODE, reg);
1334 for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1335 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1339 if (i >= MAC_RESET_TIMEOUT) {
1340 device_printf(sc->dev, "Can't reset DWC.\n");
1344 if (sc->mactype != DWC_GMAC_EXT_DESC) {
1345 reg = BUS_MODE_FIXEDBURST;
1346 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT);
1348 reg = (BUS_MODE_EIGHTXPBL);
1349 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1350 WRITE4(sc, BUS_MODE, reg);
1353 * DMA must be stop while changing descriptor list addresses.
1355 reg = READ4(sc, OPERATION_MODE);
1356 reg &= ~(MODE_ST | MODE_SR);
1357 WRITE4(sc, OPERATION_MODE, reg);
1362 /* Setup addresses */
1363 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1364 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1366 mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1367 MTX_NETWORK_LOCK, MTX_DEF);
1369 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1371 /* Setup interrupt handler. */
1372 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1373 NULL, dwc_intr, sc, &sc->intr_cookie);
1375 device_printf(dev, "could not setup interrupt handler.\n");
1379 /* Set up the ethernet interface. */
1380 sc->ifp = ifp = if_alloc(IFT_ETHER);
1383 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1385 ifp->if_capabilities = IFCAP_VLAN_MTU;
1386 ifp->if_capenable = ifp->if_capabilities;
1387 ifp->if_start = dwc_txstart;
1388 ifp->if_ioctl = dwc_ioctl;
1389 ifp->if_init = dwc_init;
1390 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1391 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1392 IFQ_SET_READY(&ifp->if_snd);
1394 /* Attach the mii driver. */
1395 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1396 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1400 device_printf(dev, "PHY attach failed\n");
1403 sc->mii_softc = device_get_softc(sc->miibus);
1405 /* All ready to run, attach the ethernet interface. */
1406 ether_ifattach(ifp, macaddr);
1407 sc->is_attached = true;
1413 dwc_miibus_read_reg(device_t dev, int phy, int reg)
1415 struct dwc_softc *sc;
1420 sc = device_get_softc(dev);
1422 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1423 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1424 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1425 | GMII_ADDRESS_GB; /* Busy flag */
1427 WRITE4(sc, GMII_ADDRESS, mii);
1429 for (cnt = 0; cnt < 1000; cnt++) {
1430 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1431 rv = READ4(sc, GMII_DATA);
1441 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1443 struct dwc_softc *sc;
1447 sc = device_get_softc(dev);
1449 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1450 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1451 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1452 | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
1454 WRITE4(sc, GMII_DATA, val);
1455 WRITE4(sc, GMII_ADDRESS, mii);
1457 for (cnt = 0; cnt < 1000; cnt++) {
1458 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1468 dwc_miibus_statchg(device_t dev)
1470 struct dwc_softc *sc;
1471 struct mii_data *mii;
1475 * Called by the MII bus driver when the PHY establishes
1476 * link to set the MAC interface registers.
1479 sc = device_get_softc(dev);
1481 DWC_ASSERT_LOCKED(sc);
1483 mii = sc->mii_softc;
1485 if (mii->mii_media_status & IFM_ACTIVE)
1486 sc->link_is_up = true;
1488 sc->link_is_up = false;
1490 reg = READ4(sc, MAC_CONFIGURATION);
1491 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1494 reg &= ~(CONF_FES | CONF_PS);
1497 reg |= (CONF_FES | CONF_PS);
1504 sc->link_is_up = false;
1507 sc->link_is_up = false;
1508 device_printf(dev, "Unsupported media %u\n",
1509 IFM_SUBTYPE(mii->mii_media_active));
1512 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1516 WRITE4(sc, MAC_CONFIGURATION, reg);
1518 IF_DWC_SET_SPEED(dev, IFM_SUBTYPE(mii->mii_media_active));
1522 static device_method_t dwc_methods[] = {
1523 DEVMETHOD(device_probe, dwc_probe),
1524 DEVMETHOD(device_attach, dwc_attach),
1527 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg),
1528 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg),
1529 DEVMETHOD(miibus_statchg, dwc_miibus_statchg),
1534 driver_t dwc_driver = {
1537 sizeof(struct dwc_softc),
1540 static devclass_t dwc_devclass;
1542 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1543 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1545 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1546 MODULE_DEPEND(dwc, miibus, 1, 1, 1);