2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Ethernet media access controller (EMAC)
33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
35 * EMAC is an instance of the Synopsys DesignWare 3504-0
36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_var.h>
64 #include <machine/bus.h>
66 #include <dev/dwc/if_dwc.h>
67 #include <dev/dwc/if_dwcvar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
72 #include <dev/mii/mii_fdt.h>
74 #include <dev/extres/clk/clk.h>
75 #include <dev/extres/hwreset/hwreset.h>
77 #include "if_dwc_if.h"
79 #include "miibus_if.h"
81 #define READ4(_sc, _reg) \
82 bus_read_4((_sc)->res[0], _reg)
83 #define WRITE4(_sc, _reg, _val) \
84 bus_write_4((_sc)->res[0], _reg, _val)
86 #define MAC_RESET_TIMEOUT 100
87 #define WATCHDOG_TIMEOUT_SECS 5
88 #define STATS_HARVEST_INTERVAL 2
90 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
91 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
92 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
93 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
95 /* TX descriptors - TDESC0 is almost unified */
96 #define TDESC0_OWN (1U << 31)
97 #define TDESC0_IHE (1U << 16) /* IP Header Error */
98 #define TDESC0_ES (1U << 15) /* Error Summary */
99 #define TDESC0_JT (1U << 14) /* Jabber Timeout */
100 #define TDESC0_FF (1U << 13) /* Frame Flushed */
101 #define TDESC0_PCE (1U << 12) /* Payload Checksum Error */
102 #define TDESC0_LOC (1U << 11) /* Loss of Carrier */
103 #define TDESC0_NC (1U << 10) /* No Carrier */
104 #define TDESC0_LC (1U << 9) /* Late Collision */
105 #define TDESC0_EC (1U << 8) /* Excessive Collision */
106 #define TDESC0_VF (1U << 7) /* VLAN Frame */
107 #define TDESC0_CC_MASK 0xf
108 #define TDESC0_CC_SHIFT 3 /* Collision Count */
109 #define TDESC0_ED (1U << 2) /* Excessive Deferral */
110 #define TDESC0_UF (1U << 1) /* Underflow Error */
111 #define TDESC0_DB (1U << 0) /* Deferred Bit */
112 /* TX descriptors - TDESC0 extended format only */
113 #define ETDESC0_IC (1U << 30) /* Interrupt on Completion */
114 #define ETDESC0_LS (1U << 29) /* Last Segment */
115 #define ETDESC0_FS (1U << 28) /* First Segment */
116 #define ETDESC0_DC (1U << 27) /* Disable CRC */
117 #define ETDESC0_DP (1U << 26) /* Disable Padding */
118 #define ETDESC0_CIC_NONE (0U << 22) /* Checksum Insertion Control */
119 #define ETDESC0_CIC_HDR (1U << 22)
120 #define ETDESC0_CIC_SEG (2U << 22)
121 #define ETDESC0_CIC_FULL (3U << 22)
122 #define ETDESC0_TER (1U << 21) /* Transmit End of Ring */
123 #define ETDESC0_TCH (1U << 20) /* Second Address Chained */
125 /* TX descriptors - TDESC1 normal format */
126 #define NTDESC1_IC (1U << 31) /* Interrupt on Completion */
127 #define NTDESC1_LS (1U << 30) /* Last Segment */
128 #define NTDESC1_FS (1U << 29) /* First Segment */
129 #define NTDESC1_CIC_NONE (0U << 27) /* Checksum Insertion Control */
130 #define NTDESC1_CIC_HDR (1U << 27)
131 #define NTDESC1_CIC_SEG (2U << 27)
132 #define NTDESC1_CIC_FULL (3U << 27)
133 #define NTDESC1_DC (1U << 26) /* Disable CRC */
134 #define NTDESC1_TER (1U << 25) /* Transmit End of Ring */
135 #define NTDESC1_TCH (1U << 24) /* Second Address Chained */
136 /* TX descriptors - TDESC1 extended format */
137 #define ETDESC1_DP (1U << 23) /* Disable Padding */
138 #define ETDESC1_TBS2_MASK 0x7ff
139 #define ETDESC1_TBS2_SHIFT 11 /* Receive Buffer 2 Size */
140 #define ETDESC1_TBS1_MASK 0x7ff
141 #define ETDESC1_TBS1_SHIFT 0 /* Receive Buffer 1 Size */
143 /* RX descriptor - RDESC0 is unified */
144 #define RDESC0_OWN (1U << 31)
145 #define RDESC0_AFM (1U << 30) /* Dest. Address Filter Fail */
146 #define RDESC0_FL_MASK 0x3fff
147 #define RDESC0_FL_SHIFT 16 /* Frame Length */
148 #define RDESC0_ES (1U << 15) /* Error Summary */
149 #define RDESC0_DE (1U << 14) /* Descriptor Error */
150 #define RDESC0_SAF (1U << 13) /* Source Address Filter Fail */
151 #define RDESC0_LE (1U << 12) /* Length Error */
152 #define RDESC0_OE (1U << 11) /* Overflow Error */
153 #define RDESC0_VLAN (1U << 10) /* VLAN Tag */
154 #define RDESC0_FS (1U << 9) /* First Descriptor */
155 #define RDESC0_LS (1U << 8) /* Last Descriptor */
156 #define RDESC0_ICE (1U << 7) /* IPC Checksum Error */
157 #define RDESC0_LC (1U << 6) /* Late Collision */
158 #define RDESC0_FT (1U << 5) /* Frame Type */
159 #define RDESC0_RWT (1U << 4) /* Receive Watchdog Timeout */
160 #define RDESC0_RE (1U << 3) /* Receive Error */
161 #define RDESC0_DBE (1U << 2) /* Dribble Bit Error */
162 #define RDESC0_CE (1U << 1) /* CRC Error */
163 #define RDESC0_PCE (1U << 0) /* Payload Checksum Error */
164 #define RDESC0_RXMA (1U << 0) /* Rx MAC Address */
166 /* RX descriptors - RDESC1 normal format */
167 #define NRDESC1_DIC (1U << 31) /* Disable Intr on Completion */
168 #define NRDESC1_RER (1U << 25) /* Receive End of Ring */
169 #define NRDESC1_RCH (1U << 24) /* Second Address Chained */
170 #define NRDESC1_RBS2_MASK 0x7ff
171 #define NRDESC1_RBS2_SHIFT 11 /* Receive Buffer 2 Size */
172 #define NRDESC1_RBS1_MASK 0x7ff
173 #define NRDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */
175 /* RX descriptors - RDESC1 enhanced format */
176 #define ERDESC1_DIC (1U << 31) /* Disable Intr on Completion */
177 #define ERDESC1_RBS2_MASK 0x7ffff
178 #define ERDESC1_RBS2_SHIFT 16 /* Receive Buffer 2 Size */
179 #define ERDESC1_RER (1U << 15) /* Receive End of Ring */
180 #define ERDESC1_RCH (1U << 14) /* Second Address Chained */
181 #define ERDESC1_RBS1_MASK 0x7ffff
182 #define ERDESC1_RBS1_SHIFT 0 /* Receive Buffer 1 Size */
185 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
186 * layout, but the bits in the fields have different meanings.
192 uint32_t addr1; /* ptr to first buffer data */
193 uint32_t addr2; /* ptr to next descriptor / second buffer data*/
197 struct dwc_hash_maddr_ctx {
198 struct dwc_softc *sc;
203 * The hardware imposes alignment restrictions on various objects involved in
204 * DMA transfers. These values are expressed in bytes (not bits).
206 #define DWC_DESC_RING_ALIGN 2048
208 static struct resource_spec dwc_spec[] = {
209 { SYS_RES_MEMORY, 0, RF_ACTIVE },
210 { SYS_RES_IRQ, 0, RF_ACTIVE },
214 static void dwc_txfinish_locked(struct dwc_softc *sc);
215 static void dwc_rxfinish_locked(struct dwc_softc *sc);
216 static void dwc_stop_locked(struct dwc_softc *sc);
217 static void dwc_setup_rxfilter(struct dwc_softc *sc);
218 static void dwc_setup_core(struct dwc_softc *sc);
219 static void dwc_enable_mac(struct dwc_softc *sc, bool enable);
220 static void dwc_init_dma(struct dwc_softc *sc);
221 static void dwc_stop_dma(struct dwc_softc *sc);
223 static void dwc_tick(void *arg);
225 /* Pause time field in the transmitted control frame */
226 static int dwc_pause_time = 0xffff;
227 TUNABLE_INT("hw.dwc.pause_time", &dwc_pause_time);
234 dwc_miibus_read_reg(device_t dev, int phy, int reg)
236 struct dwc_softc *sc;
241 sc = device_get_softc(dev);
243 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
244 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
245 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
246 | GMII_ADDRESS_GB; /* Busy flag */
248 WRITE4(sc, GMII_ADDRESS, mii);
250 for (cnt = 0; cnt < 1000; cnt++) {
251 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
252 rv = READ4(sc, GMII_DATA);
262 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
264 struct dwc_softc *sc;
268 sc = device_get_softc(dev);
270 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
271 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
272 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
273 | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
275 WRITE4(sc, GMII_DATA, val);
276 WRITE4(sc, GMII_ADDRESS, mii);
278 for (cnt = 0; cnt < 1000; cnt++) {
279 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
289 dwc_miibus_statchg(device_t dev)
291 struct dwc_softc *sc;
292 struct mii_data *mii;
296 * Called by the MII bus driver when the PHY establishes
297 * link to set the MAC interface registers.
300 sc = device_get_softc(dev);
302 DWC_ASSERT_LOCKED(sc);
306 if (mii->mii_media_status & IFM_ACTIVE)
307 sc->link_is_up = true;
309 sc->link_is_up = false;
311 reg = READ4(sc, MAC_CONFIGURATION);
312 switch (IFM_SUBTYPE(mii->mii_media_active)) {
315 reg &= ~(CONF_FES | CONF_PS);
318 reg |= (CONF_FES | CONF_PS);
325 sc->link_is_up = false;
328 sc->link_is_up = false;
329 device_printf(dev, "Unsupported media %u\n",
330 IFM_SUBTYPE(mii->mii_media_active));
333 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
337 WRITE4(sc, MAC_CONFIGURATION, reg);
339 reg = FLOW_CONTROL_UP;
340 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
341 reg |= FLOW_CONTROL_TX;
342 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
343 reg |= FLOW_CONTROL_RX;
344 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
345 reg |= dwc_pause_time << FLOW_CONTROL_PT_SHIFT;
346 WRITE4(sc, FLOW_CONTROL, reg);
348 IF_DWC_SET_SPEED(dev, IFM_SUBTYPE(mii->mii_media_active));
357 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
359 struct dwc_softc *sc;
360 struct mii_data *mii;
366 ifmr->ifm_active = mii->mii_media_active;
367 ifmr->ifm_status = mii->mii_media_status;
372 dwc_media_change_locked(struct dwc_softc *sc)
375 return (mii_mediachg(sc->mii_softc));
379 dwc_media_change(struct ifnet * ifp)
381 struct dwc_softc *sc;
387 error = dwc_media_change_locked(sc);
396 static const uint8_t nibbletab[] = {
397 /* 0x0 0000 -> 0000 */ 0x0,
398 /* 0x1 0001 -> 1000 */ 0x8,
399 /* 0x2 0010 -> 0100 */ 0x4,
400 /* 0x3 0011 -> 1100 */ 0xc,
401 /* 0x4 0100 -> 0010 */ 0x2,
402 /* 0x5 0101 -> 1010 */ 0xa,
403 /* 0x6 0110 -> 0110 */ 0x6,
404 /* 0x7 0111 -> 1110 */ 0xe,
405 /* 0x8 1000 -> 0001 */ 0x1,
406 /* 0x9 1001 -> 1001 */ 0x9,
407 /* 0xa 1010 -> 0101 */ 0x5,
408 /* 0xb 1011 -> 1101 */ 0xd,
409 /* 0xc 1100 -> 0011 */ 0x3,
410 /* 0xd 1101 -> 1011 */ 0xb,
411 /* 0xe 1110 -> 0111 */ 0x7,
412 /* 0xf 1111 -> 1111 */ 0xf, };
415 bitreverse(uint8_t x)
418 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
422 dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
424 struct dwc_hash_maddr_ctx *ctx = arg;
425 uint32_t crc, hashbit, hashreg;
428 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
429 /* Take lower 8 bits and reverse it */
430 val = bitreverse(~crc & 0xff);
431 if (ctx->sc->mactype != DWC_GMAC_EXT_DESC)
432 val >>= 2; /* Only need lower 6 bits */
433 hashreg = (val >> 5);
434 hashbit = (val & 31);
435 ctx->hash[hashreg] |= (1 << hashbit);
441 dwc_setup_rxfilter(struct dwc_softc *sc)
443 struct dwc_hash_maddr_ctx ctx;
446 uint32_t ffval, hi, lo;
449 DWC_ASSERT_LOCKED(sc);
452 nhash = sc->mactype != DWC_GMAC_EXT_DESC ? 2 : 8;
455 * Set the multicast (group) filter hash.
457 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
458 ffval = (FRAME_FILTER_PM);
459 for (i = 0; i < nhash; i++)
462 ffval = (FRAME_FILTER_HMC);
463 for (i = 0; i < nhash; i++)
466 if_foreach_llmaddr(ifp, dwc_hash_maddr, &ctx);
470 * Set the individual address filter hash.
472 if (ifp->if_flags & IFF_PROMISC)
473 ffval |= (FRAME_FILTER_PR);
476 * Set the primary address.
478 eaddr = IF_LLADDR(ifp);
479 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
481 hi = eaddr[4] | (eaddr[5] << 8);
482 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
483 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
484 WRITE4(sc, MAC_FRAME_FILTER, ffval);
485 if (sc->mactype != DWC_GMAC_EXT_DESC) {
486 WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);
487 WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);
489 for (i = 0; i < nhash; i++)
490 WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]);
495 dwc_setup_core(struct dwc_softc *sc)
499 DWC_ASSERT_LOCKED(sc);
502 reg = READ4(sc, MAC_CONFIGURATION);
503 reg |= (CONF_JD | CONF_ACS | CONF_BE);
504 WRITE4(sc, MAC_CONFIGURATION, reg);
508 dwc_enable_mac(struct dwc_softc *sc, bool enable)
512 DWC_ASSERT_LOCKED(sc);
513 reg = READ4(sc, MAC_CONFIGURATION);
515 reg |= CONF_TE | CONF_RE;
517 reg &= ~(CONF_TE | CONF_RE);
518 WRITE4(sc, MAC_CONFIGURATION, reg);
522 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
524 uint32_t hi, lo, rnd;
527 * Try to recover a MAC address from the running hardware. If there's
528 * something non-zero there, assume the bootloader did the right thing
531 * Otherwise, set the address to a convenient locally assigned address,
532 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
533 * assigned bit set, and the broadcast/multicast bit clear.
535 lo = READ4(sc, MAC_ADDRESS_LOW(0));
536 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
537 if ((lo != 0xffffffff) || (hi != 0xffff)) {
538 hwaddr[0] = (lo >> 0) & 0xff;
539 hwaddr[1] = (lo >> 8) & 0xff;
540 hwaddr[2] = (lo >> 16) & 0xff;
541 hwaddr[3] = (lo >> 24) & 0xff;
542 hwaddr[4] = (hi >> 0) & 0xff;
543 hwaddr[5] = (hi >> 8) & 0xff;
545 rnd = arc4random() & 0x00ffffff;
549 hwaddr[3] = rnd >> 16;
550 hwaddr[4] = rnd >> 8;
551 hwaddr[5] = rnd >> 0;
560 dwc_init_dma(struct dwc_softc *sc)
564 DWC_ASSERT_LOCKED(sc);
566 /* Initializa DMA and enable transmitters */
567 reg = READ4(sc, OPERATION_MODE);
568 reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
570 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
571 WRITE4(sc, OPERATION_MODE, reg);
573 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
576 reg = READ4(sc, OPERATION_MODE);
577 reg |= (MODE_ST | MODE_SR);
578 WRITE4(sc, OPERATION_MODE, reg);
582 dwc_stop_dma(struct dwc_softc *sc)
586 DWC_ASSERT_LOCKED(sc);
589 reg = READ4(sc, OPERATION_MODE);
591 WRITE4(sc, OPERATION_MODE, reg);
594 reg = READ4(sc, OPERATION_MODE);
596 WRITE4(sc, OPERATION_MODE, reg);
599 reg = READ4(sc, OPERATION_MODE);
601 WRITE4(sc, OPERATION_MODE, reg);
604 static inline uint32_t
605 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
608 return ((curidx + 1) % RX_DESC_COUNT);
611 static inline uint32_t
612 next_txidx(struct dwc_softc *sc, uint32_t curidx)
615 return ((curidx + 1) % TX_DESC_COUNT);
619 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
624 *(bus_addr_t *)arg = segs[0].ds_addr;
628 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
629 uint32_t len, uint32_t flags, bool first, bool last)
631 uint32_t desc0, desc1;
633 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
634 if (paddr == 0 || len == 0) {
639 if (sc->mactype != DWC_GMAC_EXT_DESC) {
641 desc1 = NTDESC1_TCH | len | flags;
645 desc1 |= NTDESC1_LS | NTDESC1_IC;
647 desc0 = ETDESC0_TCH | flags;
651 desc0 |= ETDESC0_LS | ETDESC0_IC;
657 sc->txdesc_ring[idx].addr1 = (uint32_t)(paddr);
658 sc->txdesc_ring[idx].desc0 = desc0;
659 sc->txdesc_ring[idx].desc1 = desc1;
663 dwc_set_owner(struct dwc_softc *sc, int idx)
666 sc->txdesc_ring[idx].desc0 |= TDESC0_OWN;
671 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
673 struct bus_dma_segment segs[TX_MAP_MAX_SEGS];
680 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
681 *mp, segs, &nsegs, 0);
682 if (error == EFBIG) {
684 * The map may be partially mapped from the first call.
685 * Make sure to reset it.
687 bus_dmamap_unload(sc->txbuf_tag, sc->txbuf_map[idx].map);
688 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
691 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
692 *mp, segs, &nsegs, 0);
697 if (sc->tx_desccount + nsegs > TX_DESC_COUNT) {
698 bus_dmamap_unload(sc->txbuf_tag, sc->txbuf_map[idx].map);
704 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
705 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) {
706 if (sc->mactype != DWC_GMAC_EXT_DESC)
707 flags = NTDESC1_CIC_FULL;
709 flags = ETDESC0_CIC_FULL;
711 if (sc->mactype != DWC_GMAC_EXT_DESC)
712 flags = NTDESC1_CIC_HDR;
714 flags = ETDESC0_CIC_HDR;
718 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
719 BUS_DMASYNC_PREWRITE);
721 sc->txbuf_map[idx].mbuf = m;
723 first = sc->tx_desc_head;
724 for (i = 0; i < nsegs; i++) {
725 dwc_setup_txdesc(sc, sc->tx_desc_head,
726 segs[i].ds_addr, segs[i].ds_len,
727 (i == 0) ? flags : 0, /* only first desc needs flags */
731 dwc_set_owner(sc, sc->tx_desc_head);
732 last = sc->tx_desc_head;
733 sc->tx_desc_head = next_txidx(sc, sc->tx_desc_head);
736 sc->txbuf_map[idx].last_desc_idx = last;
738 dwc_set_owner(sc, first);
743 inline static uint32_t
744 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
748 sc->rxdesc_ring[idx].addr1 = (uint32_t)paddr;
749 nidx = next_rxidx(sc, idx);
750 sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr +
751 (nidx * sizeof(struct dwc_hwdesc));
752 if (sc->mactype != DWC_GMAC_EXT_DESC)
753 sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH |
754 MIN(MCLBYTES, NRDESC1_RBS1_MASK);
756 sc->rxdesc_ring[idx].desc1 = ERDESC1_RCH |
757 MIN(MCLBYTES, ERDESC1_RBS1_MASK);
760 sc->rxdesc_ring[idx].desc0 = RDESC0_OWN;
766 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
768 struct bus_dma_segment seg;
771 m_adj(m, ETHER_ALIGN);
773 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
778 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
780 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
781 BUS_DMASYNC_PREREAD);
783 sc->rxbuf_map[idx].mbuf = m;
784 dwc_setup_rxdesc(sc, idx, seg.ds_addr);
790 dwc_alloc_mbufcl(struct dwc_softc *sc)
794 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
796 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
802 dwc_rxfinish_one(struct dwc_softc *sc, struct dwc_hwdesc *desc,
803 struct dwc_bufmap *map)
812 rdesc0 = desc ->desc0;
813 /* Validate descriptor. */
814 if (rdesc0 & RDESC0_ES) {
816 * Errored packet. Statistic counters are updated
817 * globally, so do nothing
822 if ((rdesc0 & (RDESC0_FS | RDESC0_LS)) !=
823 (RDESC0_FS | RDESC0_LS)) {
825 * Something very wrong happens. The whole packet should be
826 * recevied in one descriptr. Report problem.
828 device_printf(sc->dev,
829 "%s: RX descriptor without FIRST and LAST bit set: 0x%08X",
834 len = (rdesc0 >> RDESC0_FL_SHIFT) & RDESC0_FL_MASK;
837 * Lenght is invalid, recycle old mbuf
838 * Probably impossible case
843 /* Allocate new buffer */
844 m0 = dwc_alloc_mbufcl(sc);
846 /* no new mbuf available, recycle old */
847 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
850 /* Do dmasync for newly received packet */
851 bus_dmamap_sync(sc->rxbuf_tag, map->map, BUS_DMASYNC_POSTREAD);
852 bus_dmamap_unload(sc->rxbuf_tag, map->map);
854 /* Received packet is valid, process it */
855 m->m_pkthdr.rcvif = ifp;
856 m->m_pkthdr.len = len;
858 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
860 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
861 (rdesc0 & RDESC0_FT) != 0) {
862 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
863 if ((rdesc0 & RDESC0_ICE) == 0)
864 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
865 if ((rdesc0 & RDESC0_PCE) == 0) {
866 m->m_pkthdr.csum_flags |=
867 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
868 m->m_pkthdr.csum_data = 0xffff;
872 /* Remove trailing FCS */
873 m_adj(m, -ETHER_CRC_LEN);
876 (*ifp->if_input)(ifp, m);
882 setup_dma(struct dwc_softc *sc)
890 * Set up TX descriptor ring, descriptors, and dma maps.
892 error = bus_dma_tag_create(
893 bus_get_dma_tag(sc->dev), /* Parent tag. */
894 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
895 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
896 BUS_SPACE_MAXADDR, /* highaddr */
897 NULL, NULL, /* filter, filterarg */
898 TX_DESC_SIZE, 1, /* maxsize, nsegments */
899 TX_DESC_SIZE, /* maxsegsize */
901 NULL, NULL, /* lockfunc, lockarg */
904 device_printf(sc->dev,
905 "could not create TX ring DMA tag.\n");
909 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
910 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
913 device_printf(sc->dev,
914 "could not allocate TX descriptor ring.\n");
918 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
919 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
920 &sc->txdesc_ring_paddr, 0);
922 device_printf(sc->dev,
923 "could not load TX descriptor ring map.\n");
927 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
928 nidx = next_txidx(sc, idx);
929 sc->txdesc_ring[idx].addr2 = sc->txdesc_ring_paddr +
930 (nidx * sizeof(struct dwc_hwdesc));
933 error = bus_dma_tag_create(
934 bus_get_dma_tag(sc->dev), /* Parent tag. */
935 1, 0, /* alignment, boundary */
936 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
937 BUS_SPACE_MAXADDR, /* highaddr */
938 NULL, NULL, /* filter, filterarg */
939 MCLBYTES*TX_MAP_MAX_SEGS, /* maxsize */
940 TX_MAP_MAX_SEGS, /* nsegments */
941 MCLBYTES, /* maxsegsize */
943 NULL, NULL, /* lockfunc, lockarg */
946 device_printf(sc->dev,
947 "could not create TX ring DMA tag.\n");
951 for (idx = 0; idx < TX_MAP_COUNT; idx++) {
952 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
953 &sc->txbuf_map[idx].map);
955 device_printf(sc->dev,
956 "could not create TX buffer DMA map.\n");
961 for (idx = 0; idx < TX_DESC_COUNT; idx++)
962 dwc_setup_txdesc(sc, idx, 0, 0, 0, false, false);
965 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
967 error = bus_dma_tag_create(
968 bus_get_dma_tag(sc->dev), /* Parent tag. */
969 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
970 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
971 BUS_SPACE_MAXADDR, /* highaddr */
972 NULL, NULL, /* filter, filterarg */
973 RX_DESC_SIZE, 1, /* maxsize, nsegments */
974 RX_DESC_SIZE, /* maxsegsize */
976 NULL, NULL, /* lockfunc, lockarg */
979 device_printf(sc->dev,
980 "could not create RX ring DMA tag.\n");
984 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
985 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
988 device_printf(sc->dev,
989 "could not allocate RX descriptor ring.\n");
993 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
994 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
995 &sc->rxdesc_ring_paddr, 0);
997 device_printf(sc->dev,
998 "could not load RX descriptor ring map.\n");
1002 error = bus_dma_tag_create(
1003 bus_get_dma_tag(sc->dev), /* Parent tag. */
1004 1, 0, /* alignment, boundary */
1005 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1006 BUS_SPACE_MAXADDR, /* highaddr */
1007 NULL, NULL, /* filter, filterarg */
1008 MCLBYTES, 1, /* maxsize, nsegments */
1009 MCLBYTES, /* maxsegsize */
1011 NULL, NULL, /* lockfunc, lockarg */
1014 device_printf(sc->dev,
1015 "could not create RX buf DMA tag.\n");
1019 for (idx = 0; idx < RX_DESC_COUNT; idx++) {
1020 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
1021 &sc->rxbuf_map[idx].map);
1023 device_printf(sc->dev,
1024 "could not create RX buffer DMA map.\n");
1027 if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
1028 device_printf(sc->dev, "Could not alloc mbuf\n");
1032 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
1033 device_printf(sc->dev,
1034 "could not create new RX buffer.\n");
1051 dwc_txstart_locked(struct dwc_softc *sc)
1057 DWC_ASSERT_LOCKED(sc);
1059 if (!sc->link_is_up)
1064 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1071 if (sc->tx_desccount > (TX_DESC_COUNT - TX_MAP_MAX_SEGS + 1)) {
1072 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1076 if (sc->tx_mapcount == (TX_MAP_COUNT - 1)) {
1077 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1081 m = if_dequeue(ifp);
1084 if (dwc_setup_txbuf(sc, sc->tx_map_head, &m) != 0) {
1085 if_sendq_prepend(ifp, m);
1086 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1090 sc->tx_map_head = next_txidx(sc, sc->tx_map_head);
1095 if (enqueued != 0) {
1096 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
1097 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
1102 dwc_txstart(struct ifnet *ifp)
1104 struct dwc_softc *sc = ifp->if_softc;
1107 dwc_txstart_locked(sc);
1112 dwc_init_locked(struct dwc_softc *sc)
1114 struct ifnet *ifp = sc->ifp;
1116 DWC_ASSERT_LOCKED(sc);
1118 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1121 dwc_setup_rxfilter(sc);
1123 dwc_enable_mac(sc, true);
1126 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1129 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
1130 * to set up the remaining config registers based on current media.
1132 mii_mediachg(sc->mii_softc);
1133 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
1137 dwc_init(void *if_softc)
1139 struct dwc_softc *sc = if_softc;
1142 dwc_init_locked(sc);
1147 dwc_stop_locked(struct dwc_softc *sc)
1151 DWC_ASSERT_LOCKED(sc);
1154 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1155 sc->tx_watchdog_count = 0;
1156 sc->stats_harvest_count = 0;
1158 callout_stop(&sc->dwc_callout);
1161 dwc_enable_mac(sc, false);
1165 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1167 struct dwc_softc *sc;
1168 struct mii_data *mii;
1170 int flags, mask, error;
1173 ifr = (struct ifreq *)data;
1179 if (if_getflags(ifp) & IFF_UP) {
1180 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1181 flags = if_getflags(ifp) ^ sc->if_flags;
1182 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1183 dwc_setup_rxfilter(sc);
1185 if (!sc->is_detaching)
1186 dwc_init_locked(sc);
1189 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1190 dwc_stop_locked(sc);
1192 sc->if_flags = if_getflags(ifp);
1197 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1199 dwc_setup_rxfilter(sc);
1205 mii = sc->mii_softc;
1206 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1209 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1210 if (mask & IFCAP_VLAN_MTU) {
1211 /* No work to do except acknowledge the change took */
1212 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1214 if (mask & IFCAP_RXCSUM)
1215 if_togglecapenable(ifp, IFCAP_RXCSUM);
1216 if (mask & IFCAP_TXCSUM)
1217 if_togglecapenable(ifp, IFCAP_TXCSUM);
1218 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1219 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1221 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1225 error = ether_ioctl(ifp, cmd, data);
1233 * Interrupts functions
1237 dwc_txfinish_locked(struct dwc_softc *sc)
1239 struct dwc_bufmap *bmap;
1240 struct dwc_hwdesc *desc;
1245 DWC_ASSERT_LOCKED(sc);
1248 /* check if all descriptors of the map are done */
1249 while (sc->tx_map_tail != sc->tx_map_head) {
1250 map_finished = true;
1251 bmap = &sc->txbuf_map[sc->tx_map_tail];
1252 idx = sc->tx_desc_tail;
1253 last_idx = next_txidx(sc, bmap->last_desc_idx);
1254 while (idx != last_idx) {
1255 desc = &sc->txdesc_ring[idx];
1256 if ((desc->desc0 & TDESC0_OWN) != 0) {
1257 map_finished = false;
1260 idx = next_txidx(sc, idx);
1265 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
1266 BUS_DMASYNC_POSTWRITE);
1267 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1268 m_freem(bmap->mbuf);
1271 while (sc->tx_desc_tail != last_idx) {
1272 dwc_setup_txdesc(sc, sc->tx_desc_tail, 0, 0, 0, false, false);
1273 sc->tx_desc_tail = next_txidx(sc, sc->tx_desc_tail);
1275 sc->tx_map_tail = next_txidx(sc, sc->tx_map_tail);
1276 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1277 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1280 /* If there are no buffers outstanding, muzzle the watchdog. */
1281 if (sc->tx_desc_tail == sc->tx_desc_head) {
1282 sc->tx_watchdog_count = 0;
1287 dwc_rxfinish_locked(struct dwc_softc *sc)
1291 struct dwc_hwdesc *desc;
1293 DWC_ASSERT_LOCKED(sc);
1296 desc = sc->rxdesc_ring + idx;
1297 if ((desc->desc0 & RDESC0_OWN) != 0)
1300 m = dwc_rxfinish_one(sc, desc, sc->rxbuf_map + idx);
1303 desc->desc0 = RDESC0_OWN;
1306 /* We cannot create hole in RX ring */
1307 error = dwc_setup_rxbuf(sc, idx, m);
1309 panic("dwc_setup_rxbuf failed: error %d\n",
1313 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
1320 struct dwc_softc *sc;
1327 reg = READ4(sc, INTERRUPT_STATUS);
1329 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
1331 reg = READ4(sc, DMA_STATUS);
1332 if (reg & DMA_STATUS_NIS) {
1333 if (reg & DMA_STATUS_RI)
1334 dwc_rxfinish_locked(sc);
1336 if (reg & DMA_STATUS_TI) {
1337 dwc_txfinish_locked(sc);
1338 dwc_txstart_locked(sc);
1342 if (reg & DMA_STATUS_AIS) {
1343 if (reg & DMA_STATUS_FBI) {
1344 /* Fatal bus error */
1345 device_printf(sc->dev,
1346 "Ethernet DMA error, restarting controller.\n");
1347 dwc_stop_locked(sc);
1348 dwc_init_locked(sc);
1352 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
1360 static void dwc_clear_stats(struct dwc_softc *sc)
1364 reg = READ4(sc, MMC_CONTROL);
1365 reg |= (MMC_CONTROL_CNTRST);
1366 WRITE4(sc, MMC_CONTROL, reg);
1370 dwc_harvest_stats(struct dwc_softc *sc)
1374 /* We don't need to harvest too often. */
1375 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
1378 sc->stats_harvest_count = 0;
1381 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
1382 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
1383 if_inc_counter(ifp, IFCOUNTER_IERRORS,
1384 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
1385 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
1386 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
1387 READ4(sc, RXLENGTHERROR));
1389 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
1390 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
1391 if_inc_counter(ifp, IFCOUNTER_OERRORS,
1392 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
1393 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
1395 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1396 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
1398 dwc_clear_stats(sc);
1404 struct dwc_softc *sc;
1410 DWC_ASSERT_LOCKED(sc);
1414 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1418 * Typical tx watchdog. If this fires it indicates that we enqueued
1419 * packets for output and never got a txdone interrupt for them. Maybe
1420 * it's a missed interrupt somehow, just pretend we got one.
1422 if (sc->tx_watchdog_count > 0) {
1423 if (--sc->tx_watchdog_count == 0) {
1424 dwc_txfinish_locked(sc);
1428 /* Gather stats from hardware counters. */
1429 dwc_harvest_stats(sc);
1431 /* Check the media status. */
1432 link_was_up = sc->link_is_up;
1433 mii_tick(sc->mii_softc);
1434 if (sc->link_is_up && !link_was_up)
1435 dwc_txstart_locked(sc);
1437 /* Schedule another check one second from now. */
1438 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
1442 * Probe/Attach functions
1445 #define GPIO_ACTIVE_LOW 1
1448 dwc_reset(device_t dev)
1450 pcell_t gpio_prop[4];
1451 pcell_t delay_prop[3];
1452 phandle_t node, gpio_node;
1454 uint32_t pin, flags;
1457 node = ofw_bus_get_node(dev);
1458 if (OF_getencprop(node, "snps,reset-gpio",
1459 gpio_prop, sizeof(gpio_prop)) <= 0)
1462 if (OF_getencprop(node, "snps,reset-delays-us",
1463 delay_prop, sizeof(delay_prop)) <= 0) {
1465 "Wrong property for snps,reset-delays-us");
1469 gpio_node = OF_node_from_xref(gpio_prop[0]);
1470 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
1472 "Can't find gpio controller for phy reset\n");
1476 if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
1477 nitems(gpio_prop) - 1,
1478 gpio_prop + 1, &pin, &flags) != 0) {
1479 device_printf(dev, "Can't map gpio for phy reset\n");
1483 pin_value = GPIO_PIN_LOW;
1484 if (OF_hasprop(node, "snps,reset-active-low"))
1485 pin_value = GPIO_PIN_HIGH;
1487 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1488 GPIO_PIN_SET(gpio, pin, pin_value);
1489 DELAY(delay_prop[0] * 5);
1490 GPIO_PIN_SET(gpio, pin, !pin_value);
1491 DELAY(delay_prop[1] * 5);
1492 GPIO_PIN_SET(gpio, pin, pin_value);
1493 DELAY(delay_prop[2] * 5);
1499 dwc_clock_init(device_t dev)
1507 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
1508 error = clk_enable(clk);
1510 device_printf(dev, "could not enable main clock\n");
1514 clk_get_freq(clk, &freq);
1515 device_printf(dev, "MAC clock(%s) freq: %jd\n",
1516 clk_get_name(clk), (intmax_t)freq);
1520 device_printf(dev, "could not find clock stmmaceth\n");
1523 /* De-assert reset */
1524 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
1525 error = hwreset_deassert(rst);
1527 device_printf(dev, "could not de-assert reset\n");
1536 dwc_probe(device_t dev)
1539 if (!ofw_bus_status_okay(dev))
1542 if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1545 device_set_desc(dev, "Gigabit Ethernet Controller");
1546 return (BUS_PROBE_DEFAULT);
1550 dwc_attach(device_t dev)
1552 uint8_t macaddr[ETHER_ADDR_LEN];
1553 struct dwc_softc *sc;
1558 uint32_t txpbl, rxpbl, pbl;
1559 bool nopblx8 = false;
1560 bool fixed_burst = false;
1562 sc = device_get_softc(dev);
1565 sc->tx_desccount = TX_DESC_COUNT;
1566 sc->tx_mapcount = 0;
1567 sc->mii_clk = IF_DWC_MII_CLK(dev);
1568 sc->mactype = IF_DWC_MAC_TYPE(dev);
1570 node = ofw_bus_get_node(dev);
1571 switch (mii_fdt_get_contype(node)) {
1572 case MII_CONTYPE_RGMII:
1573 case MII_CONTYPE_RGMII_ID:
1574 case MII_CONTYPE_RGMII_RXID:
1575 case MII_CONTYPE_RGMII_TXID:
1576 sc->phy_mode = PHY_MODE_RGMII;
1578 case MII_CONTYPE_RMII:
1579 sc->phy_mode = PHY_MODE_RMII;
1582 device_printf(dev, "Unsupported MII type\n");
1586 if (OF_getencprop(node, "snps,pbl", &pbl, sizeof(uint32_t)) <= 0)
1587 pbl = BUS_MODE_DEFAULT_PBL;
1588 if (OF_getencprop(node, "snps,txpbl", &txpbl, sizeof(uint32_t)) <= 0)
1590 if (OF_getencprop(node, "snps,rxpbl", &rxpbl, sizeof(uint32_t)) <= 0)
1592 if (OF_hasprop(node, "snps,no-pbl-x8") == 1)
1594 if (OF_hasprop(node, "snps,fixed-burst") == 1)
1597 if (IF_DWC_INIT(dev) != 0)
1600 if (dwc_clock_init(dev) != 0)
1603 if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1604 device_printf(dev, "could not allocate resources\n");
1608 /* Read MAC before reset */
1609 dwc_get_hwaddr(sc, macaddr);
1611 /* Reset the PHY if needed */
1612 if (dwc_reset(dev) != 0) {
1613 device_printf(dev, "Can't reset the PHY\n");
1614 bus_release_resources(dev, dwc_spec, sc->res);
1619 reg = READ4(sc, BUS_MODE);
1620 reg |= (BUS_MODE_SWR);
1621 WRITE4(sc, BUS_MODE, reg);
1623 for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1624 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1628 if (i >= MAC_RESET_TIMEOUT) {
1629 device_printf(sc->dev, "Can't reset DWC.\n");
1630 bus_release_resources(dev, dwc_spec, sc->res);
1636 reg |= BUS_MODE_EIGHTXPBL;
1637 reg |= (txpbl << BUS_MODE_PBL_SHIFT);
1638 reg |= (rxpbl << BUS_MODE_RPBL_SHIFT);
1640 reg |= BUS_MODE_FIXEDBURST;
1642 WRITE4(sc, BUS_MODE, reg);
1645 * DMA must be stop while changing descriptor list addresses.
1647 reg = READ4(sc, OPERATION_MODE);
1648 reg &= ~(MODE_ST | MODE_SR);
1649 WRITE4(sc, OPERATION_MODE, reg);
1651 if (setup_dma(sc)) {
1652 bus_release_resources(dev, dwc_spec, sc->res);
1656 /* Setup addresses */
1657 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1658 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1660 mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1661 MTX_NETWORK_LOCK, MTX_DEF);
1663 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1665 /* Setup interrupt handler. */
1666 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1667 NULL, dwc_intr, sc, &sc->intr_cookie);
1669 device_printf(dev, "could not setup interrupt handler.\n");
1670 bus_release_resources(dev, dwc_spec, sc->res);
1674 /* Set up the ethernet interface. */
1675 sc->ifp = ifp = if_alloc(IFT_ETHER);
1678 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1679 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1680 if_setstartfn(ifp, dwc_txstart);
1681 if_setioctlfn(ifp, dwc_ioctl);
1682 if_setinitfn(ifp, dwc_init);
1683 if_setsendqlen(ifp, TX_MAP_COUNT - 1);
1684 if_setsendqready(sc->ifp);
1685 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1686 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1687 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1689 /* Attach the mii driver. */
1690 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1691 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1695 device_printf(dev, "PHY attach failed\n");
1696 bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
1697 bus_release_resources(dev, dwc_spec, sc->res);
1700 sc->mii_softc = device_get_softc(sc->miibus);
1702 /* All ready to run, attach the ethernet interface. */
1703 ether_ifattach(ifp, macaddr);
1704 sc->is_attached = true;
1709 static device_method_t dwc_methods[] = {
1710 DEVMETHOD(device_probe, dwc_probe),
1711 DEVMETHOD(device_attach, dwc_attach),
1714 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg),
1715 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg),
1716 DEVMETHOD(miibus_statchg, dwc_miibus_statchg),
1721 driver_t dwc_driver = {
1724 sizeof(struct dwc_softc),
1727 static devclass_t dwc_devclass;
1729 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1730 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1732 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1733 MODULE_DEPEND(dwc, miibus, 1, 1, 1);