2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Register names were taken almost as is from the documentation.
40 #define MAC_CONFIGURATION 0x0
41 #define CONF_JD (1 << 22) /* jabber timer disable */
42 #define CONF_BE (1 << 21) /* Frame Burst Enable */
43 #define CONF_PS (1 << 15) /* GMII/MII */
44 #define CONF_FES (1 << 14) /* MII speed select */
45 #define CONF_DM (1 << 11) /* Full Duplex Enable */
46 #define CONF_ACS (1 << 7)
47 #define CONF_TE (1 << 3)
48 #define CONF_RE (1 << 2)
49 #define MAC_FRAME_FILTER 0x4
50 #define FRAME_FILTER_RA (1U << 31) /* Receive All */
51 #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */
52 #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */
53 #define FRAME_FILTER_HMC (1 << 2)
54 #define FRAME_FILTER_HUC (1 << 1)
55 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
56 #define GMAC_MAC_HTHIGH 0x08
57 #define GMAC_MAC_HTLOW 0x0c
58 #define GMII_ADDRESS 0x10
59 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
60 #define GMII_ADDRESS_PA_SHIFT 11
61 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
62 #define GMII_ADDRESS_GR_SHIFT 6
63 #define GMII_ADDRESS_CR_MASK 0xf
64 #define GMII_ADDRESS_CR_SHIFT 2 /* Clock */
65 #define GMII_ADDRESS_GW (1 << 1) /* Write operation */
66 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
67 #define GMII_DATA 0x14
68 #define FLOW_CONTROL 0x18
69 #define GMAC_VLAN_TAG 0x1C
72 #define LPI_CONTROL_STATUS 0x30
73 #define LPI_TIMERS_CONTROL 0x34
74 #define INTERRUPT_STATUS 0x38
75 #define INTERRUPT_MASK 0x3C
76 #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n)
77 #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n)
79 #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8
80 #define MMC_CONTROL 0x100
81 #define MMC_CONTROL_CNTRST (1 << 0)
82 #define MMC_RECEIVE_INTERRUPT 0x104
83 #define MMC_TRANSMIT_INTERRUPT 0x108
84 #define MMC_RECEIVE_INTERRUPT_MASK 0x10C
85 #define MMC_TRANSMIT_INTERRUPT_MASK 0x110
86 #define TXOCTETCOUNT_GB 0x114
87 #define TXFRAMECOUNT_GB 0x118
88 #define TXBROADCASTFRAMES_G 0x11C
89 #define TXMULTICASTFRAMES_G 0x120
90 #define TX64OCTETS_GB 0x124
91 #define TX65TO127OCTETS_GB 0x128
92 #define TX128TO255OCTETS_GB 0x12C
93 #define TX256TO511OCTETS_GB 0x130
94 #define TX512TO1023OCTETS_GB 0x134
95 #define TX1024TOMAXOCTETS_GB 0x138
96 #define TXUNICASTFRAMES_GB 0x13C
97 #define TXMULTICASTFRAMES_GB 0x140
98 #define TXBROADCASTFRAMES_GB 0x144
99 #define TXUNDERFLOWERROR 0x148
100 #define TXSINGLECOL_G 0x14C
101 #define TXMULTICOL_G 0x150
102 #define TXDEFERRED 0x154
103 #define TXLATECOL 0x158
104 #define TXEXESSCOL 0x15C
105 #define TXCARRIERERR 0x160
106 #define TXOCTETCNT 0x164
107 #define TXFRAMECOUNT_G 0x168
108 #define TXEXCESSDEF 0x16C
109 #define TXPAUSEFRAMES 0x170
110 #define TXVLANFRAMES_G 0x174
111 #define TXOVERSIZE_G 0x178
112 #define RXFRAMECOUNT_GB 0x180
113 #define RXOCTETCOUNT_GB 0x184
114 #define RXOCTETCOUNT_G 0x188
115 #define RXBROADCASTFRAMES_G 0x18C
116 #define RXMULTICASTFRAMES_G 0x190
117 #define RXCRCERROR 0x194
118 #define RXALIGNMENTERROR 0x198
119 #define RXRUNTERROR 0x19C
120 #define RXJABBERERROR 0x1A0
121 #define RXUNDERSIZE_G 0x1A4
122 #define RXOVERSIZE_G 0x1A8
123 #define RX64OCTETS_GB 0x1AC
124 #define RX65TO127OCTETS_GB 0x1B0
125 #define RX128TO255OCTETS_GB 0x1B4
126 #define RX256TO511OCTETS_GB 0x1B8
127 #define RX512TO1023OCTETS_GB 0x1BC
128 #define RX1024TOMAXOCTETS_GB 0x1C0
129 #define RXUNICASTFRAMES_G 0x1C4
130 #define RXLENGTHERROR 0x1C8
131 #define RXOUTOFRANGETYPE 0x1CC
132 #define RXPAUSEFRAMES 0x1D0
133 #define RXFIFOOVERFLOW 0x1D4
134 #define RXVLANFRAMES_GB 0x1D8
135 #define RXWATCHDOGERROR 0x1DC
136 #define RXRCVERROR 0x1E0
137 #define RXCTRLFRAMES_G 0x1E4
138 #define MMC_IPC_RECEIVE_INT_MASK 0x200
139 #define MMC_IPC_RECEIVE_INT 0x208
140 #define RXIPV4_GD_FRMS 0x210
141 #define RXIPV4_HDRERR_FRMS 0x214
142 #define RXIPV4_NOPAY_FRMS 0x218
143 #define RXIPV4_FRAG_FRMS 0x21C
144 #define RXIPV4_UDSBL_FRMS 0x220
145 #define RXIPV6_GD_FRMS 0x224
146 #define RXIPV6_HDRERR_FRMS 0x228
147 #define RXIPV6_NOPAY_FRMS 0x22C
148 #define RXUDP_GD_FRMS 0x230
149 #define RXUDP_ERR_FRMS 0x234
150 #define RXTCP_GD_FRMS 0x238
151 #define RXTCP_ERR_FRMS 0x23C
152 #define RXICMP_GD_FRMS 0x240
153 #define RXICMP_ERR_FRMS 0x244
154 #define RXIPV4_GD_OCTETS 0x250
155 #define RXIPV4_HDRERR_OCTETS 0x254
156 #define RXIPV4_NOPAY_OCTETS 0x258
157 #define RXIPV4_FRAG_OCTETS 0x25C
158 #define RXIPV4_UDSBL_OCTETS 0x260
159 #define RXIPV6_GD_OCTETS 0x264
160 #define RXIPV6_HDRERR_OCTETS 0x268
161 #define RXIPV6_NOPAY_OCTETS 0x26C
162 #define RXUDP_GD_OCTETS 0x270
163 #define RXUDP_ERR_OCTETS 0x274
164 #define RXTCP_GD_OCTETS 0x278
165 #define RXTCPERROCTETS 0x27C
166 #define RXICMP_GD_OCTETS 0x280
167 #define RXICMP_ERR_OCTETS 0x284
168 #define L3_L4_CONTROL0 0x400
169 #define LAYER4_ADDRESS0 0x404
170 #define LAYER3_ADDR0_REG0 0x410
171 #define LAYER3_ADDR1_REG0 0x414
172 #define LAYER3_ADDR2_REG0 0x418
173 #define LAYER3_ADDR3_REG0 0x41C
174 #define L3_L4_CONTROL1 0x430
175 #define LAYER4_ADDRESS1 0x434
176 #define LAYER3_ADDR0_REG1 0x440
177 #define LAYER3_ADDR1_REG1 0x444
178 #define LAYER3_ADDR2_REG1 0x448
179 #define LAYER3_ADDR3_REG1 0x44C
180 #define L3_L4_CONTROL2 0x460
181 #define LAYER4_ADDRESS2 0x464
182 #define LAYER3_ADDR0_REG2 0x470
183 #define LAYER3_ADDR1_REG2 0x474
184 #define LAYER3_ADDR2_REG2 0x478
185 #define LAYER3_ADDR3_REG2 0x47C
186 #define L3_L4_CONTROL3 0x490
187 #define LAYER4_ADDRESS3 0x494
188 #define LAYER3_ADDR0_REG3 0x4A0
189 #define LAYER3_ADDR1_REG3 0x4A4
190 #define LAYER3_ADDR2_REG3 0x4A8
191 #define LAYER3_ADDR3_REG3 0x4AC
192 #define HASH_TABLE_REG(n) 0x500 + (0x4 * n)
193 #define VLAN_INCL_REG 0x584
194 #define VLAN_HASH_TABLE_REG 0x588
195 #define TIMESTAMP_CONTROL 0x700
196 #define SUB_SECOND_INCREMENT 0x704
197 #define SYSTEM_TIME_SECONDS 0x708
198 #define SYSTEM_TIME_NANOSECONDS 0x70C
199 #define SYSTEM_TIME_SECONDS_UPDATE 0x710
200 #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714
201 #define TIMESTAMP_ADDEND 0x718
202 #define TARGET_TIME_SECONDS 0x71C
203 #define TARGET_TIME_NANOSECONDS 0x720
204 #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724
205 #define TIMESTAMP_STATUS 0x728
206 #define PPS_CONTROL 0x72C
207 #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730
208 #define AUXILIARY_TIMESTAMP_SECONDS 0x734
209 #define PPS0_INTERVAL 0x760
210 #define PPS0_WIDTH 0x764
213 #define BUS_MODE 0x1000
214 #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */
215 #define BUS_MODE_FIXEDBURST (1 << 16)
216 #define BUS_MODE_PRIORXTX_SHIFT 14
217 #define BUS_MODE_PRIORXTX_41 3
218 #define BUS_MODE_PRIORXTX_31 2
219 #define BUS_MODE_PRIORXTX_21 1
220 #define BUS_MODE_PRIORXTX_11 0
221 #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */
222 #define BUS_MODE_PBL_BEATS_8 8
223 #define BUS_MODE_SWR (1 << 0) /* Reset */
224 #define TRANSMIT_POLL_DEMAND 0x1004
225 #define RECEIVE_POLL_DEMAND 0x1008
226 #define RX_DESCR_LIST_ADDR 0x100C
227 #define TX_DESCR_LIST_ADDR 0x1010
228 #define DMA_STATUS 0x1014
229 #define DMA_STATUS_NIS (1 << 16)
230 #define DMA_STATUS_AIS (1 << 15)
231 #define DMA_STATUS_FBI (1 << 13)
232 #define DMA_STATUS_RI (1 << 6)
233 #define DMA_STATUS_TI (1 << 0)
234 #define DMA_STATUS_INTR_MASK 0x1ffff
235 #define OPERATION_MODE 0x1018
236 #define MODE_RSF (1 << 25) /* RX Full Frame */
237 #define MODE_TSF (1 << 21) /* TX Full Frame */
238 #define MODE_FTF (1 << 20) /* Flush TX FIFO */
239 #define MODE_ST (1 << 13) /* Start DMA TX */
240 #define MODE_FUF (1 << 6) /* TX frames < 64bytes */
241 #define MODE_RTC_LEV32 0x1
242 #define MODE_RTC_SHIFT 3
243 #define MODE_OSF (1 << 2) /* Process Second frame */
244 #define MODE_SR (1 << 1) /* Start DMA RX */
245 #define INTERRUPT_ENABLE 0x101C
246 #define INT_EN_NIE (1 << 16) /* Normal/Summary */
247 #define INT_EN_AIE (1 << 15) /* Abnormal/Summary */
248 #define INT_EN_ERE (1 << 14) /* Early receive */
249 #define INT_EN_FBE (1 << 13) /* Fatal bus error */
250 #define INT_EN_ETE (1 << 10) /* Early transmit */
251 #define INT_EN_RWE (1 << 9) /* Receive watchdog */
252 #define INT_EN_RSE (1 << 8) /* Receive stopped */
253 #define INT_EN_RUE (1 << 7) /* Recv buf unavailable */
254 #define INT_EN_RIE (1 << 6) /* Receive interrupt */
255 #define INT_EN_UNE (1 << 5) /* Tx underflow */
256 #define INT_EN_OVE (1 << 4) /* Receive overflow */
257 #define INT_EN_TJE (1 << 3) /* Transmit jabber */
258 #define INT_EN_TUE (1 << 2) /* Tx. buf unavailable */
259 #define INT_EN_TSE (1 << 1) /* Transmit stopped */
260 #define INT_EN_TIE (1 << 0) /* Transmit interrupt */
261 #define INT_EN_DEFAULT (INT_EN_TIE|INT_EN_RIE| \
262 INT_EN_NIE|INT_EN_AIE| \
263 INT_EN_FBE|INT_EN_UNE)
265 #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020
266 #define RECEIVE_INT_WATCHDOG_TMR 0x1024
267 #define AXI_BUS_MODE 0x1028
268 #define AHB_OR_AXI_STATUS 0x102C
269 #define CURRENT_HOST_TRANSMIT_DESCR 0x1048
270 #define CURRENT_HOST_RECEIVE_DESCR 0x104C
271 #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050
272 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
273 #define HW_FEATURE 0x1058
276 #define DWC_GMAC_ALT_DESC 0x2
277 #define GMAC_MII_CLK_60_100M_DIV42 0x0
278 #define GMAC_MII_CLK_100_150M_DIV62 0x1
279 #define GMAC_MII_CLK_25_35M_DIV16 0x2
280 #define GMAC_MII_CLK_35_60M_DIV26 0x3
281 #define GMAC_MII_CLK_150_250M_DIV102 0x4
282 #define GMAC_MII_CLK_250_300M_DIV124 0x5
283 #define GMAC_MII_CLK_DIV4 0x8
284 #define GMAC_MII_CLK_DIV6 0x9
285 #define GMAC_MII_CLK_DIV8 0xa
286 #define GMAC_MII_CLK_DIV10 0xb
287 #define GMAC_MII_CLK_DIV12 0xc
288 #define GMAC_MII_CLK_DIV14 0xd
289 #define GMAC_MII_CLK_DIV16 0xe
290 #define GMAC_MII_CLK_DIV18 0xf
292 #endif /* __IF_DWC_H__ */