2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Register names were taken almost as is from the documentation.
40 #define PHY_MODE_UNKNOWN 0x0
41 #define PHY_MODE_RMII 0x1
42 #define PHY_MODE_RGMII 0x2
44 #define MAC_CONFIGURATION 0x0
45 #define CONF_JD (1 << 22) /* jabber timer disable */
46 #define CONF_BE (1 << 21) /* Frame Burst Enable */
47 #define CONF_PS (1 << 15) /* GMII/MII */
48 #define CONF_FES (1 << 14) /* MII speed select */
49 #define CONF_DM (1 << 11) /* Full Duplex Enable */
50 #define CONF_ACS (1 << 7)
51 #define CONF_TE (1 << 3)
52 #define CONF_RE (1 << 2)
53 #define MAC_FRAME_FILTER 0x4
54 #define FRAME_FILTER_RA (1U << 31) /* Receive All */
55 #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */
56 #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */
57 #define FRAME_FILTER_HMC (1 << 2)
58 #define FRAME_FILTER_HUC (1 << 1)
59 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
60 #define GMAC_MAC_HTHIGH 0x08
61 #define GMAC_MAC_HTLOW 0x0c
62 #define GMII_ADDRESS 0x10
63 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
64 #define GMII_ADDRESS_PA_SHIFT 11
65 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
66 #define GMII_ADDRESS_GR_SHIFT 6
67 #define GMII_ADDRESS_CR_MASK 0xf
68 #define GMII_ADDRESS_CR_SHIFT 2 /* Clock */
69 #define GMII_ADDRESS_GW (1 << 1) /* Write operation */
70 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
71 #define GMII_DATA 0x14
72 #define FLOW_CONTROL 0x18
73 #define GMAC_VLAN_TAG 0x1C
76 #define LPI_CONTROL_STATUS 0x30
77 #define LPI_TIMERS_CONTROL 0x34
78 #define INTERRUPT_STATUS 0x38
79 #define INTERRUPT_MASK 0x3C
80 #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n)
81 #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n)
83 #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8
84 #define MMC_CONTROL 0x100
85 #define MMC_CONTROL_CNTRST (1 << 0)
86 #define MMC_RECEIVE_INTERRUPT 0x104
87 #define MMC_TRANSMIT_INTERRUPT 0x108
88 #define MMC_RECEIVE_INTERRUPT_MASK 0x10C
89 #define MMC_TRANSMIT_INTERRUPT_MASK 0x110
90 #define TXOCTETCOUNT_GB 0x114
91 #define TXFRAMECOUNT_GB 0x118
92 #define TXBROADCASTFRAMES_G 0x11C
93 #define TXMULTICASTFRAMES_G 0x120
94 #define TX64OCTETS_GB 0x124
95 #define TX65TO127OCTETS_GB 0x128
96 #define TX128TO255OCTETS_GB 0x12C
97 #define TX256TO511OCTETS_GB 0x130
98 #define TX512TO1023OCTETS_GB 0x134
99 #define TX1024TOMAXOCTETS_GB 0x138
100 #define TXUNICASTFRAMES_GB 0x13C
101 #define TXMULTICASTFRAMES_GB 0x140
102 #define TXBROADCASTFRAMES_GB 0x144
103 #define TXUNDERFLOWERROR 0x148
104 #define TXSINGLECOL_G 0x14C
105 #define TXMULTICOL_G 0x150
106 #define TXDEFERRED 0x154
107 #define TXLATECOL 0x158
108 #define TXEXESSCOL 0x15C
109 #define TXCARRIERERR 0x160
110 #define TXOCTETCNT 0x164
111 #define TXFRAMECOUNT_G 0x168
112 #define TXEXCESSDEF 0x16C
113 #define TXPAUSEFRAMES 0x170
114 #define TXVLANFRAMES_G 0x174
115 #define TXOVERSIZE_G 0x178
116 #define RXFRAMECOUNT_GB 0x180
117 #define RXOCTETCOUNT_GB 0x184
118 #define RXOCTETCOUNT_G 0x188
119 #define RXBROADCASTFRAMES_G 0x18C
120 #define RXMULTICASTFRAMES_G 0x190
121 #define RXCRCERROR 0x194
122 #define RXALIGNMENTERROR 0x198
123 #define RXRUNTERROR 0x19C
124 #define RXJABBERERROR 0x1A0
125 #define RXUNDERSIZE_G 0x1A4
126 #define RXOVERSIZE_G 0x1A8
127 #define RX64OCTETS_GB 0x1AC
128 #define RX65TO127OCTETS_GB 0x1B0
129 #define RX128TO255OCTETS_GB 0x1B4
130 #define RX256TO511OCTETS_GB 0x1B8
131 #define RX512TO1023OCTETS_GB 0x1BC
132 #define RX1024TOMAXOCTETS_GB 0x1C0
133 #define RXUNICASTFRAMES_G 0x1C4
134 #define RXLENGTHERROR 0x1C8
135 #define RXOUTOFRANGETYPE 0x1CC
136 #define RXPAUSEFRAMES 0x1D0
137 #define RXFIFOOVERFLOW 0x1D4
138 #define RXVLANFRAMES_GB 0x1D8
139 #define RXWATCHDOGERROR 0x1DC
140 #define RXRCVERROR 0x1E0
141 #define RXCTRLFRAMES_G 0x1E4
142 #define MMC_IPC_RECEIVE_INT_MASK 0x200
143 #define MMC_IPC_RECEIVE_INT 0x208
144 #define RXIPV4_GD_FRMS 0x210
145 #define RXIPV4_HDRERR_FRMS 0x214
146 #define RXIPV4_NOPAY_FRMS 0x218
147 #define RXIPV4_FRAG_FRMS 0x21C
148 #define RXIPV4_UDSBL_FRMS 0x220
149 #define RXIPV6_GD_FRMS 0x224
150 #define RXIPV6_HDRERR_FRMS 0x228
151 #define RXIPV6_NOPAY_FRMS 0x22C
152 #define RXUDP_GD_FRMS 0x230
153 #define RXUDP_ERR_FRMS 0x234
154 #define RXTCP_GD_FRMS 0x238
155 #define RXTCP_ERR_FRMS 0x23C
156 #define RXICMP_GD_FRMS 0x240
157 #define RXICMP_ERR_FRMS 0x244
158 #define RXIPV4_GD_OCTETS 0x250
159 #define RXIPV4_HDRERR_OCTETS 0x254
160 #define RXIPV4_NOPAY_OCTETS 0x258
161 #define RXIPV4_FRAG_OCTETS 0x25C
162 #define RXIPV4_UDSBL_OCTETS 0x260
163 #define RXIPV6_GD_OCTETS 0x264
164 #define RXIPV6_HDRERR_OCTETS 0x268
165 #define RXIPV6_NOPAY_OCTETS 0x26C
166 #define RXUDP_GD_OCTETS 0x270
167 #define RXUDP_ERR_OCTETS 0x274
168 #define RXTCP_GD_OCTETS 0x278
169 #define RXTCPERROCTETS 0x27C
170 #define RXICMP_GD_OCTETS 0x280
171 #define RXICMP_ERR_OCTETS 0x284
172 #define L3_L4_CONTROL0 0x400
173 #define LAYER4_ADDRESS0 0x404
174 #define LAYER3_ADDR0_REG0 0x410
175 #define LAYER3_ADDR1_REG0 0x414
176 #define LAYER3_ADDR2_REG0 0x418
177 #define LAYER3_ADDR3_REG0 0x41C
178 #define L3_L4_CONTROL1 0x430
179 #define LAYER4_ADDRESS1 0x434
180 #define LAYER3_ADDR0_REG1 0x440
181 #define LAYER3_ADDR1_REG1 0x444
182 #define LAYER3_ADDR2_REG1 0x448
183 #define LAYER3_ADDR3_REG1 0x44C
184 #define L3_L4_CONTROL2 0x460
185 #define LAYER4_ADDRESS2 0x464
186 #define LAYER3_ADDR0_REG2 0x470
187 #define LAYER3_ADDR1_REG2 0x474
188 #define LAYER3_ADDR2_REG2 0x478
189 #define LAYER3_ADDR3_REG2 0x47C
190 #define L3_L4_CONTROL3 0x490
191 #define LAYER4_ADDRESS3 0x494
192 #define LAYER3_ADDR0_REG3 0x4A0
193 #define LAYER3_ADDR1_REG3 0x4A4
194 #define LAYER3_ADDR2_REG3 0x4A8
195 #define LAYER3_ADDR3_REG3 0x4AC
196 #define HASH_TABLE_REG(n) 0x500 + (0x4 * n)
197 #define VLAN_INCL_REG 0x584
198 #define VLAN_HASH_TABLE_REG 0x588
199 #define TIMESTAMP_CONTROL 0x700
200 #define SUB_SECOND_INCREMENT 0x704
201 #define SYSTEM_TIME_SECONDS 0x708
202 #define SYSTEM_TIME_NANOSECONDS 0x70C
203 #define SYSTEM_TIME_SECONDS_UPDATE 0x710
204 #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714
205 #define TIMESTAMP_ADDEND 0x718
206 #define TARGET_TIME_SECONDS 0x71C
207 #define TARGET_TIME_NANOSECONDS 0x720
208 #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724
209 #define TIMESTAMP_STATUS 0x728
210 #define PPS_CONTROL 0x72C
211 #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730
212 #define AUXILIARY_TIMESTAMP_SECONDS 0x734
213 #define PPS0_INTERVAL 0x760
214 #define PPS0_WIDTH 0x764
217 #define BUS_MODE 0x1000
218 #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */
219 #define BUS_MODE_FIXEDBURST (1 << 16)
220 #define BUS_MODE_PRIORXTX_SHIFT 14
221 #define BUS_MODE_PRIORXTX_41 3
222 #define BUS_MODE_PRIORXTX_31 2
223 #define BUS_MODE_PRIORXTX_21 1
224 #define BUS_MODE_PRIORXTX_11 0
225 #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */
226 #define BUS_MODE_PBL_BEATS_8 8
227 #define BUS_MODE_SWR (1 << 0) /* Reset */
228 #define TRANSMIT_POLL_DEMAND 0x1004
229 #define RECEIVE_POLL_DEMAND 0x1008
230 #define RX_DESCR_LIST_ADDR 0x100C
231 #define TX_DESCR_LIST_ADDR 0x1010
232 #define DMA_STATUS 0x1014
233 #define DMA_STATUS_NIS (1 << 16)
234 #define DMA_STATUS_AIS (1 << 15)
235 #define DMA_STATUS_FBI (1 << 13)
236 #define DMA_STATUS_RI (1 << 6)
237 #define DMA_STATUS_TI (1 << 0)
238 #define DMA_STATUS_INTR_MASK 0x1ffff
239 #define OPERATION_MODE 0x1018
240 #define MODE_RSF (1 << 25) /* RX Full Frame */
241 #define MODE_TSF (1 << 21) /* TX Full Frame */
242 #define MODE_FTF (1 << 20) /* Flush TX FIFO */
243 #define MODE_ST (1 << 13) /* Start DMA TX */
244 #define MODE_FUF (1 << 6) /* TX frames < 64bytes */
245 #define MODE_RTC_LEV32 0x1
246 #define MODE_RTC_SHIFT 3
247 #define MODE_OSF (1 << 2) /* Process Second frame */
248 #define MODE_SR (1 << 1) /* Start DMA RX */
249 #define INTERRUPT_ENABLE 0x101C
250 #define INT_EN_NIE (1 << 16) /* Normal/Summary */
251 #define INT_EN_AIE (1 << 15) /* Abnormal/Summary */
252 #define INT_EN_ERE (1 << 14) /* Early receive */
253 #define INT_EN_FBE (1 << 13) /* Fatal bus error */
254 #define INT_EN_ETE (1 << 10) /* Early transmit */
255 #define INT_EN_RWE (1 << 9) /* Receive watchdog */
256 #define INT_EN_RSE (1 << 8) /* Receive stopped */
257 #define INT_EN_RUE (1 << 7) /* Recv buf unavailable */
258 #define INT_EN_RIE (1 << 6) /* Receive interrupt */
259 #define INT_EN_UNE (1 << 5) /* Tx underflow */
260 #define INT_EN_OVE (1 << 4) /* Receive overflow */
261 #define INT_EN_TJE (1 << 3) /* Transmit jabber */
262 #define INT_EN_TUE (1 << 2) /* Tx. buf unavailable */
263 #define INT_EN_TSE (1 << 1) /* Transmit stopped */
264 #define INT_EN_TIE (1 << 0) /* Transmit interrupt */
265 #define INT_EN_DEFAULT (INT_EN_TIE|INT_EN_RIE| \
266 INT_EN_NIE|INT_EN_AIE| \
267 INT_EN_FBE|INT_EN_UNE)
269 #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020
270 #define RECEIVE_INT_WATCHDOG_TMR 0x1024
271 #define AXI_BUS_MODE 0x1028
272 #define AHB_OR_AXI_STATUS 0x102C
273 #define CURRENT_HOST_TRANSMIT_DESCR 0x1048
274 #define CURRENT_HOST_RECEIVE_DESCR 0x104C
275 #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050
276 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
277 #define HW_FEATURE 0x1058
279 #define DWC_GMAC_NORMAL_DESC 0x1
280 #define DWC_GMAC_EXT_DESC 0x2
282 #define GMAC_MII_CLK_60_100M_DIV42 0x0
283 #define GMAC_MII_CLK_100_150M_DIV62 0x1
284 #define GMAC_MII_CLK_25_35M_DIV16 0x2
285 #define GMAC_MII_CLK_35_60M_DIV26 0x3
286 #define GMAC_MII_CLK_150_250M_DIV102 0x4
287 #define GMAC_MII_CLK_250_300M_DIV124 0x5
288 #define GMAC_MII_CLK_DIV4 0x8
289 #define GMAC_MII_CLK_DIV6 0x9
290 #define GMAC_MII_CLK_DIV8 0xa
291 #define GMAC_MII_CLK_DIV10 0xb
292 #define GMAC_MII_CLK_DIV12 0xc
293 #define GMAC_MII_CLK_DIV14 0xd
294 #define GMAC_MII_CLK_DIV16 0xe
295 #define GMAC_MII_CLK_DIV18 0xf
297 #endif /* __IF_DWC_H__ */