2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Register names were taken almost as is from the documentation.
40 #define MAC_CONFIGURATION 0x0
41 #define CONF_JD (1 << 22) /* jabber timer disable */
42 #define CONF_BE (1 << 21) /* Frame Burst Enable */
43 #define CONF_PS (1 << 15) /* GMII/MII */
44 #define CONF_FES (1 << 14) /* MII speed select */
45 #define CONF_DM (1 << 11) /* Full Duplex Enable */
46 #define CONF_ACS (1 << 7)
47 #define CONF_TE (1 << 3)
48 #define CONF_RE (1 << 2)
49 #define MAC_FRAME_FILTER 0x4
50 #define FRAME_FILTER_RA (1U << 31) /* Receive All */
51 #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */
52 #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */
53 #define FRAME_FILTER_HMC (1 << 2)
54 #define FRAME_FILTER_HUC (1 << 1)
55 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
56 #define GMII_ADDRESS 0x10
57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
58 #define GMII_ADDRESS_PA_SHIFT 11
59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
60 #define GMII_ADDRESS_GR_SHIFT 6
61 #define GMII_ADDRESS_CR_MASK 0xf
62 #define GMII_ADDRESS_CR_SHIFT 2 /* Clock */
63 #define GMII_ADDRESS_GW (1 << 1) /* Write operation */
64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
65 #define GMII_DATA 0x14
66 #define FLOW_CONTROL 0x18
67 #define GMAC_VLAN_TAG 0x1C
70 #define LPI_CONTROL_STATUS 0x30
71 #define LPI_TIMERS_CONTROL 0x34
72 #define INTERRUPT_STATUS 0x38
73 #define INTERRUPT_MASK 0x3C
74 #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n)
75 #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n)
77 #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8
78 #define MMC_CONTROL 0x100
79 #define MMC_CONTROL_CNTRST (1 << 0)
80 #define MMC_RECEIVE_INTERRUPT 0x104
81 #define MMC_TRANSMIT_INTERRUPT 0x108
82 #define MMC_RECEIVE_INTERRUPT_MASK 0x10C
83 #define MMC_TRANSMIT_INTERRUPT_MASK 0x110
84 #define TXOCTETCOUNT_GB 0x114
85 #define TXFRAMECOUNT_GB 0x118
86 #define TXBROADCASTFRAMES_G 0x11C
87 #define TXMULTICASTFRAMES_G 0x120
88 #define TX64OCTETS_GB 0x124
89 #define TX65TO127OCTETS_GB 0x128
90 #define TX128TO255OCTETS_GB 0x12C
91 #define TX256TO511OCTETS_GB 0x130
92 #define TX512TO1023OCTETS_GB 0x134
93 #define TX1024TOMAXOCTETS_GB 0x138
94 #define TXUNICASTFRAMES_GB 0x13C
95 #define TXMULTICASTFRAMES_GB 0x140
96 #define TXBROADCASTFRAMES_GB 0x144
97 #define TXUNDERFLOWERROR 0x148
98 #define TXSINGLECOL_G 0x14C
99 #define TXMULTICOL_G 0x150
100 #define TXDEFERRED 0x154
101 #define TXLATECOL 0x158
102 #define TXEXESSCOL 0x15C
103 #define TXCARRIERERR 0x160
104 #define TXOCTETCNT 0x164
105 #define TXFRAMECOUNT_G 0x168
106 #define TXEXCESSDEF 0x16C
107 #define TXPAUSEFRAMES 0x170
108 #define TXVLANFRAMES_G 0x174
109 #define TXOVERSIZE_G 0x178
110 #define RXFRAMECOUNT_GB 0x180
111 #define RXOCTETCOUNT_GB 0x184
112 #define RXOCTETCOUNT_G 0x188
113 #define RXBROADCASTFRAMES_G 0x18C
114 #define RXMULTICASTFRAMES_G 0x190
115 #define RXCRCERROR 0x194
116 #define RXALIGNMENTERROR 0x198
117 #define RXRUNTERROR 0x19C
118 #define RXJABBERERROR 0x1A0
119 #define RXUNDERSIZE_G 0x1A4
120 #define RXOVERSIZE_G 0x1A8
121 #define RX64OCTETS_GB 0x1AC
122 #define RX65TO127OCTETS_GB 0x1B0
123 #define RX128TO255OCTETS_GB 0x1B4
124 #define RX256TO511OCTETS_GB 0x1B8
125 #define RX512TO1023OCTETS_GB 0x1BC
126 #define RX1024TOMAXOCTETS_GB 0x1C0
127 #define RXUNICASTFRAMES_G 0x1C4
128 #define RXLENGTHERROR 0x1C8
129 #define RXOUTOFRANGETYPE 0x1CC
130 #define RXPAUSEFRAMES 0x1D0
131 #define RXFIFOOVERFLOW 0x1D4
132 #define RXVLANFRAMES_GB 0x1D8
133 #define RXWATCHDOGERROR 0x1DC
134 #define RXRCVERROR 0x1E0
135 #define RXCTRLFRAMES_G 0x1E4
136 #define MMC_IPC_RECEIVE_INT_MASK 0x200
137 #define MMC_IPC_RECEIVE_INT 0x208
138 #define RXIPV4_GD_FRMS 0x210
139 #define RXIPV4_HDRERR_FRMS 0x214
140 #define RXIPV4_NOPAY_FRMS 0x218
141 #define RXIPV4_FRAG_FRMS 0x21C
142 #define RXIPV4_UDSBL_FRMS 0x220
143 #define RXIPV6_GD_FRMS 0x224
144 #define RXIPV6_HDRERR_FRMS 0x228
145 #define RXIPV6_NOPAY_FRMS 0x22C
146 #define RXUDP_GD_FRMS 0x230
147 #define RXUDP_ERR_FRMS 0x234
148 #define RXTCP_GD_FRMS 0x238
149 #define RXTCP_ERR_FRMS 0x23C
150 #define RXICMP_GD_FRMS 0x240
151 #define RXICMP_ERR_FRMS 0x244
152 #define RXIPV4_GD_OCTETS 0x250
153 #define RXIPV4_HDRERR_OCTETS 0x254
154 #define RXIPV4_NOPAY_OCTETS 0x258
155 #define RXIPV4_FRAG_OCTETS 0x25C
156 #define RXIPV4_UDSBL_OCTETS 0x260
157 #define RXIPV6_GD_OCTETS 0x264
158 #define RXIPV6_HDRERR_OCTETS 0x268
159 #define RXIPV6_NOPAY_OCTETS 0x26C
160 #define RXUDP_GD_OCTETS 0x270
161 #define RXUDP_ERR_OCTETS 0x274
162 #define RXTCP_GD_OCTETS 0x278
163 #define RXTCPERROCTETS 0x27C
164 #define RXICMP_GD_OCTETS 0x280
165 #define RXICMP_ERR_OCTETS 0x284
166 #define L3_L4_CONTROL0 0x400
167 #define LAYER4_ADDRESS0 0x404
168 #define LAYER3_ADDR0_REG0 0x410
169 #define LAYER3_ADDR1_REG0 0x414
170 #define LAYER3_ADDR2_REG0 0x418
171 #define LAYER3_ADDR3_REG0 0x41C
172 #define L3_L4_CONTROL1 0x430
173 #define LAYER4_ADDRESS1 0x434
174 #define LAYER3_ADDR0_REG1 0x440
175 #define LAYER3_ADDR1_REG1 0x444
176 #define LAYER3_ADDR2_REG1 0x448
177 #define LAYER3_ADDR3_REG1 0x44C
178 #define L3_L4_CONTROL2 0x460
179 #define LAYER4_ADDRESS2 0x464
180 #define LAYER3_ADDR0_REG2 0x470
181 #define LAYER3_ADDR1_REG2 0x474
182 #define LAYER3_ADDR2_REG2 0x478
183 #define LAYER3_ADDR3_REG2 0x47C
184 #define L3_L4_CONTROL3 0x490
185 #define LAYER4_ADDRESS3 0x494
186 #define LAYER3_ADDR0_REG3 0x4A0
187 #define LAYER3_ADDR1_REG3 0x4A4
188 #define LAYER3_ADDR2_REG3 0x4A8
189 #define LAYER3_ADDR3_REG3 0x4AC
190 #define HASH_TABLE_REG(n) 0x500 + (0x4 * n)
191 #define VLAN_INCL_REG 0x584
192 #define VLAN_HASH_TABLE_REG 0x588
193 #define TIMESTAMP_CONTROL 0x700
194 #define SUB_SECOND_INCREMENT 0x704
195 #define SYSTEM_TIME_SECONDS 0x708
196 #define SYSTEM_TIME_NANOSECONDS 0x70C
197 #define SYSTEM_TIME_SECONDS_UPDATE 0x710
198 #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714
199 #define TIMESTAMP_ADDEND 0x718
200 #define TARGET_TIME_SECONDS 0x71C
201 #define TARGET_TIME_NANOSECONDS 0x720
202 #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724
203 #define TIMESTAMP_STATUS 0x728
204 #define PPS_CONTROL 0x72C
205 #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730
206 #define AUXILIARY_TIMESTAMP_SECONDS 0x734
207 #define PPS0_INTERVAL 0x760
208 #define PPS0_WIDTH 0x764
211 #define BUS_MODE 0x1000
212 #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */
213 #define BUS_MODE_FIXEDBURST (1 << 16)
214 #define BUS_MODE_PRIORXTX_SHIFT 14
215 #define BUS_MODE_PRIORXTX_41 3
216 #define BUS_MODE_PRIORXTX_31 2
217 #define BUS_MODE_PRIORXTX_21 1
218 #define BUS_MODE_PRIORXTX_11 0
219 #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */
220 #define BUS_MODE_PBL_BEATS_8 8
221 #define BUS_MODE_SWR (1 << 0) /* Reset */
222 #define TRANSMIT_POLL_DEMAND 0x1004
223 #define RECEIVE_POLL_DEMAND 0x1008
224 #define RX_DESCR_LIST_ADDR 0x100C
225 #define TX_DESCR_LIST_ADDR 0x1010
226 #define DMA_STATUS 0x1014
227 #define DMA_STATUS_NIS (1 << 16)
228 #define DMA_STATUS_AIS (1 << 15)
229 #define DMA_STATUS_FBI (1 << 13)
230 #define DMA_STATUS_RI (1 << 6)
231 #define DMA_STATUS_TI (1 << 0)
232 #define DMA_STATUS_INTR_MASK 0x1ffff
233 #define OPERATION_MODE 0x1018
234 #define MODE_RSF (1 << 25) /* RX Full Frame */
235 #define MODE_TSF (1 << 21) /* TX Full Frame */
236 #define MODE_FTF (1 << 20) /* Flush TX FIFO */
237 #define MODE_ST (1 << 13) /* Start DMA TX */
238 #define MODE_FUF (1 << 6) /* TX frames < 64bytes */
239 #define MODE_RTC_LEV32 0x1
240 #define MODE_RTC_SHIFT 3
241 #define MODE_OSF (1 << 2) /* Process Second frame */
242 #define MODE_SR (1 << 1) /* Start DMA RX */
243 #define INTERRUPT_ENABLE 0x101C
244 #define INT_EN_NIE (1 << 16) /* Normal/Summary */
245 #define INT_EN_AIE (1 << 15) /* Abnormal/Summary */
246 #define INT_EN_ERE (1 << 14) /* Early receive */
247 #define INT_EN_FBE (1 << 13) /* Fatal bus error */
248 #define INT_EN_ETE (1 << 10) /* Early transmit */
249 #define INT_EN_RWE (1 << 9) /* Receive watchdog */
250 #define INT_EN_RSE (1 << 8) /* Receive stopped */
251 #define INT_EN_RUE (1 << 7) /* Recv buf unavailable */
252 #define INT_EN_RIE (1 << 6) /* Receive interrupt */
253 #define INT_EN_UNE (1 << 5) /* Tx underflow */
254 #define INT_EN_OVE (1 << 4) /* Receive overflow */
255 #define INT_EN_TJE (1 << 3) /* Transmit jabber */
256 #define INT_EN_TUE (1 << 2) /* Tx. buf unavailable */
257 #define INT_EN_TSE (1 << 1) /* Transmit stopped */
258 #define INT_EN_TIE (1 << 0) /* Transmit interrupt */
259 #define INT_EN_DEFAULT (INT_EN_TIE|INT_EN_RIE| \
260 INT_EN_NIE|INT_EN_AIE| \
261 INT_EN_FBE|INT_EN_UNE)
263 #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020
264 #define RECEIVE_INT_WATCHDOG_TMR 0x1024
265 #define AXI_BUS_MODE 0x1028
266 #define AHB_OR_AXI_STATUS 0x102C
267 #define CURRENT_HOST_TRANSMIT_DESCR 0x1048
268 #define CURRENT_HOST_RECEIVE_DESCR 0x104C
269 #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050
270 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
271 #define HW_FEATURE 0x1058
274 #define DWC_GMAC_ALT_DESC 0x2
275 #define GMAC_MII_CLK_60_100M_DIV42 0x0
276 #define GMAC_MII_CLK_100_150M_DIV62 0x1
277 #define GMAC_MII_CLK_25_35M_DIV16 0x2
278 #define GMAC_MII_CLK_35_60M_DIV26 0x3
279 #define GMAC_MII_CLK_150_250M_DIV102 0x4
280 #define GMAC_MII_CLK_250_300M_DIV124 0x5
281 #define GMAC_MII_CLK_DIV4 0x8
282 #define GMAC_MII_CLK_DIV6 0x9
283 #define GMAC_MII_CLK_DIV8 0xa
284 #define GMAC_MII_CLK_DIV10 0xb
285 #define GMAC_MII_CLK_DIV12 0xc
286 #define GMAC_MII_CLK_DIV14 0xd
287 #define GMAC_MII_CLK_DIV16 0xe
288 #define GMAC_MII_CLK_DIV18 0xf
290 #endif /* __IF_DWC_H__ */