1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
36 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
39 #include "e1000_api.h"
41 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
44 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
48 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
51 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
54 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
71 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
72 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
73 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
75 /* A table for the GG82563 cable length where the range is defined
76 * with a lower bound at "index" and the upper bound at
79 static const u16 e1000_gg82563_cable_length_table[] = {
80 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
81 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
82 (sizeof(e1000_gg82563_cable_length_table) / \
83 sizeof(e1000_gg82563_cable_length_table[0]))
86 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
87 * @hw: pointer to the HW structure
89 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
91 struct e1000_phy_info *phy = &hw->phy;
94 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
96 if (hw->phy.media_type != e1000_media_type_copper) {
97 phy->type = e1000_phy_none;
100 phy->ops.power_up = e1000_power_up_phy_copper;
101 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
107 phy->type = e1000_phy_gg82563;
109 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
110 phy->ops.check_polarity = e1000_check_polarity_m88;
111 phy->ops.check_reset_block = e1000_check_reset_block_generic;
112 phy->ops.commit = e1000_phy_sw_reset_generic;
113 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
114 phy->ops.get_info = e1000_get_phy_info_m88;
115 phy->ops.release = e1000_release_phy_80003es2lan;
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
119 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
120 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
121 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
124 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
126 /* This can only be done after all function pointers are setup. */
127 ret_val = e1000_get_phy_id(hw);
130 if (phy->id != GG82563_E_PHY_ID)
131 return -E1000_ERR_PHY;
137 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
138 * @hw: pointer to the HW structure
140 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
146 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
148 nvm->opcode_bits = 8;
150 switch (nvm->override) {
151 case e1000_nvm_override_spi_large:
153 nvm->address_bits = 16;
155 case e1000_nvm_override_spi_small:
157 nvm->address_bits = 8;
160 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
161 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
165 nvm->type = e1000_nvm_eeprom_spi;
167 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
168 E1000_EECD_SIZE_EX_SHIFT);
170 /* Added to a constant, "size" becomes the left-shift value
171 * for setting word_size.
173 size += NVM_WORD_SIZE_BASE_SHIFT;
175 /* EEPROM access above 16k is unsupported */
178 nvm->word_size = 1 << size;
180 /* Function Pointers */
181 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
182 nvm->ops.read = e1000_read_nvm_eerd;
183 nvm->ops.release = e1000_release_nvm_80003es2lan;
184 nvm->ops.update = e1000_update_nvm_checksum_generic;
185 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
186 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
187 nvm->ops.write = e1000_write_nvm_80003es2lan;
189 return E1000_SUCCESS;
193 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
194 * @hw: pointer to the HW structure
196 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
198 struct e1000_mac_info *mac = &hw->mac;
200 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
202 /* Set media type and media-dependent function pointers */
203 switch (hw->device_id) {
204 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
205 hw->phy.media_type = e1000_media_type_internal_serdes;
206 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
207 mac->ops.setup_physical_interface =
208 e1000_setup_fiber_serdes_link_generic;
211 hw->phy.media_type = e1000_media_type_copper;
212 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
213 mac->ops.setup_physical_interface =
214 e1000_setup_copper_link_80003es2lan;
218 /* Set mta register count */
219 mac->mta_reg_count = 128;
220 /* Set rar entry count */
221 mac->rar_entry_count = E1000_RAR_ENTRIES;
222 /* Set if part includes ASF firmware */
223 mac->asf_firmware_present = TRUE;
225 mac->has_fwsm = TRUE;
226 /* ARC supported; valid only if manageability features are enabled. */
227 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
228 E1000_FWSM_MODE_MASK);
229 /* Adaptive IFS not supported */
230 mac->adaptive_ifs = FALSE;
232 /* Function pointers */
234 /* bus type/speed/width */
235 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
237 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
238 /* hw initialization */
239 mac->ops.init_hw = e1000_init_hw_80003es2lan;
241 mac->ops.setup_link = e1000_setup_link_generic;
242 /* check management mode */
243 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
244 /* multicast address update */
245 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
247 mac->ops.write_vfta = e1000_write_vfta_generic;
249 mac->ops.clear_vfta = e1000_clear_vfta_generic;
250 /* read mac address */
251 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
253 mac->ops.id_led_init = e1000_id_led_init_generic;
255 mac->ops.blink_led = e1000_blink_led_generic;
257 mac->ops.setup_led = e1000_setup_led_generic;
259 mac->ops.cleanup_led = e1000_cleanup_led_generic;
260 /* turn on/off LED */
261 mac->ops.led_on = e1000_led_on_generic;
262 mac->ops.led_off = e1000_led_off_generic;
263 /* clear hardware counters */
264 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
266 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
268 /* set lan id for port to determine which phy lock to use */
269 hw->mac.ops.set_lan_id(hw);
271 return E1000_SUCCESS;
275 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
276 * @hw: pointer to the HW structure
278 * Called to initialize all function pointers and parameters.
280 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
282 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
284 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
285 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
286 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
290 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
291 * @hw: pointer to the HW structure
293 * A wrapper to acquire access rights to the correct PHY.
295 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
299 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
301 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
302 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
306 * e1000_release_phy_80003es2lan - Release rights to access PHY
307 * @hw: pointer to the HW structure
309 * A wrapper to release access rights to the correct PHY.
311 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
315 DEBUGFUNC("e1000_release_phy_80003es2lan");
317 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
318 e1000_release_swfw_sync_80003es2lan(hw, mask);
322 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
323 * @hw: pointer to the HW structure
325 * Acquire the semaphore to access the Kumeran interface.
328 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
332 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
334 mask = E1000_SWFW_CSR_SM;
336 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
340 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
341 * @hw: pointer to the HW structure
343 * Release the semaphore used to access the Kumeran interface
345 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
349 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
351 mask = E1000_SWFW_CSR_SM;
353 e1000_release_swfw_sync_80003es2lan(hw, mask);
357 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
358 * @hw: pointer to the HW structure
360 * Acquire the semaphore to access the EEPROM.
362 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
366 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
368 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
372 ret_val = e1000_acquire_nvm_generic(hw);
375 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
381 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
382 * @hw: pointer to the HW structure
384 * Release the semaphore used to access the EEPROM.
386 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
388 DEBUGFUNC("e1000_release_nvm_80003es2lan");
390 e1000_release_nvm_generic(hw);
391 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
395 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
396 * @hw: pointer to the HW structure
397 * @mask: specifies which semaphore to acquire
399 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
400 * will also specify which port we're acquiring the lock for.
402 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
406 u32 fwmask = mask << 16;
410 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
412 while (i < timeout) {
413 if (e1000_get_hw_semaphore_generic(hw))
414 return -E1000_ERR_SWFW_SYNC;
416 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
417 if (!(swfw_sync & (fwmask | swmask)))
420 /* Firmware currently using resource (fwmask)
421 * or other software thread using resource (swmask)
423 e1000_put_hw_semaphore_generic(hw);
429 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
430 return -E1000_ERR_SWFW_SYNC;
434 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
436 e1000_put_hw_semaphore_generic(hw);
438 return E1000_SUCCESS;
442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
443 * @hw: pointer to the HW structure
444 * @mask: specifies which semaphore to acquire
446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
447 * will also specify which port we're releasing the lock for.
449 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
462 e1000_put_hw_semaphore_generic(hw);
466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
467 * @hw: pointer to the HW structure
468 * @offset: offset of the register to read
469 * @data: pointer to the data returned from the operation
471 * Read the GG82563 PHY register.
473 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
474 u32 offset, u16 *data)
480 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
482 ret_val = e1000_acquire_phy_80003es2lan(hw);
486 /* Select Configuration Page */
487 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
488 page_select = GG82563_PHY_PAGE_SELECT;
490 /* Use Alternative Page Select register to access
491 * registers 30 and 31
493 page_select = GG82563_PHY_PAGE_SELECT_ALT;
496 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
497 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
499 e1000_release_phy_80003es2lan(hw);
503 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
504 /* The "ready" bit in the MDIC register may be incorrectly set
505 * before the device has completed the "Page Select" MDI
506 * transaction. So we wait 200us after each MDI command...
510 /* ...and verify the command was successful. */
511 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
513 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
514 e1000_release_phy_80003es2lan(hw);
515 return -E1000_ERR_PHY;
520 ret_val = e1000_read_phy_reg_mdic(hw,
521 MAX_PHY_REG_ADDRESS & offset,
526 ret_val = e1000_read_phy_reg_mdic(hw,
527 MAX_PHY_REG_ADDRESS & offset,
531 e1000_release_phy_80003es2lan(hw);
537 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
538 * @hw: pointer to the HW structure
539 * @offset: offset of the register to read
540 * @data: value to write to the register
542 * Write to the GG82563 PHY register.
544 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
545 u32 offset, u16 data)
551 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
553 ret_val = e1000_acquire_phy_80003es2lan(hw);
557 /* Select Configuration Page */
558 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
559 page_select = GG82563_PHY_PAGE_SELECT;
561 /* Use Alternative Page Select register to access
562 * registers 30 and 31
564 page_select = GG82563_PHY_PAGE_SELECT_ALT;
567 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
570 e1000_release_phy_80003es2lan(hw);
574 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
575 /* The "ready" bit in the MDIC register may be incorrectly set
576 * before the device has completed the "Page Select" MDI
577 * transaction. So we wait 200us after each MDI command...
581 /* ...and verify the command was successful. */
582 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
584 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
585 e1000_release_phy_80003es2lan(hw);
586 return -E1000_ERR_PHY;
591 ret_val = e1000_write_phy_reg_mdic(hw,
592 MAX_PHY_REG_ADDRESS & offset,
597 ret_val = e1000_write_phy_reg_mdic(hw,
598 MAX_PHY_REG_ADDRESS & offset,
602 e1000_release_phy_80003es2lan(hw);
608 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
609 * @hw: pointer to the HW structure
610 * @offset: offset of the register to read
611 * @words: number of words to write
612 * @data: buffer of data to write to the NVM
614 * Write "words" of data to the ESB2 NVM.
616 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
617 u16 words, u16 *data)
619 DEBUGFUNC("e1000_write_nvm_80003es2lan");
621 return e1000_write_nvm_spi(hw, offset, words, data);
625 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
626 * @hw: pointer to the HW structure
628 * Wait a specific amount of time for manageability processes to complete.
629 * This is a function pointer entry point called by the phy module.
631 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
633 s32 timeout = PHY_CFG_TIMEOUT;
634 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
636 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
638 if (hw->bus.func == 1)
639 mask = E1000_NVM_CFG_DONE_PORT_1;
642 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
648 DEBUGOUT("MNG configuration cycle has not completed.\n");
649 return -E1000_ERR_RESET;
652 return E1000_SUCCESS;
656 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
657 * @hw: pointer to the HW structure
659 * Force the speed and duplex settings onto the PHY. This is a
660 * function pointer entry point called by the phy module.
662 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
668 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
670 if (!(hw->phy.ops.read_reg))
671 return E1000_SUCCESS;
673 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
674 * forced whenever speed and duplex are forced.
676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
680 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
685 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
691 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
693 /* Reset the phy to commit changes. */
694 phy_data |= MII_CR_RESET;
696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
702 if (hw->phy.autoneg_wait_to_complete) {
703 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
711 /* We didn't get link.
712 * Reset the DSP and cross our fingers.
714 ret_val = e1000_phy_reset_dsp_generic(hw);
720 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
731 /* Resetting the phy means we need to verify the TX_CLK corresponds
732 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
734 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
735 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
736 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
738 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
740 /* In addition, we must re-enable CRS on Tx for both half and full
743 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
751 * e1000_get_cable_length_80003es2lan - Set approximate cable length
752 * @hw: pointer to the HW structure
754 * Find the approximate cable length as measured by the GG82563 PHY.
755 * This is a function pointer entry point called by the phy module.
757 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
759 struct e1000_phy_info *phy = &hw->phy;
763 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
765 if (!(hw->phy.ops.read_reg))
766 return E1000_SUCCESS;
768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
772 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
774 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
775 return -E1000_ERR_PHY;
777 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
778 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
782 return E1000_SUCCESS;
786 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
787 * @hw: pointer to the HW structure
788 * @speed: pointer to speed buffer
789 * @duplex: pointer to duplex buffer
791 * Retrieve the current speed and duplex configuration.
793 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
798 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
800 if (hw->phy.media_type == e1000_media_type_copper) {
801 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
803 hw->phy.ops.cfg_on_link_up(hw);
805 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
814 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
815 * @hw: pointer to the HW structure
817 * Perform a global reset to the ESB2 controller.
819 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
825 DEBUGFUNC("e1000_reset_hw_80003es2lan");
827 /* Prevent the PCI-E bus from sticking if there is no TLP connection
828 * on the last TLP read/write transaction when MAC is reset.
830 ret_val = e1000_disable_pcie_master_generic(hw);
832 DEBUGOUT("PCI-E Master disable polling has failed.\n");
834 DEBUGOUT("Masking off all interrupts\n");
835 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
837 E1000_WRITE_REG(hw, E1000_RCTL, 0);
838 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
839 E1000_WRITE_FLUSH(hw);
843 ctrl = E1000_READ_REG(hw, E1000_CTRL);
845 ret_val = e1000_acquire_phy_80003es2lan(hw);
849 DEBUGOUT("Issuing a global reset to MAC\n");
850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
851 e1000_release_phy_80003es2lan(hw);
853 /* Disable IBIST slave mode (far-end loopback) */
854 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
856 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
857 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
860 ret_val = e1000_get_auto_rd_done_generic(hw);
862 /* We don't want to continue accessing MAC registers. */
865 /* Clear any pending interrupt events. */
866 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
867 E1000_READ_REG(hw, E1000_ICR);
869 return e1000_check_alt_mac_addr_generic(hw);
873 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
874 * @hw: pointer to the HW structure
876 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
878 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
880 struct e1000_mac_info *mac = &hw->mac;
886 DEBUGFUNC("e1000_init_hw_80003es2lan");
888 e1000_initialize_hw_bits_80003es2lan(hw);
890 /* Initialize identification LED */
891 ret_val = mac->ops.id_led_init(hw);
892 /* An error is not fatal and we should not stop init due to this */
894 DEBUGOUT("Error initializing identification LED\n");
896 /* Disabling VLAN filtering */
897 DEBUGOUT("Initializing the IEEE VLAN\n");
898 mac->ops.clear_vfta(hw);
900 /* Setup the receive address. */
901 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
903 /* Zero out the Multicast HASH table */
904 DEBUGOUT("Zeroing the MTA\n");
905 for (i = 0; i < mac->mta_reg_count; i++)
906 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
908 /* Setup link and flow control */
909 ret_val = mac->ops.setup_link(hw);
913 /* Disable IBIST slave mode (far-end loopback) */
914 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
916 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
917 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
920 /* Set the transmit descriptor write-back policy */
921 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
922 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
923 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
924 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
926 /* ...for both queues. */
927 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
928 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
929 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
930 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
932 /* Enable retransmit on late collisions */
933 reg_data = E1000_READ_REG(hw, E1000_TCTL);
934 reg_data |= E1000_TCTL_RTLC;
935 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
937 /* Configure Gigabit Carry Extend Padding */
938 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
939 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
940 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
941 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
943 /* Configure Transmit Inter-Packet Gap */
944 reg_data = E1000_READ_REG(hw, E1000_TIPG);
945 reg_data &= ~E1000_TIPG_IPGT_MASK;
946 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
947 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
949 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
950 reg_data &= ~0x00100000;
951 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
953 /* default to TRUE to enable the MDIC W/A */
954 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
957 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
958 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
960 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
961 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
962 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
965 /* Clear all of the statistics registers (clear on read). It is
966 * important that we do this after we have tried to establish link
967 * because the symbol error count will increment wildly if there
970 e1000_clear_hw_cntrs_80003es2lan(hw);
976 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
977 * @hw: pointer to the HW structure
979 * Initializes required hardware-dependent bits needed for normal operation.
981 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
985 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
987 /* Transmit Descriptor Control 0 */
988 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
990 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
992 /* Transmit Descriptor Control 1 */
993 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
995 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
997 /* Transmit Arbitration Control 0 */
998 reg = E1000_READ_REG(hw, E1000_TARC(0));
999 reg &= ~(0xF << 27); /* 30:27 */
1000 if (hw->phy.media_type != e1000_media_type_copper)
1002 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1004 /* Transmit Arbitration Control 1 */
1005 reg = E1000_READ_REG(hw, E1000_TARC(1));
1006 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1010 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1012 /* Disable IPv6 extension header parsing because some malformed
1013 * IPv6 headers can hang the Rx.
1015 reg = E1000_READ_REG(hw, E1000_RFCTL);
1016 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1017 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1023 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1024 * @hw: pointer to the HW structure
1026 * Setup some GG82563 PHY registers for obtaining link
1028 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1030 struct e1000_phy_info *phy = &hw->phy;
1035 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1037 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1041 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1042 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1043 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1045 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1050 * MDI/MDI-X = 0 (default)
1051 * 0 - Auto for all speeds
1054 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1056 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1060 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1062 switch (phy->mdix) {
1064 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1067 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1071 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1076 * disable_polarity_correction = 0 (default)
1077 * Automatic Correction for Reversed Cable Polarity
1081 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1082 if (phy->disable_polarity_correction)
1083 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1085 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1089 /* SW Reset the PHY so all changes take effect */
1090 ret_val = hw->phy.ops.commit(hw);
1092 DEBUGOUT("Error Resetting the PHY\n");
1096 /* Bypass Rx and Tx FIFO's */
1097 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1098 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1099 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1100 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1104 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1105 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1108 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1109 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1113 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1117 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1118 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1122 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1123 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1124 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1130 /* Do not init these registers when the HW is in IAMT mode, since the
1131 * firmware will have already initialized them. We only initialize
1132 * them if the HW is not in IAMT mode.
1134 if (!hw->mac.ops.check_mng_mode(hw)) {
1135 /* Enable Electrical Idle on the PHY */
1136 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1137 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1142 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1147 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1148 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1154 /* Workaround: Disable padding in Kumeran interface in the MAC
1155 * and in the PHY to avoid CRC errors.
1157 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1161 data |= GG82563_ICR_DIS_PADDING;
1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1166 return E1000_SUCCESS;
1170 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1171 * @hw: pointer to the HW structure
1173 * Essentially a wrapper for setting up all things "copper" related.
1174 * This is a function pointer entry point called by the mac module.
1176 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1182 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1184 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1185 ctrl |= E1000_CTRL_SLU;
1186 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1187 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1189 /* Set the mac to wait the maximum time between each
1190 * iteration and increase the max iterations when
1191 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1193 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1197 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1202 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1207 e1000_read_kmrn_reg_80003es2lan(hw,
1208 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1212 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1214 e1000_write_kmrn_reg_80003es2lan(hw,
1215 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1220 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1224 return e1000_setup_copper_link_generic(hw);
1228 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1229 * @hw: pointer to the HW structure
1230 * @duplex: current duplex setting
1232 * Configure the KMRN interface by applying last minute quirks for
1235 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1237 s32 ret_val = E1000_SUCCESS;
1241 DEBUGFUNC("e1000_configure_on_link_up");
1243 if (hw->phy.media_type == e1000_media_type_copper) {
1244 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1249 if (speed == SPEED_1000)
1250 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1252 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1259 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1260 * @hw: pointer to the HW structure
1261 * @duplex: current duplex setting
1263 * Configure the KMRN interface by applying last minute quirks for
1266 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1271 u16 reg_data, reg_data2;
1273 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1275 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1277 e1000_write_kmrn_reg_80003es2lan(hw,
1278 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1283 /* Configure Transmit Inter-Packet Gap */
1284 tipg = E1000_READ_REG(hw, E1000_TIPG);
1285 tipg &= ~E1000_TIPG_IPGT_MASK;
1286 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1287 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1290 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1295 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1300 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1302 if (duplex == HALF_DUPLEX)
1303 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1305 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1307 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1311 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1312 * @hw: pointer to the HW structure
1314 * Configure the KMRN interface by applying last minute quirks for
1315 * gigabit operation.
1317 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1320 u16 reg_data, reg_data2;
1324 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1326 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1328 e1000_write_kmrn_reg_80003es2lan(hw,
1329 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1334 /* Configure Transmit Inter-Packet Gap */
1335 tipg = E1000_READ_REG(hw, E1000_TIPG);
1336 tipg &= ~E1000_TIPG_IPGT_MASK;
1337 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1338 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1341 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1346 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1351 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1353 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1355 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1359 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1360 * @hw: pointer to the HW structure
1361 * @offset: register offset to be read
1362 * @data: pointer to the read data
1364 * Acquire semaphore, then read the PHY register at offset
1365 * using the kumeran interface. The information retrieved is stored in data.
1366 * Release the semaphore before exiting.
1368 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1374 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1376 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1380 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1381 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1382 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1383 E1000_WRITE_FLUSH(hw);
1387 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1388 *data = (u16)kmrnctrlsta;
1390 e1000_release_mac_csr_80003es2lan(hw);
1396 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1397 * @hw: pointer to the HW structure
1398 * @offset: register offset to write to
1399 * @data: data to write at register offset
1401 * Acquire semaphore, then write the data to PHY register
1402 * at the offset using the kumeran interface. Release semaphore
1405 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1411 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1413 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1417 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1418 E1000_KMRNCTRLSTA_OFFSET) | data;
1419 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1420 E1000_WRITE_FLUSH(hw);
1424 e1000_release_mac_csr_80003es2lan(hw);
1430 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1431 * @hw: pointer to the HW structure
1433 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1437 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1439 /* If there's an alternate MAC address place it in RAR0
1440 * so that it will override the Si installed default perm
1443 ret_val = e1000_check_alt_mac_addr_generic(hw);
1447 return e1000_read_mac_addr_generic(hw);
1451 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1452 * @hw: pointer to the HW structure
1454 * In the case of a PHY power down to save power, or to turn off link during a
1455 * driver unload, or wake on lan is not enabled, remove the link.
1457 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1459 /* If the management interface is not enabled, then power down */
1460 if (!(hw->mac.ops.check_mng_mode(hw) ||
1461 hw->phy.ops.check_reset_block(hw)))
1462 e1000_power_down_phy_copper(hw);
1468 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1469 * @hw: pointer to the HW structure
1471 * Clears the hardware counters by reading the counter registers.
1473 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1475 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1477 e1000_clear_hw_cntrs_base_generic(hw);
1479 E1000_READ_REG(hw, E1000_PRC64);
1480 E1000_READ_REG(hw, E1000_PRC127);
1481 E1000_READ_REG(hw, E1000_PRC255);
1482 E1000_READ_REG(hw, E1000_PRC511);
1483 E1000_READ_REG(hw, E1000_PRC1023);
1484 E1000_READ_REG(hw, E1000_PRC1522);
1485 E1000_READ_REG(hw, E1000_PTC64);
1486 E1000_READ_REG(hw, E1000_PTC127);
1487 E1000_READ_REG(hw, E1000_PTC255);
1488 E1000_READ_REG(hw, E1000_PTC511);
1489 E1000_READ_REG(hw, E1000_PTC1023);
1490 E1000_READ_REG(hw, E1000_PTC1522);
1492 E1000_READ_REG(hw, E1000_ALGNERRC);
1493 E1000_READ_REG(hw, E1000_RXERRC);
1494 E1000_READ_REG(hw, E1000_TNCRS);
1495 E1000_READ_REG(hw, E1000_CEXTERR);
1496 E1000_READ_REG(hw, E1000_TSCTC);
1497 E1000_READ_REG(hw, E1000_TSCTFC);
1499 E1000_READ_REG(hw, E1000_MGTPRC);
1500 E1000_READ_REG(hw, E1000_MGTPDC);
1501 E1000_READ_REG(hw, E1000_MGTPTC);
1503 E1000_READ_REG(hw, E1000_IAC);
1504 E1000_READ_REG(hw, E1000_ICRXOC);
1506 E1000_READ_REG(hw, E1000_ICRXPTC);
1507 E1000_READ_REG(hw, E1000_ICRXATC);
1508 E1000_READ_REG(hw, E1000_ICTXPTC);
1509 E1000_READ_REG(hw, E1000_ICTXATC);
1510 E1000_READ_REG(hw, E1000_ICTXQEC);
1511 E1000_READ_REG(hw, E1000_ICTXQMTC);
1512 E1000_READ_REG(hw, E1000_ICRXDMTC);