1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
38 #include "e1000_api.h"
40 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
41 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
42 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
44 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
46 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
47 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
57 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
58 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
60 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
61 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
63 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
65 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
66 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
67 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
68 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
69 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
70 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
71 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
74 * A table for the GG82563 cable length where the range is defined
75 * with a lower bound at "index" and the upper bound at
78 static const u16 e1000_gg82563_cable_length_table[] =
79 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
80 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
81 (sizeof(e1000_gg82563_cable_length_table) / \
82 sizeof(e1000_gg82563_cable_length_table[0]))
85 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
86 * @hw: pointer to the HW structure
88 * This is a function pointer entry point called by the api module.
90 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
92 struct e1000_phy_info *phy = &hw->phy;
93 s32 ret_val = E1000_SUCCESS;
95 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
97 if (hw->phy.media_type != e1000_media_type_copper) {
98 phy->type = e1000_phy_none;
101 phy->ops.power_up = e1000_power_up_phy_copper;
102 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
107 phy->reset_delay_us = 100;
108 phy->type = e1000_phy_gg82563;
110 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
111 phy->ops.check_polarity = e1000_check_polarity_m88;
112 phy->ops.check_reset_block = e1000_check_reset_block_generic;
113 phy->ops.commit = e1000_phy_sw_reset_generic;
114 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
115 phy->ops.get_info = e1000_get_phy_info_m88;
116 phy->ops.release = e1000_release_phy_80003es2lan;
117 phy->ops.reset = e1000_phy_hw_reset_generic;
118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
120 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
121 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
122 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
123 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
125 /* This can only be done after all function pointers are setup. */
126 ret_val = e1000_get_phy_id(hw);
129 if (phy->id != GG82563_E_PHY_ID) {
130 ret_val = -E1000_ERR_PHY;
139 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
140 * @hw: pointer to the HW structure
142 * This is a function pointer entry point called by the api module.
144 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
146 struct e1000_nvm_info *nvm = &hw->nvm;
147 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
150 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
152 nvm->opcode_bits = 8;
154 switch (nvm->override) {
155 case e1000_nvm_override_spi_large:
157 nvm->address_bits = 16;
159 case e1000_nvm_override_spi_small:
161 nvm->address_bits = 8;
164 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
165 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
169 nvm->type = e1000_nvm_eeprom_spi;
171 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
172 E1000_EECD_SIZE_EX_SHIFT);
175 * Added to a constant, "size" becomes the left-shift value
176 * for setting word_size.
178 size += NVM_WORD_SIZE_BASE_SHIFT;
180 /* EEPROM access above 16k is unsupported */
183 nvm->word_size = 1 << size;
185 /* Function Pointers */
186 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
187 nvm->ops.read = e1000_read_nvm_eerd;
188 nvm->ops.release = e1000_release_nvm_80003es2lan;
189 nvm->ops.update = e1000_update_nvm_checksum_generic;
190 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
191 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
192 nvm->ops.write = e1000_write_nvm_80003es2lan;
194 return E1000_SUCCESS;
198 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
199 * @hw: pointer to the HW structure
201 * This is a function pointer entry point called by the api module.
203 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
205 struct e1000_mac_info *mac = &hw->mac;
206 s32 ret_val = E1000_SUCCESS;
208 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
211 switch (hw->device_id) {
212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
213 hw->phy.media_type = e1000_media_type_internal_serdes;
216 hw->phy.media_type = e1000_media_type_copper;
220 /* Set mta register count */
221 mac->mta_reg_count = 128;
222 /* Set rar entry count */
223 mac->rar_entry_count = E1000_RAR_ENTRIES;
224 /* Set if part includes ASF firmware */
225 mac->asf_firmware_present = TRUE;
226 /* Set if manageability features are enabled. */
227 mac->arc_subsystem_valid =
228 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
231 /* Function pointers */
233 /* bus type/speed/width */
234 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
236 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
237 /* hw initialization */
238 mac->ops.init_hw = e1000_init_hw_80003es2lan;
240 mac->ops.setup_link = e1000_setup_link_generic;
241 /* physical interface link setup */
242 mac->ops.setup_physical_interface =
243 (hw->phy.media_type == e1000_media_type_copper)
244 ? e1000_setup_copper_link_80003es2lan
245 : e1000_setup_fiber_serdes_link_generic;
247 switch (hw->phy.media_type) {
248 case e1000_media_type_copper:
249 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
251 case e1000_media_type_fiber:
252 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
254 case e1000_media_type_internal_serdes:
255 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
258 ret_val = -E1000_ERR_CONFIG;
262 /* check management mode */
263 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
264 /* multicast address update */
265 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
267 mac->ops.write_vfta = e1000_write_vfta_generic;
269 mac->ops.clear_vfta = e1000_clear_vfta_generic;
271 mac->ops.mta_set = e1000_mta_set_generic;
272 /* read mac address */
273 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
275 mac->ops.blink_led = e1000_blink_led_generic;
277 mac->ops.setup_led = e1000_setup_led_generic;
279 mac->ops.cleanup_led = e1000_cleanup_led_generic;
280 /* turn on/off LED */
281 mac->ops.led_on = e1000_led_on_generic;
282 mac->ops.led_off = e1000_led_off_generic;
284 mac->ops.remove_device = e1000_remove_device_generic;
285 /* clear hardware counters */
286 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
288 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
295 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
296 * @hw: pointer to the HW structure
298 * The only function explicitly called by the api module to initialize
299 * all function pointers and parameters.
301 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
303 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
305 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
306 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
307 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
311 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
312 * @hw: pointer to the HW structure
314 * A wrapper to acquire access rights to the correct PHY. This is a
315 * function pointer entry point called by the api module.
317 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
321 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
323 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
324 mask |= E1000_SWFW_CSR_SM;
326 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
330 * e1000_release_phy_80003es2lan - Release rights to access PHY
331 * @hw: pointer to the HW structure
333 * A wrapper to release access rights to the correct PHY. This is a
334 * function pointer entry point called by the api module.
336 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
340 DEBUGFUNC("e1000_release_phy_80003es2lan");
342 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
343 mask |= E1000_SWFW_CSR_SM;
345 e1000_release_swfw_sync_80003es2lan(hw, mask);
349 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
350 * @hw: pointer to the HW structure
352 * Acquire the semaphore to access the EEPROM. This is a function
353 * pointer entry point called by the api module.
355 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
359 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
361 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
365 ret_val = e1000_acquire_nvm_generic(hw);
368 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
375 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
376 * @hw: pointer to the HW structure
378 * Release the semaphore used to access the EEPROM. This is a
379 * function pointer entry point called by the api module.
381 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
383 DEBUGFUNC("e1000_release_nvm_80003es2lan");
385 e1000_release_nvm_generic(hw);
386 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
390 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
391 * @hw: pointer to the HW structure
392 * @mask: specifies which semaphore to acquire
394 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
395 * will also specify which port we're acquiring the lock for.
397 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
401 u32 fwmask = mask << 16;
402 s32 ret_val = E1000_SUCCESS;
403 s32 i = 0, timeout = 200;
405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
407 while (i < timeout) {
408 if (e1000_get_hw_semaphore_generic(hw)) {
409 ret_val = -E1000_ERR_SWFW_SYNC;
413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
414 if (!(swfw_sync & (fwmask | swmask)))
418 * Firmware currently using resource (fwmask)
419 * or other software thread using resource (swmask)
421 e1000_put_hw_semaphore_generic(hw);
427 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
428 ret_val = -E1000_ERR_SWFW_SYNC;
433 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
435 e1000_put_hw_semaphore_generic(hw);
442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
443 * @hw: pointer to the HW structure
444 * @mask: specifies which semaphore to acquire
446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
447 * will also specify which port we're releasing the lock for.
449 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
462 e1000_put_hw_semaphore_generic(hw);
466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
467 * @hw: pointer to the HW structure
468 * @offset: offset of the register to read
469 * @data: pointer to the data returned from the operation
471 * Read the GG82563 PHY register. This is a function pointer entry
472 * point called by the api module.
474 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
475 u32 offset, u16 *data)
481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
483 ret_val = e1000_acquire_phy_80003es2lan(hw);
487 /* Select Configuration Page */
488 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
489 page_select = GG82563_PHY_PAGE_SELECT;
492 * Use Alternative Page Select register to access
493 * registers 30 and 31
495 page_select = GG82563_PHY_PAGE_SELECT_ALT;
498 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
499 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
501 e1000_release_phy_80003es2lan(hw);
506 * The "ready" bit in the MDIC register may be incorrectly set
507 * before the device has completed the "Page Select" MDI
508 * transaction. So we wait 200us after each MDI command...
512 /* ...and verify the command was successful. */
513 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
515 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
516 ret_val = -E1000_ERR_PHY;
517 e1000_release_phy_80003es2lan(hw);
523 ret_val = e1000_read_phy_reg_mdic(hw,
524 MAX_PHY_REG_ADDRESS & offset,
528 e1000_release_phy_80003es2lan(hw);
535 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
536 * @hw: pointer to the HW structure
537 * @offset: offset of the register to read
538 * @data: value to write to the register
540 * Write to the GG82563 PHY register. This is a function pointer entry
541 * point called by the api module.
543 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
544 u32 offset, u16 data)
550 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
552 ret_val = e1000_acquire_phy_80003es2lan(hw);
556 /* Select Configuration Page */
557 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
558 page_select = GG82563_PHY_PAGE_SELECT;
561 * Use Alternative Page Select register to access
562 * registers 30 and 31
564 page_select = GG82563_PHY_PAGE_SELECT_ALT;
567 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
570 e1000_release_phy_80003es2lan(hw);
576 * The "ready" bit in the MDIC register may be incorrectly set
577 * before the device has completed the "Page Select" MDI
578 * transaction. So we wait 200us after each MDI command...
582 /* ...and verify the command was successful. */
583 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
585 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
586 ret_val = -E1000_ERR_PHY;
587 e1000_release_phy_80003es2lan(hw);
593 ret_val = e1000_write_phy_reg_mdic(hw,
594 MAX_PHY_REG_ADDRESS & offset,
598 e1000_release_phy_80003es2lan(hw);
605 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
606 * @hw: pointer to the HW structure
607 * @offset: offset of the register to read
608 * @words: number of words to write
609 * @data: buffer of data to write to the NVM
611 * Write "words" of data to the ESB2 NVM. This is a function
612 * pointer entry point called by the api module.
614 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
615 u16 words, u16 *data)
617 DEBUGFUNC("e1000_write_nvm_80003es2lan");
619 return e1000_write_nvm_spi(hw, offset, words, data);
623 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
624 * @hw: pointer to the HW structure
626 * Wait a specific amount of time for manageability processes to complete.
627 * This is a function pointer entry point called by the phy module.
629 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
631 s32 timeout = PHY_CFG_TIMEOUT;
632 s32 ret_val = E1000_SUCCESS;
633 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
635 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
637 if (hw->bus.func == 1)
638 mask = E1000_NVM_CFG_DONE_PORT_1;
641 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
647 DEBUGOUT("MNG configuration cycle has not completed.\n");
648 ret_val = -E1000_ERR_RESET;
657 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
658 * @hw: pointer to the HW structure
660 * Force the speed and duplex settings onto the PHY. This is a
661 * function pointer entry point called by the phy module.
663 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
665 s32 ret_val = E1000_SUCCESS;
669 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
671 if (!(hw->phy.ops.read_reg))
675 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
676 * forced whenever speed and duplex are forced.
678 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
682 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
683 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
687 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
689 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
693 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
695 /* Reset the phy to commit changes. */
696 phy_data |= MII_CR_RESET;
698 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
704 if (hw->phy.autoneg_wait_to_complete) {
705 DEBUGOUT("Waiting for forced speed/duplex link "
706 "on GG82563 phy.\n");
708 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
715 * We didn't get link.
716 * Reset the DSP and cross our fingers.
718 ret_val = e1000_phy_reset_dsp_generic(hw);
724 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
730 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
735 * Resetting the phy means we need to verify the TX_CLK corresponds
736 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
738 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
739 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
740 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
742 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
745 * In addition, we must re-enable CRS on Tx for both half and full
748 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
749 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
756 * e1000_get_cable_length_80003es2lan - Set approximate cable length
757 * @hw: pointer to the HW structure
759 * Find the approximate cable length as measured by the GG82563 PHY.
760 * This is a function pointer entry point called by the phy module.
762 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
764 struct e1000_phy_info *phy = &hw->phy;
765 s32 ret_val = E1000_SUCCESS;
768 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
770 if (!(hw->phy.ops.read_reg))
773 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
777 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
778 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
779 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
781 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
788 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
789 * @hw: pointer to the HW structure
790 * @speed: pointer to speed buffer
791 * @duplex: pointer to duplex buffer
793 * Retrieve the current speed and duplex configuration.
794 * This is a function pointer entry point called by the api module.
796 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
801 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
803 if (hw->phy.media_type == e1000_media_type_copper) {
804 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
809 if (*speed == SPEED_1000)
810 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
812 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
815 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
825 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
826 * @hw: pointer to the HW structure
828 * Perform a global reset to the ESB2 controller.
829 * This is a function pointer entry point called by the api module.
831 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
836 DEBUGFUNC("e1000_reset_hw_80003es2lan");
839 * Prevent the PCI-E bus from sticking if there is no TLP connection
840 * on the last TLP read/write transaction when MAC is reset.
842 ret_val = e1000_disable_pcie_master_generic(hw);
844 DEBUGOUT("PCI-E Master disable polling has failed.\n");
847 DEBUGOUT("Masking off all interrupts\n");
848 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
850 E1000_WRITE_REG(hw, E1000_RCTL, 0);
851 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
852 E1000_WRITE_FLUSH(hw);
856 ctrl = E1000_READ_REG(hw, E1000_CTRL);
858 DEBUGOUT("Issuing a global reset to MAC\n");
859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
861 ret_val = e1000_get_auto_rd_done_generic(hw);
863 /* We don't want to continue accessing MAC registers. */
866 /* Clear any pending interrupt events. */
867 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
868 icr = E1000_READ_REG(hw, E1000_ICR);
870 e1000_check_alt_mac_addr_generic(hw);
877 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
878 * @hw: pointer to the HW structure
880 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
881 * This is a function pointer entry point called by the api module.
883 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
885 struct e1000_mac_info *mac = &hw->mac;
890 DEBUGFUNC("e1000_init_hw_80003es2lan");
892 e1000_initialize_hw_bits_80003es2lan(hw);
894 /* Initialize identification LED */
895 ret_val = e1000_id_led_init_generic(hw);
897 DEBUGOUT("Error initializing identification LED\n");
898 /* This is not fatal and we should not stop init due to this */
901 /* Disabling VLAN filtering */
902 DEBUGOUT("Initializing the IEEE VLAN\n");
903 mac->ops.clear_vfta(hw);
905 /* Setup the receive address. */
906 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
908 /* Zero out the Multicast HASH table */
909 DEBUGOUT("Zeroing the MTA\n");
910 for (i = 0; i < mac->mta_reg_count; i++)
911 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
913 /* Setup link and flow control */
914 ret_val = mac->ops.setup_link(hw);
916 /* Set the transmit descriptor write-back policy */
917 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
918 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
919 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
920 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
922 /* ...for both queues. */
923 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
924 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
925 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
926 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
928 /* Enable retransmit on late collisions */
929 reg_data = E1000_READ_REG(hw, E1000_TCTL);
930 reg_data |= E1000_TCTL_RTLC;
931 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
933 /* Configure Gigabit Carry Extend Padding */
934 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
935 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
936 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
937 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
939 /* Configure Transmit Inter-Packet Gap */
940 reg_data = E1000_READ_REG(hw, E1000_TIPG);
941 reg_data &= ~E1000_TIPG_IPGT_MASK;
942 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
943 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
945 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
946 reg_data &= ~0x00100000;
947 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
950 * Clear all of the statistics registers (clear on read). It is
951 * important that we do this after we have tried to establish link
952 * because the symbol error count will increment wildly if there
955 e1000_clear_hw_cntrs_80003es2lan(hw);
961 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
962 * @hw: pointer to the HW structure
964 * Initializes required hardware-dependent bits needed for normal operation.
966 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
970 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
972 if (hw->mac.disable_hw_init_bits)
975 /* Transmit Descriptor Control 0 */
976 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
978 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
980 /* Transmit Descriptor Control 1 */
981 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
983 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
985 /* Transmit Arbitration Control 0 */
986 reg = E1000_READ_REG(hw, E1000_TARC(0));
987 reg &= ~(0xF << 27); /* 30:27 */
988 if (hw->phy.media_type != e1000_media_type_copper)
990 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
992 /* Transmit Arbitration Control 1 */
993 reg = E1000_READ_REG(hw, E1000_TARC(1));
994 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
998 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1005 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1006 * @hw: pointer to the HW structure
1008 * Setup some GG82563 PHY registers for obtaining link
1010 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1012 struct e1000_phy_info *phy = &hw->phy;
1018 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1020 if (!phy->reset_disable) {
1021 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1026 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1027 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1028 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1030 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1037 * MDI/MDI-X = 0 (default)
1038 * 0 - Auto for all speeds
1041 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1043 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1047 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1049 switch (phy->mdix) {
1051 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1054 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1058 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1064 * disable_polarity_correction = 0 (default)
1065 * Automatic Correction for Reversed Cable Polarity
1069 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1070 if (phy->disable_polarity_correction)
1071 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1073 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1077 /* SW Reset the PHY so all changes take effect */
1078 ret_val = hw->phy.ops.commit(hw);
1080 DEBUGOUT("Error Resetting the PHY\n");
1086 /* Bypass Rx and Tx FIFO's */
1087 ret_val = e1000_write_kmrn_reg_generic(hw,
1088 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1089 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1090 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1094 ret_val = e1000_read_kmrn_reg_generic(hw,
1095 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1099 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1100 ret_val = e1000_write_kmrn_reg_generic(hw,
1101 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1106 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1110 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1111 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1115 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1116 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1117 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1119 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1124 * Do not init these registers when the HW is in IAMT mode, since the
1125 * firmware will have already initialized them. We only initialize
1126 * them if the HW is not in IAMT mode.
1128 if (!(hw->mac.ops.check_mng_mode(hw))) {
1129 /* Enable Electrical Idle on the PHY */
1130 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1131 ret_val = hw->phy.ops.write_reg(hw,
1132 GG82563_PHY_PWR_MGMT_CTRL,
1138 ret_val = hw->phy.ops.read_reg(hw,
1139 GG82563_PHY_KMRN_MODE_CTRL,
1144 ret_val = hw->phy.ops.read_reg(hw,
1145 GG82563_PHY_KMRN_MODE_CTRL,
1150 } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY));
1152 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1153 ret_val = hw->phy.ops.write_reg(hw,
1154 GG82563_PHY_KMRN_MODE_CTRL,
1162 * Workaround: Disable padding in Kumeran interface in the MAC
1163 * and in the PHY to avoid CRC errors.
1165 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1169 data |= GG82563_ICR_DIS_PADDING;
1170 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1179 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1180 * @hw: pointer to the HW structure
1182 * Essentially a wrapper for setting up all things "copper" related.
1183 * This is a function pointer entry point called by the mac module.
1185 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1191 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1193 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1194 ctrl |= E1000_CTRL_SLU;
1195 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1196 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1199 * Set the mac to wait the maximum time between each
1200 * iteration and increase the max iterations when
1201 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1203 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4),
1207 ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
1212 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
1216 ret_val = e1000_read_kmrn_reg_generic(hw,
1217 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1221 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1222 ret_val = e1000_write_kmrn_reg_generic(hw,
1223 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1228 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1232 ret_val = e1000_setup_copper_link_generic(hw);
1239 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1240 * @hw: pointer to the HW structure
1241 * @duplex: current duplex setting
1243 * Configure the KMRN interface by applying last minute quirks for
1246 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1248 s32 ret_val = E1000_SUCCESS;
1251 u16 reg_data, reg_data2;
1253 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1255 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1256 ret_val = e1000_write_kmrn_reg_generic(hw,
1257 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1262 /* Configure Transmit Inter-Packet Gap */
1263 tipg = E1000_READ_REG(hw, E1000_TIPG);
1264 tipg &= ~E1000_TIPG_IPGT_MASK;
1265 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1266 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1270 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1275 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1280 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1282 if (duplex == HALF_DUPLEX)
1283 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1285 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1287 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1294 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1295 * @hw: pointer to the HW structure
1297 * Configure the KMRN interface by applying last minute quirks for
1298 * gigabit operation.
1300 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1302 s32 ret_val = E1000_SUCCESS;
1303 u16 reg_data, reg_data2;
1307 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1309 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1310 ret_val = e1000_write_kmrn_reg_generic(hw,
1311 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1316 /* Configure Transmit Inter-Packet Gap */
1317 tipg = E1000_READ_REG(hw, E1000_TIPG);
1318 tipg &= ~E1000_TIPG_IPGT_MASK;
1319 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1320 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1324 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1329 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1334 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1336 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1337 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1344 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1345 * @hw: pointer to the HW structure
1347 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1349 s32 ret_val = E1000_SUCCESS;
1351 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1352 if (e1000_check_alt_mac_addr_generic(hw))
1353 ret_val = e1000_read_mac_addr_generic(hw);
1359 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1360 * @hw: pointer to the HW structure
1362 * In the case of a PHY power down to save power, or to turn off link during a
1363 * driver unload, or wake on lan is not enabled, remove the link.
1365 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1367 /* If the management interface is not enabled, then power down */
1368 if (!(hw->mac.ops.check_mng_mode(hw) ||
1369 hw->phy.ops.check_reset_block(hw)))
1370 e1000_power_down_phy_copper(hw);
1376 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1377 * @hw: pointer to the HW structure
1379 * Clears the hardware counters by reading the counter registers.
1381 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1385 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1387 e1000_clear_hw_cntrs_base_generic(hw);
1389 temp = E1000_READ_REG(hw, E1000_PRC64);
1390 temp = E1000_READ_REG(hw, E1000_PRC127);
1391 temp = E1000_READ_REG(hw, E1000_PRC255);
1392 temp = E1000_READ_REG(hw, E1000_PRC511);
1393 temp = E1000_READ_REG(hw, E1000_PRC1023);
1394 temp = E1000_READ_REG(hw, E1000_PRC1522);
1395 temp = E1000_READ_REG(hw, E1000_PTC64);
1396 temp = E1000_READ_REG(hw, E1000_PTC127);
1397 temp = E1000_READ_REG(hw, E1000_PTC255);
1398 temp = E1000_READ_REG(hw, E1000_PTC511);
1399 temp = E1000_READ_REG(hw, E1000_PTC1023);
1400 temp = E1000_READ_REG(hw, E1000_PTC1522);
1402 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1403 temp = E1000_READ_REG(hw, E1000_RXERRC);
1404 temp = E1000_READ_REG(hw, E1000_TNCRS);
1405 temp = E1000_READ_REG(hw, E1000_CEXTERR);
1406 temp = E1000_READ_REG(hw, E1000_TSCTC);
1407 temp = E1000_READ_REG(hw, E1000_TSCTFC);
1409 temp = E1000_READ_REG(hw, E1000_MGTPRC);
1410 temp = E1000_READ_REG(hw, E1000_MGTPDC);
1411 temp = E1000_READ_REG(hw, E1000_MGTPTC);
1413 temp = E1000_READ_REG(hw, E1000_IAC);
1414 temp = E1000_READ_REG(hw, E1000_ICRXOC);
1416 temp = E1000_READ_REG(hw, E1000_ICRXPTC);
1417 temp = E1000_READ_REG(hw, E1000_ICRXATC);
1418 temp = E1000_READ_REG(hw, E1000_ICTXPTC);
1419 temp = E1000_READ_REG(hw, E1000_ICTXATC);
1420 temp = E1000_READ_REG(hw, E1000_ICTXQEC);
1421 temp = E1000_READ_REG(hw, E1000_ICTXQMTC);
1422 temp = E1000_READ_REG(hw, E1000_ICRXDMTC);