1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
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33 ******************************************************************************/
36 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
40 #include "e1000_api.h"
42 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
43 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
44 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
45 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
46 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
49 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
52 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
53 u16 words, u16 *data);
54 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
57 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
59 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
61 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
62 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
71 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
72 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
74 /* A table for the GG82563 cable length where the range is defined
75 * with a lower bound at "index" and the upper bound at
78 static const u16 e1000_gg82563_cable_length_table[] = {
79 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
80 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
81 (sizeof(e1000_gg82563_cable_length_table) / \
82 sizeof(e1000_gg82563_cable_length_table[0]))
85 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
86 * @hw: pointer to the HW structure
88 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
90 struct e1000_phy_info *phy = &hw->phy;
93 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
95 if (hw->phy.media_type != e1000_media_type_copper) {
96 phy->type = e1000_phy_none;
99 phy->ops.power_up = e1000_power_up_phy_copper;
100 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106 phy->type = e1000_phy_gg82563;
108 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
109 phy->ops.check_polarity = e1000_check_polarity_m88;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.commit = e1000_phy_sw_reset_generic;
112 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
113 phy->ops.get_info = e1000_get_phy_info_m88;
114 phy->ops.release = e1000_release_phy_80003es2lan;
115 phy->ops.reset = e1000_phy_hw_reset_generic;
116 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
118 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
119 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
120 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
121 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
123 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
125 /* This can only be done after all function pointers are setup. */
126 ret_val = e1000_get_phy_id(hw);
129 if (phy->id != GG82563_E_PHY_ID)
130 return -E1000_ERR_PHY;
136 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
137 * @hw: pointer to the HW structure
139 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
141 struct e1000_nvm_info *nvm = &hw->nvm;
142 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
145 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
147 nvm->opcode_bits = 8;
149 switch (nvm->override) {
150 case e1000_nvm_override_spi_large:
152 nvm->address_bits = 16;
154 case e1000_nvm_override_spi_small:
156 nvm->address_bits = 8;
159 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
160 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
164 nvm->type = e1000_nvm_eeprom_spi;
166 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
167 E1000_EECD_SIZE_EX_SHIFT);
169 /* Added to a constant, "size" becomes the left-shift value
170 * for setting word_size.
172 size += NVM_WORD_SIZE_BASE_SHIFT;
174 /* EEPROM access above 16k is unsupported */
177 nvm->word_size = 1 << size;
179 /* Function Pointers */
180 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
181 nvm->ops.read = e1000_read_nvm_eerd;
182 nvm->ops.release = e1000_release_nvm_80003es2lan;
183 nvm->ops.update = e1000_update_nvm_checksum_generic;
184 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
185 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
186 nvm->ops.write = e1000_write_nvm_80003es2lan;
188 return E1000_SUCCESS;
192 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
193 * @hw: pointer to the HW structure
195 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
197 struct e1000_mac_info *mac = &hw->mac;
199 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
201 /* Set media type and media-dependent function pointers */
202 switch (hw->device_id) {
203 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
204 hw->phy.media_type = e1000_media_type_internal_serdes;
205 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
206 mac->ops.setup_physical_interface =
207 e1000_setup_fiber_serdes_link_generic;
210 hw->phy.media_type = e1000_media_type_copper;
211 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
212 mac->ops.setup_physical_interface =
213 e1000_setup_copper_link_80003es2lan;
217 /* Set mta register count */
218 mac->mta_reg_count = 128;
219 /* Set rar entry count */
220 mac->rar_entry_count = E1000_RAR_ENTRIES;
221 /* Set if part includes ASF firmware */
222 mac->asf_firmware_present = TRUE;
224 mac->has_fwsm = TRUE;
225 /* ARC supported; valid only if manageability features are enabled. */
226 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
227 E1000_FWSM_MODE_MASK);
228 /* Adaptive IFS not supported */
229 mac->adaptive_ifs = FALSE;
231 /* Function pointers */
233 /* bus type/speed/width */
234 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
236 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
237 /* hw initialization */
238 mac->ops.init_hw = e1000_init_hw_80003es2lan;
240 mac->ops.setup_link = e1000_setup_link_generic;
241 /* check management mode */
242 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
243 /* multicast address update */
244 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
246 mac->ops.write_vfta = e1000_write_vfta_generic;
248 mac->ops.clear_vfta = e1000_clear_vfta_generic;
249 /* read mac address */
250 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
252 mac->ops.id_led_init = e1000_id_led_init_generic;
254 mac->ops.blink_led = e1000_blink_led_generic;
256 mac->ops.setup_led = e1000_setup_led_generic;
258 mac->ops.cleanup_led = e1000_cleanup_led_generic;
259 /* turn on/off LED */
260 mac->ops.led_on = e1000_led_on_generic;
261 mac->ops.led_off = e1000_led_off_generic;
262 /* clear hardware counters */
263 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
265 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
267 /* set lan id for port to determine which phy lock to use */
268 hw->mac.ops.set_lan_id(hw);
270 return E1000_SUCCESS;
274 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
275 * @hw: pointer to the HW structure
277 * Called to initialize all function pointers and parameters.
279 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
281 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
283 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
284 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
285 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
289 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
290 * @hw: pointer to the HW structure
292 * A wrapper to acquire access rights to the correct PHY.
294 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
298 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
300 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
301 return e1000_acquire_swfw_sync(hw, mask);
305 * e1000_release_phy_80003es2lan - Release rights to access PHY
306 * @hw: pointer to the HW structure
308 * A wrapper to release access rights to the correct PHY.
310 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
314 DEBUGFUNC("e1000_release_phy_80003es2lan");
316 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
317 e1000_release_swfw_sync(hw, mask);
321 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
322 * @hw: pointer to the HW structure
324 * Acquire the semaphore to access the Kumeran interface.
327 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
331 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
333 mask = E1000_SWFW_CSR_SM;
335 return e1000_acquire_swfw_sync(hw, mask);
339 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
340 * @hw: pointer to the HW structure
342 * Release the semaphore used to access the Kumeran interface
344 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
348 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
350 mask = E1000_SWFW_CSR_SM;
352 e1000_release_swfw_sync(hw, mask);
356 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
357 * @hw: pointer to the HW structure
359 * Acquire the semaphore to access the EEPROM.
361 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
365 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
367 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
371 ret_val = e1000_acquire_nvm_generic(hw);
374 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
380 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
381 * @hw: pointer to the HW structure
383 * Release the semaphore used to access the EEPROM.
385 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
387 DEBUGFUNC("e1000_release_nvm_80003es2lan");
389 e1000_release_nvm_generic(hw);
390 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
394 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
395 * @hw: pointer to the HW structure
396 * @offset: offset of the register to read
397 * @data: pointer to the data returned from the operation
399 * Read the GG82563 PHY register.
401 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
402 u32 offset, u16 *data)
408 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
410 ret_val = e1000_acquire_phy_80003es2lan(hw);
414 /* Select Configuration Page */
415 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
416 page_select = GG82563_PHY_PAGE_SELECT;
418 /* Use Alternative Page Select register to access
419 * registers 30 and 31
421 page_select = GG82563_PHY_PAGE_SELECT_ALT;
424 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
425 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
427 e1000_release_phy_80003es2lan(hw);
431 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
432 /* The "ready" bit in the MDIC register may be incorrectly set
433 * before the device has completed the "Page Select" MDI
434 * transaction. So we wait 200us after each MDI command...
438 /* ...and verify the command was successful. */
439 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
441 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
442 e1000_release_phy_80003es2lan(hw);
443 return -E1000_ERR_PHY;
448 ret_val = e1000_read_phy_reg_mdic(hw,
449 MAX_PHY_REG_ADDRESS & offset,
454 ret_val = e1000_read_phy_reg_mdic(hw,
455 MAX_PHY_REG_ADDRESS & offset,
459 e1000_release_phy_80003es2lan(hw);
465 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
466 * @hw: pointer to the HW structure
467 * @offset: offset of the register to read
468 * @data: value to write to the register
470 * Write to the GG82563 PHY register.
472 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
473 u32 offset, u16 data)
479 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
481 ret_val = e1000_acquire_phy_80003es2lan(hw);
485 /* Select Configuration Page */
486 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
487 page_select = GG82563_PHY_PAGE_SELECT;
489 /* Use Alternative Page Select register to access
490 * registers 30 and 31
492 page_select = GG82563_PHY_PAGE_SELECT_ALT;
495 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
496 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
498 e1000_release_phy_80003es2lan(hw);
502 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
503 /* The "ready" bit in the MDIC register may be incorrectly set
504 * before the device has completed the "Page Select" MDI
505 * transaction. So we wait 200us after each MDI command...
509 /* ...and verify the command was successful. */
510 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
512 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
513 e1000_release_phy_80003es2lan(hw);
514 return -E1000_ERR_PHY;
519 ret_val = e1000_write_phy_reg_mdic(hw,
520 MAX_PHY_REG_ADDRESS & offset,
525 ret_val = e1000_write_phy_reg_mdic(hw,
526 MAX_PHY_REG_ADDRESS & offset,
530 e1000_release_phy_80003es2lan(hw);
536 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
537 * @hw: pointer to the HW structure
538 * @offset: offset of the register to read
539 * @words: number of words to write
540 * @data: buffer of data to write to the NVM
542 * Write "words" of data to the ESB2 NVM.
544 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
545 u16 words, u16 *data)
547 DEBUGFUNC("e1000_write_nvm_80003es2lan");
549 return e1000_write_nvm_spi(hw, offset, words, data);
553 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
554 * @hw: pointer to the HW structure
556 * Wait a specific amount of time for manageability processes to complete.
557 * This is a function pointer entry point called by the phy module.
559 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
561 s32 timeout = PHY_CFG_TIMEOUT;
562 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
564 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
566 if (hw->bus.func == 1)
567 mask = E1000_NVM_CFG_DONE_PORT_1;
570 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
576 DEBUGOUT("MNG configuration cycle has not completed.\n");
577 return -E1000_ERR_RESET;
580 return E1000_SUCCESS;
584 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
585 * @hw: pointer to the HW structure
587 * Force the speed and duplex settings onto the PHY. This is a
588 * function pointer entry point called by the phy module.
590 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
596 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
598 if (!(hw->phy.ops.read_reg))
599 return E1000_SUCCESS;
601 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
602 * forced whenever speed and duplex are forced.
604 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
608 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
609 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
613 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
615 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
619 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
621 /* Reset the phy to commit changes. */
622 phy_data |= MII_CR_RESET;
624 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
630 if (hw->phy.autoneg_wait_to_complete) {
631 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
633 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
639 /* We didn't get link.
640 * Reset the DSP and cross our fingers.
642 ret_val = e1000_phy_reset_dsp_generic(hw);
648 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
654 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
659 /* Resetting the phy means we need to verify the TX_CLK corresponds
660 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
662 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
663 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
664 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
666 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
668 /* In addition, we must re-enable CRS on Tx for both half and full
671 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
672 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
679 * e1000_get_cable_length_80003es2lan - Set approximate cable length
680 * @hw: pointer to the HW structure
682 * Find the approximate cable length as measured by the GG82563 PHY.
683 * This is a function pointer entry point called by the phy module.
685 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
687 struct e1000_phy_info *phy = &hw->phy;
691 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
693 if (!(hw->phy.ops.read_reg))
694 return E1000_SUCCESS;
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
700 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
702 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
703 return -E1000_ERR_PHY;
705 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
706 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
708 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
710 return E1000_SUCCESS;
714 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
715 * @hw: pointer to the HW structure
716 * @speed: pointer to speed buffer
717 * @duplex: pointer to duplex buffer
719 * Retrieve the current speed and duplex configuration.
721 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
726 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
728 if (hw->phy.media_type == e1000_media_type_copper) {
729 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
731 hw->phy.ops.cfg_on_link_up(hw);
733 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
742 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
743 * @hw: pointer to the HW structure
745 * Perform a global reset to the ESB2 controller.
747 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
753 DEBUGFUNC("e1000_reset_hw_80003es2lan");
755 /* Prevent the PCI-E bus from sticking if there is no TLP connection
756 * on the last TLP read/write transaction when MAC is reset.
758 ret_val = e1000_disable_pcie_master_generic(hw);
760 DEBUGOUT("PCI-E Master disable polling has failed.\n");
762 DEBUGOUT("Masking off all interrupts\n");
763 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
765 E1000_WRITE_REG(hw, E1000_RCTL, 0);
766 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
767 E1000_WRITE_FLUSH(hw);
771 ctrl = E1000_READ_REG(hw, E1000_CTRL);
773 ret_val = e1000_acquire_phy_80003es2lan(hw);
777 DEBUGOUT("Issuing a global reset to MAC\n");
778 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
779 e1000_release_phy_80003es2lan(hw);
781 /* Disable IBIST slave mode (far-end loopback) */
782 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
783 E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
785 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
786 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
787 E1000_KMRNCTRLSTA_INBAND_PARAM,
790 DEBUGOUT("Error disabling far-end loopback\n");
792 DEBUGOUT("Error disabling far-end loopback\n");
794 ret_val = e1000_get_auto_rd_done_generic(hw);
796 /* We don't want to continue accessing MAC registers. */
799 /* Clear any pending interrupt events. */
800 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
801 E1000_READ_REG(hw, E1000_ICR);
803 return e1000_check_alt_mac_addr_generic(hw);
807 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
808 * @hw: pointer to the HW structure
810 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
812 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
814 struct e1000_mac_info *mac = &hw->mac;
820 DEBUGFUNC("e1000_init_hw_80003es2lan");
822 e1000_initialize_hw_bits_80003es2lan(hw);
824 /* Initialize identification LED */
825 ret_val = mac->ops.id_led_init(hw);
826 /* An error is not fatal and we should not stop init due to this */
828 DEBUGOUT("Error initializing identification LED\n");
830 /* Disabling VLAN filtering */
831 DEBUGOUT("Initializing the IEEE VLAN\n");
832 mac->ops.clear_vfta(hw);
834 /* Setup the receive address. */
835 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
837 /* Zero out the Multicast HASH table */
838 DEBUGOUT("Zeroing the MTA\n");
839 for (i = 0; i < mac->mta_reg_count; i++)
840 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
842 /* Setup link and flow control */
843 ret_val = mac->ops.setup_link(hw);
847 /* Disable IBIST slave mode (far-end loopback) */
849 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
852 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
853 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
854 E1000_KMRNCTRLSTA_INBAND_PARAM,
857 DEBUGOUT("Error disabling far-end loopback\n");
859 DEBUGOUT("Error disabling far-end loopback\n");
861 /* Set the transmit descriptor write-back policy */
862 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
863 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
864 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
865 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
867 /* ...for both queues. */
868 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
869 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
870 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
871 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
873 /* Enable retransmit on late collisions */
874 reg_data = E1000_READ_REG(hw, E1000_TCTL);
875 reg_data |= E1000_TCTL_RTLC;
876 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
878 /* Configure Gigabit Carry Extend Padding */
879 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
880 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
881 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
882 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
884 /* Configure Transmit Inter-Packet Gap */
885 reg_data = E1000_READ_REG(hw, E1000_TIPG);
886 reg_data &= ~E1000_TIPG_IPGT_MASK;
887 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
888 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
890 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
891 reg_data &= ~0x00100000;
892 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
894 /* default to TRUE to enable the MDIC W/A */
895 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
898 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
899 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
901 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
902 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
903 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
906 /* Clear all of the statistics registers (clear on read). It is
907 * important that we do this after we have tried to establish link
908 * because the symbol error count will increment wildly if there
911 e1000_clear_hw_cntrs_80003es2lan(hw);
917 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
918 * @hw: pointer to the HW structure
920 * Initializes required hardware-dependent bits needed for normal operation.
922 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
926 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
928 /* Transmit Descriptor Control 0 */
929 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
931 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
933 /* Transmit Descriptor Control 1 */
934 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
936 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
938 /* Transmit Arbitration Control 0 */
939 reg = E1000_READ_REG(hw, E1000_TARC(0));
940 reg &= ~(0xF << 27); /* 30:27 */
941 if (hw->phy.media_type != e1000_media_type_copper)
943 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
945 /* Transmit Arbitration Control 1 */
946 reg = E1000_READ_REG(hw, E1000_TARC(1));
947 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
951 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
953 /* Disable IPv6 extension header parsing because some malformed
954 * IPv6 headers can hang the Rx.
956 reg = E1000_READ_REG(hw, E1000_RFCTL);
957 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
958 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
964 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
965 * @hw: pointer to the HW structure
967 * Setup some GG82563 PHY registers for obtaining link
969 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
971 struct e1000_phy_info *phy = &hw->phy;
976 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
978 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
982 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
983 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
984 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
986 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
991 * MDI/MDI-X = 0 (default)
992 * 0 - Auto for all speeds
995 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
997 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1001 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1003 switch (phy->mdix) {
1005 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1008 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1012 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1017 * disable_polarity_correction = 0 (default)
1018 * Automatic Correction for Reversed Cable Polarity
1022 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1023 if (phy->disable_polarity_correction)
1024 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1026 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1030 /* SW Reset the PHY so all changes take effect */
1031 ret_val = hw->phy.ops.commit(hw);
1033 DEBUGOUT("Error Resetting the PHY\n");
1037 /* Bypass Rx and Tx FIFO's */
1038 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1039 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1040 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1045 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1046 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1049 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1050 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1054 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1058 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1059 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1063 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1064 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1065 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1067 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1071 /* Do not init these registers when the HW is in IAMT mode, since the
1072 * firmware will have already initialized them. We only initialize
1073 * them if the HW is not in IAMT mode.
1075 if (!hw->mac.ops.check_mng_mode(hw)) {
1076 /* Enable Electrical Idle on the PHY */
1077 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1078 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1088 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1089 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1095 /* Workaround: Disable padding in Kumeran interface in the MAC
1096 * and in the PHY to avoid CRC errors.
1098 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1102 data |= GG82563_ICR_DIS_PADDING;
1103 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1107 return E1000_SUCCESS;
1111 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1112 * @hw: pointer to the HW structure
1114 * Essentially a wrapper for setting up all things "copper" related.
1115 * This is a function pointer entry point called by the mac module.
1117 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1123 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1125 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1126 ctrl |= E1000_CTRL_SLU;
1127 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1128 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1130 /* Set the mac to wait the maximum time between each
1131 * iteration and increase the max iterations when
1132 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1134 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1138 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1143 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1148 e1000_read_kmrn_reg_80003es2lan(hw,
1149 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1153 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1155 e1000_write_kmrn_reg_80003es2lan(hw,
1156 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1161 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1165 return e1000_setup_copper_link_generic(hw);
1169 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1170 * @hw: pointer to the HW structure
1171 * @duplex: current duplex setting
1173 * Configure the KMRN interface by applying last minute quirks for
1176 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1178 s32 ret_val = E1000_SUCCESS;
1182 DEBUGFUNC("e1000_configure_on_link_up");
1184 if (hw->phy.media_type == e1000_media_type_copper) {
1185 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1190 if (speed == SPEED_1000)
1191 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1193 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1200 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1201 * @hw: pointer to the HW structure
1202 * @duplex: current duplex setting
1204 * Configure the KMRN interface by applying last minute quirks for
1207 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1212 u16 reg_data, reg_data2;
1214 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1216 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1218 e1000_write_kmrn_reg_80003es2lan(hw,
1219 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1224 /* Configure Transmit Inter-Packet Gap */
1225 tipg = E1000_READ_REG(hw, E1000_TIPG);
1226 tipg &= ~E1000_TIPG_IPGT_MASK;
1227 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1228 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1231 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1236 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1241 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1243 if (duplex == HALF_DUPLEX)
1244 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1246 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1248 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1252 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1253 * @hw: pointer to the HW structure
1255 * Configure the KMRN interface by applying last minute quirks for
1256 * gigabit operation.
1258 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1261 u16 reg_data, reg_data2;
1265 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1267 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1269 e1000_write_kmrn_reg_80003es2lan(hw,
1270 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1275 /* Configure Transmit Inter-Packet Gap */
1276 tipg = E1000_READ_REG(hw, E1000_TIPG);
1277 tipg &= ~E1000_TIPG_IPGT_MASK;
1278 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1279 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1282 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1287 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1292 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1294 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1296 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1300 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1301 * @hw: pointer to the HW structure
1302 * @offset: register offset to be read
1303 * @data: pointer to the read data
1305 * Acquire semaphore, then read the PHY register at offset
1306 * using the kumeran interface. The information retrieved is stored in data.
1307 * Release the semaphore before exiting.
1309 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1315 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1317 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1321 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1322 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1323 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1324 E1000_WRITE_FLUSH(hw);
1328 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1329 *data = (u16)kmrnctrlsta;
1331 e1000_release_mac_csr_80003es2lan(hw);
1337 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1338 * @hw: pointer to the HW structure
1339 * @offset: register offset to write to
1340 * @data: data to write at register offset
1342 * Acquire semaphore, then write the data to PHY register
1343 * at the offset using the kumeran interface. Release semaphore
1346 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1352 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1354 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1358 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1359 E1000_KMRNCTRLSTA_OFFSET) | data;
1360 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1361 E1000_WRITE_FLUSH(hw);
1365 e1000_release_mac_csr_80003es2lan(hw);
1371 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1372 * @hw: pointer to the HW structure
1374 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1378 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1380 /* If there's an alternate MAC address place it in RAR0
1381 * so that it will override the Si installed default perm
1384 ret_val = e1000_check_alt_mac_addr_generic(hw);
1388 return e1000_read_mac_addr_generic(hw);
1392 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1393 * @hw: pointer to the HW structure
1395 * In the case of a PHY power down to save power, or to turn off link during a
1396 * driver unload, or wake on lan is not enabled, remove the link.
1398 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1400 /* If the management interface is not enabled, then power down */
1401 if (!(hw->mac.ops.check_mng_mode(hw) ||
1402 hw->phy.ops.check_reset_block(hw)))
1403 e1000_power_down_phy_copper(hw);
1409 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1410 * @hw: pointer to the HW structure
1412 * Clears the hardware counters by reading the counter registers.
1414 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1416 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1418 e1000_clear_hw_cntrs_base_generic(hw);
1420 E1000_READ_REG(hw, E1000_PRC64);
1421 E1000_READ_REG(hw, E1000_PRC127);
1422 E1000_READ_REG(hw, E1000_PRC255);
1423 E1000_READ_REG(hw, E1000_PRC511);
1424 E1000_READ_REG(hw, E1000_PRC1023);
1425 E1000_READ_REG(hw, E1000_PRC1522);
1426 E1000_READ_REG(hw, E1000_PTC64);
1427 E1000_READ_REG(hw, E1000_PTC127);
1428 E1000_READ_REG(hw, E1000_PTC255);
1429 E1000_READ_REG(hw, E1000_PTC511);
1430 E1000_READ_REG(hw, E1000_PTC1023);
1431 E1000_READ_REG(hw, E1000_PTC1522);
1433 E1000_READ_REG(hw, E1000_ALGNERRC);
1434 E1000_READ_REG(hw, E1000_RXERRC);
1435 E1000_READ_REG(hw, E1000_TNCRS);
1436 E1000_READ_REG(hw, E1000_CEXTERR);
1437 E1000_READ_REG(hw, E1000_TSCTC);
1438 E1000_READ_REG(hw, E1000_TSCTFC);
1440 E1000_READ_REG(hw, E1000_MGTPRC);
1441 E1000_READ_REG(hw, E1000_MGTPDC);
1442 E1000_READ_REG(hw, E1000_MGTPTC);
1444 E1000_READ_REG(hw, E1000_IAC);
1445 E1000_READ_REG(hw, E1000_ICRXOC);
1447 E1000_READ_REG(hw, E1000_ICRXPTC);
1448 E1000_READ_REG(hw, E1000_ICRXATC);
1449 E1000_READ_REG(hw, E1000_ICTXPTC);
1450 E1000_READ_REG(hw, E1000_ICTXATC);
1451 E1000_READ_REG(hw, E1000_ICTXQEC);
1452 E1000_READ_REG(hw, E1000_ICTXQMTC);
1453 E1000_READ_REG(hw, E1000_ICRXDMTC);