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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82540EM Gigabit Ethernet Controller
37 * 82540EP Gigabit Ethernet Controller
38 * 82545EM Gigabit Ethernet Controller (Copper)
39 * 82545EM Gigabit Ethernet Controller (Fiber)
40 * 82545GM Gigabit Ethernet Controller
41 * 82546EB Gigabit Ethernet Controller (Copper)
42 * 82546EB Gigabit Ethernet Controller (Fiber)
43 * 82546GB Gigabit Ethernet Controller
46 #include "e1000_api.h"
48 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
49 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
50 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
51 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
53 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
54 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
55 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
56 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
57 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
58 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
60 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
63 * e1000_init_phy_params_82540 - Init PHY func ptrs.
64 * @hw: pointer to the HW structure
66 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
68 struct e1000_phy_info *phy = &hw->phy;
69 s32 ret_val = E1000_SUCCESS;
72 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
73 phy->reset_delay_us = 10000;
74 phy->type = e1000_phy_m88;
76 /* Function Pointers */
77 phy->ops.check_polarity = e1000_check_polarity_m88;
78 phy->ops.commit = e1000_phy_sw_reset_generic;
79 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
80 phy->ops.get_cable_length = e1000_get_cable_length_m88;
81 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
82 phy->ops.read_reg = e1000_read_phy_reg_m88;
83 phy->ops.reset = e1000_phy_hw_reset_generic;
84 phy->ops.write_reg = e1000_write_phy_reg_m88;
85 phy->ops.get_info = e1000_get_phy_info_m88;
86 phy->ops.power_up = e1000_power_up_phy_copper;
87 phy->ops.power_down = e1000_power_down_phy_copper_82540;
89 ret_val = e1000_get_phy_id(hw);
94 switch (hw->mac.type) {
97 case e1000_82545_rev_3:
99 case e1000_82546_rev_3:
100 if (phy->id == M88E1011_I_PHY_ID)
104 ret_val = -E1000_ERR_PHY;
114 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
115 * @hw: pointer to the HW structure
117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
119 struct e1000_nvm_info *nvm = &hw->nvm;
120 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
122 DEBUGFUNC("e1000_init_nvm_params_82540");
124 nvm->type = e1000_nvm_eeprom_microwire;
125 nvm->delay_usec = 50;
126 nvm->opcode_bits = 3;
127 switch (nvm->override) {
128 case e1000_nvm_override_microwire_large:
129 nvm->address_bits = 8;
130 nvm->word_size = 256;
132 case e1000_nvm_override_microwire_small:
133 nvm->address_bits = 6;
137 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
138 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
142 /* Function Pointers */
143 nvm->ops.acquire = e1000_acquire_nvm_generic;
144 nvm->ops.read = e1000_read_nvm_microwire;
145 nvm->ops.release = e1000_release_nvm_generic;
146 nvm->ops.update = e1000_update_nvm_checksum_generic;
147 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
148 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
149 nvm->ops.write = e1000_write_nvm_microwire;
151 return E1000_SUCCESS;
155 * e1000_init_mac_params_82540 - Init MAC func ptrs.
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
160 struct e1000_mac_info *mac = &hw->mac;
161 s32 ret_val = E1000_SUCCESS;
163 DEBUGFUNC("e1000_init_mac_params_82540");
166 switch (hw->device_id) {
167 case E1000_DEV_ID_82545EM_FIBER:
168 case E1000_DEV_ID_82545GM_FIBER:
169 case E1000_DEV_ID_82546EB_FIBER:
170 case E1000_DEV_ID_82546GB_FIBER:
171 hw->phy.media_type = e1000_media_type_fiber;
173 case E1000_DEV_ID_82545GM_SERDES:
174 case E1000_DEV_ID_82546GB_SERDES:
175 hw->phy.media_type = e1000_media_type_internal_serdes;
178 hw->phy.media_type = e1000_media_type_copper;
182 /* Set mta register count */
183 mac->mta_reg_count = 128;
184 /* Set rar entry count */
185 mac->rar_entry_count = E1000_RAR_ENTRIES;
187 /* Function pointers */
189 /* bus type/speed/width */
190 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
192 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
194 mac->ops.reset_hw = e1000_reset_hw_82540;
195 /* hw initialization */
196 mac->ops.init_hw = e1000_init_hw_82540;
198 mac->ops.setup_link = e1000_setup_link_generic;
199 /* physical interface setup */
200 mac->ops.setup_physical_interface =
201 (hw->phy.media_type == e1000_media_type_copper)
202 ? e1000_setup_copper_link_82540
203 : e1000_setup_fiber_serdes_link_82540;
205 switch (hw->phy.media_type) {
206 case e1000_media_type_copper:
207 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
209 case e1000_media_type_fiber:
210 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
212 case e1000_media_type_internal_serdes:
213 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
216 ret_val = -E1000_ERR_CONFIG;
221 mac->ops.get_link_up_info =
222 (hw->phy.media_type == e1000_media_type_copper)
223 ? e1000_get_speed_and_duplex_copper_generic
224 : e1000_get_speed_and_duplex_fiber_serdes_generic;
225 /* multicast address update */
226 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
228 mac->ops.write_vfta = e1000_write_vfta_generic;
230 mac->ops.clear_vfta = e1000_clear_vfta_generic;
231 /* read mac address */
232 mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
234 mac->ops.id_led_init = e1000_id_led_init_generic;
236 mac->ops.setup_led = e1000_setup_led_generic;
238 mac->ops.cleanup_led = e1000_cleanup_led_generic;
239 /* turn on/off LED */
240 mac->ops.led_on = e1000_led_on_generic;
241 mac->ops.led_off = e1000_led_off_generic;
242 /* clear hardware counters */
243 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
250 * e1000_init_function_pointers_82540 - Init func ptrs.
251 * @hw: pointer to the HW structure
253 * Called to initialize all function pointers and parameters.
255 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
257 DEBUGFUNC("e1000_init_function_pointers_82540");
259 hw->mac.ops.init_params = e1000_init_mac_params_82540;
260 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
261 hw->phy.ops.init_params = e1000_init_phy_params_82540;
265 * e1000_reset_hw_82540 - Reset hardware
266 * @hw: pointer to the HW structure
268 * This resets the hardware into a known state.
270 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
273 s32 ret_val = E1000_SUCCESS;
275 DEBUGFUNC("e1000_reset_hw_82540");
277 DEBUGOUT("Masking off all interrupts\n");
278 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
280 E1000_WRITE_REG(hw, E1000_RCTL, 0);
281 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
282 E1000_WRITE_FLUSH(hw);
285 * Delay to allow any outstanding PCI transactions to complete
286 * before resetting the device.
290 ctrl = E1000_READ_REG(hw, E1000_CTRL);
292 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
293 switch (hw->mac.type) {
294 case e1000_82545_rev_3:
295 case e1000_82546_rev_3:
296 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
300 * These controllers can't ack the 64-bit write when
301 * issuing the reset, so we use IO-mapping as a
302 * workaround to issue the reset.
304 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
308 /* Wait for EEPROM reload */
311 /* Disable HW ARPs on ASF enabled adapters */
312 manc = E1000_READ_REG(hw, E1000_MANC);
313 manc &= ~E1000_MANC_ARP_EN;
314 E1000_WRITE_REG(hw, E1000_MANC, manc);
316 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
317 E1000_READ_REG(hw, E1000_ICR);
323 * e1000_init_hw_82540 - Initialize hardware
324 * @hw: pointer to the HW structure
326 * This inits the hardware readying it for operation.
328 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
330 struct e1000_mac_info *mac = &hw->mac;
331 u32 txdctl, ctrl_ext;
332 s32 ret_val = E1000_SUCCESS;
335 DEBUGFUNC("e1000_init_hw_82540");
337 /* Initialize identification LED */
338 ret_val = mac->ops.id_led_init(hw);
340 DEBUGOUT("Error initializing identification LED\n");
341 /* This is not fatal and we should not stop init due to this */
344 /* Disabling VLAN filtering */
345 DEBUGOUT("Initializing the IEEE VLAN\n");
346 if (mac->type < e1000_82545_rev_3)
347 E1000_WRITE_REG(hw, E1000_VET, 0);
349 mac->ops.clear_vfta(hw);
351 /* Setup the receive address. */
352 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
354 /* Zero out the Multicast HASH table */
355 DEBUGOUT("Zeroing the MTA\n");
356 for (i = 0; i < mac->mta_reg_count; i++) {
357 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
359 * Avoid back to back register writes by adding the register
360 * read (flush). This is to protect against some strange
361 * bridge configurations that may issue Memory Write Block
362 * (MWB) to our register space. The *_rev_3 hardware at
363 * least doesn't respond correctly to every other dword in an
364 * MWB to our register space.
366 E1000_WRITE_FLUSH(hw);
369 if (mac->type < e1000_82545_rev_3)
370 e1000_pcix_mmrbc_workaround_generic(hw);
372 /* Setup link and flow control */
373 ret_val = mac->ops.setup_link(hw);
375 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
376 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
377 E1000_TXDCTL_FULL_TX_DESC_WB;
378 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
381 * Clear all of the statistics registers (clear on read). It is
382 * important that we do this after we have tried to establish link
383 * because the symbol error count will increment wildly if there
386 e1000_clear_hw_cntrs_82540(hw);
388 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
389 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
390 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
392 * Relaxed ordering must be disabled to avoid a parity
393 * error crash in a PCI slot.
395 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
396 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
403 * e1000_setup_copper_link_82540 - Configure copper link settings
404 * @hw: pointer to the HW structure
406 * Calls the appropriate function to configure the link for auto-neg or forced
407 * speed and duplex. Then we check for link, once link is established calls
408 * to configure collision distance and flow control are called. If link is
409 * not established, we return -E1000_ERR_PHY (-2).
411 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
414 s32 ret_val = E1000_SUCCESS;
417 DEBUGFUNC("e1000_setup_copper_link_82540");
419 ctrl = E1000_READ_REG(hw, E1000_CTRL);
420 ctrl |= E1000_CTRL_SLU;
421 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
422 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
424 ret_val = e1000_set_phy_mode_82540(hw);
428 if (hw->mac.type == e1000_82545_rev_3 ||
429 hw->mac.type == e1000_82546_rev_3) {
430 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
435 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
441 ret_val = e1000_copper_link_setup_m88(hw);
445 ret_val = e1000_setup_copper_link_generic(hw);
452 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
453 * @hw: pointer to the HW structure
455 * Set the output amplitude to the value in the EEPROM and adjust the VCO
456 * speed to improve Bit Error Rate (BER) performance. Configures collision
457 * distance and flow control for fiber and serdes links. Upon successful
458 * setup, poll for link.
460 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
462 struct e1000_mac_info *mac = &hw->mac;
463 s32 ret_val = E1000_SUCCESS;
465 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
468 case e1000_82545_rev_3:
469 case e1000_82546_rev_3:
470 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
472 * If we're on serdes media, adjust the output
473 * amplitude to value set in the EEPROM.
475 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
479 /* Adjust VCO speed to improve BER performance */
480 ret_val = e1000_set_vco_speed_82540(hw);
487 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
494 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
495 * @hw: pointer to the HW structure
497 * Adjust the SERDES output amplitude based on the EEPROM settings.
499 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
501 s32 ret_val = E1000_SUCCESS;
504 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
506 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
510 if (nvm_data != NVM_RESERVED_WORD) {
511 /* Adjust serdes output amplitude only. */
512 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
513 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
524 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
525 * @hw: pointer to the HW structure
527 * Set the VCO speed to improve Bit Error Rate (BER) performance.
529 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
531 s32 ret_val = E1000_SUCCESS;
532 u16 default_page = 0;
535 DEBUGFUNC("e1000_set_vco_speed_82540");
537 /* Set PHY register 30, page 5, bit 8 to 0 */
539 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
544 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
548 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
552 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
557 /* Set PHY register 30, page 4, bit 11 to 1 */
559 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
563 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
567 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
572 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
580 * e1000_set_phy_mode_82540 - Set PHY to class A mode
581 * @hw: pointer to the HW structure
583 * Sets the PHY to class A mode and assumes the following operations will
584 * follow to enable the new class mode:
585 * 1. Do a PHY soft reset.
586 * 2. Restart auto-negotiation or force link.
588 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
590 s32 ret_val = E1000_SUCCESS;
593 DEBUGFUNC("e1000_set_phy_mode_82540");
595 if (hw->mac.type != e1000_82545_rev_3)
598 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
600 ret_val = -E1000_ERR_PHY;
604 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
605 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
608 ret_val = -E1000_ERR_PHY;
611 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
614 ret_val = -E1000_ERR_PHY;
625 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
626 * @hw: pointer to the HW structure
628 * In the case of a PHY power down to save power, or to turn off link during a
629 * driver unload, or wake on lan is not enabled, remove the link.
631 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
633 /* If the management interface is not enabled, then power down */
634 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
635 e1000_power_down_phy_copper(hw);
641 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
642 * @hw: pointer to the HW structure
644 * Clears the hardware counters by reading the counter registers.
646 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
648 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
650 e1000_clear_hw_cntrs_base_generic(hw);
652 E1000_READ_REG(hw, E1000_PRC64);
653 E1000_READ_REG(hw, E1000_PRC127);
654 E1000_READ_REG(hw, E1000_PRC255);
655 E1000_READ_REG(hw, E1000_PRC511);
656 E1000_READ_REG(hw, E1000_PRC1023);
657 E1000_READ_REG(hw, E1000_PRC1522);
658 E1000_READ_REG(hw, E1000_PTC64);
659 E1000_READ_REG(hw, E1000_PTC127);
660 E1000_READ_REG(hw, E1000_PTC255);
661 E1000_READ_REG(hw, E1000_PTC511);
662 E1000_READ_REG(hw, E1000_PTC1023);
663 E1000_READ_REG(hw, E1000_PTC1522);
665 E1000_READ_REG(hw, E1000_ALGNERRC);
666 E1000_READ_REG(hw, E1000_RXERRC);
667 E1000_READ_REG(hw, E1000_TNCRS);
668 E1000_READ_REG(hw, E1000_CEXTERR);
669 E1000_READ_REG(hw, E1000_TSCTC);
670 E1000_READ_REG(hw, E1000_TSCTFC);
672 E1000_READ_REG(hw, E1000_MGTPRC);
673 E1000_READ_REG(hw, E1000_MGTPDC);
674 E1000_READ_REG(hw, E1000_MGTPTC);
678 * e1000_read_mac_addr_82540 - Read device MAC address
679 * @hw: pointer to the HW structure
681 * Reads the device MAC address from the EEPROM and stores the value.
682 * Since devices with two ports use the same EEPROM, we increment the
683 * last bit in the MAC address for the second port.
685 * This version is being used over generic because of customer issues
686 * with VmWare and Virtual Box when using generic. It seems in
687 * the emulated 82545, RAR[0] does NOT have a valid address after a
688 * reset, this older method works and using this breaks nothing for
689 * these legacy adapters.
691 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
693 s32 ret_val = E1000_SUCCESS;
694 u16 offset, nvm_data, i;
696 DEBUGFUNC("e1000_read_mac_addr");
698 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
700 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
702 DEBUGOUT("NVM Read Error\n");
705 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
706 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
709 /* Flip last bit of mac address if we're on second port */
710 if (hw->bus.func == E1000_FUNC_1)
711 hw->mac.perm_addr[5] ^= 1;
713 for (i = 0; i < ETH_ADDR_LEN; i++)
714 hw->mac.addr[i] = hw->mac.perm_addr[i];