1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
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8 modification, are permitted provided that the following conditions are met:
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33 ******************************************************************************/
37 * 82540EM Gigabit Ethernet Controller
38 * 82540EP Gigabit Ethernet Controller
39 * 82545EM Gigabit Ethernet Controller (Copper)
40 * 82545EM Gigabit Ethernet Controller (Fiber)
41 * 82545GM Gigabit Ethernet Controller
42 * 82546EB Gigabit Ethernet Controller (Copper)
43 * 82546EB Gigabit Ethernet Controller (Fiber)
44 * 82546GB Gigabit Ethernet Controller
47 #include "e1000_api.h"
49 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
50 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
51 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
52 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
53 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
54 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
56 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
57 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
60 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
61 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
64 * e1000_init_phy_params_82540 - Init PHY func ptrs.
65 * @hw: pointer to the HW structure
67 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
69 struct e1000_phy_info *phy = &hw->phy;
73 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
74 phy->reset_delay_us = 10000;
75 phy->type = e1000_phy_m88;
77 /* Function Pointers */
78 phy->ops.check_polarity = e1000_check_polarity_m88;
79 phy->ops.commit = e1000_phy_sw_reset_generic;
80 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
81 phy->ops.get_cable_length = e1000_get_cable_length_m88;
82 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
83 phy->ops.read_reg = e1000_read_phy_reg_m88;
84 phy->ops.reset = e1000_phy_hw_reset_generic;
85 phy->ops.write_reg = e1000_write_phy_reg_m88;
86 phy->ops.get_info = e1000_get_phy_info_m88;
87 phy->ops.power_up = e1000_power_up_phy_copper;
88 phy->ops.power_down = e1000_power_down_phy_copper_82540;
90 ret_val = e1000_get_phy_id(hw);
95 switch (hw->mac.type) {
98 case e1000_82545_rev_3:
100 case e1000_82546_rev_3:
101 if (phy->id == M88E1011_I_PHY_ID)
105 ret_val = -E1000_ERR_PHY;
115 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
116 * @hw: pointer to the HW structure
118 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
120 struct e1000_nvm_info *nvm = &hw->nvm;
121 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
123 DEBUGFUNC("e1000_init_nvm_params_82540");
125 nvm->type = e1000_nvm_eeprom_microwire;
126 nvm->delay_usec = 50;
127 nvm->opcode_bits = 3;
128 switch (nvm->override) {
129 case e1000_nvm_override_microwire_large:
130 nvm->address_bits = 8;
131 nvm->word_size = 256;
133 case e1000_nvm_override_microwire_small:
134 nvm->address_bits = 6;
138 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
139 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
143 /* Function Pointers */
144 nvm->ops.acquire = e1000_acquire_nvm_generic;
145 nvm->ops.read = e1000_read_nvm_microwire;
146 nvm->ops.release = e1000_release_nvm_generic;
147 nvm->ops.update = e1000_update_nvm_checksum_generic;
148 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
149 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
150 nvm->ops.write = e1000_write_nvm_microwire;
152 return E1000_SUCCESS;
156 * e1000_init_mac_params_82540 - Init MAC func ptrs.
157 * @hw: pointer to the HW structure
159 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
161 struct e1000_mac_info *mac = &hw->mac;
162 s32 ret_val = E1000_SUCCESS;
164 DEBUGFUNC("e1000_init_mac_params_82540");
167 switch (hw->device_id) {
168 case E1000_DEV_ID_82545EM_FIBER:
169 case E1000_DEV_ID_82545GM_FIBER:
170 case E1000_DEV_ID_82546EB_FIBER:
171 case E1000_DEV_ID_82546GB_FIBER:
172 hw->phy.media_type = e1000_media_type_fiber;
174 case E1000_DEV_ID_82545GM_SERDES:
175 case E1000_DEV_ID_82546GB_SERDES:
176 hw->phy.media_type = e1000_media_type_internal_serdes;
179 hw->phy.media_type = e1000_media_type_copper;
183 /* Set mta register count */
184 mac->mta_reg_count = 128;
185 /* Set rar entry count */
186 mac->rar_entry_count = E1000_RAR_ENTRIES;
188 /* Function pointers */
190 /* bus type/speed/width */
191 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
193 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
195 mac->ops.reset_hw = e1000_reset_hw_82540;
196 /* hw initialization */
197 mac->ops.init_hw = e1000_init_hw_82540;
199 mac->ops.setup_link = e1000_setup_link_generic;
200 /* physical interface setup */
201 mac->ops.setup_physical_interface =
202 (hw->phy.media_type == e1000_media_type_copper)
203 ? e1000_setup_copper_link_82540
204 : e1000_setup_fiber_serdes_link_82540;
206 switch (hw->phy.media_type) {
207 case e1000_media_type_copper:
208 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
210 case e1000_media_type_fiber:
211 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
213 case e1000_media_type_internal_serdes:
214 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
217 ret_val = -E1000_ERR_CONFIG;
222 mac->ops.get_link_up_info =
223 (hw->phy.media_type == e1000_media_type_copper)
224 ? e1000_get_speed_and_duplex_copper_generic
225 : e1000_get_speed_and_duplex_fiber_serdes_generic;
226 /* multicast address update */
227 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
229 mac->ops.write_vfta = e1000_write_vfta_generic;
231 mac->ops.clear_vfta = e1000_clear_vfta_generic;
232 /* read mac address */
233 mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
235 mac->ops.id_led_init = e1000_id_led_init_generic;
237 mac->ops.setup_led = e1000_setup_led_generic;
239 mac->ops.cleanup_led = e1000_cleanup_led_generic;
240 /* turn on/off LED */
241 mac->ops.led_on = e1000_led_on_generic;
242 mac->ops.led_off = e1000_led_off_generic;
243 /* clear hardware counters */
244 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
251 * e1000_init_function_pointers_82540 - Init func ptrs.
252 * @hw: pointer to the HW structure
254 * Called to initialize all function pointers and parameters.
256 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
258 DEBUGFUNC("e1000_init_function_pointers_82540");
260 hw->mac.ops.init_params = e1000_init_mac_params_82540;
261 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
262 hw->phy.ops.init_params = e1000_init_phy_params_82540;
266 * e1000_reset_hw_82540 - Reset hardware
267 * @hw: pointer to the HW structure
269 * This resets the hardware into a known state.
271 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
274 s32 ret_val = E1000_SUCCESS;
276 DEBUGFUNC("e1000_reset_hw_82540");
278 DEBUGOUT("Masking off all interrupts\n");
279 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
281 E1000_WRITE_REG(hw, E1000_RCTL, 0);
282 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
283 E1000_WRITE_FLUSH(hw);
286 * Delay to allow any outstanding PCI transactions to complete
287 * before resetting the device.
291 ctrl = E1000_READ_REG(hw, E1000_CTRL);
293 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
294 switch (hw->mac.type) {
295 case e1000_82545_rev_3:
296 case e1000_82546_rev_3:
297 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
301 * These controllers can't ack the 64-bit write when
302 * issuing the reset, so we use IO-mapping as a
303 * workaround to issue the reset.
305 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
309 /* Wait for EEPROM reload */
312 /* Disable HW ARPs on ASF enabled adapters */
313 manc = E1000_READ_REG(hw, E1000_MANC);
314 manc &= ~E1000_MANC_ARP_EN;
315 E1000_WRITE_REG(hw, E1000_MANC, manc);
317 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
318 E1000_READ_REG(hw, E1000_ICR);
324 * e1000_init_hw_82540 - Initialize hardware
325 * @hw: pointer to the HW structure
327 * This inits the hardware readying it for operation.
329 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
331 struct e1000_mac_info *mac = &hw->mac;
332 u32 txdctl, ctrl_ext;
336 DEBUGFUNC("e1000_init_hw_82540");
338 /* Initialize identification LED */
339 ret_val = mac->ops.id_led_init(hw);
341 DEBUGOUT("Error initializing identification LED\n");
342 /* This is not fatal and we should not stop init due to this */
345 /* Disabling VLAN filtering */
346 DEBUGOUT("Initializing the IEEE VLAN\n");
347 if (mac->type < e1000_82545_rev_3)
348 E1000_WRITE_REG(hw, E1000_VET, 0);
350 mac->ops.clear_vfta(hw);
352 /* Setup the receive address. */
353 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
355 /* Zero out the Multicast HASH table */
356 DEBUGOUT("Zeroing the MTA\n");
357 for (i = 0; i < mac->mta_reg_count; i++) {
358 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
360 * Avoid back to back register writes by adding the register
361 * read (flush). This is to protect against some strange
362 * bridge configurations that may issue Memory Write Block
363 * (MWB) to our register space. The *_rev_3 hardware at
364 * least doesn't respond correctly to every other dword in an
365 * MWB to our register space.
367 E1000_WRITE_FLUSH(hw);
370 if (mac->type < e1000_82545_rev_3)
371 e1000_pcix_mmrbc_workaround_generic(hw);
373 /* Setup link and flow control */
374 ret_val = mac->ops.setup_link(hw);
376 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
377 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
378 E1000_TXDCTL_FULL_TX_DESC_WB;
379 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
382 * Clear all of the statistics registers (clear on read). It is
383 * important that we do this after we have tried to establish link
384 * because the symbol error count will increment wildly if there
387 e1000_clear_hw_cntrs_82540(hw);
389 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
390 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
391 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
393 * Relaxed ordering must be disabled to avoid a parity
394 * error crash in a PCI slot.
396 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
404 * e1000_setup_copper_link_82540 - Configure copper link settings
405 * @hw: pointer to the HW structure
407 * Calls the appropriate function to configure the link for auto-neg or forced
408 * speed and duplex. Then we check for link, once link is established calls
409 * to configure collision distance and flow control are called. If link is
410 * not established, we return -E1000_ERR_PHY (-2).
412 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
418 DEBUGFUNC("e1000_setup_copper_link_82540");
420 ctrl = E1000_READ_REG(hw, E1000_CTRL);
421 ctrl |= E1000_CTRL_SLU;
422 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
423 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
425 ret_val = e1000_set_phy_mode_82540(hw);
429 if (hw->mac.type == e1000_82545_rev_3 ||
430 hw->mac.type == e1000_82546_rev_3) {
431 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
436 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
442 ret_val = e1000_copper_link_setup_m88(hw);
446 ret_val = e1000_setup_copper_link_generic(hw);
453 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
454 * @hw: pointer to the HW structure
456 * Set the output amplitude to the value in the EEPROM and adjust the VCO
457 * speed to improve Bit Error Rate (BER) performance. Configures collision
458 * distance and flow control for fiber and serdes links. Upon successful
459 * setup, poll for link.
461 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
463 struct e1000_mac_info *mac = &hw->mac;
464 s32 ret_val = E1000_SUCCESS;
466 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
469 case e1000_82545_rev_3:
470 case e1000_82546_rev_3:
471 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
473 * If we're on serdes media, adjust the output
474 * amplitude to value set in the EEPROM.
476 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
480 /* Adjust VCO speed to improve BER performance */
481 ret_val = e1000_set_vco_speed_82540(hw);
488 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
495 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
496 * @hw: pointer to the HW structure
498 * Adjust the SERDES output amplitude based on the EEPROM settings.
500 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
505 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
507 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
511 if (nvm_data != NVM_RESERVED_WORD) {
512 /* Adjust serdes output amplitude only. */
513 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
514 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
525 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
526 * @hw: pointer to the HW structure
528 * Set the VCO speed to improve Bit Error Rate (BER) performance.
530 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
533 u16 default_page = 0;
536 DEBUGFUNC("e1000_set_vco_speed_82540");
538 /* Set PHY register 30, page 5, bit 8 to 0 */
540 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
545 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
549 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
553 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
554 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
558 /* Set PHY register 30, page 4, bit 11 to 1 */
560 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
564 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
568 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
569 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
573 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
581 * e1000_set_phy_mode_82540 - Set PHY to class A mode
582 * @hw: pointer to the HW structure
584 * Sets the PHY to class A mode and assumes the following operations will
585 * follow to enable the new class mode:
586 * 1. Do a PHY soft reset.
587 * 2. Restart auto-negotiation or force link.
589 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
591 s32 ret_val = E1000_SUCCESS;
594 DEBUGFUNC("e1000_set_phy_mode_82540");
596 if (hw->mac.type != e1000_82545_rev_3)
599 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
601 ret_val = -E1000_ERR_PHY;
605 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
606 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
609 ret_val = -E1000_ERR_PHY;
612 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
615 ret_val = -E1000_ERR_PHY;
626 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
627 * @hw: pointer to the HW structure
629 * In the case of a PHY power down to save power, or to turn off link during a
630 * driver unload, or wake on lan is not enabled, remove the link.
632 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
634 /* If the management interface is not enabled, then power down */
635 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
636 e1000_power_down_phy_copper(hw);
642 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
643 * @hw: pointer to the HW structure
645 * Clears the hardware counters by reading the counter registers.
647 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
649 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
651 e1000_clear_hw_cntrs_base_generic(hw);
653 E1000_READ_REG(hw, E1000_PRC64);
654 E1000_READ_REG(hw, E1000_PRC127);
655 E1000_READ_REG(hw, E1000_PRC255);
656 E1000_READ_REG(hw, E1000_PRC511);
657 E1000_READ_REG(hw, E1000_PRC1023);
658 E1000_READ_REG(hw, E1000_PRC1522);
659 E1000_READ_REG(hw, E1000_PTC64);
660 E1000_READ_REG(hw, E1000_PTC127);
661 E1000_READ_REG(hw, E1000_PTC255);
662 E1000_READ_REG(hw, E1000_PTC511);
663 E1000_READ_REG(hw, E1000_PTC1023);
664 E1000_READ_REG(hw, E1000_PTC1522);
666 E1000_READ_REG(hw, E1000_ALGNERRC);
667 E1000_READ_REG(hw, E1000_RXERRC);
668 E1000_READ_REG(hw, E1000_TNCRS);
669 E1000_READ_REG(hw, E1000_CEXTERR);
670 E1000_READ_REG(hw, E1000_TSCTC);
671 E1000_READ_REG(hw, E1000_TSCTFC);
673 E1000_READ_REG(hw, E1000_MGTPRC);
674 E1000_READ_REG(hw, E1000_MGTPDC);
675 E1000_READ_REG(hw, E1000_MGTPTC);
679 * e1000_read_mac_addr_82540 - Read device MAC address
680 * @hw: pointer to the HW structure
682 * Reads the device MAC address from the EEPROM and stores the value.
683 * Since devices with two ports use the same EEPROM, we increment the
684 * last bit in the MAC address for the second port.
686 * This version is being used over generic because of customer issues
687 * with VmWare and Virtual Box when using generic. It seems in
688 * the emulated 82545, RAR[0] does NOT have a valid address after a
689 * reset, this older method works and using this breaks nothing for
690 * these legacy adapters.
692 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
694 s32 ret_val = E1000_SUCCESS;
695 u16 offset, nvm_data, i;
697 DEBUGFUNC("e1000_read_mac_addr");
699 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
701 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
703 DEBUGOUT("NVM Read Error\n");
706 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
707 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
710 /* Flip last bit of mac address if we're on second port */
711 if (hw->bus.func == E1000_FUNC_1)
712 hw->mac.perm_addr[5] ^= 1;
714 for (i = 0; i < ETH_ADDR_LEN; i++)
715 hw->mac.addr[i] = hw->mac.perm_addr[i];