1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
36 * 82541EI Gigabit Ethernet Controller
37 * 82541ER Gigabit Ethernet Controller
38 * 82541GI Gigabit Ethernet Controller
39 * 82541PI Gigabit Ethernet Controller
40 * 82547EI Gigabit Ethernet Controller
41 * 82547GI Gigabit Ethernet Controller
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
50 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
59 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
62 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
64 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
67 static const u16 e1000_igp_cable_length_table[] =
68 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
69 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
70 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
71 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
72 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
73 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
74 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
75 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
77 (sizeof(e1000_igp_cable_length_table) / \
78 sizeof(e1000_igp_cable_length_table[0]))
81 * e1000_init_phy_params_82541 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure
84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = E1000_SUCCESS;
89 DEBUGFUNC("e1000_init_phy_params_82541");
92 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
93 phy->reset_delay_us = 10000;
94 phy->type = e1000_phy_igp;
96 /* Function Pointers */
97 phy->ops.check_polarity = e1000_check_polarity_igp;
98 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
99 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
100 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
101 phy->ops.get_info = e1000_get_phy_info_igp;
102 phy->ops.read_reg = e1000_read_phy_reg_igp;
103 phy->ops.reset = e1000_phy_hw_reset_82541;
104 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
105 phy->ops.write_reg = e1000_write_phy_reg_igp;
106 phy->ops.power_up = e1000_power_up_phy_copper;
107 phy->ops.power_down = e1000_power_down_phy_copper_82541;
109 ret_val = e1000_get_phy_id(hw);
114 if (phy->id != IGP01E1000_I_PHY_ID) {
115 ret_val = -E1000_ERR_PHY;
124 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
125 * @hw: pointer to the HW structure
127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
129 struct e1000_nvm_info *nvm = &hw->nvm;
130 s32 ret_val = E1000_SUCCESS;
131 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
134 DEBUGFUNC("e1000_init_nvm_params_82541");
136 switch (nvm->override) {
137 case e1000_nvm_override_spi_large:
138 nvm->type = e1000_nvm_eeprom_spi;
139 eecd |= E1000_EECD_ADDR_BITS;
141 case e1000_nvm_override_spi_small:
142 nvm->type = e1000_nvm_eeprom_spi;
143 eecd &= ~E1000_EECD_ADDR_BITS;
145 case e1000_nvm_override_microwire_large:
146 nvm->type = e1000_nvm_eeprom_microwire;
147 eecd |= E1000_EECD_SIZE;
149 case e1000_nvm_override_microwire_small:
150 nvm->type = e1000_nvm_eeprom_microwire;
151 eecd &= ~E1000_EECD_SIZE;
154 nvm->type = eecd & E1000_EECD_TYPE
155 ? e1000_nvm_eeprom_spi
156 : e1000_nvm_eeprom_microwire;
160 if (nvm->type == e1000_nvm_eeprom_spi) {
161 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
164 nvm->opcode_bits = 8;
165 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
168 /* Function Pointers */
169 nvm->ops.acquire = e1000_acquire_nvm_generic;
170 nvm->ops.read = e1000_read_nvm_spi;
171 nvm->ops.release = e1000_release_nvm_generic;
172 nvm->ops.update = e1000_update_nvm_checksum_generic;
173 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
174 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
175 nvm->ops.write = e1000_write_nvm_spi;
178 * nvm->word_size must be discovered after the pointers
179 * are set so we can verify the size from the nvm image
180 * itself. Temporarily set it to a dummy value so the
184 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
187 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
189 * if size != 0, it can be added to a constant and become
190 * the left-shift value to set the word_size. Otherwise,
191 * word_size stays at 64.
194 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
195 nvm->word_size = 1 << size;
198 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
200 nvm->delay_usec = 50;
201 nvm->opcode_bits = 3;
202 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
205 /* Function Pointers */
206 nvm->ops.acquire = e1000_acquire_nvm_generic;
207 nvm->ops.read = e1000_read_nvm_microwire;
208 nvm->ops.release = e1000_release_nvm_generic;
209 nvm->ops.update = e1000_update_nvm_checksum_generic;
210 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
211 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
212 nvm->ops.write = e1000_write_nvm_microwire;
220 * e1000_init_mac_params_82541 - Init MAC func ptrs.
221 * @hw: pointer to the HW structure
223 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
225 struct e1000_mac_info *mac = &hw->mac;
227 DEBUGFUNC("e1000_init_mac_params_82541");
230 hw->phy.media_type = e1000_media_type_copper;
231 /* Set mta register count */
232 mac->mta_reg_count = 128;
233 /* Set rar entry count */
234 mac->rar_entry_count = E1000_RAR_ENTRIES;
235 /* Set if part includes ASF firmware */
236 mac->asf_firmware_present = TRUE;
238 /* Function Pointers */
240 /* bus type/speed/width */
241 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
243 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
245 mac->ops.reset_hw = e1000_reset_hw_82541;
246 /* hw initialization */
247 mac->ops.init_hw = e1000_init_hw_82541;
249 mac->ops.setup_link = e1000_setup_link_generic;
250 /* physical interface link setup */
251 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
253 mac->ops.check_for_link = e1000_check_for_link_82541;
255 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
256 /* multicast address update */
257 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
259 mac->ops.write_vfta = e1000_write_vfta_generic;
261 mac->ops.clear_vfta = e1000_clear_vfta_generic;
263 mac->ops.mta_set = e1000_mta_set_generic;
265 mac->ops.id_led_init = e1000_id_led_init_generic;
267 mac->ops.setup_led = e1000_setup_led_82541;
269 mac->ops.cleanup_led = e1000_cleanup_led_82541;
270 /* turn on/off LED */
271 mac->ops.led_on = e1000_led_on_generic;
272 mac->ops.led_off = e1000_led_off_generic;
273 /* clear hardware counters */
274 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
276 return E1000_SUCCESS;
280 * e1000_init_function_pointers_82541 - Init func ptrs.
281 * @hw: pointer to the HW structure
283 * Called to initialize all function pointers and parameters.
285 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
287 DEBUGFUNC("e1000_init_function_pointers_82541");
289 hw->mac.ops.init_params = e1000_init_mac_params_82541;
290 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
291 hw->phy.ops.init_params = e1000_init_phy_params_82541;
295 * e1000_reset_hw_82541 - Reset hardware
296 * @hw: pointer to the HW structure
298 * This resets the hardware into a known state.
300 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
302 u32 ledctl, ctrl, icr, manc;
304 DEBUGFUNC("e1000_reset_hw_82541");
306 DEBUGOUT("Masking off all interrupts\n");
307 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
309 E1000_WRITE_REG(hw, E1000_RCTL, 0);
310 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
311 E1000_WRITE_FLUSH(hw);
314 * Delay to allow any outstanding PCI transactions to complete
315 * before resetting the device.
319 ctrl = E1000_READ_REG(hw, E1000_CTRL);
321 /* Must reset the Phy before resetting the MAC */
322 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
323 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
327 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
328 switch (hw->mac.type) {
330 case e1000_82541_rev_2:
332 * These controllers can't ack the 64-bit write when
333 * issuing the reset, so we use IO-mapping as a
334 * workaround to issue the reset.
336 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
343 /* Wait for NVM reload */
346 /* Disable HW ARPs on ASF enabled adapters */
347 manc = E1000_READ_REG(hw, E1000_MANC);
348 manc &= ~E1000_MANC_ARP_EN;
349 E1000_WRITE_REG(hw, E1000_MANC, manc);
351 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
352 e1000_phy_init_script_82541(hw);
354 /* Configure activity LED after Phy reset */
355 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
356 ledctl &= IGP_ACTIVITY_LED_MASK;
357 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
358 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
361 /* Once again, mask the interrupts */
362 DEBUGOUT("Masking off all interrupts\n");
363 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
365 /* Clear any pending interrupt events. */
366 icr = E1000_READ_REG(hw, E1000_ICR);
368 return E1000_SUCCESS;
372 * e1000_init_hw_82541 - Initialize hardware
373 * @hw: pointer to the HW structure
375 * This inits the hardware readying it for operation.
377 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
379 struct e1000_mac_info *mac = &hw->mac;
380 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
384 DEBUGFUNC("e1000_init_hw_82541");
386 /* Initialize identification LED */
387 ret_val = mac->ops.id_led_init(hw);
389 DEBUGOUT("Error initializing identification LED\n");
390 /* This is not fatal and we should not stop init due to this */
393 /* Storing the Speed Power Down value for later use */
394 ret_val = hw->phy.ops.read_reg(hw,
395 IGP01E1000_GMII_FIFO,
396 &dev_spec->spd_default);
400 /* Disabling VLAN filtering */
401 DEBUGOUT("Initializing the IEEE VLAN\n");
402 mac->ops.clear_vfta(hw);
404 /* Setup the receive address. */
405 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
407 /* Zero out the Multicast HASH table */
408 DEBUGOUT("Zeroing the MTA\n");
409 for (i = 0; i < mac->mta_reg_count; i++) {
410 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
412 * Avoid back to back register writes by adding the register
413 * read (flush). This is to protect against some strange
414 * bridge configurations that may issue Memory Write Block
415 * (MWB) to our register space.
417 E1000_WRITE_FLUSH(hw);
420 /* Setup link and flow control */
421 ret_val = mac->ops.setup_link(hw);
423 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
424 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
425 E1000_TXDCTL_FULL_TX_DESC_WB;
426 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
429 * Clear all of the statistics registers (clear on read). It is
430 * important that we do this after we have tried to establish link
431 * because the symbol error count will increment wildly if there
434 e1000_clear_hw_cntrs_82541(hw);
441 * e1000_get_link_up_info_82541 - Report speed and duplex
442 * @hw: pointer to the HW structure
443 * @speed: pointer to speed buffer
444 * @duplex: pointer to duplex buffer
446 * Retrieve the current speed and duplex configuration.
448 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
451 struct e1000_phy_info *phy = &hw->phy;
455 DEBUGFUNC("e1000_get_link_up_info_82541");
457 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
461 if (!phy->speed_downgraded)
465 * IGP01 PHY may advertise full duplex operation after speed
466 * downgrade even if it is operating at half duplex.
467 * Here we set the duplex settings to match the duplex in the
468 * link partner's capabilities.
470 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
474 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
475 *duplex = HALF_DUPLEX;
477 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
481 if (*speed == SPEED_100) {
482 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
483 *duplex = HALF_DUPLEX;
484 } else if (*speed == SPEED_10) {
485 if (!(data & NWAY_LPAR_10T_FD_CAPS))
486 *duplex = HALF_DUPLEX;
495 * e1000_phy_hw_reset_82541 - PHY hardware reset
496 * @hw: pointer to the HW structure
498 * Verify the reset block is not blocking us from resetting. Acquire
499 * semaphore (if necessary) and read/set/write the device control reset
500 * bit in the PHY. Wait the appropriate delay time for the device to
501 * reset and release the semaphore (if necessary).
503 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
508 DEBUGFUNC("e1000_phy_hw_reset_82541");
510 ret_val = e1000_phy_hw_reset_generic(hw);
514 e1000_phy_init_script_82541(hw);
516 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
517 /* Configure activity LED after PHY reset */
518 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
519 ledctl &= IGP_ACTIVITY_LED_MASK;
520 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
521 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
529 * e1000_setup_copper_link_82541 - Configure copper link settings
530 * @hw: pointer to the HW structure
532 * Calls the appropriate function to configure the link for auto-neg or forced
533 * speed and duplex. Then we check for link, once link is established calls
534 * to configure collision distance and flow control are called. If link is
535 * not established, we return -E1000_ERR_PHY (-2).
537 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
539 struct e1000_phy_info *phy = &hw->phy;
540 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
544 DEBUGFUNC("e1000_setup_copper_link_82541");
546 ctrl = E1000_READ_REG(hw, E1000_CTRL);
547 ctrl |= E1000_CTRL_SLU;
548 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
549 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
551 hw->phy.reset_disable = FALSE;
553 /* Earlier revs of the IGP phy require us to force MDI. */
554 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
555 dev_spec->dsp_config = e1000_dsp_config_disabled;
558 dev_spec->dsp_config = e1000_dsp_config_enabled;
561 ret_val = e1000_copper_link_setup_igp(hw);
565 if (hw->mac.autoneg) {
566 if (dev_spec->ffe_config == e1000_ffe_config_active)
567 dev_spec->ffe_config = e1000_ffe_config_enabled;
570 /* Configure activity LED after Phy reset */
571 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
572 ledctl &= IGP_ACTIVITY_LED_MASK;
573 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
574 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
576 ret_val = e1000_setup_copper_link_generic(hw);
583 * e1000_check_for_link_82541 - Check/Store link connection
584 * @hw: pointer to the HW structure
586 * This checks the link condition of the adapter and stores the
587 * results in the hw->mac structure.
589 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
591 struct e1000_mac_info *mac = &hw->mac;
595 DEBUGFUNC("e1000_check_for_link_82541");
598 * We only want to go out to the PHY registers to see if Auto-Neg
599 * has completed and/or if our link status has changed. The
600 * get_link_status flag is set upon receiving a Link Status
601 * Change or Rx Sequence Error interrupt.
603 if (!mac->get_link_status) {
604 ret_val = E1000_SUCCESS;
609 * First we want to see if the MII Status Register reports
610 * link. If so, then we want to get the current speed/duplex
613 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
618 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
619 goto out; /* No link detected */
622 mac->get_link_status = FALSE;
625 * Check if there was DownShift, must be checked
626 * immediately after link-up
628 e1000_check_downshift_generic(hw);
631 * If we are forcing speed/duplex, then we simply return since
632 * we have already determined whether we have link or not.
635 ret_val = -E1000_ERR_CONFIG;
639 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
642 * Auto-Neg is enabled. Auto Speed Detection takes care
643 * of MAC speed/duplex configuration. So we only need to
644 * configure Collision Distance in the MAC.
646 e1000_config_collision_dist_generic(hw);
649 * Configure Flow Control now that Auto-Neg has completed.
650 * First, we need to restore the desired flow control
651 * settings because we may have had to re-autoneg with a
652 * different link partner.
654 ret_val = e1000_config_fc_after_link_up_generic(hw);
656 DEBUGOUT("Error configuring flow control\n");
664 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
665 * @hw: pointer to the HW structure
666 * @link_up: boolean flag for link up status
668 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
671 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
672 * gigabit link is achieved to improve link quality.
674 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
677 struct e1000_phy_info *phy = &hw->phy;
678 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
681 u16 phy_data, phy_saved_data, speed, duplex, i;
682 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
683 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
684 {IGP01E1000_PHY_AGC_PARAM_A,
685 IGP01E1000_PHY_AGC_PARAM_B,
686 IGP01E1000_PHY_AGC_PARAM_C,
687 IGP01E1000_PHY_AGC_PARAM_D};
689 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
692 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
694 DEBUGOUT("Error getting link speed and duplex\n");
698 if (speed != SPEED_1000) {
699 ret_val = E1000_SUCCESS;
703 ret_val = phy->ops.get_cable_length(hw);
707 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
708 phy->min_cable_length >= 50) {
710 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
711 ret_val = phy->ops.read_reg(hw,
717 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
719 ret_val = phy->ops.write_reg(hw,
725 dev_spec->dsp_config = e1000_dsp_config_activated;
728 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
729 (phy->min_cable_length >= 50)) {
730 ret_val = E1000_SUCCESS;
734 /* clear previous idle error counts */
735 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
739 for (i = 0; i < ffe_idle_err_timeout; i++) {
741 ret_val = phy->ops.read_reg(hw,
747 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
748 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
749 dev_spec->ffe_config = e1000_ffe_config_active;
751 ret_val = phy->ops.write_reg(hw,
752 IGP01E1000_PHY_DSP_FFE,
753 IGP01E1000_PHY_DSP_FFE_CM_CP);
760 ffe_idle_err_timeout =
761 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
764 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
766 * Save off the current value of register 0x2F5B
767 * to be restored at the end of the routines.
769 ret_val = phy->ops.read_reg(hw,
775 /* Disable the PHY transmitter */
776 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
782 ret_val = phy->ops.write_reg(hw,
784 IGP01E1000_IEEE_FORCE_GIG);
787 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
788 ret_val = phy->ops.read_reg(hw,
794 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
795 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
797 ret_val = phy->ops.write_reg(hw,
804 ret_val = phy->ops.write_reg(hw,
806 IGP01E1000_IEEE_RESTART_AUTONEG);
812 /* Now enable the transmitter */
813 ret_val = phy->ops.write_reg(hw,
819 dev_spec->dsp_config = e1000_dsp_config_enabled;
822 if (dev_spec->ffe_config != e1000_ffe_config_active) {
823 ret_val = E1000_SUCCESS;
828 * Save off the current value of register 0x2F5B
829 * to be restored at the end of the routines.
831 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
835 /* Disable the PHY transmitter */
836 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
842 ret_val = phy->ops.write_reg(hw,
844 IGP01E1000_IEEE_FORCE_GIG);
848 ret_val = phy->ops.write_reg(hw,
849 IGP01E1000_PHY_DSP_FFE,
850 IGP01E1000_PHY_DSP_FFE_DEFAULT);
854 ret_val = phy->ops.write_reg(hw,
856 IGP01E1000_IEEE_RESTART_AUTONEG);
862 /* Now enable the transmitter */
863 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
868 dev_spec->ffe_config = e1000_ffe_config_enabled;
876 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
877 * @hw: pointer to the HW structure
879 * The automatic gain control (agc) normalizes the amplitude of the
880 * received signal, adjusting for the attenuation produced by the
881 * cable. By reading the AGC registers, which represent the
882 * combination of coarse and fine gain value, the value can be put
883 * into a lookup table to obtain the approximate cable length
886 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
888 struct e1000_phy_info *phy = &hw->phy;
889 s32 ret_val = E1000_SUCCESS;
891 u16 cur_agc_value, agc_value = 0;
892 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
893 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
894 {IGP01E1000_PHY_AGC_A,
895 IGP01E1000_PHY_AGC_B,
896 IGP01E1000_PHY_AGC_C,
897 IGP01E1000_PHY_AGC_D};
899 DEBUGFUNC("e1000_get_cable_length_igp_82541");
901 /* Read the AGC registers for all channels */
902 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
903 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
907 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
909 /* Bounds checking */
910 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
911 (cur_agc_value == 0)) {
912 ret_val = -E1000_ERR_PHY;
916 agc_value += cur_agc_value;
918 if (min_agc_value > cur_agc_value)
919 min_agc_value = cur_agc_value;
922 /* Remove the minimal AGC result for length < 50m */
923 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
924 agc_value -= min_agc_value;
925 /* Average the three remaining channels for the length. */
926 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
928 /* Average the channels for the length. */
929 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
932 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
933 IGP01E1000_AGC_RANGE)
934 ? (e1000_igp_cable_length_table[agc_value] -
935 IGP01E1000_AGC_RANGE)
937 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
938 IGP01E1000_AGC_RANGE;
940 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
947 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
948 * @hw: pointer to the HW structure
949 * @active: boolean used to enable/disable lplu
951 * Success returns 0, Failure returns 1
953 * The low power link up (lplu) state is set to the power management level D3
954 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
955 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
956 * is used during Dx states where the power conservation is most important.
957 * During driver activity, SmartSpeed should be enabled so performance is
960 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
962 struct e1000_phy_info *phy = &hw->phy;
966 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
968 switch (hw->mac.type) {
969 case e1000_82541_rev_2:
970 case e1000_82547_rev_2:
973 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
978 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
983 data &= ~IGP01E1000_GMII_FLEX_SPD;
984 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
989 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
990 * during Dx states where the power conservation is most
991 * important. During driver activity we should enable
992 * SmartSpeed, so performance is maintained.
994 if (phy->smart_speed == e1000_smart_speed_on) {
995 ret_val = phy->ops.read_reg(hw,
996 IGP01E1000_PHY_PORT_CONFIG,
1001 data |= IGP01E1000_PSCFR_SMART_SPEED;
1002 ret_val = phy->ops.write_reg(hw,
1003 IGP01E1000_PHY_PORT_CONFIG,
1007 } else if (phy->smart_speed == e1000_smart_speed_off) {
1008 ret_val = phy->ops.read_reg(hw,
1009 IGP01E1000_PHY_PORT_CONFIG,
1014 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1015 ret_val = phy->ops.write_reg(hw,
1016 IGP01E1000_PHY_PORT_CONFIG,
1021 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1022 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1023 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1024 data |= IGP01E1000_GMII_FLEX_SPD;
1025 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1029 /* When LPLU is enabled, we should disable SmartSpeed */
1030 ret_val = phy->ops.read_reg(hw,
1031 IGP01E1000_PHY_PORT_CONFIG,
1036 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1037 ret_val = phy->ops.write_reg(hw,
1038 IGP01E1000_PHY_PORT_CONFIG,
1047 * e1000_setup_led_82541 - Configures SW controllable LED
1048 * @hw: pointer to the HW structure
1050 * This prepares the SW controllable LED for use and saves the current state
1051 * of the LED so it can be later restored.
1053 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1055 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1058 DEBUGFUNC("e1000_setup_led_82541");
1060 ret_val = hw->phy.ops.read_reg(hw,
1061 IGP01E1000_GMII_FIFO,
1062 &dev_spec->spd_default);
1066 ret_val = hw->phy.ops.write_reg(hw,
1067 IGP01E1000_GMII_FIFO,
1068 (u16)(dev_spec->spd_default &
1069 ~IGP01E1000_GMII_SPD));
1073 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1080 * e1000_cleanup_led_82541 - Set LED config to default operation
1081 * @hw: pointer to the HW structure
1083 * Remove the current LED configuration and set the LED configuration
1084 * to the default value, saved from the EEPROM.
1086 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1088 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1091 DEBUGFUNC("e1000_cleanup_led_82541");
1093 ret_val = hw->phy.ops.write_reg(hw,
1094 IGP01E1000_GMII_FIFO,
1095 dev_spec->spd_default);
1099 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1106 * e1000_phy_init_script_82541 - Initialize GbE PHY
1107 * @hw: pointer to the HW structure
1109 * Initializes the IGP PHY.
1111 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1113 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1117 DEBUGFUNC("e1000_phy_init_script_82541");
1119 if (!dev_spec->phy_init_script) {
1120 ret_val = E1000_SUCCESS;
1124 /* Delay after phy reset to enable NVM configuration to load */
1128 * Save off the current value of register 0x2F5B to be restored at
1129 * the end of this routine.
1131 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1133 /* Disabled the PHY transmitter */
1134 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1138 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1142 switch (hw->mac.type) {
1145 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1147 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1149 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1151 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1153 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1155 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1157 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1159 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1161 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1163 case e1000_82541_rev_2:
1164 case e1000_82547_rev_2:
1165 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1171 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1175 /* Now enable the transmitter */
1176 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1178 if (hw->mac.type == e1000_82547) {
1179 u16 fused, fine, coarse;
1181 /* Move to analog registers page */
1182 hw->phy.ops.read_reg(hw,
1183 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1186 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1187 hw->phy.ops.read_reg(hw,
1188 IGP01E1000_ANALOG_FUSE_STATUS,
1191 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1192 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1194 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1195 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1196 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1197 } else if (coarse ==
1198 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1199 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1201 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1202 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1203 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1205 hw->phy.ops.write_reg(hw,
1206 IGP01E1000_ANALOG_FUSE_CONTROL,
1208 hw->phy.ops.write_reg(hw,
1209 IGP01E1000_ANALOG_FUSE_BYPASS,
1210 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1219 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1220 * @hw: pointer to the HW structure
1221 * @state: boolean value used to enable/disable PHY init script
1223 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1226 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1228 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1230 DEBUGFUNC("e1000_init_script_state_82541");
1232 if (hw->phy.type != e1000_phy_igp) {
1233 DEBUGOUT("Initialization script not necessary.\n");
1237 dev_spec->phy_init_script = state;
1244 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1245 * @hw: pointer to the HW structure
1247 * In the case of a PHY power down to save power, or to turn off link during a
1248 * driver unload, or wake on lan is not enabled, remove the link.
1250 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1252 /* If the management interface is not enabled, then power down */
1253 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1254 e1000_power_down_phy_copper(hw);
1260 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1261 * @hw: pointer to the HW structure
1263 * Clears the hardware counters by reading the counter registers.
1265 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1267 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1269 e1000_clear_hw_cntrs_base_generic(hw);
1271 E1000_READ_REG(hw, E1000_PRC64);
1272 E1000_READ_REG(hw, E1000_PRC127);
1273 E1000_READ_REG(hw, E1000_PRC255);
1274 E1000_READ_REG(hw, E1000_PRC511);
1275 E1000_READ_REG(hw, E1000_PRC1023);
1276 E1000_READ_REG(hw, E1000_PRC1522);
1277 E1000_READ_REG(hw, E1000_PTC64);
1278 E1000_READ_REG(hw, E1000_PTC127);
1279 E1000_READ_REG(hw, E1000_PTC255);
1280 E1000_READ_REG(hw, E1000_PTC511);
1281 E1000_READ_REG(hw, E1000_PTC1023);
1282 E1000_READ_REG(hw, E1000_PTC1522);
1284 E1000_READ_REG(hw, E1000_ALGNERRC);
1285 E1000_READ_REG(hw, E1000_RXERRC);
1286 E1000_READ_REG(hw, E1000_TNCRS);
1287 E1000_READ_REG(hw, E1000_CEXTERR);
1288 E1000_READ_REG(hw, E1000_TSCTC);
1289 E1000_READ_REG(hw, E1000_TSCTFC);
1291 E1000_READ_REG(hw, E1000_MGTPRC);
1292 E1000_READ_REG(hw, E1000_MGTPDC);
1293 E1000_READ_REG(hw, E1000_MGTPTC);