sys/dev/e1000/e1000_82541.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82541EI Gigabit Ethernet Controller
  37  * 82541ER Gigabit Ethernet Controller
  38  * 82541GI Gigabit Ethernet Controller
  39  * 82541PI Gigabit Ethernet Controller
  40  * 82547EI Gigabit Ethernet Controller
  41  * 82547GI Gigabit Ethernet Controller
  42  */
  43
  44 #include "e1000_api.h"
  45
  46 static s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
  47 static s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
  48 static s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
  49 static s32  e1000_reset_hw_82541(struct e1000_hw *hw);
  50 static s32  e1000_init_hw_82541(struct e1000_hw *hw);
  51 static s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
  52                                          u16 *duplex);
  53 static s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
  54 static s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_82541(struct e1000_hw *hw);
  56 static s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
  57 static s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
  58                                           bool active);
  59 static s32  e1000_setup_led_82541(struct e1000_hw *hw);
  60 static s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
  61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
  62 static s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
  63                                                      bool link_up);
  64 static s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
  65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
  66
  67 static const u16 e1000_igp_cable_length_table[] =
  68     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
  69       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
  70       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
  71       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
  72       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
  73       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
  74       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
  75       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
  76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
  77                 (sizeof(e1000_igp_cable_length_table) / \
  78                  sizeof(e1000_igp_cable_length_table[0]))
  79
  80 /**
  81  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
  82  *  @hw: pointer to the HW structure
  83  **/
  84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
  85 {
  86         struct e1000_phy_info *phy = &hw->phy;
  87         s32 ret_val = E1000_SUCCESS;
  88
  89         DEBUGFUNC("e1000_init_phy_params_82541");
  90
  91         phy->addr                      = 1;
  92         phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  93         phy->reset_delay_us            = 10000;
  94         phy->type                      = e1000_phy_igp;
  95
  96         /* Function Pointers */
  97         phy->ops.check_polarity        = e1000_check_polarity_igp;
  98         phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_igp;
  99         phy->ops.get_cable_length      = e1000_get_cable_length_igp_82541;
 100         phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
 101         phy->ops.get_info              = e1000_get_phy_info_igp;
 102         phy->ops.read_reg              = e1000_read_phy_reg_igp;
 103         phy->ops.reset                 = e1000_phy_hw_reset_82541;
 104         phy->ops.set_d3_lplu_state     = e1000_set_d3_lplu_state_82541;
 105         phy->ops.write_reg             = e1000_write_phy_reg_igp;
 106         phy->ops.power_up              = e1000_power_up_phy_copper;
 107         phy->ops.power_down            = e1000_power_down_phy_copper_82541;
 108
 109         ret_val = e1000_get_phy_id(hw);
 110         if (ret_val)
 111                 goto out;
 112
 113         /* Verify phy id */
 114         if (phy->id != IGP01E1000_I_PHY_ID) {
 115                 ret_val = -E1000_ERR_PHY;
 116                 goto out;
 117         }
 118
 119 out:
 120         return ret_val;
 121 }
 122
 123 /**
 124  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
 125  *  @hw: pointer to the HW structure
 126  **/
 127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
 128 {
 129         struct   e1000_nvm_info *nvm = &hw->nvm;
 130         s32  ret_val = E1000_SUCCESS;
 131         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 132         u16 size;
 133
 134         DEBUGFUNC("e1000_init_nvm_params_82541");
 135
 136         switch (nvm->override) {
 137         case e1000_nvm_override_spi_large:
 138                 nvm->type = e1000_nvm_eeprom_spi;
 139                 eecd |= E1000_EECD_ADDR_BITS;
 140                 break;
 141         case e1000_nvm_override_spi_small:
 142                 nvm->type = e1000_nvm_eeprom_spi;
 143                 eecd &= ~E1000_EECD_ADDR_BITS;
 144                 break;
 145         case e1000_nvm_override_microwire_large:
 146                 nvm->type = e1000_nvm_eeprom_microwire;
 147                 eecd |= E1000_EECD_SIZE;
 148                 break;
 149         case e1000_nvm_override_microwire_small:
 150                 nvm->type = e1000_nvm_eeprom_microwire;
 151                 eecd &= ~E1000_EECD_SIZE;
 152                 break;
 153         default:
 154                 nvm->type = eecd & E1000_EECD_TYPE
 155                             ? e1000_nvm_eeprom_spi
 156                             : e1000_nvm_eeprom_microwire;
 157                 break;
 158         }
 159
 160         if (nvm->type == e1000_nvm_eeprom_spi) {
 161                 nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
 162                                           ? 16 : 8;
 163                 nvm->delay_usec         = 1;
 164                 nvm->opcode_bits        = 8;
 165                 nvm->page_size          = (eecd & E1000_EECD_ADDR_BITS)
 166                                           ? 32 : 8;
 167
 168                 /* Function Pointers */
 169                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 170                 nvm->ops.read           = e1000_read_nvm_spi;
 171                 nvm->ops.release        = e1000_release_nvm_generic;
 172                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 173                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 174                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 175                 nvm->ops.write          = e1000_write_nvm_spi;
 176
 177                 /*
 178                  * nvm->word_size must be discovered after the pointers
 179                  * are set so we can verify the size from the nvm image
 180                  * itself.  Temporarily set it to a dummy value so the
 181                  * read will work.
 182                  */
 183                 nvm->word_size = 64;
 184                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
 185                 if (ret_val)
 186                         goto out;
 187                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
 188                 /*
 189                  * if size != 0, it can be added to a constant and become
 190                  * the left-shift value to set the word_size.  Otherwise,
 191                  * word_size stays at 64.
 192                  */
 193                 if (size) {
 194                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
 195                         nvm->word_size = 1 << size;
 196                 }
 197         } else {
 198                 nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
 199                                           ? 8 : 6;
 200                 nvm->delay_usec         = 50;
 201                 nvm->opcode_bits        = 3;
 202                 nvm->word_size          = (eecd & E1000_EECD_ADDR_BITS)
 203                                           ? 256 : 64;
 204
 205                 /* Function Pointers */
 206                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 207                 nvm->ops.read           = e1000_read_nvm_microwire;
 208                 nvm->ops.release        = e1000_release_nvm_generic;
 209                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 210                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 211                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 212                 nvm->ops.write          = e1000_write_nvm_microwire;
 213         }
 214
 215 out:
 216         return ret_val;
 217 }
 218
 219 /**
 220  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
 221  *  @hw: pointer to the HW structure
 222  **/
 223 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
 224 {
 225         struct e1000_mac_info *mac = &hw->mac;
 226
 227         DEBUGFUNC("e1000_init_mac_params_82541");
 228
 229         /* Set media type */
 230         hw->phy.media_type = e1000_media_type_copper;
 231         /* Set mta register count */
 232         mac->mta_reg_count = 128;
 233         /* Set rar entry count */
 234         mac->rar_entry_count = E1000_RAR_ENTRIES;
 235         /* Set if part includes ASF firmware */
 236         mac->asf_firmware_present = TRUE;
 237
 238         /* Function Pointers */
 239
 240         /* bus type/speed/width */
 241         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 242         /* function id */
 243         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 244         /* reset */
 245         mac->ops.reset_hw = e1000_reset_hw_82541;
 246         /* hw initialization */
 247         mac->ops.init_hw = e1000_init_hw_82541;
 248         /* link setup */
 249         mac->ops.setup_link = e1000_setup_link_generic;
 250         /* physical interface link setup */
 251         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
 252         /* check for link */
 253         mac->ops.check_for_link = e1000_check_for_link_82541;
 254         /* link info */
 255         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
 256         /* multicast address update */
 257         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 258         /* writing VFTA */
 259         mac->ops.write_vfta = e1000_write_vfta_generic;
 260         /* clearing VFTA */
 261         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 262         /* setting MTA */
 263         mac->ops.mta_set = e1000_mta_set_generic;
 264         /* ID LED init */
 265         mac->ops.id_led_init = e1000_id_led_init_generic;
 266         /* setup LED */
 267         mac->ops.setup_led = e1000_setup_led_82541;
 268         /* cleanup LED */
 269         mac->ops.cleanup_led = e1000_cleanup_led_82541;
 270         /* turn on/off LED */
 271         mac->ops.led_on = e1000_led_on_generic;
 272         mac->ops.led_off = e1000_led_off_generic;
 273         /* clear hardware counters */
 274         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
 275
 276         return E1000_SUCCESS;
 277 }
 278
 279 /**
 280  *  e1000_init_function_pointers_82541 - Init func ptrs.
 281  *  @hw: pointer to the HW structure
 282  *
 283  *  Called to initialize all function pointers and parameters.
 284  **/
 285 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
 286 {
 287         DEBUGFUNC("e1000_init_function_pointers_82541");
 288
 289         hw->mac.ops.init_params = e1000_init_mac_params_82541;
 290         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
 291         hw->phy.ops.init_params = e1000_init_phy_params_82541;
 292 }
 293
 294 /**
 295  *  e1000_reset_hw_82541 - Reset hardware
 296  *  @hw: pointer to the HW structure
 297  *
 298  *  This resets the hardware into a known state.
 299  **/
 300 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 301 {
 302         u32 ledctl, ctrl, icr, manc;
 303
 304         DEBUGFUNC("e1000_reset_hw_82541");
 305
 306         DEBUGOUT("Masking off all interrupts\n");
 307         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 308
 309         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 310         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 311         E1000_WRITE_FLUSH(hw);
 312
 313         /*
 314          * Delay to allow any outstanding PCI transactions to complete
 315          * before resetting the device.
 316          */
 317         msec_delay(10);
 318
 319         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 320
 321         /* Must reset the Phy before resetting the MAC */
 322         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 323                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
 324                 msec_delay(5);
 325         }
 326
 327         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
 328         switch (hw->mac.type) {
 329         case e1000_82541:
 330         case e1000_82541_rev_2:
 331                 /*
 332                  * These controllers can't ack the 64-bit write when
 333                  * issuing the reset, so we use IO-mapping as a
 334                  * workaround to issue the reset.
 335                  */
 336                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 337                 break;
 338         default:
 339                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 340                 break;
 341         }
 342
 343         /* Wait for NVM reload */
 344         msec_delay(20);
 345
 346         /* Disable HW ARPs on ASF enabled adapters */
 347         manc = E1000_READ_REG(hw, E1000_MANC);
 348         manc &= ~E1000_MANC_ARP_EN;
 349         E1000_WRITE_REG(hw, E1000_MANC, manc);
 350
 351         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 352                 e1000_phy_init_script_82541(hw);
 353
 354                 /* Configure activity LED after Phy reset */
 355                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 356                 ledctl &= IGP_ACTIVITY_LED_MASK;
 357                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 358                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 359         }
 360
 361         /* Once again, mask the interrupts */
 362         DEBUGOUT("Masking off all interrupts\n");
 363         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 364
 365         /* Clear any pending interrupt events. */
 366         icr = E1000_READ_REG(hw, E1000_ICR);
 367
 368         return E1000_SUCCESS;
 369 }
 370
 371 /**
 372  *  e1000_init_hw_82541 - Initialize hardware
 373  *  @hw: pointer to the HW structure
 374  *
 375  *  This inits the hardware readying it for operation.
 376  **/
 377 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
 378 {
 379         struct e1000_mac_info *mac = &hw->mac;
 380         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 381         u32 i, txdctl;
 382         s32 ret_val;
 383
 384         DEBUGFUNC("e1000_init_hw_82541");
 385
 386         /* Initialize identification LED */
 387         ret_val = mac->ops.id_led_init(hw);
 388         if (ret_val) {
 389                 DEBUGOUT("Error initializing identification LED\n");
 390                 /* This is not fatal and we should not stop init due to this */
 391         }
 392
 393         /* Storing the Speed Power Down  value for later use */
 394         ret_val = hw->phy.ops.read_reg(hw,
 395                                        IGP01E1000_GMII_FIFO,
 396                                        &dev_spec->spd_default);
 397         if (ret_val)
 398                 goto out;
 399
 400         /* Disabling VLAN filtering */
 401         DEBUGOUT("Initializing the IEEE VLAN\n");
 402         mac->ops.clear_vfta(hw);
 403
 404         /* Setup the receive address. */
 405         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 406
 407         /* Zero out the Multicast HASH table */
 408         DEBUGOUT("Zeroing the MTA\n");
 409         for (i = 0; i < mac->mta_reg_count; i++) {
 410                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 411                 /*
 412                  * Avoid back to back register writes by adding the register
 413                  * read (flush).  This is to protect against some strange
 414                  * bridge configurations that may issue Memory Write Block
 415                  * (MWB) to our register space.
 416                  */
 417                 E1000_WRITE_FLUSH(hw);
 418         }
 419
 420         /* Setup link and flow control */
 421         ret_val = mac->ops.setup_link(hw);
 422
 423         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 424         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 425                  E1000_TXDCTL_FULL_TX_DESC_WB;
 426         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 427
 428         /*
 429          * Clear all of the statistics registers (clear on read).  It is
 430          * important that we do this after we have tried to establish link
 431          * because the symbol error count will increment wildly if there
 432          * is no link.
 433          */
 434         e1000_clear_hw_cntrs_82541(hw);
 435
 436 out:
 437         return ret_val;
 438 }
 439
 440 /**
 441  * e1000_get_link_up_info_82541 - Report speed and duplex
 442  * @hw: pointer to the HW structure
 443  * @speed: pointer to speed buffer
 444  * @duplex: pointer to duplex buffer
 445  *
 446  * Retrieve the current speed and duplex configuration.
 447  **/
 448 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
 449                                         u16 *duplex)
 450 {
 451         struct e1000_phy_info *phy = &hw->phy;
 452         s32 ret_val;
 453         u16 data;
 454
 455         DEBUGFUNC("e1000_get_link_up_info_82541");
 456
 457         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
 458         if (ret_val)
 459                 goto out;
 460
 461         if (!phy->speed_downgraded)
 462                 goto out;
 463
 464         /*
 465          * IGP01 PHY may advertise full duplex operation after speed
 466          * downgrade even if it is operating at half duplex.
 467          * Here we set the duplex settings to match the duplex in the
 468          * link partner's capabilities.
 469          */
 470         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
 471         if (ret_val)
 472                 goto out;
 473
 474         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
 475                 *duplex = HALF_DUPLEX;
 476         } else {
 477                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
 478                 if (ret_val)
 479                         goto out;
 480
 481                 if (*speed == SPEED_100) {
 482                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
 483                                 *duplex = HALF_DUPLEX;
 484                 } else if (*speed == SPEED_10) {
 485                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
 486                                 *duplex = HALF_DUPLEX;
 487                 }
 488         }
 489
 490 out:
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  e1000_phy_hw_reset_82541 - PHY hardware reset
 496  *  @hw: pointer to the HW structure
 497  *
 498  *  Verify the reset block is not blocking us from resetting.  Acquire
 499  *  semaphore (if necessary) and read/set/write the device control reset
 500  *  bit in the PHY.  Wait the appropriate delay time for the device to
 501  *  reset and release the semaphore (if necessary).
 502  **/
 503 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
 504 {
 505         s32 ret_val;
 506         u32 ledctl;
 507
 508         DEBUGFUNC("e1000_phy_hw_reset_82541");
 509
 510         ret_val = e1000_phy_hw_reset_generic(hw);
 511         if (ret_val)
 512                 goto out;
 513
 514         e1000_phy_init_script_82541(hw);
 515
 516         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 517                 /* Configure activity LED after PHY reset */
 518                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 519                 ledctl &= IGP_ACTIVITY_LED_MASK;
 520                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 521                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 522         }
 523
 524 out:
 525         return ret_val;
 526 }
 527
 528 /**
 529  *  e1000_setup_copper_link_82541 - Configure copper link settings
 530  *  @hw: pointer to the HW structure
 531  *
 532  *  Calls the appropriate function to configure the link for auto-neg or forced
 533  *  speed and duplex.  Then we check for link, once link is established calls
 534  *  to configure collision distance and flow control are called.  If link is
 535  *  not established, we return -E1000_ERR_PHY (-2).
 536  **/
 537 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 538 {
 539         struct e1000_phy_info *phy = &hw->phy;
 540         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 541         s32  ret_val;
 542         u32 ctrl, ledctl;
 543
 544         DEBUGFUNC("e1000_setup_copper_link_82541");
 545
 546         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 547         ctrl |= E1000_CTRL_SLU;
 548         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 549         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 550
 551         hw->phy.reset_disable = FALSE;
 552
 553         /* Earlier revs of the IGP phy require us to force MDI. */
 554         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 555                 dev_spec->dsp_config = e1000_dsp_config_disabled;
 556                 phy->mdix = 1;
 557         } else {
 558                 dev_spec->dsp_config = e1000_dsp_config_enabled;
 559         }
 560
 561         ret_val = e1000_copper_link_setup_igp(hw);
 562         if (ret_val)
 563                 goto out;
 564
 565         if (hw->mac.autoneg) {
 566                 if (dev_spec->ffe_config == e1000_ffe_config_active)
 567                         dev_spec->ffe_config = e1000_ffe_config_enabled;
 568         }
 569
 570         /* Configure activity LED after Phy reset */
 571         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 572         ledctl &= IGP_ACTIVITY_LED_MASK;
 573         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 574         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 575
 576         ret_val = e1000_setup_copper_link_generic(hw);
 577
 578 out:
 579         return ret_val;
 580 }
 581
 582 /**
 583  *  e1000_check_for_link_82541 - Check/Store link connection
 584  *  @hw: pointer to the HW structure
 585  *
 586  *  This checks the link condition of the adapter and stores the
 587  *  results in the hw->mac structure.
 588  **/
 589 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
 590 {
 591         struct e1000_mac_info *mac = &hw->mac;
 592         s32 ret_val;
 593         bool link;
 594
 595         DEBUGFUNC("e1000_check_for_link_82541");
 596
 597         /*
 598          * We only want to go out to the PHY registers to see if Auto-Neg
 599          * has completed and/or if our link status has changed.  The
 600          * get_link_status flag is set upon receiving a Link Status
 601          * Change or Rx Sequence Error interrupt.
 602          */
 603         if (!mac->get_link_status) {
 604                 ret_val = E1000_SUCCESS;
 605                 goto out;
 606         }
 607
 608         /*
 609          * First we want to see if the MII Status Register reports
 610          * link.  If so, then we want to get the current speed/duplex
 611          * of the PHY.
 612          */
 613         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 614         if (ret_val)
 615                 goto out;
 616
 617         if (!link) {
 618                 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
 619                 goto out; /* No link detected */
 620         }
 621
 622         mac->get_link_status = FALSE;
 623
 624         /*
 625          * Check if there was DownShift, must be checked
 626          * immediately after link-up
 627          */
 628         e1000_check_downshift_generic(hw);
 629
 630         /*
 631          * If we are forcing speed/duplex, then we simply return since
 632          * we have already determined whether we have link or not.
 633          */
 634         if (!mac->autoneg) {
 635                 ret_val = -E1000_ERR_CONFIG;
 636                 goto out;
 637         }
 638
 639         ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
 640
 641         /*
 642          * Auto-Neg is enabled.  Auto Speed Detection takes care
 643          * of MAC speed/duplex configuration.  So we only need to
 644          * configure Collision Distance in the MAC.
 645          */
 646         e1000_config_collision_dist_generic(hw);
 647
 648         /*
 649          * Configure Flow Control now that Auto-Neg has completed.
 650          * First, we need to restore the desired flow control
 651          * settings because we may have had to re-autoneg with a
 652          * different link partner.
 653          */
 654         ret_val = e1000_config_fc_after_link_up_generic(hw);
 655         if (ret_val) {
 656                 DEBUGOUT("Error configuring flow control\n");
 657         }
 658
 659 out:
 660         return ret_val;
 661 }
 662
 663 /**
 664  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
 665  *  @hw: pointer to the HW structure
 666  *  @link_up: boolean flag for link up status
 667  *
 668  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
 669  *  at any other case.
 670  *
 671  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 672  *  gigabit link is achieved to improve link quality.
 673  **/
 674 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
 675                                                     bool link_up)
 676 {
 677         struct e1000_phy_info *phy = &hw->phy;
 678         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 679         s32 ret_val;
 680         u32 idle_errs = 0;
 681         u16 phy_data, phy_saved_data, speed, duplex, i;
 682         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
 683         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 684                                                    {IGP01E1000_PHY_AGC_PARAM_A,
 685                                                     IGP01E1000_PHY_AGC_PARAM_B,
 686                                                     IGP01E1000_PHY_AGC_PARAM_C,
 687                                                     IGP01E1000_PHY_AGC_PARAM_D};
 688
 689         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
 690
 691         if (link_up) {
 692                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 693                 if (ret_val) {
 694                         DEBUGOUT("Error getting link speed and duplex\n");
 695                         goto out;
 696                 }
 697
 698                 if (speed != SPEED_1000) {
 699                         ret_val = E1000_SUCCESS;
 700                         goto out;
 701                 }
 702
 703                 ret_val = phy->ops.get_cable_length(hw);
 704                 if (ret_val)
 705                         goto out;
 706
 707                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
 708                     phy->min_cable_length >= 50) {
 709
 710                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 711                                 ret_val = phy->ops.read_reg(hw,
 712                                                             dsp_reg_array[i],
 713                                                             &phy_data);
 714                                 if (ret_val)
 715                                         goto out;
 716
 717                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 718
 719                                 ret_val = phy->ops.write_reg(hw,
 720                                                              dsp_reg_array[i],
 721                                                              phy_data);
 722                                 if (ret_val)
 723                                         goto out;
 724                         }
 725                         dev_spec->dsp_config = e1000_dsp_config_activated;
 726                 }
 727
 728                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
 729                     (phy->min_cable_length >= 50)) {
 730                         ret_val = E1000_SUCCESS;
 731                         goto out;
 732                 }
 733
 734                 /* clear previous idle error counts */
 735                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
 736                 if (ret_val)
 737                         goto out;
 738
 739                 for (i = 0; i < ffe_idle_err_timeout; i++) {
 740                         usec_delay(1000);
 741                         ret_val = phy->ops.read_reg(hw,
 742                                                     PHY_1000T_STATUS,
 743                                                     &phy_data);
 744                         if (ret_val)
 745                                 goto out;
 746
 747                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 748                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
 749                                 dev_spec->ffe_config = e1000_ffe_config_active;
 750
 751                                 ret_val = phy->ops.write_reg(hw,
 752                                                   IGP01E1000_PHY_DSP_FFE,
 753                                                   IGP01E1000_PHY_DSP_FFE_CM_CP);
 754                                 if (ret_val)
 755                                         goto out;
 756                                 break;
 757                         }
 758
 759                         if (idle_errs)
 760                                 ffe_idle_err_timeout =
 761                                                  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 762                 }
 763         } else {
 764                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
 765                         /*
 766                          * Save off the current value of register 0x2F5B
 767                          * to be restored at the end of the routines.
 768                          */
 769                         ret_val = phy->ops.read_reg(hw,
 770                                                     0x2F5B,
 771                                                     &phy_saved_data);
 772                         if (ret_val)
 773                                 goto out;
 774
 775                         /* Disable the PHY transmitter */
 776                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 777                         if (ret_val)
 778                                 goto out;
 779
 780                         msec_delay_irq(20);
 781
 782                         ret_val = phy->ops.write_reg(hw,
 783                                                      0x0000,
 784                                                      IGP01E1000_IEEE_FORCE_GIG);
 785                         if (ret_val)
 786                                 goto out;
 787                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 788                                 ret_val = phy->ops.read_reg(hw,
 789                                                             dsp_reg_array[i],
 790                                                             &phy_data);
 791                                 if (ret_val)
 792                                         goto out;
 793
 794                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 795                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
 796
 797                                 ret_val = phy->ops.write_reg(hw,
 798                                                              dsp_reg_array[i],
 799                                                              phy_data);
 800                                 if (ret_val)
 801                                         goto out;
 802                         }
 803
 804                         ret_val = phy->ops.write_reg(hw,
 805                                                0x0000,
 806                                                IGP01E1000_IEEE_RESTART_AUTONEG);
 807                         if (ret_val)
 808                                 goto out;
 809
 810                         msec_delay_irq(20);
 811
 812                         /* Now enable the transmitter */
 813                         ret_val = phy->ops.write_reg(hw,
 814                                                      0x2F5B,
 815                                                      phy_saved_data);
 816                         if (ret_val)
 817                                 goto out;
 818
 819                         dev_spec->dsp_config = e1000_dsp_config_enabled;
 820                 }
 821
 822                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
 823                         ret_val = E1000_SUCCESS;
 824                         goto out;
 825                 }
 826
 827                 /*
 828                  * Save off the current value of register 0x2F5B
 829                  * to be restored at the end of the routines.
 830                  */
 831                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
 832                 if (ret_val)
 833                         goto out;
 834
 835                 /* Disable the PHY transmitter */
 836                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 837                 if (ret_val)
 838                         goto out;
 839
 840                 msec_delay_irq(20);
 841
 842                 ret_val = phy->ops.write_reg(hw,
 843                                              0x0000,
 844                                              IGP01E1000_IEEE_FORCE_GIG);
 845                 if (ret_val)
 846                         goto out;
 847
 848                 ret_val = phy->ops.write_reg(hw,
 849                                              IGP01E1000_PHY_DSP_FFE,
 850                                              IGP01E1000_PHY_DSP_FFE_DEFAULT);
 851                 if (ret_val)
 852                         goto out;
 853
 854                 ret_val = phy->ops.write_reg(hw,
 855                                              0x0000,
 856                                              IGP01E1000_IEEE_RESTART_AUTONEG);
 857                 if (ret_val)
 858                         goto out;
 859
 860                 msec_delay_irq(20);
 861
 862                 /* Now enable the transmitter */
 863                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
 864
 865                 if (ret_val)
 866                         goto out;
 867
 868                 dev_spec->ffe_config = e1000_ffe_config_enabled;
 869         }
 870
 871 out:
 872         return ret_val;
 873 }
 874
 875 /**
 876  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
 877  *  @hw: pointer to the HW structure
 878  *
 879  *  The automatic gain control (agc) normalizes the amplitude of the
 880  *  received signal, adjusting for the attenuation produced by the
 881  *  cable.  By reading the AGC registers, which represent the
 882  *  combination of coarse and fine gain value, the value can be put
 883  *  into a lookup table to obtain the approximate cable length
 884  *  for each channel.
 885  **/
 886 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
 887 {
 888         struct e1000_phy_info *phy = &hw->phy;
 889         s32 ret_val = E1000_SUCCESS;
 890         u16 i, data;
 891         u16 cur_agc_value, agc_value = 0;
 892         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
 893         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 894                                                          {IGP01E1000_PHY_AGC_A,
 895                                                           IGP01E1000_PHY_AGC_B,
 896                                                           IGP01E1000_PHY_AGC_C,
 897                                                           IGP01E1000_PHY_AGC_D};
 898
 899         DEBUGFUNC("e1000_get_cable_length_igp_82541");
 900
 901         /* Read the AGC registers for all channels */
 902         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 903                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
 904                 if (ret_val)
 905                         goto out;
 906
 907                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
 908
 909                 /* Bounds checking */
 910                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 911                     (cur_agc_value == 0)) {
 912                         ret_val = -E1000_ERR_PHY;
 913                         goto out;
 914                 }
 915
 916                 agc_value += cur_agc_value;
 917
 918                 if (min_agc_value > cur_agc_value)
 919                         min_agc_value = cur_agc_value;
 920         }
 921
 922         /* Remove the minimal AGC result for length < 50m */
 923         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
 924                 agc_value -= min_agc_value;
 925                 /* Average the three remaining channels for the length. */
 926                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 927         } else {
 928                 /* Average the channels for the length. */
 929                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 930         }
 931
 932         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
 933                                  IGP01E1000_AGC_RANGE)
 934                                 ? (e1000_igp_cable_length_table[agc_value] -
 935                                    IGP01E1000_AGC_RANGE)
 936                                 : 0;
 937         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
 938                                 IGP01E1000_AGC_RANGE;
 939
 940         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 941
 942 out:
 943         return ret_val;
 944 }
 945
 946 /**
 947  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
 948  *  @hw: pointer to the HW structure
 949  *  @active: boolean used to enable/disable lplu
 950  *
 951  *  Success returns 0, Failure returns 1
 952  *
 953  *  The low power link up (lplu) state is set to the power management level D3
 954  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 955  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 956  *  is used during Dx states where the power conservation is most important.
 957  *  During driver activity, SmartSpeed should be enabled so performance is
 958  *  maintained.
 959  **/
 960 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
 961 {
 962         struct e1000_phy_info *phy = &hw->phy;
 963         s32 ret_val;
 964         u16 data;
 965
 966         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
 967
 968         switch (hw->mac.type) {
 969         case e1000_82541_rev_2:
 970         case e1000_82547_rev_2:
 971                 break;
 972         default:
 973                 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
 974                 goto out;
 975                 break;
 976         }
 977
 978         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
 979         if (ret_val)
 980                 goto out;
 981
 982         if (!active) {
 983                 data &= ~IGP01E1000_GMII_FLEX_SPD;
 984                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 985                 if (ret_val)
 986                         goto out;
 987
 988                 /*
 989                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 990                  * during Dx states where the power conservation is most
 991                  * important.  During driver activity we should enable
 992                  * SmartSpeed, so performance is maintained.
 993                  */
 994                 if (phy->smart_speed == e1000_smart_speed_on) {
 995                         ret_val = phy->ops.read_reg(hw,
 996                                                     IGP01E1000_PHY_PORT_CONFIG,
 997                                                     &data);
 998                         if (ret_val)
 999                                 goto out;
1000
1001                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1002                         ret_val = phy->ops.write_reg(hw,
1003                                                      IGP01E1000_PHY_PORT_CONFIG,
1004                                                      data);
1005                         if (ret_val)
1006                                 goto out;
1007                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1008                         ret_val = phy->ops.read_reg(hw,
1009                                                     IGP01E1000_PHY_PORT_CONFIG,
1010                                                     &data);
1011                         if (ret_val)
1012                                 goto out;
1013
1014                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1015                         ret_val = phy->ops.write_reg(hw,
1016                                                      IGP01E1000_PHY_PORT_CONFIG,
1017                                                      data);
1018                         if (ret_val)
1019                                 goto out;
1020                 }
1021         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1022                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1023                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1024                 data |= IGP01E1000_GMII_FLEX_SPD;
1025                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1026                 if (ret_val)
1027                         goto out;
1028
1029                 /* When LPLU is enabled, we should disable SmartSpeed */
1030                 ret_val = phy->ops.read_reg(hw,
1031                                             IGP01E1000_PHY_PORT_CONFIG,
1032                                             &data);
1033                 if (ret_val)
1034                         goto out;
1035
1036                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1037                 ret_val = phy->ops.write_reg(hw,
1038                                              IGP01E1000_PHY_PORT_CONFIG,
1039                                              data);
1040         }
1041
1042 out:
1043         return ret_val;
1044 }
1045
1046 /**
1047  *  e1000_setup_led_82541 - Configures SW controllable LED
1048  *  @hw: pointer to the HW structure
1049  *
1050  *  This prepares the SW controllable LED for use and saves the current state
1051  *  of the LED so it can be later restored.
1052  **/
1053 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1054 {
1055         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1056         s32 ret_val;
1057
1058         DEBUGFUNC("e1000_setup_led_82541");
1059
1060         ret_val = hw->phy.ops.read_reg(hw,
1061                                        IGP01E1000_GMII_FIFO,
1062                                        &dev_spec->spd_default);
1063         if (ret_val)
1064                 goto out;
1065
1066         ret_val = hw->phy.ops.write_reg(hw,
1067                                         IGP01E1000_GMII_FIFO,
1068                                         (u16)(dev_spec->spd_default &
1069                                                 ~IGP01E1000_GMII_SPD));
1070         if (ret_val)
1071                 goto out;
1072
1073         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1074
1075 out:
1076         return ret_val;
1077 }
1078
1079 /**
1080  *  e1000_cleanup_led_82541 - Set LED config to default operation
1081  *  @hw: pointer to the HW structure
1082  *
1083  *  Remove the current LED configuration and set the LED configuration
1084  *  to the default value, saved from the EEPROM.
1085  **/
1086 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1087 {
1088         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1089         s32 ret_val;
1090
1091         DEBUGFUNC("e1000_cleanup_led_82541");
1092
1093         ret_val = hw->phy.ops.write_reg(hw,
1094                                         IGP01E1000_GMII_FIFO,
1095                                         dev_spec->spd_default);
1096         if (ret_val)
1097                 goto out;
1098
1099         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1100
1101 out:
1102         return ret_val;
1103 }
1104
1105 /**
1106  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1107  *  @hw: pointer to the HW structure
1108  *
1109  *  Initializes the IGP PHY.
1110  **/
1111 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1112 {
1113         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1114         u32 ret_val;
1115         u16 phy_saved_data;
1116
1117         DEBUGFUNC("e1000_phy_init_script_82541");
1118
1119         if (!dev_spec->phy_init_script) {
1120                 ret_val = E1000_SUCCESS;
1121                 goto out;
1122         }
1123
1124         /* Delay after phy reset to enable NVM configuration to load */
1125         msec_delay(20);
1126
1127         /*
1128          * Save off the current value of register 0x2F5B to be restored at
1129          * the end of this routine.
1130          */
1131         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1132
1133         /* Disabled the PHY transmitter */
1134         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1135
1136         msec_delay(20);
1137
1138         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1139
1140         msec_delay(5);
1141
1142         switch (hw->mac.type) {
1143         case e1000_82541:
1144         case e1000_82547:
1145                 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1146
1147                 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1148
1149                 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1150
1151                 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1152
1153                 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1154
1155                 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1156
1157                 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1158
1159                 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1160
1161                 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1162                 break;
1163         case e1000_82541_rev_2:
1164         case e1000_82547_rev_2:
1165                 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1166                 break;
1167         default:
1168                 break;
1169         }
1170
1171         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1172
1173         msec_delay(20);
1174
1175         /* Now enable the transmitter */
1176         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1177
1178         if (hw->mac.type == e1000_82547) {
1179                 u16 fused, fine, coarse;
1180
1181                 /* Move to analog registers page */
1182                 hw->phy.ops.read_reg(hw,
1183                                   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1184                                   &fused);
1185
1186                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1187                         hw->phy.ops.read_reg(hw,
1188                                           IGP01E1000_ANALOG_FUSE_STATUS,
1189                                           &fused);
1190
1191                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1192                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1193
1194                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1195                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1196                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1197                         } else if (coarse ==
1198                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1199                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1200
1201                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1202                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1203                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1204
1205                         hw->phy.ops.write_reg(hw,
1206                                            IGP01E1000_ANALOG_FUSE_CONTROL,
1207                                            fused);
1208                         hw->phy.ops.write_reg(hw,
1209                                       IGP01E1000_ANALOG_FUSE_BYPASS,
1210                                       IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1211                 }
1212         }
1213
1214 out:
1215         return ret_val;
1216 }
1217
1218 /**
1219  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1220  *  @hw: pointer to the HW structure
1221  *  @state: boolean value used to enable/disable PHY init script
1222  *
1223  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1224  *  IGP PHY.
1225  **/
1226 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1227 {
1228         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1229
1230         DEBUGFUNC("e1000_init_script_state_82541");
1231
1232         if (hw->phy.type != e1000_phy_igp) {
1233                 DEBUGOUT("Initialization script not necessary.\n");
1234                 goto out;
1235         }
1236
1237         dev_spec->phy_init_script = state;
1238
1239 out:
1240         return;
1241 }
1242
1243 /**
1244  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1245  * @hw: pointer to the HW structure
1246  *
1247  * In the case of a PHY power down to save power, or to turn off link during a
1248  * driver unload, or wake on lan is not enabled, remove the link.
1249  **/
1250 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1251 {
1252         /* If the management interface is not enabled, then power down */
1253         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1254                 e1000_power_down_phy_copper(hw);
1255
1256         return;
1257 }
1258
1259 /**
1260  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1261  *  @hw: pointer to the HW structure
1262  *
1263  *  Clears the hardware counters by reading the counter registers.
1264  **/
1265 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1266 {
1267         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1268
1269         e1000_clear_hw_cntrs_base_generic(hw);
1270
1271         E1000_READ_REG(hw, E1000_PRC64);
1272         E1000_READ_REG(hw, E1000_PRC127);
1273         E1000_READ_REG(hw, E1000_PRC255);
1274         E1000_READ_REG(hw, E1000_PRC511);
1275         E1000_READ_REG(hw, E1000_PRC1023);
1276         E1000_READ_REG(hw, E1000_PRC1522);
1277         E1000_READ_REG(hw, E1000_PTC64);
1278         E1000_READ_REG(hw, E1000_PTC127);
1279         E1000_READ_REG(hw, E1000_PTC255);
1280         E1000_READ_REG(hw, E1000_PTC511);
1281         E1000_READ_REG(hw, E1000_PTC1023);
1282         E1000_READ_REG(hw, E1000_PTC1522);
1283
1284         E1000_READ_REG(hw, E1000_ALGNERRC);
1285         E1000_READ_REG(hw, E1000_RXERRC);
1286         E1000_READ_REG(hw, E1000_TNCRS);
1287         E1000_READ_REG(hw, E1000_CEXTERR);
1288         E1000_READ_REG(hw, E1000_TSCTC);
1289         E1000_READ_REG(hw, E1000_TSCTFC);
1290
1291         E1000_READ_REG(hw, E1000_MGTPRC);
1292         E1000_READ_REG(hw, E1000_MGTPDC);
1293         E1000_READ_REG(hw, E1000_MGTPTC);
1294 }