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32 ******************************************************************************/
36 * 82542 Gigabit Ethernet Controller
39 #include "e1000_api.h"
41 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
42 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
43 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
44 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
45 static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
46 static s32 e1000_init_hw_82542(struct e1000_hw *hw);
47 static s32 e1000_setup_link_82542(struct e1000_hw *hw);
48 static s32 e1000_led_on_82542(struct e1000_hw *hw);
49 static s32 e1000_led_off_82542(struct e1000_hw *hw);
50 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
52 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);
55 * e1000_init_phy_params_82542 - Init PHY func ptrs.
56 * @hw: pointer to the HW structure
58 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
60 struct e1000_phy_info *phy = &hw->phy;
61 s32 ret_val = E1000_SUCCESS;
63 DEBUGFUNC("e1000_init_phy_params_82542");
65 phy->type = e1000_phy_none;
71 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
72 * @hw: pointer to the HW structure
74 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
76 struct e1000_nvm_info *nvm = &hw->nvm;
78 DEBUGFUNC("e1000_init_nvm_params_82542");
80 nvm->address_bits = 6;
83 nvm->type = e1000_nvm_eeprom_microwire;
86 /* Function Pointers */
87 nvm->ops.read = e1000_read_nvm_microwire;
88 nvm->ops.release = e1000_stop_nvm;
89 nvm->ops.write = e1000_write_nvm_microwire;
90 nvm->ops.update = e1000_update_nvm_checksum_generic;
91 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
97 * e1000_init_mac_params_82542 - Init MAC func ptrs.
98 * @hw: pointer to the HW structure
100 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
102 struct e1000_mac_info *mac = &hw->mac;
104 DEBUGFUNC("e1000_init_mac_params_82542");
107 hw->phy.media_type = e1000_media_type_fiber;
109 /* Set mta register count */
110 mac->mta_reg_count = 128;
111 /* Set rar entry count */
112 mac->rar_entry_count = E1000_RAR_ENTRIES;
114 /* Function pointers */
116 /* bus type/speed/width */
117 mac->ops.get_bus_info = e1000_get_bus_info_82542;
119 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
121 mac->ops.reset_hw = e1000_reset_hw_82542;
122 /* hw initialization */
123 mac->ops.init_hw = e1000_init_hw_82542;
125 mac->ops.setup_link = e1000_setup_link_82542;
126 /* phy/fiber/serdes setup */
127 mac->ops.setup_physical_interface =
128 e1000_setup_fiber_serdes_link_generic;
130 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
131 /* multicast address update */
132 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
134 mac->ops.write_vfta = e1000_write_vfta_generic;
136 mac->ops.clear_vfta = e1000_clear_vfta_generic;
137 /* read mac address */
138 mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
140 mac->ops.rar_set = e1000_rar_set_82542;
141 /* turn on/off LED */
142 mac->ops.led_on = e1000_led_on_82542;
143 mac->ops.led_off = e1000_led_off_82542;
144 /* clear hardware counters */
145 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
147 mac->ops.get_link_up_info =
148 e1000_get_speed_and_duplex_fiber_serdes_generic;
150 return E1000_SUCCESS;
154 * e1000_init_function_pointers_82542 - Init func ptrs.
155 * @hw: pointer to the HW structure
157 * Called to initialize all function pointers and parameters.
159 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
161 DEBUGFUNC("e1000_init_function_pointers_82542");
163 hw->mac.ops.init_params = e1000_init_mac_params_82542;
164 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
165 hw->phy.ops.init_params = e1000_init_phy_params_82542;
169 * e1000_get_bus_info_82542 - Obtain bus information for adapter
170 * @hw: pointer to the HW structure
172 * This will obtain information about the HW bus for which the
173 * adapter is attached and stores it in the hw structure.
175 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
177 DEBUGFUNC("e1000_get_bus_info_82542");
179 hw->bus.type = e1000_bus_type_pci;
180 hw->bus.speed = e1000_bus_speed_unknown;
181 hw->bus.width = e1000_bus_width_unknown;
183 return E1000_SUCCESS;
187 * e1000_reset_hw_82542 - Reset hardware
188 * @hw: pointer to the HW structure
190 * This resets the hardware into a known state.
192 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
194 struct e1000_bus_info *bus = &hw->bus;
195 s32 ret_val = E1000_SUCCESS;
198 DEBUGFUNC("e1000_reset_hw_82542");
200 if (hw->revision_id == E1000_REVISION_2) {
201 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
202 e1000_pci_clear_mwi(hw);
205 DEBUGOUT("Masking off all interrupts\n");
206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
208 E1000_WRITE_REG(hw, E1000_RCTL, 0);
209 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
210 E1000_WRITE_FLUSH(hw);
213 * Delay to allow any outstanding PCI transactions to complete before
214 * resetting the device
218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
220 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
221 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
223 hw->nvm.ops.reload(hw);
226 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
227 E1000_READ_REG(hw, E1000_ICR);
229 if (hw->revision_id == E1000_REVISION_2) {
230 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
231 e1000_pci_set_mwi(hw);
238 * e1000_init_hw_82542 - Initialize hardware
239 * @hw: pointer to the HW structure
241 * This inits the hardware readying it for operation.
243 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
245 struct e1000_mac_info *mac = &hw->mac;
246 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
247 s32 ret_val = E1000_SUCCESS;
251 DEBUGFUNC("e1000_init_hw_82542");
253 /* Disabling VLAN filtering */
254 E1000_WRITE_REG(hw, E1000_VET, 0);
255 mac->ops.clear_vfta(hw);
257 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
258 if (hw->revision_id == E1000_REVISION_2) {
259 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
260 e1000_pci_clear_mwi(hw);
261 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
262 E1000_WRITE_FLUSH(hw);
266 /* Setup the receive address. */
267 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
269 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
270 if (hw->revision_id == E1000_REVISION_2) {
271 E1000_WRITE_REG(hw, E1000_RCTL, 0);
272 E1000_WRITE_FLUSH(hw);
274 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
275 e1000_pci_set_mwi(hw);
278 /* Zero out the Multicast HASH table */
279 DEBUGOUT("Zeroing the MTA\n");
280 for (i = 0; i < mac->mta_reg_count; i++)
281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
284 * Set the PCI priority bit correctly in the CTRL register. This
285 * determines if the adapter gives priority to receives, or if it
286 * gives equal priority to transmits and receives.
288 if (dev_spec->dma_fairness) {
289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
290 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
293 /* Setup link and flow control */
294 ret_val = e1000_setup_link_82542(hw);
297 * Clear all of the statistics registers (clear on read). It is
298 * important that we do this after we have tried to establish link
299 * because the symbol error count will increment wildly if there
302 e1000_clear_hw_cntrs_82542(hw);
308 * e1000_setup_link_82542 - Setup flow control and link settings
309 * @hw: pointer to the HW structure
311 * Determines which flow control settings to use, then configures flow
312 * control. Calls the appropriate media-specific link configuration
313 * function. Assuming the adapter has a valid link partner, a valid link
314 * should be established. Assumes the hardware has previously been reset
315 * and the transmitter and receiver are not enabled.
317 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
319 struct e1000_mac_info *mac = &hw->mac;
322 DEBUGFUNC("e1000_setup_link_82542");
324 ret_val = e1000_set_default_fc_generic(hw);
328 hw->fc.requested_mode &= ~e1000_fc_tx_pause;
330 if (mac->report_tx_early)
331 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
334 * Save off the requested flow control mode for use later. Depending
335 * on the link partner's capabilities, we may or may not use this mode.
337 hw->fc.current_mode = hw->fc.requested_mode;
339 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
340 hw->fc.current_mode);
342 /* Call the necessary subroutine to configure the link. */
343 ret_val = mac->ops.setup_physical_interface(hw);
348 * Initialize the flow control address, type, and PAUSE timer
349 * registers to their default values. This is done even if flow
350 * control is disabled, because it does not hurt anything to
351 * initialize these registers.
353 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
355 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
356 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
357 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
359 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
361 ret_val = e1000_set_fc_watermarks_generic(hw);
368 * e1000_led_on_82542 - Turn on SW controllable LED
369 * @hw: pointer to the HW structure
371 * Turns the SW defined LED on.
373 static s32 e1000_led_on_82542(struct e1000_hw *hw)
375 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
377 DEBUGFUNC("e1000_led_on_82542");
379 ctrl |= E1000_CTRL_SWDPIN0;
380 ctrl |= E1000_CTRL_SWDPIO0;
381 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
383 return E1000_SUCCESS;
387 * e1000_led_off_82542 - Turn off SW controllable LED
388 * @hw: pointer to the HW structure
390 * Turns the SW defined LED off.
392 static s32 e1000_led_off_82542(struct e1000_hw *hw)
394 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
396 DEBUGFUNC("e1000_led_off_82542");
398 ctrl &= ~E1000_CTRL_SWDPIN0;
399 ctrl |= E1000_CTRL_SWDPIO0;
400 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
402 return E1000_SUCCESS;
406 * e1000_rar_set_82542 - Set receive address register
407 * @hw: pointer to the HW structure
408 * @addr: pointer to the receive address
409 * @index: receive address array register
411 * Sets the receive address array register at index to the address passed
414 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
416 u32 rar_low, rar_high;
418 DEBUGFUNC("e1000_rar_set_82542");
421 * HW expects these in little endian so we reverse the byte order
422 * from network order (big endian) to little endian
424 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
425 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
427 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
429 /* If MAC address zero, no need to set the AV bit */
430 if (rar_low || rar_high)
431 rar_high |= E1000_RAH_AV;
433 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
434 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
436 return E1000_SUCCESS;
440 * e1000_translate_register_82542 - Translate the proper register offset
441 * @reg: e1000 register to be read
443 * Registers in 82542 are located in different offsets than other adapters
444 * even though they function in the same manner. This function takes in
445 * the name of the register to read and returns the correct offset for
448 u32 e1000_translate_register_82542(u32 reg)
451 * Some of the 82542 registers are located at different
452 * offsets than they are in newer adapters.
453 * Despite the difference in location, the registers
454 * function in the same manner.
537 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
538 * @hw: pointer to the HW structure
540 * Clears the hardware counters by reading the counter registers.
542 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
544 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
546 e1000_clear_hw_cntrs_base_generic(hw);
548 E1000_READ_REG(hw, E1000_PRC64);
549 E1000_READ_REG(hw, E1000_PRC127);
550 E1000_READ_REG(hw, E1000_PRC255);
551 E1000_READ_REG(hw, E1000_PRC511);
552 E1000_READ_REG(hw, E1000_PRC1023);
553 E1000_READ_REG(hw, E1000_PRC1522);
554 E1000_READ_REG(hw, E1000_PTC64);
555 E1000_READ_REG(hw, E1000_PTC127);
556 E1000_READ_REG(hw, E1000_PTC255);
557 E1000_READ_REG(hw, E1000_PTC511);
558 E1000_READ_REG(hw, E1000_PTC1023);
559 E1000_READ_REG(hw, E1000_PTC1522);
563 * e1000_read_mac_addr_82542 - Read device MAC address
564 * @hw: pointer to the HW structure
566 * Reads the device MAC address from the EEPROM and stores the value.
568 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
570 s32 ret_val = E1000_SUCCESS;
571 u16 offset, nvm_data, i;
573 DEBUGFUNC("e1000_read_mac_addr");
575 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
577 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
579 DEBUGOUT("NVM Read Error\n");
582 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
583 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
586 for (i = 0; i < ETH_ADDR_LEN; i++)
587 hw->mac.addr[i] = hw->mac.perm_addr[i];