1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
37 * 82542 Gigabit Ethernet Controller
40 #include "e1000_api.h"
42 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
45 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
46 static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
47 static s32 e1000_init_hw_82542(struct e1000_hw *hw);
48 static s32 e1000_setup_link_82542(struct e1000_hw *hw);
49 static s32 e1000_led_on_82542(struct e1000_hw *hw);
50 static s32 e1000_led_off_82542(struct e1000_hw *hw);
51 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
52 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
53 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);
56 * e1000_init_phy_params_82542 - Init PHY func ptrs.
57 * @hw: pointer to the HW structure
59 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val = E1000_SUCCESS;
64 DEBUGFUNC("e1000_init_phy_params_82542");
66 phy->type = e1000_phy_none;
72 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
73 * @hw: pointer to the HW structure
75 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
77 struct e1000_nvm_info *nvm = &hw->nvm;
79 DEBUGFUNC("e1000_init_nvm_params_82542");
81 nvm->address_bits = 6;
84 nvm->type = e1000_nvm_eeprom_microwire;
87 /* Function Pointers */
88 nvm->ops.read = e1000_read_nvm_microwire;
89 nvm->ops.release = e1000_stop_nvm;
90 nvm->ops.write = e1000_write_nvm_microwire;
91 nvm->ops.update = e1000_update_nvm_checksum_generic;
92 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
98 * e1000_init_mac_params_82542 - Init MAC func ptrs.
99 * @hw: pointer to the HW structure
101 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
103 struct e1000_mac_info *mac = &hw->mac;
105 DEBUGFUNC("e1000_init_mac_params_82542");
108 hw->phy.media_type = e1000_media_type_fiber;
110 /* Set mta register count */
111 mac->mta_reg_count = 128;
112 /* Set rar entry count */
113 mac->rar_entry_count = E1000_RAR_ENTRIES;
115 /* Function pointers */
117 /* bus type/speed/width */
118 mac->ops.get_bus_info = e1000_get_bus_info_82542;
120 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
122 mac->ops.reset_hw = e1000_reset_hw_82542;
123 /* hw initialization */
124 mac->ops.init_hw = e1000_init_hw_82542;
126 mac->ops.setup_link = e1000_setup_link_82542;
127 /* phy/fiber/serdes setup */
128 mac->ops.setup_physical_interface =
129 e1000_setup_fiber_serdes_link_generic;
131 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
132 /* multicast address update */
133 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
135 mac->ops.write_vfta = e1000_write_vfta_generic;
137 mac->ops.clear_vfta = e1000_clear_vfta_generic;
138 /* read mac address */
139 mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
141 mac->ops.rar_set = e1000_rar_set_82542;
142 /* turn on/off LED */
143 mac->ops.led_on = e1000_led_on_82542;
144 mac->ops.led_off = e1000_led_off_82542;
145 /* clear hardware counters */
146 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
148 mac->ops.get_link_up_info =
149 e1000_get_speed_and_duplex_fiber_serdes_generic;
151 return E1000_SUCCESS;
155 * e1000_init_function_pointers_82542 - Init func ptrs.
156 * @hw: pointer to the HW structure
158 * Called to initialize all function pointers and parameters.
160 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
162 DEBUGFUNC("e1000_init_function_pointers_82542");
164 hw->mac.ops.init_params = e1000_init_mac_params_82542;
165 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
166 hw->phy.ops.init_params = e1000_init_phy_params_82542;
170 * e1000_get_bus_info_82542 - Obtain bus information for adapter
171 * @hw: pointer to the HW structure
173 * This will obtain information about the HW bus for which the
174 * adapter is attached and stores it in the hw structure.
176 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
178 DEBUGFUNC("e1000_get_bus_info_82542");
180 hw->bus.type = e1000_bus_type_pci;
181 hw->bus.speed = e1000_bus_speed_unknown;
182 hw->bus.width = e1000_bus_width_unknown;
184 return E1000_SUCCESS;
188 * e1000_reset_hw_82542 - Reset hardware
189 * @hw: pointer to the HW structure
191 * This resets the hardware into a known state.
193 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
195 struct e1000_bus_info *bus = &hw->bus;
196 s32 ret_val = E1000_SUCCESS;
199 DEBUGFUNC("e1000_reset_hw_82542");
201 if (hw->revision_id == E1000_REVISION_2) {
202 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
203 e1000_pci_clear_mwi(hw);
206 DEBUGOUT("Masking off all interrupts\n");
207 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
209 E1000_WRITE_REG(hw, E1000_RCTL, 0);
210 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
211 E1000_WRITE_FLUSH(hw);
214 * Delay to allow any outstanding PCI transactions to complete before
215 * resetting the device
219 ctrl = E1000_READ_REG(hw, E1000_CTRL);
221 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
222 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
224 hw->nvm.ops.reload(hw);
227 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
228 E1000_READ_REG(hw, E1000_ICR);
230 if (hw->revision_id == E1000_REVISION_2) {
231 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
232 e1000_pci_set_mwi(hw);
239 * e1000_init_hw_82542 - Initialize hardware
240 * @hw: pointer to the HW structure
242 * This inits the hardware readying it for operation.
244 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
246 struct e1000_mac_info *mac = &hw->mac;
247 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
248 s32 ret_val = E1000_SUCCESS;
252 DEBUGFUNC("e1000_init_hw_82542");
254 /* Disabling VLAN filtering */
255 E1000_WRITE_REG(hw, E1000_VET, 0);
256 mac->ops.clear_vfta(hw);
258 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
259 if (hw->revision_id == E1000_REVISION_2) {
260 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
261 e1000_pci_clear_mwi(hw);
262 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
263 E1000_WRITE_FLUSH(hw);
267 /* Setup the receive address. */
268 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
270 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
271 if (hw->revision_id == E1000_REVISION_2) {
272 E1000_WRITE_REG(hw, E1000_RCTL, 0);
273 E1000_WRITE_FLUSH(hw);
275 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
276 e1000_pci_set_mwi(hw);
279 /* Zero out the Multicast HASH table */
280 DEBUGOUT("Zeroing the MTA\n");
281 for (i = 0; i < mac->mta_reg_count; i++)
282 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
285 * Set the PCI priority bit correctly in the CTRL register. This
286 * determines if the adapter gives priority to receives, or if it
287 * gives equal priority to transmits and receives.
289 if (dev_spec->dma_fairness) {
290 ctrl = E1000_READ_REG(hw, E1000_CTRL);
291 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
294 /* Setup link and flow control */
295 ret_val = e1000_setup_link_82542(hw);
298 * Clear all of the statistics registers (clear on read). It is
299 * important that we do this after we have tried to establish link
300 * because the symbol error count will increment wildly if there
303 e1000_clear_hw_cntrs_82542(hw);
309 * e1000_setup_link_82542 - Setup flow control and link settings
310 * @hw: pointer to the HW structure
312 * Determines which flow control settings to use, then configures flow
313 * control. Calls the appropriate media-specific link configuration
314 * function. Assuming the adapter has a valid link partner, a valid link
315 * should be established. Assumes the hardware has previously been reset
316 * and the transmitter and receiver are not enabled.
318 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
320 struct e1000_mac_info *mac = &hw->mac;
323 DEBUGFUNC("e1000_setup_link_82542");
325 ret_val = e1000_set_default_fc_generic(hw);
329 hw->fc.requested_mode &= ~e1000_fc_tx_pause;
331 if (mac->report_tx_early)
332 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
335 * Save off the requested flow control mode for use later. Depending
336 * on the link partner's capabilities, we may or may not use this mode.
338 hw->fc.current_mode = hw->fc.requested_mode;
340 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
341 hw->fc.current_mode);
343 /* Call the necessary subroutine to configure the link. */
344 ret_val = mac->ops.setup_physical_interface(hw);
349 * Initialize the flow control address, type, and PAUSE timer
350 * registers to their default values. This is done even if flow
351 * control is disabled, because it does not hurt anything to
352 * initialize these registers.
354 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
356 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
357 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
358 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
360 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
362 ret_val = e1000_set_fc_watermarks_generic(hw);
369 * e1000_led_on_82542 - Turn on SW controllable LED
370 * @hw: pointer to the HW structure
372 * Turns the SW defined LED on.
374 static s32 e1000_led_on_82542(struct e1000_hw *hw)
376 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
378 DEBUGFUNC("e1000_led_on_82542");
380 ctrl |= E1000_CTRL_SWDPIN0;
381 ctrl |= E1000_CTRL_SWDPIO0;
382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
384 return E1000_SUCCESS;
388 * e1000_led_off_82542 - Turn off SW controllable LED
389 * @hw: pointer to the HW structure
391 * Turns the SW defined LED off.
393 static s32 e1000_led_off_82542(struct e1000_hw *hw)
395 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
397 DEBUGFUNC("e1000_led_off_82542");
399 ctrl &= ~E1000_CTRL_SWDPIN0;
400 ctrl |= E1000_CTRL_SWDPIO0;
401 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
403 return E1000_SUCCESS;
407 * e1000_rar_set_82542 - Set receive address register
408 * @hw: pointer to the HW structure
409 * @addr: pointer to the receive address
410 * @index: receive address array register
412 * Sets the receive address array register at index to the address passed
415 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
417 u32 rar_low, rar_high;
419 DEBUGFUNC("e1000_rar_set_82542");
422 * HW expects these in little endian so we reverse the byte order
423 * from network order (big endian) to little endian
425 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
426 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
428 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
430 /* If MAC address zero, no need to set the AV bit */
431 if (rar_low || rar_high)
432 rar_high |= E1000_RAH_AV;
434 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
435 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
437 return E1000_SUCCESS;
441 * e1000_translate_register_82542 - Translate the proper register offset
442 * @reg: e1000 register to be read
444 * Registers in 82542 are located in different offsets than other adapters
445 * even though they function in the same manner. This function takes in
446 * the name of the register to read and returns the correct offset for
449 u32 e1000_translate_register_82542(u32 reg)
452 * Some of the 82542 registers are located at different
453 * offsets than they are in newer adapters.
454 * Despite the difference in location, the registers
455 * function in the same manner.
538 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
539 * @hw: pointer to the HW structure
541 * Clears the hardware counters by reading the counter registers.
543 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
545 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
547 e1000_clear_hw_cntrs_base_generic(hw);
549 E1000_READ_REG(hw, E1000_PRC64);
550 E1000_READ_REG(hw, E1000_PRC127);
551 E1000_READ_REG(hw, E1000_PRC255);
552 E1000_READ_REG(hw, E1000_PRC511);
553 E1000_READ_REG(hw, E1000_PRC1023);
554 E1000_READ_REG(hw, E1000_PRC1522);
555 E1000_READ_REG(hw, E1000_PTC64);
556 E1000_READ_REG(hw, E1000_PTC127);
557 E1000_READ_REG(hw, E1000_PTC255);
558 E1000_READ_REG(hw, E1000_PTC511);
559 E1000_READ_REG(hw, E1000_PTC1023);
560 E1000_READ_REG(hw, E1000_PTC1522);
564 * e1000_read_mac_addr_82542 - Read device MAC address
565 * @hw: pointer to the HW structure
567 * Reads the device MAC address from the EEPROM and stores the value.
569 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
571 s32 ret_val = E1000_SUCCESS;
572 u16 offset, nvm_data, i;
574 DEBUGFUNC("e1000_read_mac_addr");
576 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
578 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
580 DEBUGOUT("NVM Read Error\n");
583 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
584 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
587 for (i = 0; i < ETH_ADDR_LEN; i++)
588 hw->mac.addr[i] = hw->mac.perm_addr[i];