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32 ******************************************************************************/
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure
84 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = E1000_SUCCESS;
89 DEBUGFUNC("e1000_init_phy_params_82543");
91 if (hw->phy.media_type != e1000_media_type_copper) {
92 phy->type = e1000_phy_none;
95 phy->ops.power_up = e1000_power_up_phy_copper;
96 phy->ops.power_down = e1000_power_down_phy_copper;
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
101 phy->reset_delay_us = 10000;
102 phy->type = e1000_phy_m88;
104 /* Function Pointers */
105 phy->ops.check_polarity = e1000_check_polarity_m88;
106 phy->ops.commit = e1000_phy_sw_reset_generic;
107 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
108 phy->ops.get_cable_length = e1000_get_cable_length_m88;
109 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
111 ? e1000_read_phy_reg_82543
112 : e1000_read_phy_reg_m88;
113 phy->ops.reset = (hw->mac.type == e1000_82543)
114 ? e1000_phy_hw_reset_82543
115 : e1000_phy_hw_reset_generic;
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
117 ? e1000_write_phy_reg_82543
118 : e1000_write_phy_reg_m88;
119 phy->ops.get_info = e1000_get_phy_info_m88;
122 * The external PHY of the 82543 can be in a funky state.
123 * Resetting helps us read the PHY registers for acquiring
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
129 DEBUGOUT("Resetting PHY during init failed.\n");
135 ret_val = e1000_get_phy_id(hw);
140 switch (hw->mac.type) {
142 if (phy->id != M88E1000_E_PHY_ID) {
143 ret_val = -E1000_ERR_PHY;
148 if (phy->id != M88E1000_I_PHY_ID) {
149 ret_val = -E1000_ERR_PHY;
154 ret_val = -E1000_ERR_PHY;
164 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
165 * @hw: pointer to the HW structure
167 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
169 struct e1000_nvm_info *nvm = &hw->nvm;
171 DEBUGFUNC("e1000_init_nvm_params_82543");
173 nvm->type = e1000_nvm_eeprom_microwire;
175 nvm->delay_usec = 50;
176 nvm->address_bits = 6;
177 nvm->opcode_bits = 3;
179 /* Function Pointers */
180 nvm->ops.read = e1000_read_nvm_microwire;
181 nvm->ops.update = e1000_update_nvm_checksum_generic;
182 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
183 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
184 nvm->ops.write = e1000_write_nvm_microwire;
186 return E1000_SUCCESS;
190 * e1000_init_mac_params_82543 - Init MAC func ptrs.
191 * @hw: pointer to the HW structure
193 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
195 struct e1000_mac_info *mac = &hw->mac;
197 DEBUGFUNC("e1000_init_mac_params_82543");
200 switch (hw->device_id) {
201 case E1000_DEV_ID_82543GC_FIBER:
202 case E1000_DEV_ID_82544EI_FIBER:
203 hw->phy.media_type = e1000_media_type_fiber;
206 hw->phy.media_type = e1000_media_type_copper;
210 /* Set mta register count */
211 mac->mta_reg_count = 128;
212 /* Set rar entry count */
213 mac->rar_entry_count = E1000_RAR_ENTRIES;
215 /* Function pointers */
217 /* bus type/speed/width */
218 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
220 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
222 mac->ops.reset_hw = e1000_reset_hw_82543;
223 /* hw initialization */
224 mac->ops.init_hw = e1000_init_hw_82543;
226 mac->ops.setup_link = e1000_setup_link_82543;
227 /* physical interface setup */
228 mac->ops.setup_physical_interface =
229 (hw->phy.media_type == e1000_media_type_copper)
230 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;
232 mac->ops.check_for_link =
233 (hw->phy.media_type == e1000_media_type_copper)
234 ? e1000_check_for_copper_link_82543
235 : e1000_check_for_fiber_link_82543;
237 mac->ops.get_link_up_info =
238 (hw->phy.media_type == e1000_media_type_copper)
239 ? e1000_get_speed_and_duplex_copper_generic
240 : e1000_get_speed_and_duplex_fiber_serdes_generic;
241 /* multicast address update */
242 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
244 mac->ops.write_vfta = e1000_write_vfta_82543;
246 mac->ops.clear_vfta = e1000_clear_vfta_generic;
247 /* read mac address */
248 mac->ops.read_mac_addr = e1000_read_mac_addr_82543;
249 /* turn on/off LED */
250 mac->ops.led_on = e1000_led_on_82543;
251 mac->ops.led_off = e1000_led_off_82543;
252 /* clear hardware counters */
253 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
255 /* Set tbi compatibility */
256 if ((hw->mac.type != e1000_82543) ||
257 (hw->phy.media_type == e1000_media_type_fiber))
258 e1000_set_tbi_compatibility_82543(hw, FALSE);
260 return E1000_SUCCESS;
264 * e1000_init_function_pointers_82543 - Init func ptrs.
265 * @hw: pointer to the HW structure
267 * Called to initialize all function pointers and parameters.
269 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
271 DEBUGFUNC("e1000_init_function_pointers_82543");
273 hw->mac.ops.init_params = e1000_init_mac_params_82543;
274 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
275 hw->phy.ops.init_params = e1000_init_phy_params_82543;
279 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
280 * @hw: pointer to the HW structure
282 * Returns the current status of 10-bit Interface (TBI) compatibility
283 * (enabled/disabled).
285 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
287 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
290 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
292 if (hw->mac.type != e1000_82543) {
293 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
297 state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);
304 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
305 * @hw: pointer to the HW structure
306 * @state: enable/disable TBI compatibility
308 * Enables or disabled 10-bit Interface (TBI) compatibility.
310 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
312 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
314 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
316 if (hw->mac.type != e1000_82543) {
317 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
322 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
324 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
331 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
332 * @hw: pointer to the HW structure
334 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
335 * (enabled/disabled).
337 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
339 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
342 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
344 if (hw->mac.type != e1000_82543) {
345 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
349 state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);
356 * e1000_set_tbi_sbp_82543 - Set TBI SBP
357 * @hw: pointer to the HW structure
358 * @state: enable/disable TBI store bad packet
360 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
362 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
364 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
366 DEBUGFUNC("e1000_set_tbi_sbp_82543");
368 if (state && e1000_tbi_compatibility_enabled_82543(hw))
369 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
371 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
377 * e1000_init_phy_disabled_82543 - Returns init PHY status
378 * @hw: pointer to the HW structure
380 * Returns the current status of whether PHY initialization is disabled.
381 * True if PHY initialization is disabled else FALSE.
383 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
385 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
388 DEBUGFUNC("e1000_init_phy_disabled_82543");
390 if (hw->mac.type != e1000_82543) {
395 ret_val = dev_spec->init_phy_disabled;
402 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
403 * @hw: pointer to the HW structure
404 * @stats: Struct containing statistic register values
405 * @frame_len: The length of the frame in question
406 * @mac_addr: The Ethernet destination address of the frame in question
407 * @max_frame_size: The maximum frame size
409 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
411 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
412 struct e1000_hw_stats *stats, u32 frame_len,
413 u8 *mac_addr, u32 max_frame_size)
415 if (!(e1000_tbi_sbp_enabled_82543(hw)))
418 /* First adjust the frame length. */
421 * We need to adjust the statistics counters, since the hardware
422 * counters overcount this packet as a CRC error and undercount
423 * the packet as a good packet
425 /* This packet should not be counted as a CRC error. */
427 /* This packet does count as a Good Packet Received. */
430 /* Adjust the Good Octets received counters */
431 stats->gorc += frame_len;
434 * Is this a broadcast or multicast? Check broadcast first,
435 * since the test for a multicast frame will test positive on
438 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
439 /* Broadcast packet */
441 else if (*mac_addr & 0x01)
442 /* Multicast packet */
446 * In this case, the hardware has over counted the number of
449 if ((frame_len == max_frame_size) && (stats->roc > 0))
453 * Adjust the bin counters when the extra byte put the frame in the
454 * wrong bin. Remember that the frame_len was adjusted above.
456 if (frame_len == 64) {
459 } else if (frame_len == 127) {
462 } else if (frame_len == 255) {
465 } else if (frame_len == 511) {
468 } else if (frame_len == 1023) {
471 } else if (frame_len == 1522) {
480 * e1000_read_phy_reg_82543 - Read PHY register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to be read
483 * @data: pointer to the read data
485 * Reads the PHY at offset and stores the information read to data.
487 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
490 s32 ret_val = E1000_SUCCESS;
492 DEBUGFUNC("e1000_read_phy_reg_82543");
494 if (offset > MAX_PHY_REG_ADDRESS) {
495 DEBUGOUT1("PHY Address %d is out of range\n", offset);
496 ret_val = -E1000_ERR_PARAM;
501 * We must first send a preamble through the MDIO pin to signal the
502 * beginning of an MII instruction. This is done by sending 32
503 * consecutive "1" bits.
505 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
508 * Now combine the next few fields that are required for a read
509 * operation. We use this method instead of calling the
510 * e1000_shift_out_mdi_bits routine five different times. The format
511 * of an MII read instruction consists of a shift out of 14 bits and
512 * is defined as follows:
513 * <Preamble><SOF><Op Code><Phy Addr><Offset>
514 * followed by a shift in of 18 bits. This first two bits shifted in
515 * are TurnAround bits used to avoid contention on the MDIO pin when a
516 * READ operation is performed. These two bits are thrown away
517 * followed by a shift in of 16 bits which contains the desired data.
519 mdic = (offset | (hw->phy.addr << 5) |
520 (PHY_OP_READ << 10) | (PHY_SOF << 12));
522 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
525 * Now that we've shifted out the read command to the MII, we need to
526 * "shift in" the 16-bit value (18 total bits) of the requested PHY
529 *data = e1000_shift_in_mdi_bits_82543(hw);
536 * e1000_write_phy_reg_82543 - Write PHY register
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be written
539 * @data: pointer to the data to be written at offset
541 * Writes data to the PHY at offset.
543 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
546 s32 ret_val = E1000_SUCCESS;
548 DEBUGFUNC("e1000_write_phy_reg_82543");
550 if (offset > MAX_PHY_REG_ADDRESS) {
551 DEBUGOUT1("PHY Address %d is out of range\n", offset);
552 ret_val = -E1000_ERR_PARAM;
557 * We'll need to use the SW defined pins to shift the write command
558 * out to the PHY. We first send a preamble to the PHY to signal the
559 * beginning of the MII instruction. This is done by sending 32
560 * consecutive "1" bits.
562 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
565 * Now combine the remaining required fields that will indicate a
566 * write operation. We use this method instead of calling the
567 * e1000_shift_out_mdi_bits routine for each field in the command. The
568 * format of a MII write instruction is as follows:
569 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
571 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
572 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
576 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
583 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
584 * @hw: pointer to the HW structure
585 * @ctrl: pointer to the control register
587 * Raise the management data input clock by setting the MDC bit in the control
590 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
593 * Raise the clock input to the Management Data Clock (by setting the
594 * MDC bit), and then delay a sufficient amount of time.
596 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
597 E1000_WRITE_FLUSH(hw);
602 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
603 * @hw: pointer to the HW structure
604 * @ctrl: pointer to the control register
606 * Lower the management data input clock by clearing the MDC bit in the
609 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
612 * Lower the clock input to the Management Data Clock (by clearing the
613 * MDC bit), and then delay a sufficient amount of time.
615 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
616 E1000_WRITE_FLUSH(hw);
621 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
622 * @hw: pointer to the HW structure
623 * @data: data to send to the PHY
624 * @count: number of bits to shift out
626 * We need to shift 'count' bits out to the PHY. So, the value in the
627 * "data" parameter will be shifted out to the PHY one bit at a time.
628 * In order to do this, "data" must be broken down into bits.
630 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
636 * We need to shift "count" number of bits out to the PHY. So, the
637 * value in the "data" parameter will be shifted out to the PHY one
638 * bit at a time. In order to do this, "data" must be broken down
642 mask <<= (count - 1);
644 ctrl = E1000_READ_REG(hw, E1000_CTRL);
646 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
647 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
651 * A "1" is shifted out to the PHY by setting the MDIO bit to
652 * "1" and then raising and lowering the Management Data Clock.
653 * A "0" is shifted out to the PHY by setting the MDIO bit to
654 * "0" and then raising and lowering the clock.
657 ctrl |= E1000_CTRL_MDIO;
659 ctrl &= ~E1000_CTRL_MDIO;
661 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
662 E1000_WRITE_FLUSH(hw);
666 e1000_raise_mdi_clk_82543(hw, &ctrl);
667 e1000_lower_mdi_clk_82543(hw, &ctrl);
674 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
675 * @hw: pointer to the HW structure
677 * In order to read a register from the PHY, we need to shift 18 bits
678 * in from the PHY. Bits are "shifted in" by raising the clock input to
679 * the PHY (setting the MDC bit), and then reading the value of the data out
682 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
689 * In order to read a register from the PHY, we need to shift in a
690 * total of 18 bits from the PHY. The first two bit (turnaround)
691 * times are used to avoid contention on the MDIO pin when a read
692 * operation is performed. These two bits are ignored by us and
693 * thrown away. Bits are "shifted in" by raising the input to the
694 * Management Data Clock (setting the MDC bit) and then reading the
695 * value of the MDIO bit.
697 ctrl = E1000_READ_REG(hw, E1000_CTRL);
700 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
703 ctrl &= ~E1000_CTRL_MDIO_DIR;
704 ctrl &= ~E1000_CTRL_MDIO;
706 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
707 E1000_WRITE_FLUSH(hw);
710 * Raise and lower the clock before reading in the data. This accounts
711 * for the turnaround bits. The first clock occurred when we clocked
712 * out the last bit of the Register Address.
714 e1000_raise_mdi_clk_82543(hw, &ctrl);
715 e1000_lower_mdi_clk_82543(hw, &ctrl);
717 for (data = 0, i = 0; i < 16; i++) {
719 e1000_raise_mdi_clk_82543(hw, &ctrl);
720 ctrl = E1000_READ_REG(hw, E1000_CTRL);
721 /* Check to see if we shifted in a "1". */
722 if (ctrl & E1000_CTRL_MDIO)
724 e1000_lower_mdi_clk_82543(hw, &ctrl);
727 e1000_raise_mdi_clk_82543(hw, &ctrl);
728 e1000_lower_mdi_clk_82543(hw, &ctrl);
734 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
735 * @hw: pointer to the HW structure
737 * Calls the function to force speed and duplex for the m88 PHY, and
738 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
739 * then call the function for polarity reversal workaround.
741 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
745 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
747 ret_val = e1000_phy_force_speed_duplex_m88(hw);
751 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
753 ret_val = e1000_polarity_reversal_workaround_82543(hw);
760 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
761 * @hw: pointer to the HW structure
763 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
764 * inadvertently. To workaround the issue, we disable the transmitter on
765 * the PHY until we have established the link partner's link parameters.
767 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
769 s32 ret_val = E1000_SUCCESS;
774 if (!(hw->phy.ops.write_reg))
777 /* Polarity reversal workaround for forced 10F/10H links. */
779 /* Disable the transmitter on the PHY */
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
793 * This loop will early-out if the NO link condition has been met.
794 * In other words, DO NOT use e1000_phy_has_link_generic() here.
796 for (i = PHY_FORCE_TIME; i > 0; i--) {
798 * Read the MII Status Register and wait for Link Status bit
802 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
806 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
810 if (!(mii_status_reg & ~MII_SR_LINK_STATUS))
815 /* Recommended delay time after link has been lost */
816 msec_delay_irq(1000);
818 /* Now we will re-enable the transmitter on the PHY */
820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
841 * Read the MII Status Register and wait for Link Status bit
844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
853 * e1000_phy_hw_reset_82543 - PHY hardware reset
854 * @hw: pointer to the HW structure
856 * Sets the PHY_RESET_DIR bit in the extended device control register
857 * to put the PHY into a reset and waits for completion. Once the reset
858 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
861 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
866 DEBUGFUNC("e1000_phy_hw_reset_82543");
869 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
870 * bit to put the PHY into reset...
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
873 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
874 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
880 /* ...then take it out of reset. */
881 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
883 E1000_WRITE_FLUSH(hw);
887 if (!(hw->phy.ops.get_cfg_done))
888 return E1000_SUCCESS;
890 ret_val = hw->phy.ops.get_cfg_done(hw);
896 * e1000_reset_hw_82543 - Reset hardware
897 * @hw: pointer to the HW structure
899 * This resets the hardware into a known state.
901 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
904 s32 ret_val = E1000_SUCCESS;
906 DEBUGFUNC("e1000_reset_hw_82543");
908 DEBUGOUT("Masking off all interrupts\n");
909 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911 E1000_WRITE_REG(hw, E1000_RCTL, 0);
912 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
913 E1000_WRITE_FLUSH(hw);
915 e1000_set_tbi_sbp_82543(hw, FALSE);
918 * Delay to allow any outstanding PCI transactions to complete before
919 * resetting the device
923 ctrl = E1000_READ_REG(hw, E1000_CTRL);
925 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
926 if (hw->mac.type == e1000_82543) {
927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
930 * The 82544 can't ACK the 64-bit write when issuing the
931 * reset, so use IO-mapping as a workaround.
933 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
937 * After MAC reset, force reload of NVM to restore power-on
938 * settings to device.
940 hw->nvm.ops.reload(hw);
943 /* Masking off and clearing any pending interrupts */
944 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
945 E1000_READ_REG(hw, E1000_ICR);
951 * e1000_init_hw_82543 - Initialize hardware
952 * @hw: pointer to the HW structure
954 * This inits the hardware readying it for operation.
956 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
958 struct e1000_mac_info *mac = &hw->mac;
959 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
964 DEBUGFUNC("e1000_init_hw_82543");
966 /* Disabling VLAN filtering */
967 E1000_WRITE_REG(hw, E1000_VET, 0);
968 mac->ops.clear_vfta(hw);
970 /* Setup the receive address. */
971 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
973 /* Zero out the Multicast HASH table */
974 DEBUGOUT("Zeroing the MTA\n");
975 for (i = 0; i < mac->mta_reg_count; i++) {
976 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
977 E1000_WRITE_FLUSH(hw);
981 * Set the PCI priority bit correctly in the CTRL register. This
982 * determines if the adapter gives priority to receives, or if it
983 * gives equal priority to transmits and receives.
985 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
986 ctrl = E1000_READ_REG(hw, E1000_CTRL);
987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
990 e1000_pcix_mmrbc_workaround_generic(hw);
992 /* Setup link and flow control */
993 ret_val = mac->ops.setup_link(hw);
996 * Clear all of the statistics registers (clear on read). It is
997 * important that we do this after we have tried to establish link
998 * because the symbol error count will increment wildly if there
1001 e1000_clear_hw_cntrs_82543(hw);
1007 * e1000_setup_link_82543 - Setup flow control and link settings
1008 * @hw: pointer to the HW structure
1010 * Read the EEPROM to determine the initial polarity value and write the
1011 * extended device control register with the information before calling
1012 * the generic setup link function, which does the following:
1013 * Determines which flow control settings to use, then configures flow
1014 * control. Calls the appropriate media-specific link configuration
1015 * function. Assuming the adapter has a valid link partner, a valid link
1016 * should be established. Assumes the hardware has previously been reset
1017 * and the transmitter and receiver are not enabled.
1019 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1025 DEBUGFUNC("e1000_setup_link_82543");
1028 * Take the 4 bits from NVM word 0xF that determine the initial
1029 * polarity value for the SW controlled pins, and setup the
1030 * Extended Device Control reg with that info.
1031 * This is needed because one of the SW controlled pins is used for
1032 * signal detection. So this should be done before phy setup.
1034 if (hw->mac.type == e1000_82543) {
1035 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1037 DEBUGOUT("NVM Read Error\n");
1038 ret_val = -E1000_ERR_NVM;
1041 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1042 NVM_SWDPIO_EXT_SHIFT);
1043 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1046 ret_val = e1000_setup_link_generic(hw);
1053 * e1000_setup_copper_link_82543 - Configure copper link settings
1054 * @hw: pointer to the HW structure
1056 * Configures the link for auto-neg or forced speed and duplex. Then we check
1057 * for link, once link is established calls to configure collision distance
1058 * and flow control are called.
1060 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1066 DEBUGFUNC("e1000_setup_copper_link_82543");
1068 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1070 * With 82543, we need to force speed and duplex on the MAC
1071 * equal to what the PHY speed and duplex configuration is.
1072 * In addition, we need to perform a hardware reset on the
1073 * PHY to take it out of reset.
1075 if (hw->mac.type == e1000_82543) {
1076 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1078 ret_val = hw->phy.ops.reset(hw);
1082 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1083 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1086 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1087 ret_val = e1000_copper_link_setup_m88(hw);
1091 if (hw->mac.autoneg) {
1093 * Setup autoneg and flow control advertisement and perform
1096 ret_val = e1000_copper_link_autoneg(hw);
1101 * PHY will be set to 10H, 10F, 100H or 100F
1102 * depending on user settings.
1104 DEBUGOUT("Forcing Speed and Duplex\n");
1105 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1107 DEBUGOUT("Error Forcing Speed and Duplex\n");
1113 * Check link status. Wait up to 100 microseconds for link to become
1116 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1123 DEBUGOUT("Valid link established!!!\n");
1124 /* Config the MAC and PHY after link is up */
1125 if (hw->mac.type == e1000_82544) {
1126 hw->mac.ops.config_collision_dist(hw);
1128 ret_val = e1000_config_mac_to_phy_82543(hw);
1132 ret_val = e1000_config_fc_after_link_up_generic(hw);
1134 DEBUGOUT("Unable to establish link!!!\n");
1142 * e1000_setup_fiber_link_82543 - Setup link for fiber
1143 * @hw: pointer to the HW structure
1145 * Configures collision distance and flow control for fiber links. Upon
1146 * successful setup, poll for link.
1148 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1153 DEBUGFUNC("e1000_setup_fiber_link_82543");
1155 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1157 /* Take the link out of reset */
1158 ctrl &= ~E1000_CTRL_LRST;
1160 hw->mac.ops.config_collision_dist(hw);
1162 ret_val = e1000_commit_fc_settings_generic(hw);
1166 DEBUGOUT("Auto-negotiation enabled\n");
1168 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1169 E1000_WRITE_FLUSH(hw);
1173 * For these adapters, the SW definable pin 1 is cleared when the
1174 * optics detect a signal. If we have a signal, then poll for a
1175 * "Link-Up" indication.
1177 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
1178 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1180 DEBUGOUT("No signal detected\n");
1187 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1188 * @hw: pointer to the HW structure
1190 * Checks the phy for link, if link exists, do the following:
1191 * - check for downshift
1192 * - do polarity workaround (if necessary)
1193 * - configure collision distance
1194 * - configure flow control after link up
1195 * - configure tbi compatibility
1197 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1199 struct e1000_mac_info *mac = &hw->mac;
1205 DEBUGFUNC("e1000_check_for_copper_link_82543");
1207 if (!mac->get_link_status) {
1208 ret_val = E1000_SUCCESS;
1212 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1217 goto out; /* No link detected */
1219 mac->get_link_status = FALSE;
1221 e1000_check_downshift_generic(hw);
1224 * If we are forcing speed/duplex, then we can return since
1225 * we have already determined whether we have link or not.
1227 if (!mac->autoneg) {
1229 * If speed and duplex are forced to 10H or 10F, then we will
1230 * implement the polarity reversal workaround. We disable
1231 * interrupts first, and upon returning, place the devices
1232 * interrupt state to its previous value except for the link
1233 * status change interrupt which will happened due to the
1234 * execution of this workaround.
1236 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1237 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1238 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1239 icr = E1000_READ_REG(hw, E1000_ICR);
1240 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1241 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1244 ret_val = -E1000_ERR_CONFIG;
1249 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1250 * have Si on board that is 82544 or newer, Auto
1251 * Speed Detection takes care of MAC speed/duplex
1252 * configuration. So we only need to configure Collision
1253 * Distance in the MAC. Otherwise, we need to force
1254 * speed/duplex on the MAC to the current PHY speed/duplex
1257 if (mac->type == e1000_82544)
1258 hw->mac.ops.config_collision_dist(hw);
1260 ret_val = e1000_config_mac_to_phy_82543(hw);
1262 DEBUGOUT("Error configuring MAC to PHY settings\n");
1268 * Configure Flow Control now that Auto-Neg has completed.
1269 * First, we need to restore the desired flow control
1270 * settings because we may have had to re-autoneg with a
1271 * different link partner.
1273 ret_val = e1000_config_fc_after_link_up_generic(hw);
1275 DEBUGOUT("Error configuring flow control\n");
1278 * At this point we know that we are on copper and we have
1279 * auto-negotiated link. These are conditions for checking the link
1280 * partner capability register. We use the link speed to determine if
1281 * TBI compatibility needs to be turned on or off. If the link is not
1282 * at gigabit speed, then TBI compatibility is not needed. If we are
1283 * at gigabit speed, we turn on TBI compatibility.
1285 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1286 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1288 DEBUGOUT("Error getting link speed and duplex\n");
1291 if (speed != SPEED_1000) {
1293 * If link speed is not set to gigabit speed,
1294 * we do not need to enable TBI compatibility.
1296 if (e1000_tbi_sbp_enabled_82543(hw)) {
1298 * If we previously were in the mode,
1301 e1000_set_tbi_sbp_82543(hw, FALSE);
1302 rctl = E1000_READ_REG(hw, E1000_RCTL);
1303 rctl &= ~E1000_RCTL_SBP;
1304 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1308 * If TBI compatibility is was previously off,
1309 * turn it on. For compatibility with a TBI link
1310 * partner, we will store bad packets. Some
1311 * frames have an additional byte on the end and
1312 * will look like CRC errors to to the hardware.
1314 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1315 e1000_set_tbi_sbp_82543(hw, TRUE);
1316 rctl = E1000_READ_REG(hw, E1000_RCTL);
1317 rctl |= E1000_RCTL_SBP;
1318 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1327 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1328 * @hw: pointer to the HW structure
1330 * Checks for link up on the hardware. If link is not up and we have
1331 * a signal, then we need to force link up.
1333 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1335 struct e1000_mac_info *mac = &hw->mac;
1336 u32 rxcw, ctrl, status;
1337 s32 ret_val = E1000_SUCCESS;
1339 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1341 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1342 status = E1000_READ_REG(hw, E1000_STATUS);
1343 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1346 * If we don't have link (auto-negotiation failed or link partner
1347 * cannot auto-negotiate), the cable is plugged in (we have signal),
1348 * and our link partner is not trying to auto-negotiate with us (we
1349 * are receiving idles or data), we need to force link up. We also
1350 * need to give auto-negotiation time to complete, in case the cable
1351 * was just plugged in. The autoneg_failed flag does this.
1353 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1354 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1355 (!(status & E1000_STATUS_LU)) &&
1356 (!(rxcw & E1000_RXCW_C))) {
1357 if (!mac->autoneg_failed) {
1358 mac->autoneg_failed = TRUE;
1362 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1364 /* Disable auto-negotiation in the TXCW register */
1365 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1367 /* Force link-up and also force full-duplex. */
1368 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1369 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1370 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1372 /* Configure Flow Control after forcing link up. */
1373 ret_val = e1000_config_fc_after_link_up_generic(hw);
1375 DEBUGOUT("Error configuring flow control\n");
1378 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1380 * If we are forcing link and we are receiving /C/ ordered
1381 * sets, re-enable auto-negotiation in the TXCW register
1382 * and disable forced link in the Device Control register
1383 * in an attempt to auto-negotiate with our link partner.
1385 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1386 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1387 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1389 mac->serdes_has_link = TRUE;
1397 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1398 * @hw: pointer to the HW structure
1400 * For the 82543 silicon, we need to set the MAC to match the settings
1401 * of the PHY, even if the PHY is auto-negotiating.
1403 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1406 s32 ret_val = E1000_SUCCESS;
1409 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1411 if (!(hw->phy.ops.read_reg))
1414 /* Set the bits to force speed and duplex */
1415 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1416 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1417 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1420 * Set up duplex in the Device Control and Transmit Control
1421 * registers depending on negotiated values.
1423 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1427 ctrl &= ~E1000_CTRL_FD;
1428 if (phy_data & M88E1000_PSSR_DPLX)
1429 ctrl |= E1000_CTRL_FD;
1431 hw->mac.ops.config_collision_dist(hw);
1434 * Set up speed in the Device Control register depending on
1435 * negotiated values.
1437 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1438 ctrl |= E1000_CTRL_SPD_1000;
1439 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1440 ctrl |= E1000_CTRL_SPD_100;
1442 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1449 * e1000_write_vfta_82543 - Write value to VLAN filter table
1450 * @hw: pointer to the HW structure
1451 * @offset: the 32-bit offset in which to write the value to.
1452 * @value: the 32-bit value to write at location offset.
1454 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1457 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1461 DEBUGFUNC("e1000_write_vfta_82543");
1463 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1464 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1465 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1466 E1000_WRITE_FLUSH(hw);
1467 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1468 E1000_WRITE_FLUSH(hw);
1470 e1000_write_vfta_generic(hw, offset, value);
1475 * e1000_led_on_82543 - Turn on SW controllable LED
1476 * @hw: pointer to the HW structure
1478 * Turns the SW defined LED on.
1480 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1482 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1484 DEBUGFUNC("e1000_led_on_82543");
1486 if (hw->mac.type == e1000_82544 &&
1487 hw->phy.media_type == e1000_media_type_copper) {
1488 /* Clear SW-definable Pin 0 to turn on the LED */
1489 ctrl &= ~E1000_CTRL_SWDPIN0;
1490 ctrl |= E1000_CTRL_SWDPIO0;
1492 /* Fiber 82544 and all 82543 use this method */
1493 ctrl |= E1000_CTRL_SWDPIN0;
1494 ctrl |= E1000_CTRL_SWDPIO0;
1496 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1498 return E1000_SUCCESS;
1502 * e1000_led_off_82543 - Turn off SW controllable LED
1503 * @hw: pointer to the HW structure
1505 * Turns the SW defined LED off.
1507 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1509 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1511 DEBUGFUNC("e1000_led_off_82543");
1513 if (hw->mac.type == e1000_82544 &&
1514 hw->phy.media_type == e1000_media_type_copper) {
1515 /* Set SW-definable Pin 0 to turn off the LED */
1516 ctrl |= E1000_CTRL_SWDPIN0;
1517 ctrl |= E1000_CTRL_SWDPIO0;
1519 ctrl &= ~E1000_CTRL_SWDPIN0;
1520 ctrl |= E1000_CTRL_SWDPIO0;
1522 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1524 return E1000_SUCCESS;
1528 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1529 * @hw: pointer to the HW structure
1531 * Clears the hardware counters by reading the counter registers.
1533 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1535 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1537 e1000_clear_hw_cntrs_base_generic(hw);
1539 E1000_READ_REG(hw, E1000_PRC64);
1540 E1000_READ_REG(hw, E1000_PRC127);
1541 E1000_READ_REG(hw, E1000_PRC255);
1542 E1000_READ_REG(hw, E1000_PRC511);
1543 E1000_READ_REG(hw, E1000_PRC1023);
1544 E1000_READ_REG(hw, E1000_PRC1522);
1545 E1000_READ_REG(hw, E1000_PTC64);
1546 E1000_READ_REG(hw, E1000_PTC127);
1547 E1000_READ_REG(hw, E1000_PTC255);
1548 E1000_READ_REG(hw, E1000_PTC511);
1549 E1000_READ_REG(hw, E1000_PTC1023);
1550 E1000_READ_REG(hw, E1000_PTC1522);
1552 E1000_READ_REG(hw, E1000_ALGNERRC);
1553 E1000_READ_REG(hw, E1000_RXERRC);
1554 E1000_READ_REG(hw, E1000_TNCRS);
1555 E1000_READ_REG(hw, E1000_CEXTERR);
1556 E1000_READ_REG(hw, E1000_TSCTC);
1557 E1000_READ_REG(hw, E1000_TSCTFC);
1561 * e1000_read_mac_addr_82543 - Read device MAC address
1562 * @hw: pointer to the HW structure
1564 * Reads the device MAC address from the EEPROM and stores the value.
1565 * Since devices with two ports use the same EEPROM, we increment the
1566 * last bit in the MAC address for the second port.
1569 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1571 s32 ret_val = E1000_SUCCESS;
1572 u16 offset, nvm_data, i;
1574 DEBUGFUNC("e1000_read_mac_addr");
1576 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1578 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1580 DEBUGOUT("NVM Read Error\n");
1583 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1584 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1587 /* Flip last bit of mac address if we're on second port */
1588 if (hw->bus.func == E1000_FUNC_1)
1589 hw->mac.perm_addr[5] ^= 1;
1591 for (i = 0; i < ETH_ADDR_LEN; i++)
1592 hw->mac.addr[i] = hw->mac.perm_addr[i];