sys/dev/e1000/e1000_82571.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 /* 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  55 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  56 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  57                                   u16 words, u16 *data);
  58 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  59 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  60 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  61 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  62                                           bool active);
  63 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  64 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  65 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  66 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  67 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  68 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  69 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  70 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  71 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  73 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  74 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  75 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  76 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  77 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  78 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  79 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  81 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  82                                           bool active);
  83 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  84                                           bool active);
  85 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  86 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  87                                        u16 words, u16 *data);
  88 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  89 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  90
  91 /**
  92  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  96 {
  97         struct e1000_phy_info *phy = &hw->phy;
  98         s32 ret_val;
  99
 100         DEBUGFUNC("e1000_init_phy_params_82571");
 101
 102         if (hw->phy.media_type != e1000_media_type_copper) {
 103                 phy->type = e1000_phy_none;
 104                 return E1000_SUCCESS;
 105         }
 106
 107         phy->addr                       = 1;
 108         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 109         phy->reset_delay_us             = 100;
 110
 111         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
 112         phy->ops.reset                  = e1000_phy_hw_reset_generic;
 113         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
 114         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
 115         phy->ops.power_up               = e1000_power_up_phy_copper;
 116         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
 117
 118         switch (hw->mac.type) {
 119         case e1000_82571:
 120         case e1000_82572:
 121                 phy->type               = e1000_phy_igp_2;
 122                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
 123                 phy->ops.get_info       = e1000_get_phy_info_igp;
 124                 phy->ops.check_polarity = e1000_check_polarity_igp;
 125                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 126                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 127                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
 128                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
 129                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 130                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 131                 break;
 132         case e1000_82573:
 133                 phy->type               = e1000_phy_m88;
 134                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 135                 phy->ops.get_info       = e1000_get_phy_info_m88;
 136                 phy->ops.check_polarity = e1000_check_polarity_m88;
 137                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 138                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 139                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 140                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 141                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 142                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 143                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 144                 break;
 145         case e1000_82574:
 146         case e1000_82583:
 147                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 148
 149                 phy->type               = e1000_phy_bm;
 150                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 151                 phy->ops.get_info       = e1000_get_phy_info_m88;
 152                 phy->ops.check_polarity = e1000_check_polarity_m88;
 153                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 154                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 155                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 156                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 157                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 158                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 159                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 160                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 161                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 162                 break;
 163         default:
 164                 return -E1000_ERR_PHY;
 165                 break;
 166         }
 167
 168         /* This can only be done after all function pointers are setup. */
 169         ret_val = e1000_get_phy_id_82571(hw);
 170         if (ret_val) {
 171                 DEBUGOUT("Error getting PHY ID\n");
 172                 return ret_val;
 173         }
 174
 175         /* Verify phy id */
 176         switch (hw->mac.type) {
 177         case e1000_82571:
 178         case e1000_82572:
 179                 if (phy->id != IGP01E1000_I_PHY_ID)
 180                         ret_val = -E1000_ERR_PHY;
 181                 break;
 182         case e1000_82573:
 183                 if (phy->id != M88E1111_I_PHY_ID)
 184                         ret_val = -E1000_ERR_PHY;
 185                 break;
 186         case e1000_82574:
 187         case e1000_82583:
 188                 if (phy->id != BME1000_E_PHY_ID_R2)
 189                         ret_val = -E1000_ERR_PHY;
 190                 break;
 191         default:
 192                 ret_val = -E1000_ERR_PHY;
 193                 break;
 194         }
 195
 196         if (ret_val)
 197                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 198
 199         return ret_val;
 200 }
 201
 202 /**
 203  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 204  *  @hw: pointer to the HW structure
 205  **/
 206 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 207 {
 208         struct e1000_nvm_info *nvm = &hw->nvm;
 209         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 210         u16 size;
 211
 212         DEBUGFUNC("e1000_init_nvm_params_82571");
 213
 214         nvm->opcode_bits = 8;
 215         nvm->delay_usec = 1;
 216         switch (nvm->override) {
 217         case e1000_nvm_override_spi_large:
 218                 nvm->page_size = 32;
 219                 nvm->address_bits = 16;
 220                 break;
 221         case e1000_nvm_override_spi_small:
 222                 nvm->page_size = 8;
 223                 nvm->address_bits = 8;
 224                 break;
 225         default:
 226                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 227                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 228                 break;
 229         }
 230
 231         switch (hw->mac.type) {
 232         case e1000_82573:
 233         case e1000_82574:
 234         case e1000_82583:
 235                 if (((eecd >> 15) & 0x3) == 0x3) {
 236                         nvm->type = e1000_nvm_flash_hw;
 237                         nvm->word_size = 2048;
 238                         /* Autonomous Flash update bit must be cleared due
 239                          * to Flash update issue.
 240                          */
 241                         eecd &= ~E1000_EECD_AUPDEN;
 242                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 243                         break;
 244                 }
 245                 /* Fall Through */
 246         default:
 247                 nvm->type = e1000_nvm_eeprom_spi;
 248                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 249                              E1000_EECD_SIZE_EX_SHIFT);
 250                 /* Added to a constant, "size" becomes the left-shift value
 251                  * for setting word_size.
 252                  */
 253                 size += NVM_WORD_SIZE_BASE_SHIFT;
 254
 255                 /* EEPROM access above 16k is unsupported */
 256                 if (size > 14)
 257                         size = 14;
 258                 nvm->word_size = 1 << size;
 259                 break;
 260         }
 261
 262         /* Function Pointers */
 263         switch (hw->mac.type) {
 264         case e1000_82574:
 265         case e1000_82583:
 266                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 267                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 268                 break;
 269         default:
 270                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 271                 nvm->ops.release = e1000_release_nvm_82571;
 272                 break;
 273         }
 274         nvm->ops.read = e1000_read_nvm_eerd;
 275         nvm->ops.update = e1000_update_nvm_checksum_82571;
 276         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 277         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 278         nvm->ops.write = e1000_write_nvm_82571;
 279
 280         return E1000_SUCCESS;
 281 }
 282
 283 /**
 284  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 285  *  @hw: pointer to the HW structure
 286  **/
 287 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 288 {
 289         struct e1000_mac_info *mac = &hw->mac;
 290         u32 swsm = 0;
 291         u32 swsm2 = 0;
 292         bool force_clear_smbi = FALSE;
 293
 294         DEBUGFUNC("e1000_init_mac_params_82571");
 295
 296         /* Set media type and media-dependent function pointers */
 297         switch (hw->device_id) {
 298         case E1000_DEV_ID_82571EB_FIBER:
 299         case E1000_DEV_ID_82572EI_FIBER:
 300         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 301                 hw->phy.media_type = e1000_media_type_fiber;
 302                 mac->ops.setup_physical_interface =
 303                         e1000_setup_fiber_serdes_link_82571;
 304                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 305                 mac->ops.get_link_up_info =
 306                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 307                 break;
 308         case E1000_DEV_ID_82571EB_SERDES:
 309         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 310         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 311         case E1000_DEV_ID_82572EI_SERDES:
 312                 hw->phy.media_type = e1000_media_type_internal_serdes;
 313                 mac->ops.setup_physical_interface =
 314                         e1000_setup_fiber_serdes_link_82571;
 315                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 316                 mac->ops.get_link_up_info =
 317                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 318                 break;
 319         default:
 320                 hw->phy.media_type = e1000_media_type_copper;
 321                 mac->ops.setup_physical_interface =
 322                         e1000_setup_copper_link_82571;
 323                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 324                 mac->ops.get_link_up_info =
 325                         e1000_get_speed_and_duplex_copper_generic;
 326                 break;
 327         }
 328
 329         /* Set mta register count */
 330         mac->mta_reg_count = 128;
 331         /* Set rar entry count */
 332         mac->rar_entry_count = E1000_RAR_ENTRIES;
 333         /* Set if part includes ASF firmware */
 334         mac->asf_firmware_present = TRUE;
 335         /* Adaptive IFS supported */
 336         mac->adaptive_ifs = TRUE;
 337
 338         /* Function pointers */
 339
 340         /* bus type/speed/width */
 341         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 342         /* reset */
 343         mac->ops.reset_hw = e1000_reset_hw_82571;
 344         /* hw initialization */
 345         mac->ops.init_hw = e1000_init_hw_82571;
 346         /* link setup */
 347         mac->ops.setup_link = e1000_setup_link_82571;
 348         /* multicast address update */
 349         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 350         /* writing VFTA */
 351         mac->ops.write_vfta = e1000_write_vfta_generic;
 352         /* clearing VFTA */
 353         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 354         /* read mac address */
 355         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 356         /* ID LED init */
 357         mac->ops.id_led_init = e1000_id_led_init_generic;
 358         /* setup LED */
 359         mac->ops.setup_led = e1000_setup_led_generic;
 360         /* cleanup LED */
 361         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 362         /* turn off LED */
 363         mac->ops.led_off = e1000_led_off_generic;
 364         /* clear hardware counters */
 365         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 366
 367         /* MAC-specific function pointers */
 368         switch (hw->mac.type) {
 369         case e1000_82573:
 370                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 371                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 372                 mac->ops.led_on = e1000_led_on_generic;
 373                 mac->ops.blink_led = e1000_blink_led_generic;
 374
 375                 /* FWSM register */
 376                 mac->has_fwsm = TRUE;
 377                 /* ARC supported; valid only if manageability features are
 378                  * enabled.
 379                  */
 380                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 381                                               E1000_FWSM_MODE_MASK);
 382                 break;
 383         case e1000_82574:
 384         case e1000_82583:
 385                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 386                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 387                 mac->ops.led_on = e1000_led_on_82574;
 388                 break;
 389         default:
 390                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 391                 mac->ops.led_on = e1000_led_on_generic;
 392                 mac->ops.blink_led = e1000_blink_led_generic;
 393
 394                 /* FWSM register */
 395                 mac->has_fwsm = TRUE;
 396                 break;
 397         }
 398
 399         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 400          * first NVM or PHY access. This should be done for single-port
 401          * devices, and for one port only on dual-port devices so that
 402          * for those devices we can still use the SMBI lock to synchronize
 403          * inter-port accesses to the PHY & NVM.
 404          */
 405         switch (hw->mac.type) {
 406         case e1000_82571:
 407         case e1000_82572:
 408                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 409
 410                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 411                         /* Only do this for the first interface on this card */
 412                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 413                                         E1000_SWSM2_LOCK);
 414                         force_clear_smbi = TRUE;
 415                 } else {
 416                         force_clear_smbi = FALSE;
 417                 }
 418                 break;
 419         default:
 420                 force_clear_smbi = TRUE;
 421                 break;
 422         }
 423
 424         if (force_clear_smbi) {
 425                 /* Make sure SWSM.SMBI is clear */
 426                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 427                 if (swsm & E1000_SWSM_SMBI) {
 428                         /* This bit should not be set on a first interface, and
 429                          * indicates that the bootagent or EFI code has
 430                          * improperly left this bit enabled
 431                          */
 432                         DEBUGOUT("Please update your 82571 Bootagent\n");
 433                 }
 434                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 435         }
 436
 437         /* Initialze device specific counter of SMBI acquisition timeouts. */
 438          hw->dev_spec._82571.smb_counter = 0;
 439
 440         return E1000_SUCCESS;
 441 }
 442
 443 /**
 444  *  e1000_init_function_pointers_82571 - Init func ptrs.
 445  *  @hw: pointer to the HW structure
 446  *
 447  *  Called to initialize all function pointers and parameters.
 448  **/
 449 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 450 {
 451         DEBUGFUNC("e1000_init_function_pointers_82571");
 452
 453         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 454         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 455         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 456 }
 457
 458 /**
 459  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 460  *  @hw: pointer to the HW structure
 461  *
 462  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 463  *  revision in the hardware structure.
 464  **/
 465 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 466 {
 467         struct e1000_phy_info *phy = &hw->phy;
 468         s32 ret_val;
 469         u16 phy_id = 0;
 470
 471         DEBUGFUNC("e1000_get_phy_id_82571");
 472
 473         switch (hw->mac.type) {
 474         case e1000_82571:
 475         case e1000_82572:
 476                 /* The 82571 firmware may still be configuring the PHY.
 477                  * In this case, we cannot access the PHY until the
 478                  * configuration is done.  So we explicitly set the
 479                  * PHY ID.
 480                  */
 481                 phy->id = IGP01E1000_I_PHY_ID;
 482                 break;
 483         case e1000_82573:
 484                 return e1000_get_phy_id(hw);
 485                 break;
 486         case e1000_82574:
 487         case e1000_82583:
 488                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 489                 if (ret_val)
 490                         return ret_val;
 491
 492                 phy->id = (u32)(phy_id << 16);
 493                 usec_delay(20);
 494                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 495                 if (ret_val)
 496                         return ret_val;
 497
 498                 phy->id |= (u32)(phy_id);
 499                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 500                 break;
 501         default:
 502                 return -E1000_ERR_PHY;
 503                 break;
 504         }
 505
 506         return E1000_SUCCESS;
 507 }
 508
 509 /**
 510  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 511  *  @hw: pointer to the HW structure
 512  *
 513  *  Acquire the HW semaphore to access the PHY or NVM
 514  **/
 515 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 516 {
 517         u32 swsm;
 518         s32 sw_timeout = hw->nvm.word_size + 1;
 519         s32 fw_timeout = hw->nvm.word_size + 1;
 520         s32 i = 0;
 521
 522         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 523
 524         /* If we have timedout 3 times on trying to acquire
 525          * the inter-port SMBI semaphore, there is old code
 526          * operating on the other port, and it is not
 527          * releasing SMBI. Modify the number of times that
 528          * we try for the semaphore to interwork with this
 529          * older code.
 530          */
 531         if (hw->dev_spec._82571.smb_counter > 2)
 532                 sw_timeout = 1;
 533
 534         /* Get the SW semaphore */
 535         while (i < sw_timeout) {
 536                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 537                 if (!(swsm & E1000_SWSM_SMBI))
 538                         break;
 539
 540                 usec_delay(50);
 541                 i++;
 542         }
 543
 544         if (i == sw_timeout) {
 545                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 546                 hw->dev_spec._82571.smb_counter++;
 547         }
 548         /* Get the FW semaphore. */
 549         for (i = 0; i < fw_timeout; i++) {
 550                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 551                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 552
 553                 /* Semaphore acquired if bit latched */
 554                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 555                         break;
 556
 557                 usec_delay(50);
 558         }
 559
 560         if (i == fw_timeout) {
 561                 /* Release semaphores */
 562                 e1000_put_hw_semaphore_82571(hw);
 563                 DEBUGOUT("Driver can't access the NVM\n");
 564                 return -E1000_ERR_NVM;
 565         }
 566
 567         return E1000_SUCCESS;
 568 }
 569
 570 /**
 571  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 572  *  @hw: pointer to the HW structure
 573  *
 574  *  Release hardware semaphore used to access the PHY or NVM
 575  **/
 576 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 577 {
 578         u32 swsm;
 579
 580         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 581
 582         swsm = E1000_READ_REG(hw, E1000_SWSM);
 583
 584         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 585
 586         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 587 }
 588
 589 /**
 590  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 591  *  @hw: pointer to the HW structure
 592  *
 593  *  Acquire the HW semaphore during reset.
 594  *
 595  **/
 596 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 597 {
 598         u32 extcnf_ctrl;
 599         s32 i = 0;
 600
 601         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 602
 603         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 604         do {
 605                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 606                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 607                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 608
 609                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 610                         break;
 611
 612                 msec_delay(2);
 613                 i++;
 614         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 615
 616         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 617                 /* Release semaphores */
 618                 e1000_put_hw_semaphore_82573(hw);
 619                 DEBUGOUT("Driver can't access the PHY\n");
 620                 return -E1000_ERR_PHY;
 621         }
 622
 623         return E1000_SUCCESS;
 624 }
 625
 626 /**
 627  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 628  *  @hw: pointer to the HW structure
 629  *
 630  *  Release hardware semaphore used during reset.
 631  *
 632  **/
 633 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 634 {
 635         u32 extcnf_ctrl;
 636
 637         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 638
 639         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 640         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 641         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 642 }
 643
 644 /**
 645  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 646  *  @hw: pointer to the HW structure
 647  *
 648  *  Acquire the HW semaphore to access the PHY or NVM.
 649  *
 650  **/
 651 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 652 {
 653         s32 ret_val;
 654
 655         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 656
 657         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 658         ret_val = e1000_get_hw_semaphore_82573(hw);
 659         if (ret_val)
 660                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 661         return ret_val;
 662 }
 663
 664 /**
 665  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 666  *  @hw: pointer to the HW structure
 667  *
 668  *  Release hardware semaphore used to access the PHY or NVM
 669  *
 670  **/
 671 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 672 {
 673         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 674
 675         e1000_put_hw_semaphore_82573(hw);
 676         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 677 }
 678
 679 /**
 680  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 681  *  @hw: pointer to the HW structure
 682  *  @active: TRUE to enable LPLU, FALSE to disable
 683  *
 684  *  Sets the LPLU D0 state according to the active flag.
 685  *  LPLU will not be activated unless the
 686  *  device autonegotiation advertisement meets standards of
 687  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 688  *  This is a function pointer entry point only called by
 689  *  PHY setup routines.
 690  **/
 691 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 692 {
 693         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 694
 695         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 696
 697         if (active)
 698                 data |= E1000_PHY_CTRL_D0A_LPLU;
 699         else
 700                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 701
 702         E1000_WRITE_REG(hw, E1000_POEMB, data);
 703         return E1000_SUCCESS;
 704 }
 705
 706 /**
 707  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 708  *  @hw: pointer to the HW structure
 709  *  @active: boolean used to enable/disable lplu
 710  *
 711  *  The low power link up (lplu) state is set to the power management level D3
 712  *  when active is TRUE, else clear lplu for D3. LPLU
 713  *  is used during Dx states where the power conservation is most important.
 714  *  During driver activity, SmartSpeed should be enabled so performance is
 715  *  maintained.
 716  **/
 717 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 718 {
 719         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 720
 721         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 722
 723         if (!active) {
 724                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 725         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 726                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 727                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 728                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 729         }
 730
 731         E1000_WRITE_REG(hw, E1000_POEMB, data);
 732         return E1000_SUCCESS;
 733 }
 734
 735 /**
 736  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 737  *  @hw: pointer to the HW structure
 738  *
 739  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 740  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 741  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 742  *  hardware semaphore.
 743  **/
 744 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 745 {
 746         s32 ret_val;
 747
 748         DEBUGFUNC("e1000_acquire_nvm_82571");
 749
 750         ret_val = e1000_get_hw_semaphore_82571(hw);
 751         if (ret_val)
 752                 return ret_val;
 753
 754         switch (hw->mac.type) {
 755         case e1000_82573:
 756                 break;
 757         default:
 758                 ret_val = e1000_acquire_nvm_generic(hw);
 759                 break;
 760         }
 761
 762         if (ret_val)
 763                 e1000_put_hw_semaphore_82571(hw);
 764
 765         return ret_val;
 766 }
 767
 768 /**
 769  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 770  *  @hw: pointer to the HW structure
 771  *
 772  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 773  **/
 774 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 775 {
 776         DEBUGFUNC("e1000_release_nvm_82571");
 777
 778         e1000_release_nvm_generic(hw);
 779         e1000_put_hw_semaphore_82571(hw);
 780 }
 781
 782 /**
 783  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 784  *  @hw: pointer to the HW structure
 785  *  @offset: offset within the EEPROM to be written to
 786  *  @words: number of words to write
 787  *  @data: 16 bit word(s) to be written to the EEPROM
 788  *
 789  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 790  *
 791  *  If e1000_update_nvm_checksum is not called after this function, the
 792  *  EEPROM will most likely contain an invalid checksum.
 793  **/
 794 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 795                                  u16 *data)
 796 {
 797         s32 ret_val;
 798
 799         DEBUGFUNC("e1000_write_nvm_82571");
 800
 801         switch (hw->mac.type) {
 802         case e1000_82573:
 803         case e1000_82574:
 804         case e1000_82583:
 805                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 806                 break;
 807         case e1000_82571:
 808         case e1000_82572:
 809                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 810                 break;
 811         default:
 812                 ret_val = -E1000_ERR_NVM;
 813                 break;
 814         }
 815
 816         return ret_val;
 817 }
 818
 819 /**
 820  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 821  *  @hw: pointer to the HW structure
 822  *
 823  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 824  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 825  *  value to the EEPROM.
 826  **/
 827 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 828 {
 829         u32 eecd;
 830         s32 ret_val;
 831         u16 i;
 832
 833         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 834
 835         ret_val = e1000_update_nvm_checksum_generic(hw);
 836         if (ret_val)
 837                 return ret_val;
 838
 839         /* If our nvm is an EEPROM, then we're done
 840          * otherwise, commit the checksum to the flash NVM.
 841          */
 842         if (hw->nvm.type != e1000_nvm_flash_hw)
 843                 return E1000_SUCCESS;
 844
 845         /* Check for pending operations. */
 846         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 847                 msec_delay(1);
 848                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 849                         break;
 850         }
 851
 852         if (i == E1000_FLASH_UPDATES)
 853                 return -E1000_ERR_NVM;
 854
 855         /* Reset the firmware if using STM opcode. */
 856         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 857                 /* The enabling of and the actual reset must be done
 858                  * in two write cycles.
 859                  */
 860                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 861                 E1000_WRITE_FLUSH(hw);
 862                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 863         }
 864
 865         /* Commit the write to flash */
 866         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 867         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 868
 869         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 870                 msec_delay(1);
 871                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 872                         break;
 873         }
 874
 875         if (i == E1000_FLASH_UPDATES)
 876                 return -E1000_ERR_NVM;
 877
 878         return E1000_SUCCESS;
 879 }
 880
 881 /**
 882  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 883  *  @hw: pointer to the HW structure
 884  *
 885  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 886  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 887  **/
 888 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 889 {
 890         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 891
 892         if (hw->nvm.type == e1000_nvm_flash_hw)
 893                 e1000_fix_nvm_checksum_82571(hw);
 894
 895         return e1000_validate_nvm_checksum_generic(hw);
 896 }
 897
 898 /**
 899  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 900  *  @hw: pointer to the HW structure
 901  *  @offset: offset within the EEPROM to be written to
 902  *  @words: number of words to write
 903  *  @data: 16 bit word(s) to be written to the EEPROM
 904  *
 905  *  After checking for invalid values, poll the EEPROM to ensure the previous
 906  *  command has completed before trying to write the next word.  After write
 907  *  poll for completion.
 908  *
 909  *  If e1000_update_nvm_checksum is not called after this function, the
 910  *  EEPROM will most likely contain an invalid checksum.
 911  **/
 912 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 913                                       u16 words, u16 *data)
 914 {
 915         struct e1000_nvm_info *nvm = &hw->nvm;
 916         u32 i, eewr = 0;
 917         s32 ret_val = E1000_SUCCESS;
 918
 919         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 920
 921         /* A check for invalid values:  offset too large, too many words,
 922          * and not enough words.
 923          */
 924         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 925             (words == 0)) {
 926                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 927                 return -E1000_ERR_NVM;
 928         }
 929
 930         for (i = 0; i < words; i++) {
 931                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 932                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 933                         E1000_NVM_RW_REG_START);
 934
 935                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 936                 if (ret_val)
 937                         break;
 938
 939                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 940
 941                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 942                 if (ret_val)
 943                         break;
 944         }
 945
 946         return ret_val;
 947 }
 948
 949 /**
 950  *  e1000_get_cfg_done_82571 - Poll for configuration done
 951  *  @hw: pointer to the HW structure
 952  *
 953  *  Reads the management control register for the config done bit to be set.
 954  **/
 955 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 956 {
 957         s32 timeout = PHY_CFG_TIMEOUT;
 958
 959         DEBUGFUNC("e1000_get_cfg_done_82571");
 960
 961         while (timeout) {
 962                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 963                     E1000_NVM_CFG_DONE_PORT_0)
 964                         break;
 965                 msec_delay(1);
 966                 timeout--;
 967         }
 968         if (!timeout) {
 969                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 970                 return -E1000_ERR_RESET;
 971         }
 972
 973         return E1000_SUCCESS;
 974 }
 975
 976 /**
 977  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 978  *  @hw: pointer to the HW structure
 979  *  @active: TRUE to enable LPLU, FALSE to disable
 980  *
 981  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 982  *  this function also disables smart speed and vice versa.  LPLU will not be
 983  *  activated unless the device autonegotiation advertisement meets standards
 984  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 985  *  pointer entry point only called by PHY setup routines.
 986  **/
 987 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 988 {
 989         struct e1000_phy_info *phy = &hw->phy;
 990         s32 ret_val;
 991         u16 data;
 992
 993         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 994
 995         if (!(phy->ops.read_reg))
 996                 return E1000_SUCCESS;
 997
 998         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 999         if (ret_val)
1000                 return ret_val;
1001
1002         if (active) {
1003                 data |= IGP02E1000_PM_D0_LPLU;
1004                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1005                                              data);
1006                 if (ret_val)
1007                         return ret_val;
1008
1009                 /* When LPLU is enabled, we should disable SmartSpeed */
1010                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1011                                             &data);
1012                 if (ret_val)
1013                         return ret_val;
1014                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1015                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1016                                              data);
1017                 if (ret_val)
1018                         return ret_val;
1019         } else {
1020                 data &= ~IGP02E1000_PM_D0_LPLU;
1021                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1022                                              data);
1023                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1024                  * during Dx states where the power conservation is most
1025                  * important.  During driver activity we should enable
1026                  * SmartSpeed, so performance is maintained.
1027                  */
1028                 if (phy->smart_speed == e1000_smart_speed_on) {
1029                         ret_val = phy->ops.read_reg(hw,
1030                                                     IGP01E1000_PHY_PORT_CONFIG,
1031                                                     &data);
1032                         if (ret_val)
1033                                 return ret_val;
1034
1035                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1036                         ret_val = phy->ops.write_reg(hw,
1037                                                      IGP01E1000_PHY_PORT_CONFIG,
1038                                                      data);
1039                         if (ret_val)
1040                                 return ret_val;
1041                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1042                         ret_val = phy->ops.read_reg(hw,
1043                                                     IGP01E1000_PHY_PORT_CONFIG,
1044                                                     &data);
1045                         if (ret_val)
1046                                 return ret_val;
1047
1048                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1049                         ret_val = phy->ops.write_reg(hw,
1050                                                      IGP01E1000_PHY_PORT_CONFIG,
1051                                                      data);
1052                         if (ret_val)
1053                                 return ret_val;
1054                 }
1055         }
1056
1057         return E1000_SUCCESS;
1058 }
1059
1060 /**
1061  *  e1000_reset_hw_82571 - Reset hardware
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  This resets the hardware into a known state.
1065  **/
1066 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1067 {
1068         u32 ctrl, ctrl_ext, eecd, tctl;
1069         s32 ret_val;
1070
1071         DEBUGFUNC("e1000_reset_hw_82571");
1072
1073         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1074          * on the last TLP read/write transaction when MAC is reset.
1075          */
1076         ret_val = e1000_disable_pcie_master_generic(hw);
1077         if (ret_val)
1078                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1079
1080         DEBUGOUT("Masking off all interrupts\n");
1081         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1082
1083         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1084         tctl = E1000_READ_REG(hw, E1000_TCTL);
1085         tctl &= ~E1000_TCTL_EN;
1086         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1087         E1000_WRITE_FLUSH(hw);
1088
1089         msec_delay(10);
1090
1091         /* Must acquire the MDIO ownership before MAC reset.
1092          * Ownership defaults to firmware after a reset.
1093          */
1094         switch (hw->mac.type) {
1095         case e1000_82573:
1096                 ret_val = e1000_get_hw_semaphore_82573(hw);
1097                 break;
1098         case e1000_82574:
1099         case e1000_82583:
1100                 ret_val = e1000_get_hw_semaphore_82574(hw);
1101                 break;
1102         default:
1103                 break;
1104         }
1105
1106         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1107
1108         DEBUGOUT("Issuing a global reset to MAC\n");
1109         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1110
1111         /* Must release MDIO ownership and mutex after MAC reset. */
1112         switch (hw->mac.type) {
1113         case e1000_82573:
1114                 /* Release mutex only if the hw semaphore is acquired */
1115                 if (!ret_val)
1116                         e1000_put_hw_semaphore_82573(hw);
1117                 break;
1118         case e1000_82574:
1119         case e1000_82583:
1120                 /* Release mutex only if the hw semaphore is acquired */
1121                 if (!ret_val)
1122                         e1000_put_hw_semaphore_82574(hw);
1123                 break;
1124         default:
1125                 break;
1126         }
1127
1128         if (hw->nvm.type == e1000_nvm_flash_hw) {
1129                 usec_delay(10);
1130                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1131                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1132                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1133                 E1000_WRITE_FLUSH(hw);
1134         }
1135
1136         ret_val = e1000_get_auto_rd_done_generic(hw);
1137         if (ret_val)
1138                 /* We don't want to continue accessing MAC registers. */
1139                 return ret_val;
1140
1141         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1142          * Need to wait for Phy configuration completion before accessing
1143          * NVM and Phy.
1144          */
1145
1146         switch (hw->mac.type) {
1147         case e1000_82571:
1148         case e1000_82572:
1149                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1150                  * to access the EEPROM.
1151                  */
1152                 eecd = E1000_READ_REG(hw, E1000_EECD);
1153                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1154                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1155                 break;
1156         case e1000_82573:
1157         case e1000_82574:
1158         case e1000_82583:
1159                 msec_delay(25);
1160                 break;
1161         default:
1162                 break;
1163         }
1164
1165         /* Clear any pending interrupt events. */
1166         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1167         E1000_READ_REG(hw, E1000_ICR);
1168
1169         if (hw->mac.type == e1000_82571) {
1170                 /* Install any alternate MAC address into RAR0 */
1171                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1172                 if (ret_val)
1173                         return ret_val;
1174
1175                 e1000_set_laa_state_82571(hw, TRUE);
1176         }
1177
1178         /* Reinitialize the 82571 serdes link state machine */
1179         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1180                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1181
1182         return E1000_SUCCESS;
1183 }
1184
1185 /**
1186  *  e1000_init_hw_82571 - Initialize hardware
1187  *  @hw: pointer to the HW structure
1188  *
1189  *  This inits the hardware readying it for operation.
1190  **/
1191 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1192 {
1193         struct e1000_mac_info *mac = &hw->mac;
1194         u32 reg_data;
1195         s32 ret_val;
1196         u16 i, rar_count = mac->rar_entry_count;
1197
1198         DEBUGFUNC("e1000_init_hw_82571");
1199
1200         e1000_initialize_hw_bits_82571(hw);
1201
1202         /* Initialize identification LED */
1203         ret_val = mac->ops.id_led_init(hw);
1204         /* An error is not fatal and we should not stop init due to this */
1205         if (ret_val)
1206                 DEBUGOUT("Error initializing identification LED\n");
1207
1208         /* Disabling VLAN filtering */
1209         DEBUGOUT("Initializing the IEEE VLAN\n");
1210         mac->ops.clear_vfta(hw);
1211
1212         /* Setup the receive address.
1213          * If, however, a locally administered address was assigned to the
1214          * 82571, we must reserve a RAR for it to work around an issue where
1215          * resetting one port will reload the MAC on the other port.
1216          */
1217         if (e1000_get_laa_state_82571(hw))
1218                 rar_count--;
1219         e1000_init_rx_addrs_generic(hw, rar_count);
1220
1221         /* Zero out the Multicast HASH table */
1222         DEBUGOUT("Zeroing the MTA\n");
1223         for (i = 0; i < mac->mta_reg_count; i++)
1224                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1225
1226         /* Setup link and flow control */
1227         ret_val = mac->ops.setup_link(hw);
1228
1229         /* Set the transmit descriptor write-back policy */
1230         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1231         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1232                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1233         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1234
1235         /* ...for both queues. */
1236         switch (mac->type) {
1237         case e1000_82573:
1238                 e1000_enable_tx_pkt_filtering_generic(hw);
1239                 /* fall through */
1240         case e1000_82574:
1241         case e1000_82583:
1242                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1243                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1244                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1245                 break;
1246         default:
1247                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1248                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1249                             E1000_TXDCTL_FULL_TX_DESC_WB |
1250                             E1000_TXDCTL_COUNT_DESC);
1251                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1252                 break;
1253         }
1254
1255         /* Clear all of the statistics registers (clear on read).  It is
1256          * important that we do this after we have tried to establish link
1257          * because the symbol error count will increment wildly if there
1258          * is no link.
1259          */
1260         e1000_clear_hw_cntrs_82571(hw);
1261
1262         return ret_val;
1263 }
1264
1265 /**
1266  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1267  *  @hw: pointer to the HW structure
1268  *
1269  *  Initializes required hardware-dependent bits needed for normal operation.
1270  **/
1271 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1272 {
1273         u32 reg;
1274
1275         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1276
1277         /* Transmit Descriptor Control 0 */
1278         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1279         reg |= (1 << 22);
1280         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1281
1282         /* Transmit Descriptor Control 1 */
1283         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1284         reg |= (1 << 22);
1285         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1286
1287         /* Transmit Arbitration Control 0 */
1288         reg = E1000_READ_REG(hw, E1000_TARC(0));
1289         reg &= ~(0xF << 27); /* 30:27 */
1290         switch (hw->mac.type) {
1291         case e1000_82571:
1292         case e1000_82572:
1293                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1294                 break;
1295         case e1000_82574:
1296         case e1000_82583:
1297                 reg |= (1 << 26);
1298                 break;
1299         default:
1300                 break;
1301         }
1302         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1303
1304         /* Transmit Arbitration Control 1 */
1305         reg = E1000_READ_REG(hw, E1000_TARC(1));
1306         switch (hw->mac.type) {
1307         case e1000_82571:
1308         case e1000_82572:
1309                 reg &= ~((1 << 29) | (1 << 30));
1310                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1311                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1312                         reg &= ~(1 << 28);
1313                 else
1314                         reg |= (1 << 28);
1315                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1316                 break;
1317         default:
1318                 break;
1319         }
1320
1321         /* Device Control */
1322         switch (hw->mac.type) {
1323         case e1000_82573:
1324         case e1000_82574:
1325         case e1000_82583:
1326                 reg = E1000_READ_REG(hw, E1000_CTRL);
1327                 reg &= ~(1 << 29);
1328                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1329                 break;
1330         default:
1331                 break;
1332         }
1333
1334         /* Extended Device Control */
1335         switch (hw->mac.type) {
1336         case e1000_82573:
1337         case e1000_82574:
1338         case e1000_82583:
1339                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1340                 reg &= ~(1 << 23);
1341                 reg |= (1 << 22);
1342                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1343                 break;
1344         default:
1345                 break;
1346         }
1347
1348         if (hw->mac.type == e1000_82571) {
1349                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1350                 reg |= E1000_PBA_ECC_CORR_EN;
1351                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1352         }
1353
1354         /* Workaround for hardware errata.
1355          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1356          */
1357         if ((hw->mac.type == e1000_82571) ||
1358            (hw->mac.type == e1000_82572)) {
1359                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1360                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1361                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1362         }
1363
1364         /* Disable IPv6 extension header parsing because some malformed
1365          * IPv6 headers can hang the Rx.
1366          */
1367         if (hw->mac.type <= e1000_82573) {
1368                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1369                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1370                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1371         }
1372
1373         /* PCI-Ex Control Registers */
1374         switch (hw->mac.type) {
1375         case e1000_82574:
1376         case e1000_82583:
1377                 reg = E1000_READ_REG(hw, E1000_GCR);
1378                 reg |= (1 << 22);
1379                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1380
1381                 /* Workaround for hardware errata.
1382                  * apply workaround for hardware errata documented in errata
1383                  * docs Fixes issue where some error prone or unreliable PCIe
1384                  * completions are occurring, particularly with ASPM enabled.
1385                  * Without fix, issue can cause Tx timeouts.
1386                  */
1387                 reg = E1000_READ_REG(hw, E1000_GCR2);
1388                 reg |= 1;
1389                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1390                 break;
1391         default:
1392                 break;
1393         }
1394
1395         return;
1396 }
1397
1398 /**
1399  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1400  *  @hw: pointer to the HW structure
1401  *
1402  *  Clears the register array which contains the VLAN filter table by
1403  *  setting all the values to 0.
1404  **/
1405 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1406 {
1407         u32 offset;
1408         u32 vfta_value = 0;
1409         u32 vfta_offset = 0;
1410         u32 vfta_bit_in_reg = 0;
1411
1412         DEBUGFUNC("e1000_clear_vfta_82571");
1413
1414         switch (hw->mac.type) {
1415         case e1000_82573:
1416         case e1000_82574:
1417         case e1000_82583:
1418                 if (hw->mng_cookie.vlan_id != 0) {
1419                         /* The VFTA is a 4096b bit-field, each identifying
1420                          * a single VLAN ID.  The following operations
1421                          * determine which 32b entry (i.e. offset) into the
1422                          * array we want to set the VLAN ID (i.e. bit) of
1423                          * the manageability unit.
1424                          */
1425                         vfta_offset = (hw->mng_cookie.vlan_id >>
1426                                        E1000_VFTA_ENTRY_SHIFT) &
1427                             E1000_VFTA_ENTRY_MASK;
1428                         vfta_bit_in_reg =
1429                             1 << (hw->mng_cookie.vlan_id &
1430                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1431                 }
1432                 break;
1433         default:
1434                 break;
1435         }
1436         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1437                 /* If the offset we want to clear is the same offset of the
1438                  * manageability VLAN ID, then clear all bits except that of
1439                  * the manageability unit.
1440                  */
1441                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1442                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1443                 E1000_WRITE_FLUSH(hw);
1444         }
1445 }
1446
1447 /**
1448  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1449  *  @hw: pointer to the HW structure
1450  *
1451  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1452  *  (>0) if any manageability is enabled, else FALSE (0).
1453  **/
1454 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1455 {
1456         u16 data;
1457         s32 ret_val;
1458
1459         DEBUGFUNC("e1000_check_mng_mode_82574");
1460
1461         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1462         if (ret_val)
1463                 return FALSE;
1464
1465         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1466 }
1467
1468 /**
1469  *  e1000_led_on_82574 - Turn LED on
1470  *  @hw: pointer to the HW structure
1471  *
1472  *  Turn LED on.
1473  **/
1474 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1475 {
1476         u32 ctrl;
1477         u32 i;
1478
1479         DEBUGFUNC("e1000_led_on_82574");
1480
1481         ctrl = hw->mac.ledctl_mode2;
1482         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1483                 /* If no link, then turn LED on by setting the invert bit
1484                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1485                  */
1486                 for (i = 0; i < 4; i++)
1487                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1488                             E1000_LEDCTL_MODE_LED_ON)
1489                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1490         }
1491         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1492
1493         return E1000_SUCCESS;
1494 }
1495
1496 /**
1497  *  e1000_check_phy_82574 - check 82574 phy hung state
1498  *  @hw: pointer to the HW structure
1499  *
1500  *  Returns whether phy is hung or not
1501  **/
1502 bool e1000_check_phy_82574(struct e1000_hw *hw)
1503 {
1504         u16 status_1kbt = 0;
1505         u16 receive_errors = 0;
1506         s32 ret_val;
1507
1508         DEBUGFUNC("e1000_check_phy_82574");
1509
1510         /* Read PHY Receive Error counter first, if its is max - all F's then
1511          * read the Base1000T status register If both are max then PHY is hung.
1512          */
1513         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1514                                        &receive_errors);
1515         if (ret_val)
1516                 return FALSE;
1517         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1518                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1519                                                &status_1kbt);
1520                 if (ret_val)
1521                         return FALSE;
1522                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1523                     E1000_IDLE_ERROR_COUNT_MASK)
1524                         return TRUE;
1525         }
1526
1527         return FALSE;
1528 }
1529
1530
1531 /**
1532  *  e1000_setup_link_82571 - Setup flow control and link settings
1533  *  @hw: pointer to the HW structure
1534  *
1535  *  Determines which flow control settings to use, then configures flow
1536  *  control.  Calls the appropriate media-specific link configuration
1537  *  function.  Assuming the adapter has a valid link partner, a valid link
1538  *  should be established.  Assumes the hardware has previously been reset
1539  *  and the transmitter and receiver are not enabled.
1540  **/
1541 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1542 {
1543         DEBUGFUNC("e1000_setup_link_82571");
1544
1545         /* 82573 does not have a word in the NVM to determine
1546          * the default flow control setting, so we explicitly
1547          * set it to full.
1548          */
1549         switch (hw->mac.type) {
1550         case e1000_82573:
1551         case e1000_82574:
1552         case e1000_82583:
1553                 if (hw->fc.requested_mode == e1000_fc_default)
1554                         hw->fc.requested_mode = e1000_fc_full;
1555                 break;
1556         default:
1557                 break;
1558         }
1559
1560         return e1000_setup_link_generic(hw);
1561 }
1562
1563 /**
1564  *  e1000_setup_copper_link_82571 - Configure copper link settings
1565  *  @hw: pointer to the HW structure
1566  *
1567  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1568  *  for link, once link is established calls to configure collision distance
1569  *  and flow control are called.
1570  **/
1571 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1572 {
1573         u32 ctrl;
1574         s32 ret_val;
1575
1576         DEBUGFUNC("e1000_setup_copper_link_82571");
1577
1578         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1579         ctrl |= E1000_CTRL_SLU;
1580         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1581         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1582
1583         switch (hw->phy.type) {
1584         case e1000_phy_m88:
1585         case e1000_phy_bm:
1586                 ret_val = e1000_copper_link_setup_m88(hw);
1587                 break;
1588         case e1000_phy_igp_2:
1589                 ret_val = e1000_copper_link_setup_igp(hw);
1590                 break;
1591         default:
1592                 return -E1000_ERR_PHY;
1593                 break;
1594         }
1595
1596         if (ret_val)
1597                 return ret_val;
1598
1599         return e1000_setup_copper_link_generic(hw);
1600 }
1601
1602 /**
1603  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1604  *  @hw: pointer to the HW structure
1605  *
1606  *  Configures collision distance and flow control for fiber and serdes links.
1607  *  Upon successful setup, poll for link.
1608  **/
1609 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1610 {
1611         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1612
1613         switch (hw->mac.type) {
1614         case e1000_82571:
1615         case e1000_82572:
1616                 /* If SerDes loopback mode is entered, there is no form
1617                  * of reset to take the adapter out of that mode.  So we
1618                  * have to explicitly take the adapter out of loopback
1619                  * mode.  This prevents drivers from twiddling their thumbs
1620                  * if another tool failed to take it out of loopback mode.
1621                  */
1622                 E1000_WRITE_REG(hw, E1000_SCTL,
1623                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1624                 break;
1625         default:
1626                 break;
1627         }
1628
1629         return e1000_setup_fiber_serdes_link_generic(hw);
1630 }
1631
1632 /**
1633  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1634  *  @hw: pointer to the HW structure
1635  *
1636  *  Reports the link state as up or down.
1637  *
1638  *  If autonegotiation is supported by the link partner, the link state is
1639  *  determined by the result of autonegotiation. This is the most likely case.
1640  *  If autonegotiation is not supported by the link partner, and the link
1641  *  has a valid signal, force the link up.
1642  *
1643  *  The link state is represented internally here by 4 states:
1644  *
1645  *  1) down
1646  *  2) autoneg_progress
1647  *  3) autoneg_complete (the link successfully autonegotiated)
1648  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1649  *
1650  **/
1651 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1652 {
1653         struct e1000_mac_info *mac = &hw->mac;
1654         u32 rxcw;
1655         u32 ctrl;
1656         u32 status;
1657         u32 txcw;
1658         u32 i;
1659         s32 ret_val = E1000_SUCCESS;
1660
1661         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1662
1663         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1664         status = E1000_READ_REG(hw, E1000_STATUS);
1665         E1000_READ_REG(hw, E1000_RXCW);
1666         /* SYNCH bit and IV bit are sticky */
1667         usec_delay(10);
1668         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1669
1670         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1671                 /* Receiver is synchronized with no invalid bits.  */
1672                 switch (mac->serdes_link_state) {
1673                 case e1000_serdes_link_autoneg_complete:
1674                         if (!(status & E1000_STATUS_LU)) {
1675                                 /* We have lost link, retry autoneg before
1676                                  * reporting link failure
1677                                  */
1678                                 mac->serdes_link_state =
1679                                     e1000_serdes_link_autoneg_progress;
1680                                 mac->serdes_has_link = FALSE;
1681                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1682                         } else {
1683                                 mac->serdes_has_link = TRUE;
1684                         }
1685                         break;
1686
1687                 case e1000_serdes_link_forced_up:
1688                         /* If we are receiving /C/ ordered sets, re-enable
1689                          * auto-negotiation in the TXCW register and disable
1690                          * forced link in the Device Control register in an
1691                          * attempt to auto-negotiate with our link partner.
1692                          */
1693                         if (rxcw & E1000_RXCW_C) {
1694                                 /* Enable autoneg, and unforce link up */
1695                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1696                                 E1000_WRITE_REG(hw, E1000_CTRL,
1697                                     (ctrl & ~E1000_CTRL_SLU));
1698                                 mac->serdes_link_state =
1699                                     e1000_serdes_link_autoneg_progress;
1700                                 mac->serdes_has_link = FALSE;
1701                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1702                         } else {
1703                                 mac->serdes_has_link = TRUE;
1704                         }
1705                         break;
1706
1707                 case e1000_serdes_link_autoneg_progress:
1708                         if (rxcw & E1000_RXCW_C) {
1709                                 /* We received /C/ ordered sets, meaning the
1710                                  * link partner has autonegotiated, and we can
1711                                  * trust the Link Up (LU) status bit.
1712                                  */
1713                                 if (status & E1000_STATUS_LU) {
1714                                         mac->serdes_link_state =
1715                                             e1000_serdes_link_autoneg_complete;
1716                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1717                                         mac->serdes_has_link = TRUE;
1718                                 } else {
1719                                         /* Autoneg completed, but failed. */
1720                                         mac->serdes_link_state =
1721                                             e1000_serdes_link_down;
1722                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1723                                 }
1724                         } else {
1725                                 /* The link partner did not autoneg.
1726                                  * Force link up and full duplex, and change
1727                                  * state to forced.
1728                                  */
1729                                 E1000_WRITE_REG(hw, E1000_TXCW,
1730                                 (mac->txcw & ~E1000_TXCW_ANE));
1731                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1732                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1733
1734                                 /* Configure Flow Control after link up. */
1735                                 ret_val =
1736                                     e1000_config_fc_after_link_up_generic(hw);
1737                                 if (ret_val) {
1738                                         DEBUGOUT("Error config flow control\n");
1739                                         break;
1740                                 }
1741                                 mac->serdes_link_state =
1742                                                 e1000_serdes_link_forced_up;
1743                                 mac->serdes_has_link = TRUE;
1744                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1745                         }
1746                         break;
1747
1748                 case e1000_serdes_link_down:
1749                 default:
1750                         /* The link was down but the receiver has now gained
1751                          * valid sync, so lets see if we can bring the link
1752                          * up.
1753                          */
1754                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1755                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1756                                         ~E1000_CTRL_SLU));
1757                         mac->serdes_link_state =
1758                                         e1000_serdes_link_autoneg_progress;
1759                         mac->serdes_has_link = FALSE;
1760                         DEBUGOUT("DOWN      -> AN_PROG\n");
1761                         break;
1762                 }
1763         } else {
1764                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1765                         mac->serdes_has_link = FALSE;
1766                         mac->serdes_link_state = e1000_serdes_link_down;
1767                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1768                 } else {
1769                         /* Check several times, if SYNCH bit and CONFIG
1770                          * bit both are consistently 1 then simply ignore
1771                          * the IV bit and restart Autoneg
1772                          */
1773                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1774                                 usec_delay(10);
1775                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1776                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1777                                     (rxcw & E1000_RXCW_C))
1778                                         continue;
1779
1780                                 if (rxcw & E1000_RXCW_IV) {
1781                                         mac->serdes_has_link = FALSE;
1782                                         mac->serdes_link_state =
1783                                                         e1000_serdes_link_down;
1784                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1785                                         break;
1786                                 }
1787                         }
1788
1789                         if (i == AN_RETRY_COUNT) {
1790                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1791                                 txcw |= E1000_TXCW_ANE;
1792                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1793                                 mac->serdes_link_state =
1794                                         e1000_serdes_link_autoneg_progress;
1795                                 mac->serdes_has_link = FALSE;
1796                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1797                         }
1798                 }
1799         }
1800
1801         return ret_val;
1802 }
1803
1804 /**
1805  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1806  *  @hw: pointer to the HW structure
1807  *  @data: pointer to the NVM (EEPROM)
1808  *
1809  *  Read the EEPROM for the current default LED configuration.  If the
1810  *  LED configuration is not valid, set to a valid LED configuration.
1811  **/
1812 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1813 {
1814         s32 ret_val;
1815
1816         DEBUGFUNC("e1000_valid_led_default_82571");
1817
1818         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1819         if (ret_val) {
1820                 DEBUGOUT("NVM Read Error\n");
1821                 return ret_val;
1822         }
1823
1824         switch (hw->mac.type) {
1825         case e1000_82573:
1826         case e1000_82574:
1827         case e1000_82583:
1828                 if (*data == ID_LED_RESERVED_F746)
1829                         *data = ID_LED_DEFAULT_82573;
1830                 break;
1831         default:
1832                 if (*data == ID_LED_RESERVED_0000 ||
1833                     *data == ID_LED_RESERVED_FFFF)
1834                         *data = ID_LED_DEFAULT;
1835                 break;
1836         }
1837
1838         return E1000_SUCCESS;
1839 }
1840
1841 /**
1842  *  e1000_get_laa_state_82571 - Get locally administered address state
1843  *  @hw: pointer to the HW structure
1844  *
1845  *  Retrieve and return the current locally administered address state.
1846  **/
1847 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1848 {
1849         DEBUGFUNC("e1000_get_laa_state_82571");
1850
1851         if (hw->mac.type != e1000_82571)
1852                 return FALSE;
1853
1854         return hw->dev_spec._82571.laa_is_present;
1855 }
1856
1857 /**
1858  *  e1000_set_laa_state_82571 - Set locally administered address state
1859  *  @hw: pointer to the HW structure
1860  *  @state: enable/disable locally administered address
1861  *
1862  *  Enable/Disable the current locally administered address state.
1863  **/
1864 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1865 {
1866         DEBUGFUNC("e1000_set_laa_state_82571");
1867
1868         if (hw->mac.type != e1000_82571)
1869                 return;
1870
1871         hw->dev_spec._82571.laa_is_present = state;
1872
1873         /* If workaround is activated... */
1874         if (state)
1875                 /* Hold a copy of the LAA in RAR[14] This is done so that
1876                  * between the time RAR[0] gets clobbered and the time it
1877                  * gets fixed, the actual LAA is in one of the RARs and no
1878                  * incoming packets directed to this port are dropped.
1879                  * Eventually the LAA will be in RAR[0] and RAR[14].
1880                  */
1881                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1882                                     hw->mac.rar_entry_count - 1);
1883         return;
1884 }
1885
1886 /**
1887  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1888  *  @hw: pointer to the HW structure
1889  *
1890  *  Verifies that the EEPROM has completed the update.  After updating the
1891  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1892  *  the checksum fix is not implemented, we need to set the bit and update
1893  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1894  *  we need to return bad checksum.
1895  **/
1896 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1897 {
1898         struct e1000_nvm_info *nvm = &hw->nvm;
1899         s32 ret_val;
1900         u16 data;
1901
1902         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1903
1904         if (nvm->type != e1000_nvm_flash_hw)
1905                 return E1000_SUCCESS;
1906
1907         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1908          * 10h-12h.  Checksum may need to be fixed.
1909          */
1910         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1911         if (ret_val)
1912                 return ret_val;
1913
1914         if (!(data & 0x10)) {
1915                 /* Read 0x23 and check bit 15.  This bit is a 1
1916                  * when the checksum has already been fixed.  If
1917                  * the checksum is still wrong and this bit is a
1918                  * 1, we need to return bad checksum.  Otherwise,
1919                  * we need to set this bit to a 1 and update the
1920                  * checksum.
1921                  */
1922                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1923                 if (ret_val)
1924                         return ret_val;
1925
1926                 if (!(data & 0x8000)) {
1927                         data |= 0x8000;
1928                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1929                         if (ret_val)
1930                                 return ret_val;
1931                         ret_val = nvm->ops.update(hw);
1932                         if (ret_val)
1933                                 return ret_val;
1934                 }
1935         }
1936
1937         return E1000_SUCCESS;
1938 }
1939
1940
1941 /**
1942  *  e1000_read_mac_addr_82571 - Read device MAC address
1943  *  @hw: pointer to the HW structure
1944  **/
1945 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1946 {
1947         DEBUGFUNC("e1000_read_mac_addr_82571");
1948
1949         if (hw->mac.type == e1000_82571) {
1950                 s32 ret_val;
1951
1952                 /* If there's an alternate MAC address place it in RAR0
1953                  * so that it will override the Si installed default perm
1954                  * address.
1955                  */
1956                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1957                 if (ret_val)
1958                         return ret_val;
1959         }
1960
1961         return e1000_read_mac_addr_generic(hw);
1962 }
1963
1964 /**
1965  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1966  * @hw: pointer to the HW structure
1967  *
1968  * In the case of a PHY power down to save power, or to turn off link during a
1969  * driver unload, or wake on lan is not enabled, remove the link.
1970  **/
1971 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1972 {
1973         struct e1000_phy_info *phy = &hw->phy;
1974         struct e1000_mac_info *mac = &hw->mac;
1975
1976         if (!phy->ops.check_reset_block)
1977                 return;
1978
1979         /* If the management interface is not enabled, then power down */
1980         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1981                 e1000_power_down_phy_copper(hw);
1982
1983         return;
1984 }
1985
1986 /**
1987  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1988  *  @hw: pointer to the HW structure
1989  *
1990  *  Clears the hardware counters by reading the counter registers.
1991  **/
1992 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1993 {
1994         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1995
1996         e1000_clear_hw_cntrs_base_generic(hw);
1997
1998         E1000_READ_REG(hw, E1000_PRC64);
1999         E1000_READ_REG(hw, E1000_PRC127);
2000         E1000_READ_REG(hw, E1000_PRC255);
2001         E1000_READ_REG(hw, E1000_PRC511);
2002         E1000_READ_REG(hw, E1000_PRC1023);
2003         E1000_READ_REG(hw, E1000_PRC1522);
2004         E1000_READ_REG(hw, E1000_PTC64);
2005         E1000_READ_REG(hw, E1000_PTC127);
2006         E1000_READ_REG(hw, E1000_PTC255);
2007         E1000_READ_REG(hw, E1000_PTC511);
2008         E1000_READ_REG(hw, E1000_PTC1023);
2009         E1000_READ_REG(hw, E1000_PTC1522);
2010
2011         E1000_READ_REG(hw, E1000_ALGNERRC);
2012         E1000_READ_REG(hw, E1000_RXERRC);
2013         E1000_READ_REG(hw, E1000_TNCRS);
2014         E1000_READ_REG(hw, E1000_CEXTERR);
2015         E1000_READ_REG(hw, E1000_TSCTC);
2016         E1000_READ_REG(hw, E1000_TSCTFC);
2017
2018         E1000_READ_REG(hw, E1000_MGTPRC);
2019         E1000_READ_REG(hw, E1000_MGTPDC);
2020         E1000_READ_REG(hw, E1000_MGTPTC);
2021
2022         E1000_READ_REG(hw, E1000_IAC);
2023         E1000_READ_REG(hw, E1000_ICRXOC);
2024
2025         E1000_READ_REG(hw, E1000_ICRXPTC);
2026         E1000_READ_REG(hw, E1000_ICRXATC);
2027         E1000_READ_REG(hw, E1000_ICTXPTC);
2028         E1000_READ_REG(hw, E1000_ICTXATC);
2029         E1000_READ_REG(hw, E1000_ICTXQEC);
2030         E1000_READ_REG(hw, E1000_ICTXQMTC);
2031         E1000_READ_REG(hw, E1000_ICRXDMTC);
2032 }