1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ******************************************************************************/
36 /* 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * 82572EI Gigabit Ethernet Controller (Copper)
43 * 82572EI Gigabit Ethernet Controller (Fiber)
44 * 82572EI Gigabit Ethernet Controller
45 * 82573V Gigabit Ethernet Controller (Copper)
46 * 82573E Gigabit Ethernet Controller (Copper)
47 * 82573L Gigabit Ethernet Controller
48 * 82574L Gigabit Network Connection
49 * 82583V Gigabit Network Connection
52 #include "e1000_api.h"
54 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
55 static void e1000_release_nvm_82571(struct e1000_hw *hw);
56 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
60 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
61 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
63 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
64 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
65 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
66 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
67 static s32 e1000_led_on_82574(struct e1000_hw *hw);
68 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
69 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
70 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
72 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
73 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
76 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
78 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
80 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
82 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
83 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
84 u16 words, u16 *data);
85 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
86 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
89 * e1000_init_phy_params_82571 - Init PHY func ptrs.
90 * @hw: pointer to the HW structure
92 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
94 struct e1000_phy_info *phy = &hw->phy;
97 DEBUGFUNC("e1000_init_phy_params_82571");
99 if (hw->phy.media_type != e1000_media_type_copper) {
100 phy->type = e1000_phy_none;
101 return E1000_SUCCESS;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
108 phy->ops.check_reset_block = e1000_check_reset_block_generic;
109 phy->ops.reset = e1000_phy_hw_reset_generic;
110 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
111 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
112 phy->ops.power_up = e1000_power_up_phy_copper;
113 phy->ops.power_down = e1000_power_down_phy_copper_82571;
115 switch (hw->mac.type) {
118 phy->type = e1000_phy_igp_2;
119 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
120 phy->ops.get_info = e1000_get_phy_info_igp;
121 phy->ops.check_polarity = e1000_check_polarity_igp;
122 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
123 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
124 phy->ops.read_reg = e1000_read_phy_reg_igp;
125 phy->ops.write_reg = e1000_write_phy_reg_igp;
126 phy->ops.acquire = e1000_get_hw_semaphore;
127 phy->ops.release = e1000_put_hw_semaphore;
130 phy->type = e1000_phy_m88;
131 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
132 phy->ops.get_info = e1000_get_phy_info_m88;
133 phy->ops.check_polarity = e1000_check_polarity_m88;
134 phy->ops.commit = e1000_phy_sw_reset_generic;
135 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
136 phy->ops.get_cable_length = e1000_get_cable_length_m88;
137 phy->ops.read_reg = e1000_read_phy_reg_m88;
138 phy->ops.write_reg = e1000_write_phy_reg_m88;
139 phy->ops.acquire = e1000_get_hw_semaphore;
140 phy->ops.release = e1000_put_hw_semaphore;
145 phy->type = e1000_phy_bm;
146 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
147 phy->ops.get_info = e1000_get_phy_info_m88;
148 phy->ops.check_polarity = e1000_check_polarity_m88;
149 phy->ops.commit = e1000_phy_sw_reset_generic;
150 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
151 phy->ops.get_cable_length = e1000_get_cable_length_m88;
152 phy->ops.read_reg = e1000_read_phy_reg_bm2;
153 phy->ops.write_reg = e1000_write_phy_reg_bm2;
154 phy->ops.acquire = e1000_get_hw_semaphore_82574;
155 phy->ops.release = e1000_put_hw_semaphore_82574;
156 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
157 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
160 return -E1000_ERR_PHY;
164 /* This can only be done after all function pointers are setup. */
165 ret_val = e1000_get_phy_id_82571(hw);
167 DEBUGOUT("Error getting PHY ID\n");
172 switch (hw->mac.type) {
175 if (phy->id != IGP01E1000_I_PHY_ID)
176 ret_val = -E1000_ERR_PHY;
179 if (phy->id != M88E1111_I_PHY_ID)
180 ret_val = -E1000_ERR_PHY;
184 if (phy->id != BME1000_E_PHY_ID_R2)
185 ret_val = -E1000_ERR_PHY;
188 ret_val = -E1000_ERR_PHY;
193 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
199 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
200 * @hw: pointer to the HW structure
202 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
204 struct e1000_nvm_info *nvm = &hw->nvm;
205 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
208 DEBUGFUNC("e1000_init_nvm_params_82571");
210 nvm->opcode_bits = 8;
212 switch (nvm->override) {
213 case e1000_nvm_override_spi_large:
215 nvm->address_bits = 16;
217 case e1000_nvm_override_spi_small:
219 nvm->address_bits = 8;
222 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
223 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
227 switch (hw->mac.type) {
231 if (((eecd >> 15) & 0x3) == 0x3) {
232 nvm->type = e1000_nvm_flash_hw;
233 nvm->word_size = 2048;
234 /* Autonomous Flash update bit must be cleared due
235 * to Flash update issue.
237 eecd &= ~E1000_EECD_AUPDEN;
238 E1000_WRITE_REG(hw, E1000_EECD, eecd);
243 nvm->type = e1000_nvm_eeprom_spi;
244 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
245 E1000_EECD_SIZE_EX_SHIFT);
246 /* Added to a constant, "size" becomes the left-shift value
247 * for setting word_size.
249 size += NVM_WORD_SIZE_BASE_SHIFT;
251 /* EEPROM access above 16k is unsupported */
254 nvm->word_size = 1 << size;
258 /* Function Pointers */
259 switch (hw->mac.type) {
262 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
263 nvm->ops.release = e1000_put_hw_semaphore_82574;
266 nvm->ops.acquire = e1000_acquire_nvm_82571;
267 nvm->ops.release = e1000_release_nvm_82571;
270 nvm->ops.read = e1000_read_nvm_eerd;
271 nvm->ops.update = e1000_update_nvm_checksum_82571;
272 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
273 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
274 nvm->ops.write = e1000_write_nvm_82571;
276 return E1000_SUCCESS;
280 * e1000_init_mac_params_82571 - Init MAC func ptrs.
281 * @hw: pointer to the HW structure
283 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
285 struct e1000_mac_info *mac = &hw->mac;
288 bool force_clear_smbi = false;
290 DEBUGFUNC("e1000_init_mac_params_82571");
292 /* Set media type and media-dependent function pointers */
293 switch (hw->device_id) {
294 case E1000_DEV_ID_82571EB_FIBER:
295 case E1000_DEV_ID_82572EI_FIBER:
296 case E1000_DEV_ID_82571EB_QUAD_FIBER:
297 hw->phy.media_type = e1000_media_type_fiber;
298 mac->ops.setup_physical_interface =
299 e1000_setup_fiber_serdes_link_82571;
300 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
301 mac->ops.get_link_up_info =
302 e1000_get_speed_and_duplex_fiber_serdes_generic;
304 case E1000_DEV_ID_82571EB_SERDES:
305 case E1000_DEV_ID_82571EB_SERDES_DUAL:
306 case E1000_DEV_ID_82571EB_SERDES_QUAD:
307 case E1000_DEV_ID_82572EI_SERDES:
308 hw->phy.media_type = e1000_media_type_internal_serdes;
309 mac->ops.setup_physical_interface =
310 e1000_setup_fiber_serdes_link_82571;
311 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
312 mac->ops.get_link_up_info =
313 e1000_get_speed_and_duplex_fiber_serdes_generic;
316 hw->phy.media_type = e1000_media_type_copper;
317 mac->ops.setup_physical_interface =
318 e1000_setup_copper_link_82571;
319 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
320 mac->ops.get_link_up_info =
321 e1000_get_speed_and_duplex_copper_generic;
325 /* Set mta register count */
326 mac->mta_reg_count = 128;
327 /* Set rar entry count */
328 mac->rar_entry_count = E1000_RAR_ENTRIES;
329 /* Set if part includes ASF firmware */
330 mac->asf_firmware_present = true;
331 /* Adaptive IFS supported */
332 mac->adaptive_ifs = true;
334 /* Function pointers */
336 /* bus type/speed/width */
337 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
339 mac->ops.reset_hw = e1000_reset_hw_82571;
340 /* hw initialization */
341 mac->ops.init_hw = e1000_init_hw_82571;
343 mac->ops.setup_link = e1000_setup_link_82571;
344 /* multicast address update */
345 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
347 mac->ops.write_vfta = e1000_write_vfta_generic;
349 mac->ops.clear_vfta = e1000_clear_vfta_82571;
350 /* read mac address */
351 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
353 mac->ops.id_led_init = e1000_id_led_init_generic;
355 mac->ops.setup_led = e1000_setup_led_generic;
357 mac->ops.cleanup_led = e1000_cleanup_led_generic;
359 mac->ops.led_off = e1000_led_off_generic;
360 /* clear hardware counters */
361 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
363 /* MAC-specific function pointers */
364 switch (hw->mac.type) {
366 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
367 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
368 mac->ops.led_on = e1000_led_on_generic;
369 mac->ops.blink_led = e1000_blink_led_generic;
372 mac->has_fwsm = true;
373 /* ARC supported; valid only if manageability features are
376 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
377 E1000_FWSM_MODE_MASK);
381 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
382 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
383 mac->ops.led_on = e1000_led_on_82574;
386 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
387 mac->ops.led_on = e1000_led_on_generic;
388 mac->ops.blink_led = e1000_blink_led_generic;
391 mac->has_fwsm = true;
395 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
396 * first NVM or PHY access. This should be done for single-port
397 * devices, and for one port only on dual-port devices so that
398 * for those devices we can still use the SMBI lock to synchronize
399 * inter-port accesses to the PHY & NVM.
401 switch (hw->mac.type) {
404 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
406 if (!(swsm2 & E1000_SWSM2_LOCK)) {
407 /* Only do this for the first interface on this card */
408 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
410 force_clear_smbi = true;
412 force_clear_smbi = false;
416 force_clear_smbi = true;
420 if (force_clear_smbi) {
421 /* Make sure SWSM.SMBI is clear */
422 swsm = E1000_READ_REG(hw, E1000_SWSM);
423 if (swsm & E1000_SWSM_SMBI) {
424 /* This bit should not be set on a first interface, and
425 * indicates that the bootagent or EFI code has
426 * improperly left this bit enabled
428 DEBUGOUT("Please update your 82571 Bootagent\n");
430 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
433 /* Initialze device specific counter of SMBI acquisition timeouts. */
434 hw->dev_spec._82571.smb_counter = 0;
436 return E1000_SUCCESS;
440 * e1000_init_function_pointers_82571 - Init func ptrs.
441 * @hw: pointer to the HW structure
443 * Called to initialize all function pointers and parameters.
445 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
447 DEBUGFUNC("e1000_init_function_pointers_82571");
449 hw->mac.ops.init_params = e1000_init_mac_params_82571;
450 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
451 hw->phy.ops.init_params = e1000_init_phy_params_82571;
455 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
456 * @hw: pointer to the HW structure
458 * Reads the PHY registers and stores the PHY ID and possibly the PHY
459 * revision in the hardware structure.
461 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
463 struct e1000_phy_info *phy = &hw->phy;
467 DEBUGFUNC("e1000_get_phy_id_82571");
469 switch (hw->mac.type) {
472 /* The 82571 firmware may still be configuring the PHY.
473 * In this case, we cannot access the PHY until the
474 * configuration is done. So we explicitly set the
477 phy->id = IGP01E1000_I_PHY_ID;
480 return e1000_get_phy_id(hw);
484 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
488 phy->id = (u32)(phy_id << 16);
490 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
494 phy->id |= (u32)(phy_id);
495 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
498 return -E1000_ERR_PHY;
502 return E1000_SUCCESS;
506 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
507 * @hw: pointer to the HW structure
509 * Acquire the HW semaphore during reset.
513 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
517 /* XXX assert that mutex is held */
518 DEBUGFUNC("e1000_get_hw_semaphore_82574");
520 ASSERT_CTX_LOCK_HELD(hw);
521 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
523 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
524 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
525 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
527 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
532 } while (i < MDIO_OWNERSHIP_TIMEOUT);
534 if (i == MDIO_OWNERSHIP_TIMEOUT) {
535 /* Release semaphores */
536 e1000_put_hw_semaphore_82574(hw);
537 DEBUGOUT("Driver can't access the PHY\n");
538 return -E1000_ERR_PHY;
541 return E1000_SUCCESS;
545 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
546 * @hw: pointer to the HW structure
548 * Release hardware semaphore used during reset.
552 e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
556 DEBUGFUNC("e1000_put_hw_semaphore_82574");
558 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
559 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
560 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
564 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
565 * @hw: pointer to the HW structure
566 * @active: true to enable LPLU, false to disable
568 * Sets the LPLU D0 state according to the active flag.
569 * LPLU will not be activated unless the
570 * device autonegotiation advertisement meets standards of
571 * either 10 or 10/100 or 10/100/1000 at all duplexes.
572 * This is a function pointer entry point only called by
573 * PHY setup routines.
575 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
577 u32 data = E1000_READ_REG(hw, E1000_POEMB);
579 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
582 data |= E1000_PHY_CTRL_D0A_LPLU;
584 data &= ~E1000_PHY_CTRL_D0A_LPLU;
586 E1000_WRITE_REG(hw, E1000_POEMB, data);
587 return E1000_SUCCESS;
591 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
592 * @hw: pointer to the HW structure
593 * @active: boolean used to enable/disable lplu
595 * The low power link up (lplu) state is set to the power management level D3
596 * when active is true, else clear lplu for D3. LPLU
597 * is used during Dx states where the power conservation is most important.
598 * During driver activity, SmartSpeed should be enabled so performance is
601 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
603 u32 data = E1000_READ_REG(hw, E1000_POEMB);
605 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
608 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
609 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
610 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
611 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
612 data |= E1000_PHY_CTRL_NOND0A_LPLU;
615 E1000_WRITE_REG(hw, E1000_POEMB, data);
616 return E1000_SUCCESS;
620 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
621 * @hw: pointer to the HW structure
623 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
624 * Then for non-82573 hardware, set the EEPROM access request bit and wait
625 * for EEPROM access grant bit. If the access grant bit is not set, release
626 * hardware semaphore.
628 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
632 DEBUGFUNC("e1000_acquire_nvm_82571");
634 ret_val = e1000_get_hw_semaphore(hw);
638 switch (hw->mac.type) {
642 ret_val = e1000_acquire_nvm_generic(hw);
647 e1000_put_hw_semaphore(hw);
653 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
654 * @hw: pointer to the HW structure
656 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
658 static void e1000_release_nvm_82571(struct e1000_hw *hw)
660 DEBUGFUNC("e1000_release_nvm_82571");
662 e1000_release_nvm_generic(hw);
663 e1000_put_hw_semaphore(hw);
667 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
668 * @hw: pointer to the HW structure
669 * @offset: offset within the EEPROM to be written to
670 * @words: number of words to write
671 * @data: 16 bit word(s) to be written to the EEPROM
673 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
675 * If e1000_update_nvm_checksum is not called after this function, the
676 * EEPROM will most likely contain an invalid checksum.
678 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
683 DEBUGFUNC("e1000_write_nvm_82571");
685 switch (hw->mac.type) {
689 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
693 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
696 ret_val = -E1000_ERR_NVM;
704 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
705 * @hw: pointer to the HW structure
707 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
708 * up to the checksum. Then calculates the EEPROM checksum and writes the
709 * value to the EEPROM.
711 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
717 DEBUGFUNC("e1000_update_nvm_checksum_82571");
719 ret_val = e1000_update_nvm_checksum_generic(hw);
723 /* If our nvm is an EEPROM, then we're done
724 * otherwise, commit the checksum to the flash NVM.
726 if (hw->nvm.type != e1000_nvm_flash_hw)
727 return E1000_SUCCESS;
729 /* Check for pending operations. */
730 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
732 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
736 if (i == E1000_FLASH_UPDATES)
737 return -E1000_ERR_NVM;
739 /* Reset the firmware if using STM opcode. */
740 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
741 /* The enabling of and the actual reset must be done
742 * in two write cycles.
744 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
745 E1000_WRITE_FLUSH(hw);
746 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
749 /* Commit the write to flash */
750 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
751 E1000_WRITE_REG(hw, E1000_EECD, eecd);
753 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
755 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
759 if (i == E1000_FLASH_UPDATES)
760 return -E1000_ERR_NVM;
762 return E1000_SUCCESS;
766 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
767 * @hw: pointer to the HW structure
769 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
770 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
772 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
774 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
776 if (hw->nvm.type == e1000_nvm_flash_hw)
777 e1000_fix_nvm_checksum_82571(hw);
779 return e1000_validate_nvm_checksum_generic(hw);
783 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
784 * @hw: pointer to the HW structure
785 * @offset: offset within the EEPROM to be written to
786 * @words: number of words to write
787 * @data: 16 bit word(s) to be written to the EEPROM
789 * After checking for invalid values, poll the EEPROM to ensure the previous
790 * command has completed before trying to write the next word. After write
791 * poll for completion.
793 * If e1000_update_nvm_checksum is not called after this function, the
794 * EEPROM will most likely contain an invalid checksum.
796 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
797 u16 words, u16 *data)
799 struct e1000_nvm_info *nvm = &hw->nvm;
801 s32 ret_val = E1000_SUCCESS;
803 DEBUGFUNC("e1000_write_nvm_eewr_82571");
805 /* A check for invalid values: offset too large, too many words,
806 * and not enough words.
808 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
810 DEBUGOUT("nvm parameter(s) out of bounds\n");
811 return -E1000_ERR_NVM;
814 for (i = 0; i < words; i++) {
815 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
816 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
817 E1000_NVM_RW_REG_START);
819 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
823 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
825 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
834 * e1000_get_cfg_done_82571 - Poll for configuration done
835 * @hw: pointer to the HW structure
837 * Reads the management control register for the config done bit to be set.
839 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
841 s32 timeout = PHY_CFG_TIMEOUT;
843 DEBUGFUNC("e1000_get_cfg_done_82571");
846 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
847 E1000_NVM_CFG_DONE_PORT_0)
853 DEBUGOUT("MNG configuration cycle has not completed.\n");
854 return -E1000_ERR_RESET;
857 return E1000_SUCCESS;
861 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
862 * @hw: pointer to the HW structure
863 * @active: true to enable LPLU, false to disable
865 * Sets the LPLU D0 state according to the active flag. When activating LPLU
866 * this function also disables smart speed and vice versa. LPLU will not be
867 * activated unless the device autonegotiation advertisement meets standards
868 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
869 * pointer entry point only called by PHY setup routines.
871 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
873 struct e1000_phy_info *phy = &hw->phy;
877 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
879 if (!(phy->ops.read_reg))
880 return E1000_SUCCESS;
882 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
887 data |= IGP02E1000_PM_D0_LPLU;
888 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
893 /* When LPLU is enabled, we should disable SmartSpeed */
894 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
898 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
899 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
904 data &= ~IGP02E1000_PM_D0_LPLU;
905 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
907 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
908 * during Dx states where the power conservation is most
909 * important. During driver activity we should enable
910 * SmartSpeed, so performance is maintained.
912 if (phy->smart_speed == e1000_smart_speed_on) {
913 ret_val = phy->ops.read_reg(hw,
914 IGP01E1000_PHY_PORT_CONFIG,
919 data |= IGP01E1000_PSCFR_SMART_SPEED;
920 ret_val = phy->ops.write_reg(hw,
921 IGP01E1000_PHY_PORT_CONFIG,
925 } else if (phy->smart_speed == e1000_smart_speed_off) {
926 ret_val = phy->ops.read_reg(hw,
927 IGP01E1000_PHY_PORT_CONFIG,
932 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
933 ret_val = phy->ops.write_reg(hw,
934 IGP01E1000_PHY_PORT_CONFIG,
941 return E1000_SUCCESS;
945 * e1000_reset_hw_82571 - Reset hardware
946 * @hw: pointer to the HW structure
948 * This resets the hardware into a known state.
950 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
952 u32 ctrl, ctrl_ext, eecd, tctl;
955 DEBUGFUNC("e1000_reset_hw_82571");
957 /* Prevent the PCI-E bus from sticking if there is no TLP connection
958 * on the last TLP read/write transaction when MAC is reset.
960 ret_val = e1000_disable_pcie_master_generic(hw);
962 DEBUGOUT("PCI-E Master disable polling has failed.\n");
964 DEBUGOUT("Masking off all interrupts\n");
965 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
967 E1000_WRITE_REG(hw, E1000_RCTL, 0);
968 tctl = E1000_READ_REG(hw, E1000_TCTL);
969 tctl &= ~E1000_TCTL_EN;
970 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
971 E1000_WRITE_FLUSH(hw);
975 /* Must acquire the MDIO ownership before MAC reset.
976 * Ownership defaults to firmware after a reset.
978 switch (hw->mac.type) {
982 ret_val = e1000_get_hw_semaphore_82574(hw);
988 ctrl = E1000_READ_REG(hw, E1000_CTRL);
990 DEBUGOUT("Issuing a global reset to MAC\n");
991 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
993 /* Must release MDIO ownership and mutex after MAC reset. */
994 switch (hw->mac.type) {
998 /* Release mutex only if the hw semaphore is acquired */
1000 e1000_put_hw_semaphore_82574(hw);
1003 /* we didn't get the semaphore no need to put it */
1007 if (hw->nvm.type == e1000_nvm_flash_hw) {
1009 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1010 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1011 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1012 E1000_WRITE_FLUSH(hw);
1015 ret_val = e1000_get_auto_rd_done_generic(hw);
1017 /* We don't want to continue accessing MAC registers. */
1020 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1021 * Need to wait for Phy configuration completion before accessing
1025 switch (hw->mac.type) {
1028 /* REQ and GNT bits need to be cleared when using AUTO_RD
1029 * to access the EEPROM.
1031 eecd = E1000_READ_REG(hw, E1000_EECD);
1032 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1033 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1044 /* Clear any pending interrupt events. */
1045 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1046 E1000_READ_REG(hw, E1000_ICR);
1048 if (hw->mac.type == e1000_82571) {
1049 /* Install any alternate MAC address into RAR0 */
1050 ret_val = e1000_check_alt_mac_addr_generic(hw);
1054 e1000_set_laa_state_82571(hw, true);
1057 /* Reinitialize the 82571 serdes link state machine */
1058 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1059 hw->mac.serdes_link_state = e1000_serdes_link_down;
1061 return E1000_SUCCESS;
1065 * e1000_init_hw_82571 - Initialize hardware
1066 * @hw: pointer to the HW structure
1068 * This inits the hardware readying it for operation.
1070 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1072 struct e1000_mac_info *mac = &hw->mac;
1075 u16 i, rar_count = mac->rar_entry_count;
1077 DEBUGFUNC("e1000_init_hw_82571");
1079 e1000_initialize_hw_bits_82571(hw);
1081 /* Initialize identification LED */
1082 ret_val = mac->ops.id_led_init(hw);
1083 /* An error is not fatal and we should not stop init due to this */
1085 DEBUGOUT("Error initializing identification LED\n");
1087 /* Disabling VLAN filtering */
1088 DEBUGOUT("Initializing the IEEE VLAN\n");
1089 mac->ops.clear_vfta(hw);
1091 /* Setup the receive address.
1092 * If, however, a locally administered address was assigned to the
1093 * 82571, we must reserve a RAR for it to work around an issue where
1094 * resetting one port will reload the MAC on the other port.
1096 if (e1000_get_laa_state_82571(hw))
1098 e1000_init_rx_addrs_generic(hw, rar_count);
1100 /* Zero out the Multicast HASH table */
1101 DEBUGOUT("Zeroing the MTA\n");
1102 for (i = 0; i < mac->mta_reg_count; i++)
1103 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1105 /* Setup link and flow control */
1106 ret_val = mac->ops.setup_link(hw);
1108 /* Set the transmit descriptor write-back policy */
1109 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1110 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1111 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1112 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1114 /* ...for both queues. */
1115 switch (mac->type) {
1117 e1000_enable_tx_pkt_filtering_generic(hw);
1121 reg_data = E1000_READ_REG(hw, E1000_GCR);
1122 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1123 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1126 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1127 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1128 E1000_TXDCTL_FULL_TX_DESC_WB |
1129 E1000_TXDCTL_COUNT_DESC);
1130 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1134 /* Clear all of the statistics registers (clear on read). It is
1135 * important that we do this after we have tried to establish link
1136 * because the symbol error count will increment wildly if there
1139 e1000_clear_hw_cntrs_82571(hw);
1145 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1146 * @hw: pointer to the HW structure
1148 * Initializes required hardware-dependent bits needed for normal operation.
1150 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1154 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1156 /* Transmit Descriptor Control 0 */
1157 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1159 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1161 /* Transmit Descriptor Control 1 */
1162 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1164 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1166 /* Transmit Arbitration Control 0 */
1167 reg = E1000_READ_REG(hw, E1000_TARC(0));
1168 reg &= ~(0xF << 27); /* 30:27 */
1169 switch (hw->mac.type) {
1172 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1181 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1183 /* Transmit Arbitration Control 1 */
1184 reg = E1000_READ_REG(hw, E1000_TARC(1));
1185 switch (hw->mac.type) {
1188 reg &= ~((1 << 29) | (1 << 30));
1189 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1190 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1194 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1200 /* Device Control */
1201 switch (hw->mac.type) {
1205 reg = E1000_READ_REG(hw, E1000_CTRL);
1207 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1213 /* Extended Device Control */
1214 switch (hw->mac.type) {
1218 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1221 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1227 if (hw->mac.type == e1000_82571) {
1228 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1229 reg |= E1000_PBA_ECC_CORR_EN;
1230 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1233 /* Workaround for hardware errata.
1234 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1236 if ((hw->mac.type == e1000_82571) ||
1237 (hw->mac.type == e1000_82572)) {
1238 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1239 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1240 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1243 /* Disable IPv6 extension header parsing because some malformed
1244 * IPv6 headers can hang the Rx.
1246 if (hw->mac.type <= e1000_82573) {
1247 reg = E1000_READ_REG(hw, E1000_RFCTL);
1248 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1249 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1252 /* PCI-Ex Control Registers */
1253 switch (hw->mac.type) {
1256 reg = E1000_READ_REG(hw, E1000_GCR);
1258 E1000_WRITE_REG(hw, E1000_GCR, reg);
1260 /* Workaround for hardware errata.
1261 * apply workaround for hardware errata documented in errata
1262 * docs Fixes issue where some error prone or unreliable PCIe
1263 * completions are occurring, particularly with ASPM enabled.
1264 * Without fix, issue can cause Tx timeouts.
1266 reg = E1000_READ_REG(hw, E1000_GCR2);
1268 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1278 * e1000_clear_vfta_82571 - Clear VLAN filter table
1279 * @hw: pointer to the HW structure
1281 * Clears the register array which contains the VLAN filter table by
1282 * setting all the values to 0.
1284 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1288 u32 vfta_offset = 0;
1289 u32 vfta_bit_in_reg = 0;
1291 DEBUGFUNC("e1000_clear_vfta_82571");
1293 switch (hw->mac.type) {
1297 if (hw->mng_cookie.vlan_id != 0) {
1298 /* The VFTA is a 4096b bit-field, each identifying
1299 * a single VLAN ID. The following operations
1300 * determine which 32b entry (i.e. offset) into the
1301 * array we want to set the VLAN ID (i.e. bit) of
1302 * the manageability unit.
1304 vfta_offset = (hw->mng_cookie.vlan_id >>
1305 E1000_VFTA_ENTRY_SHIFT) &
1306 E1000_VFTA_ENTRY_MASK;
1308 1 << (hw->mng_cookie.vlan_id &
1309 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1315 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1316 /* If the offset we want to clear is the same offset of the
1317 * manageability VLAN ID, then clear all bits except that of
1318 * the manageability unit.
1320 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1321 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1322 E1000_WRITE_FLUSH(hw);
1327 * e1000_check_mng_mode_82574 - Check manageability is enabled
1328 * @hw: pointer to the HW structure
1330 * Reads the NVM Initialization Control Word 2 and returns true
1331 * (>0) if any manageability is enabled, else false (0).
1333 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1338 DEBUGFUNC("e1000_check_mng_mode_82574");
1340 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1344 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1348 * e1000_led_on_82574 - Turn LED on
1349 * @hw: pointer to the HW structure
1353 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1358 DEBUGFUNC("e1000_led_on_82574");
1360 ctrl = hw->mac.ledctl_mode2;
1361 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1362 /* If no link, then turn LED on by setting the invert bit
1363 * for each LED that's "on" (0x0E) in ledctl_mode2.
1365 for (i = 0; i < 4; i++)
1366 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1367 E1000_LEDCTL_MODE_LED_ON)
1368 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1370 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1372 return E1000_SUCCESS;
1376 * e1000_check_phy_82574 - check 82574 phy hung state
1377 * @hw: pointer to the HW structure
1379 * Returns whether phy is hung or not
1381 bool e1000_check_phy_82574(struct e1000_hw *hw)
1383 u16 status_1kbt = 0;
1384 u16 receive_errors = 0;
1387 DEBUGFUNC("e1000_check_phy_82574");
1389 /* Read PHY Receive Error counter first, if its is max - all F's then
1390 * read the Base1000T status register If both are max then PHY is hung.
1392 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1396 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1397 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1401 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1402 E1000_IDLE_ERROR_COUNT_MASK)
1411 * e1000_setup_link_82571 - Setup flow control and link settings
1412 * @hw: pointer to the HW structure
1414 * Determines which flow control settings to use, then configures flow
1415 * control. Calls the appropriate media-specific link configuration
1416 * function. Assuming the adapter has a valid link partner, a valid link
1417 * should be established. Assumes the hardware has previously been reset
1418 * and the transmitter and receiver are not enabled.
1420 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1422 DEBUGFUNC("e1000_setup_link_82571");
1424 /* 82573 does not have a word in the NVM to determine
1425 * the default flow control setting, so we explicitly
1428 switch (hw->mac.type) {
1432 if (hw->fc.requested_mode == e1000_fc_default)
1433 hw->fc.requested_mode = e1000_fc_full;
1439 return e1000_setup_link_generic(hw);
1443 * e1000_setup_copper_link_82571 - Configure copper link settings
1444 * @hw: pointer to the HW structure
1446 * Configures the link for auto-neg or forced speed and duplex. Then we check
1447 * for link, once link is established calls to configure collision distance
1448 * and flow control are called.
1450 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1455 DEBUGFUNC("e1000_setup_copper_link_82571");
1457 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1458 ctrl |= E1000_CTRL_SLU;
1459 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1460 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1462 switch (hw->phy.type) {
1465 ret_val = e1000_copper_link_setup_m88(hw);
1467 case e1000_phy_igp_2:
1468 ret_val = e1000_copper_link_setup_igp(hw);
1471 return -E1000_ERR_PHY;
1478 return e1000_setup_copper_link_generic(hw);
1482 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1483 * @hw: pointer to the HW structure
1485 * Configures collision distance and flow control for fiber and serdes links.
1486 * Upon successful setup, poll for link.
1488 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1490 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1492 switch (hw->mac.type) {
1495 /* If SerDes loopback mode is entered, there is no form
1496 * of reset to take the adapter out of that mode. So we
1497 * have to explicitly take the adapter out of loopback
1498 * mode. This prevents drivers from twiddling their thumbs
1499 * if another tool failed to take it out of loopback mode.
1501 E1000_WRITE_REG(hw, E1000_SCTL,
1502 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1508 return e1000_setup_fiber_serdes_link_generic(hw);
1512 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1513 * @hw: pointer to the HW structure
1515 * Reports the link state as up or down.
1517 * If autonegotiation is supported by the link partner, the link state is
1518 * determined by the result of autonegotiation. This is the most likely case.
1519 * If autonegotiation is not supported by the link partner, and the link
1520 * has a valid signal, force the link up.
1522 * The link state is represented internally here by 4 states:
1525 * 2) autoneg_progress
1526 * 3) autoneg_complete (the link successfully autonegotiated)
1527 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1530 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1532 struct e1000_mac_info *mac = &hw->mac;
1538 s32 ret_val = E1000_SUCCESS;
1540 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1542 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1543 status = E1000_READ_REG(hw, E1000_STATUS);
1544 E1000_READ_REG(hw, E1000_RXCW);
1545 /* SYNCH bit and IV bit are sticky */
1547 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1549 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1550 /* Receiver is synchronized with no invalid bits. */
1551 switch (mac->serdes_link_state) {
1552 case e1000_serdes_link_autoneg_complete:
1553 if (!(status & E1000_STATUS_LU)) {
1554 /* We have lost link, retry autoneg before
1555 * reporting link failure
1557 mac->serdes_link_state =
1558 e1000_serdes_link_autoneg_progress;
1559 mac->serdes_has_link = false;
1560 DEBUGOUT("AN_UP -> AN_PROG\n");
1562 mac->serdes_has_link = true;
1566 case e1000_serdes_link_forced_up:
1567 /* If we are receiving /C/ ordered sets, re-enable
1568 * auto-negotiation in the TXCW register and disable
1569 * forced link in the Device Control register in an
1570 * attempt to auto-negotiate with our link partner.
1572 if (rxcw & E1000_RXCW_C) {
1573 /* Enable autoneg, and unforce link up */
1574 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1575 E1000_WRITE_REG(hw, E1000_CTRL,
1576 (ctrl & ~E1000_CTRL_SLU));
1577 mac->serdes_link_state =
1578 e1000_serdes_link_autoneg_progress;
1579 mac->serdes_has_link = false;
1580 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1582 mac->serdes_has_link = true;
1586 case e1000_serdes_link_autoneg_progress:
1587 if (rxcw & E1000_RXCW_C) {
1588 /* We received /C/ ordered sets, meaning the
1589 * link partner has autonegotiated, and we can
1590 * trust the Link Up (LU) status bit.
1592 if (status & E1000_STATUS_LU) {
1593 mac->serdes_link_state =
1594 e1000_serdes_link_autoneg_complete;
1595 DEBUGOUT("AN_PROG -> AN_UP\n");
1596 mac->serdes_has_link = true;
1598 /* Autoneg completed, but failed. */
1599 mac->serdes_link_state =
1600 e1000_serdes_link_down;
1601 DEBUGOUT("AN_PROG -> DOWN\n");
1604 /* The link partner did not autoneg.
1605 * Force link up and full duplex, and change
1608 E1000_WRITE_REG(hw, E1000_TXCW,
1609 (mac->txcw & ~E1000_TXCW_ANE));
1610 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1611 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1613 /* Configure Flow Control after link up. */
1615 e1000_config_fc_after_link_up_generic(hw);
1617 DEBUGOUT("Error config flow control\n");
1620 mac->serdes_link_state =
1621 e1000_serdes_link_forced_up;
1622 mac->serdes_has_link = true;
1623 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1627 case e1000_serdes_link_down:
1629 /* The link was down but the receiver has now gained
1630 * valid sync, so lets see if we can bring the link
1633 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1634 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1636 mac->serdes_link_state =
1637 e1000_serdes_link_autoneg_progress;
1638 mac->serdes_has_link = false;
1639 DEBUGOUT("DOWN -> AN_PROG\n");
1643 if (!(rxcw & E1000_RXCW_SYNCH)) {
1644 mac->serdes_has_link = false;
1645 mac->serdes_link_state = e1000_serdes_link_down;
1646 DEBUGOUT("ANYSTATE -> DOWN\n");
1648 /* Check several times, if SYNCH bit and CONFIG
1649 * bit both are consistently 1 then simply ignore
1650 * the IV bit and restart Autoneg
1652 for (i = 0; i < AN_RETRY_COUNT; i++) {
1654 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1655 if ((rxcw & E1000_RXCW_SYNCH) &&
1656 (rxcw & E1000_RXCW_C))
1659 if (rxcw & E1000_RXCW_IV) {
1660 mac->serdes_has_link = false;
1661 mac->serdes_link_state =
1662 e1000_serdes_link_down;
1663 DEBUGOUT("ANYSTATE -> DOWN\n");
1668 if (i == AN_RETRY_COUNT) {
1669 txcw = E1000_READ_REG(hw, E1000_TXCW);
1670 txcw |= E1000_TXCW_ANE;
1671 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1672 mac->serdes_link_state =
1673 e1000_serdes_link_autoneg_progress;
1674 mac->serdes_has_link = false;
1675 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1684 * e1000_valid_led_default_82571 - Verify a valid default LED config
1685 * @hw: pointer to the HW structure
1686 * @data: pointer to the NVM (EEPROM)
1688 * Read the EEPROM for the current default LED configuration. If the
1689 * LED configuration is not valid, set to a valid LED configuration.
1691 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1695 DEBUGFUNC("e1000_valid_led_default_82571");
1697 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1699 DEBUGOUT("NVM Read Error\n");
1703 switch (hw->mac.type) {
1707 if (*data == ID_LED_RESERVED_F746)
1708 *data = ID_LED_DEFAULT_82573;
1711 if (*data == ID_LED_RESERVED_0000 ||
1712 *data == ID_LED_RESERVED_FFFF)
1713 *data = ID_LED_DEFAULT;
1717 return E1000_SUCCESS;
1721 * e1000_get_laa_state_82571 - Get locally administered address state
1722 * @hw: pointer to the HW structure
1724 * Retrieve and return the current locally administered address state.
1726 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1728 DEBUGFUNC("e1000_get_laa_state_82571");
1730 if (hw->mac.type != e1000_82571)
1733 return hw->dev_spec._82571.laa_is_present;
1737 * e1000_set_laa_state_82571 - Set locally administered address state
1738 * @hw: pointer to the HW structure
1739 * @state: enable/disable locally administered address
1741 * Enable/Disable the current locally administered address state.
1743 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1745 DEBUGFUNC("e1000_set_laa_state_82571");
1747 if (hw->mac.type != e1000_82571)
1750 hw->dev_spec._82571.laa_is_present = state;
1752 /* If workaround is activated... */
1754 /* Hold a copy of the LAA in RAR[14] This is done so that
1755 * between the time RAR[0] gets clobbered and the time it
1756 * gets fixed, the actual LAA is in one of the RARs and no
1757 * incoming packets directed to this port are dropped.
1758 * Eventually the LAA will be in RAR[0] and RAR[14].
1760 hw->mac.ops.rar_set(hw, hw->mac.addr,
1761 hw->mac.rar_entry_count - 1);
1766 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1767 * @hw: pointer to the HW structure
1769 * Verifies that the EEPROM has completed the update. After updating the
1770 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1771 * the checksum fix is not implemented, we need to set the bit and update
1772 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1773 * we need to return bad checksum.
1775 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1777 struct e1000_nvm_info *nvm = &hw->nvm;
1781 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1783 if (nvm->type != e1000_nvm_flash_hw)
1784 return E1000_SUCCESS;
1786 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1787 * 10h-12h. Checksum may need to be fixed.
1789 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1793 if (!(data & 0x10)) {
1794 /* Read 0x23 and check bit 15. This bit is a 1
1795 * when the checksum has already been fixed. If
1796 * the checksum is still wrong and this bit is a
1797 * 1, we need to return bad checksum. Otherwise,
1798 * we need to set this bit to a 1 and update the
1801 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1805 if (!(data & 0x8000)) {
1807 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1810 ret_val = nvm->ops.update(hw);
1816 return E1000_SUCCESS;
1821 * e1000_read_mac_addr_82571 - Read device MAC address
1822 * @hw: pointer to the HW structure
1824 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1826 DEBUGFUNC("e1000_read_mac_addr_82571");
1828 if (hw->mac.type == e1000_82571) {
1831 /* If there's an alternate MAC address place it in RAR0
1832 * so that it will override the Si installed default perm
1835 ret_val = e1000_check_alt_mac_addr_generic(hw);
1840 return e1000_read_mac_addr_generic(hw);
1844 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1845 * @hw: pointer to the HW structure
1847 * In the case of a PHY power down to save power, or to turn off link during a
1848 * driver unload, or wake on lan is not enabled, remove the link.
1850 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1852 struct e1000_phy_info *phy = &hw->phy;
1853 struct e1000_mac_info *mac = &hw->mac;
1855 if (!phy->ops.check_reset_block)
1858 /* If the management interface is not enabled, then power down */
1859 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1860 e1000_power_down_phy_copper(hw);
1866 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1867 * @hw: pointer to the HW structure
1869 * Clears the hardware counters by reading the counter registers.
1871 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1873 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1875 e1000_clear_hw_cntrs_base_generic(hw);
1877 E1000_READ_REG(hw, E1000_PRC64);
1878 E1000_READ_REG(hw, E1000_PRC127);
1879 E1000_READ_REG(hw, E1000_PRC255);
1880 E1000_READ_REG(hw, E1000_PRC511);
1881 E1000_READ_REG(hw, E1000_PRC1023);
1882 E1000_READ_REG(hw, E1000_PRC1522);
1883 E1000_READ_REG(hw, E1000_PTC64);
1884 E1000_READ_REG(hw, E1000_PTC127);
1885 E1000_READ_REG(hw, E1000_PTC255);
1886 E1000_READ_REG(hw, E1000_PTC511);
1887 E1000_READ_REG(hw, E1000_PTC1023);
1888 E1000_READ_REG(hw, E1000_PTC1522);
1890 E1000_READ_REG(hw, E1000_ALGNERRC);
1891 E1000_READ_REG(hw, E1000_RXERRC);
1892 E1000_READ_REG(hw, E1000_TNCRS);
1893 E1000_READ_REG(hw, E1000_CEXTERR);
1894 E1000_READ_REG(hw, E1000_TSCTC);
1895 E1000_READ_REG(hw, E1000_TSCTFC);
1897 E1000_READ_REG(hw, E1000_MGTPRC);
1898 E1000_READ_REG(hw, E1000_MGTPDC);
1899 E1000_READ_REG(hw, E1000_MGTPTC);
1901 E1000_READ_REG(hw, E1000_IAC);
1902 E1000_READ_REG(hw, E1000_ICRXOC);
1904 E1000_READ_REG(hw, E1000_ICRXPTC);
1905 E1000_READ_REG(hw, E1000_ICRXATC);
1906 E1000_READ_REG(hw, E1000_ICTXPTC);
1907 E1000_READ_REG(hw, E1000_ICTXATC);
1908 E1000_READ_REG(hw, E1000_ICTXQEC);
1909 E1000_READ_REG(hw, E1000_ICTXQMTC);
1910 E1000_READ_REG(hw, E1000_ICRXDMTC);