1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
41 #include "e1000_api.h"
43 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
44 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
45 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
46 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
47 static void e1000_release_nvm_82571(struct e1000_hw *hw);
48 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
49 u16 words, u16 *data);
50 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
51 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
52 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
53 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
55 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
57 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
58 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
59 static s32 e1000_led_on_82574(struct e1000_hw *hw);
60 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
61 u8 *mc_addr_list, u32 mc_addr_count,
62 u32 rar_used_count, u32 rar_count);
63 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
64 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
65 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
66 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
68 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
69 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
70 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
72 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
73 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
74 u16 words, u16 *data);
75 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
76 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
78 struct e1000_dev_spec_82571 {
83 * e1000_init_phy_params_82571 - Init PHY func ptrs.
84 * @hw: pointer to the HW structure
86 * This is a function pointer entry point called by the api module.
88 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
90 struct e1000_phy_info *phy = &hw->phy;
91 s32 ret_val = E1000_SUCCESS;
93 DEBUGFUNC("e1000_init_phy_params_82571");
95 if (hw->phy.media_type != e1000_media_type_copper) {
96 phy->type = e1000_phy_none;
101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
102 phy->reset_delay_us = 100;
104 phy->ops.acquire = e1000_get_hw_semaphore_82571;
105 phy->ops.check_polarity = e1000_check_polarity_igp;
106 phy->ops.check_reset_block = e1000_check_reset_block_generic;
107 phy->ops.release = e1000_put_hw_semaphore_82571;
108 phy->ops.reset = e1000_phy_hw_reset_generic;
109 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
110 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
111 phy->ops.power_up = e1000_power_up_phy_copper;
112 phy->ops.power_down = e1000_power_down_phy_copper_82571;
114 switch (hw->mac.type) {
117 phy->type = e1000_phy_igp_2;
118 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
119 phy->ops.get_info = e1000_get_phy_info_igp;
120 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
121 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
122 phy->ops.read_reg = e1000_read_phy_reg_igp;
123 phy->ops.write_reg = e1000_write_phy_reg_igp;
125 /* This uses above function pointers */
126 ret_val = e1000_get_phy_id_82571(hw);
129 if (phy->id != IGP01E1000_I_PHY_ID) {
130 ret_val = -E1000_ERR_PHY;
135 phy->type = e1000_phy_m88;
136 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
137 phy->ops.get_info = e1000_get_phy_info_m88;
138 phy->ops.commit = e1000_phy_sw_reset_generic;
139 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
140 phy->ops.get_cable_length = e1000_get_cable_length_m88;
141 phy->ops.read_reg = e1000_read_phy_reg_m88;
142 phy->ops.write_reg = e1000_write_phy_reg_m88;
144 /* This uses above function pointers */
145 ret_val = e1000_get_phy_id_82571(hw);
148 if (phy->id != M88E1111_I_PHY_ID) {
149 ret_val = -E1000_ERR_PHY;
150 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
155 phy->type = e1000_phy_bm;
156 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
157 phy->ops.get_info = e1000_get_phy_info_m88;
158 phy->ops.commit = e1000_phy_sw_reset_generic;
159 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
160 phy->ops.get_cable_length = e1000_get_cable_length_m88;
161 phy->ops.read_reg = e1000_read_phy_reg_bm2;
162 phy->ops.write_reg = e1000_write_phy_reg_bm2;
164 /* This uses above function pointers */
165 ret_val = e1000_get_phy_id_82571(hw);
167 if (phy->id != BME1000_E_PHY_ID_R2) {
168 ret_val = -E1000_ERR_PHY;
169 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
174 ret_val = -E1000_ERR_PHY;
184 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
185 * @hw: pointer to the HW structure
187 * This is a function pointer entry point called by the api module.
189 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
191 struct e1000_nvm_info *nvm = &hw->nvm;
192 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
195 DEBUGFUNC("e1000_init_nvm_params_82571");
197 nvm->opcode_bits = 8;
199 switch (nvm->override) {
200 case e1000_nvm_override_spi_large:
202 nvm->address_bits = 16;
204 case e1000_nvm_override_spi_small:
206 nvm->address_bits = 8;
209 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
210 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
214 switch (hw->mac.type) {
217 if (((eecd >> 15) & 0x3) == 0x3) {
218 nvm->type = e1000_nvm_flash_hw;
219 nvm->word_size = 2048;
221 * Autonomous Flash update bit must be cleared due
222 * to Flash update issue.
224 eecd &= ~E1000_EECD_AUPDEN;
225 E1000_WRITE_REG(hw, E1000_EECD, eecd);
230 nvm->type = e1000_nvm_eeprom_spi;
231 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
232 E1000_EECD_SIZE_EX_SHIFT);
234 * Added to a constant, "size" becomes the left-shift value
235 * for setting word_size.
237 size += NVM_WORD_SIZE_BASE_SHIFT;
239 /* EEPROM access above 16k is unsupported */
242 nvm->word_size = 1 << size;
246 /* Function Pointers */
247 nvm->ops.acquire = e1000_acquire_nvm_82571;
248 nvm->ops.read = e1000_read_nvm_eerd;
249 nvm->ops.release = e1000_release_nvm_82571;
250 nvm->ops.update = e1000_update_nvm_checksum_82571;
251 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
252 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
253 nvm->ops.write = e1000_write_nvm_82571;
255 return E1000_SUCCESS;
259 * e1000_init_mac_params_82571 - Init MAC func ptrs.
260 * @hw: pointer to the HW structure
262 * This is a function pointer entry point called by the api module.
264 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
266 struct e1000_mac_info *mac = &hw->mac;
267 s32 ret_val = E1000_SUCCESS;
269 DEBUGFUNC("e1000_init_mac_params_82571");
272 switch (hw->device_id) {
273 case E1000_DEV_ID_82571EB_FIBER:
274 case E1000_DEV_ID_82572EI_FIBER:
275 case E1000_DEV_ID_82571EB_QUAD_FIBER:
276 hw->phy.media_type = e1000_media_type_fiber;
278 case E1000_DEV_ID_82571EB_SERDES:
279 case E1000_DEV_ID_82571EB_SERDES_DUAL:
280 case E1000_DEV_ID_82571EB_SERDES_QUAD:
281 case E1000_DEV_ID_82572EI_SERDES:
282 hw->phy.media_type = e1000_media_type_internal_serdes;
285 hw->phy.media_type = e1000_media_type_copper;
289 /* Set mta register count */
290 mac->mta_reg_count = 128;
291 /* Set rar entry count */
292 mac->rar_entry_count = E1000_RAR_ENTRIES;
293 /* Set if part includes ASF firmware */
294 mac->asf_firmware_present = TRUE;
295 /* Set if manageability features are enabled. */
296 mac->arc_subsystem_valid =
297 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
300 /* Function pointers */
302 /* bus type/speed/width */
303 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
305 mac->ops.reset_hw = e1000_reset_hw_82571;
306 /* hw initialization */
307 mac->ops.init_hw = e1000_init_hw_82571;
309 mac->ops.setup_link = e1000_setup_link_82571;
310 /* physical interface link setup */
311 mac->ops.setup_physical_interface =
312 (hw->phy.media_type == e1000_media_type_copper)
313 ? e1000_setup_copper_link_82571
314 : e1000_setup_fiber_serdes_link_82571;
316 switch (hw->phy.media_type) {
317 case e1000_media_type_copper:
318 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
320 case e1000_media_type_fiber:
321 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
323 case e1000_media_type_internal_serdes:
324 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
327 ret_val = -E1000_ERR_CONFIG;
331 /* check management mode */
332 switch (hw->mac.type) {
334 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
337 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
340 /* multicast address update */
341 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571;
343 mac->ops.write_vfta = e1000_write_vfta_generic;
345 mac->ops.clear_vfta = e1000_clear_vfta_82571;
347 mac->ops.mta_set = e1000_mta_set_generic;
348 /* read mac address */
349 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
351 mac->ops.blink_led = e1000_blink_led_generic;
353 mac->ops.setup_led = e1000_setup_led_generic;
355 mac->ops.cleanup_led = e1000_cleanup_led_generic;
356 /* turn on/off LED */
357 switch (hw->mac.type) {
359 mac->ops.led_on = e1000_led_on_82574;
362 mac->ops.led_on = e1000_led_on_generic;
365 mac->ops.led_off = e1000_led_off_generic;
367 mac->ops.remove_device = e1000_remove_device_generic;
368 /* clear hardware counters */
369 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
371 mac->ops.get_link_up_info =
372 (hw->phy.media_type == e1000_media_type_copper)
373 ? e1000_get_speed_and_duplex_copper_generic
374 : e1000_get_speed_and_duplex_fiber_serdes_generic;
376 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571);
378 /* Device-specific structure allocation */
379 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
386 * e1000_init_function_pointers_82571 - Init func ptrs.
387 * @hw: pointer to the HW structure
389 * The only function explicitly called by the api module to initialize
390 * all function pointers and parameters.
392 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
394 DEBUGFUNC("e1000_init_function_pointers_82571");
396 hw->mac.ops.init_params = e1000_init_mac_params_82571;
397 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
398 hw->phy.ops.init_params = e1000_init_phy_params_82571;
402 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
403 * @hw: pointer to the HW structure
405 * Reads the PHY registers and stores the PHY ID and possibly the PHY
406 * revision in the hardware structure.
408 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
410 struct e1000_phy_info *phy = &hw->phy;
411 s32 ret_val = E1000_SUCCESS;
414 DEBUGFUNC("e1000_get_phy_id_82571");
416 switch (hw->mac.type) {
420 * The 82571 firmware may still be configuring the PHY.
421 * In this case, we cannot access the PHY until the
422 * configuration is done. So we explicitly set the
425 phy->id = IGP01E1000_I_PHY_ID;
428 ret_val = e1000_get_phy_id(hw);
431 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
435 phy->id = (u32)(phy_id << 16);
437 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
441 phy->id |= (u32)(phy_id);
442 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
445 ret_val = -E1000_ERR_PHY;
454 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
455 * @hw: pointer to the HW structure
457 * Acquire the HW semaphore to access the PHY or NVM
459 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
462 s32 ret_val = E1000_SUCCESS;
463 s32 timeout = hw->nvm.word_size + 1;
466 DEBUGFUNC("e1000_get_hw_semaphore_82571");
468 /* Get the FW semaphore. */
469 for (i = 0; i < timeout; i++) {
470 swsm = E1000_READ_REG(hw, E1000_SWSM);
471 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
473 /* Semaphore acquired if bit latched */
474 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
481 /* Release semaphores */
482 e1000_put_hw_semaphore_generic(hw);
483 DEBUGOUT("Driver can't access the NVM\n");
484 ret_val = -E1000_ERR_NVM;
493 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
494 * @hw: pointer to the HW structure
496 * Release hardware semaphore used to access the PHY or NVM
498 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
502 DEBUGFUNC("e1000_put_hw_semaphore_82571");
504 swsm = E1000_READ_REG(hw, E1000_SWSM);
506 swsm &= ~E1000_SWSM_SWESMBI;
508 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
512 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
513 * @hw: pointer to the HW structure
515 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
516 * Then for non-82573 hardware, set the EEPROM access request bit and wait
517 * for EEPROM access grant bit. If the access grant bit is not set, release
518 * hardware semaphore.
520 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
524 DEBUGFUNC("e1000_acquire_nvm_82571");
526 ret_val = e1000_get_hw_semaphore_82571(hw);
530 if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
531 ret_val = e1000_acquire_nvm_generic(hw);
534 e1000_put_hw_semaphore_82571(hw);
541 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
542 * @hw: pointer to the HW structure
544 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
546 static void e1000_release_nvm_82571(struct e1000_hw *hw)
548 DEBUGFUNC("e1000_release_nvm_82571");
550 e1000_release_nvm_generic(hw);
551 e1000_put_hw_semaphore_82571(hw);
555 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
556 * @hw: pointer to the HW structure
557 * @offset: offset within the EEPROM to be written to
558 * @words: number of words to write
559 * @data: 16 bit word(s) to be written to the EEPROM
561 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
563 * If e1000_update_nvm_checksum is not called after this function, the
564 * EEPROM will most likely contain an invalid checksum.
566 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
569 s32 ret_val = E1000_SUCCESS;
571 DEBUGFUNC("e1000_write_nvm_82571");
573 switch (hw->mac.type) {
576 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
580 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
583 ret_val = -E1000_ERR_NVM;
591 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
592 * @hw: pointer to the HW structure
594 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
595 * up to the checksum. Then calculates the EEPROM checksum and writes the
596 * value to the EEPROM.
598 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
604 DEBUGFUNC("e1000_update_nvm_checksum_82571");
606 ret_val = e1000_update_nvm_checksum_generic(hw);
611 * If our nvm is an EEPROM, then we're done
612 * otherwise, commit the checksum to the flash NVM.
614 if (hw->nvm.type != e1000_nvm_flash_hw)
617 /* Check for pending operations. */
618 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
620 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
624 if (i == E1000_FLASH_UPDATES) {
625 ret_val = -E1000_ERR_NVM;
629 /* Reset the firmware if using STM opcode. */
630 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
632 * The enabling of and the actual reset must be done
633 * in two write cycles.
635 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
636 E1000_WRITE_FLUSH(hw);
637 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
640 /* Commit the write to flash */
641 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
642 E1000_WRITE_REG(hw, E1000_EECD, eecd);
644 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
646 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
650 if (i == E1000_FLASH_UPDATES) {
651 ret_val = -E1000_ERR_NVM;
660 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
661 * @hw: pointer to the HW structure
663 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
664 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
666 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
668 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
670 if (hw->nvm.type == e1000_nvm_flash_hw)
671 e1000_fix_nvm_checksum_82571(hw);
673 return e1000_validate_nvm_checksum_generic(hw);
677 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
678 * @hw: pointer to the HW structure
679 * @offset: offset within the EEPROM to be written to
680 * @words: number of words to write
681 * @data: 16 bit word(s) to be written to the EEPROM
683 * After checking for invalid values, poll the EEPROM to ensure the previous
684 * command has completed before trying to write the next word. After write
685 * poll for completion.
687 * If e1000_update_nvm_checksum is not called after this function, the
688 * EEPROM will most likely contain an invalid checksum.
690 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
691 u16 words, u16 *data)
693 struct e1000_nvm_info *nvm = &hw->nvm;
697 DEBUGFUNC("e1000_write_nvm_eewr_82571");
700 * A check for invalid values: offset too large, too many words,
701 * and not enough words.
703 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
705 DEBUGOUT("nvm parameter(s) out of bounds\n");
706 ret_val = -E1000_ERR_NVM;
710 for (i = 0; i < words; i++) {
711 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
712 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
713 E1000_NVM_RW_REG_START;
715 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
719 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
721 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
731 * e1000_get_cfg_done_82571 - Poll for configuration done
732 * @hw: pointer to the HW structure
734 * Reads the management control register for the config done bit to be set.
736 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
738 s32 timeout = PHY_CFG_TIMEOUT;
739 s32 ret_val = E1000_SUCCESS;
741 DEBUGFUNC("e1000_get_cfg_done_82571");
744 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
750 DEBUGOUT("MNG configuration cycle has not completed.\n");
751 ret_val = -E1000_ERR_RESET;
760 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
761 * @hw: pointer to the HW structure
762 * @active: TRUE to enable LPLU, FALSE to disable
764 * Sets the LPLU D0 state according to the active flag. When activating LPLU
765 * this function also disables smart speed and vice versa. LPLU will not be
766 * activated unless the device autonegotiation advertisement meets standards
767 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
768 * pointer entry point only called by PHY setup routines.
770 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
772 struct e1000_phy_info *phy = &hw->phy;
773 s32 ret_val = E1000_SUCCESS;
776 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
778 if (!(phy->ops.read_reg))
781 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
786 data |= IGP02E1000_PM_D0_LPLU;
787 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
792 /* When LPLU is enabled, we should disable SmartSpeed */
793 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
795 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
796 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
801 data &= ~IGP02E1000_PM_D0_LPLU;
802 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
805 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
806 * during Dx states where the power conservation is most
807 * important. During driver activity we should enable
808 * SmartSpeed, so performance is maintained.
810 if (phy->smart_speed == e1000_smart_speed_on) {
811 ret_val = phy->ops.read_reg(hw,
812 IGP01E1000_PHY_PORT_CONFIG,
817 data |= IGP01E1000_PSCFR_SMART_SPEED;
818 ret_val = phy->ops.write_reg(hw,
819 IGP01E1000_PHY_PORT_CONFIG,
823 } else if (phy->smart_speed == e1000_smart_speed_off) {
824 ret_val = phy->ops.read_reg(hw,
825 IGP01E1000_PHY_PORT_CONFIG,
830 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
831 ret_val = phy->ops.write_reg(hw,
832 IGP01E1000_PHY_PORT_CONFIG,
844 * e1000_reset_hw_82571 - Reset hardware
845 * @hw: pointer to the HW structure
847 * This resets the hardware into a known state. This is a
848 * function pointer entry point called by the api module.
850 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
852 u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
856 DEBUGFUNC("e1000_reset_hw_82571");
859 * Prevent the PCI-E bus from sticking if there is no TLP connection
860 * on the last TLP read/write transaction when MAC is reset.
862 ret_val = e1000_disable_pcie_master_generic(hw);
864 DEBUGOUT("PCI-E Master disable polling has failed.\n");
867 DEBUGOUT("Masking off all interrupts\n");
868 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
870 E1000_WRITE_REG(hw, E1000_RCTL, 0);
871 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
872 E1000_WRITE_FLUSH(hw);
877 * Must acquire the MDIO ownership before MAC reset.
878 * Ownership defaults to firmware after a reset.
880 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
881 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
882 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
885 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
886 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
888 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
891 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
895 } while (i < MDIO_OWNERSHIP_TIMEOUT);
898 ctrl = E1000_READ_REG(hw, E1000_CTRL);
900 DEBUGOUT("Issuing a global reset to MAC\n");
901 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
903 if (hw->nvm.type == e1000_nvm_flash_hw) {
905 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
906 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
907 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
908 E1000_WRITE_FLUSH(hw);
911 ret_val = e1000_get_auto_rd_done_generic(hw);
913 /* We don't want to continue accessing MAC registers. */
917 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
918 * Need to wait for Phy configuration completion before accessing
921 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
924 /* Clear any pending interrupt events. */
925 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
926 icr = E1000_READ_REG(hw, E1000_ICR);
928 if (!(e1000_check_alt_mac_addr_generic(hw)))
929 e1000_set_laa_state_82571(hw, TRUE);
936 * e1000_init_hw_82571 - Initialize hardware
937 * @hw: pointer to the HW structure
939 * This inits the hardware readying it for operation.
941 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
943 struct e1000_mac_info *mac = &hw->mac;
946 u16 i, rar_count = mac->rar_entry_count;
948 DEBUGFUNC("e1000_init_hw_82571");
950 e1000_initialize_hw_bits_82571(hw);
952 /* Initialize identification LED */
953 ret_val = e1000_id_led_init_generic(hw);
955 DEBUGOUT("Error initializing identification LED\n");
956 /* This is not fatal and we should not stop init due to this */
959 /* Disabling VLAN filtering */
960 DEBUGOUT("Initializing the IEEE VLAN\n");
961 mac->ops.clear_vfta(hw);
963 /* Setup the receive address. */
965 * If, however, a locally administered address was assigned to the
966 * 82571, we must reserve a RAR for it to work around an issue where
967 * resetting one port will reload the MAC on the other port.
969 if (e1000_get_laa_state_82571(hw))
971 e1000_init_rx_addrs_generic(hw, rar_count);
973 /* Zero out the Multicast HASH table */
974 DEBUGOUT("Zeroing the MTA\n");
975 for (i = 0; i < mac->mta_reg_count; i++)
976 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
978 /* Setup link and flow control */
979 ret_val = mac->ops.setup_link(hw);
981 /* Set the transmit descriptor write-back policy */
982 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
983 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
984 E1000_TXDCTL_FULL_TX_DESC_WB |
985 E1000_TXDCTL_COUNT_DESC;
986 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
988 /* ...for both queues. */
989 if (mac->type != e1000_82573 && mac->type != e1000_82574) {
990 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
991 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
992 E1000_TXDCTL_FULL_TX_DESC_WB |
993 E1000_TXDCTL_COUNT_DESC;
994 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
996 e1000_enable_tx_pkt_filtering_generic(hw);
997 reg_data = E1000_READ_REG(hw, E1000_GCR);
998 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
999 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1003 * Clear all of the statistics registers (clear on read). It is
1004 * important that we do this after we have tried to establish link
1005 * because the symbol error count will increment wildly if there
1008 e1000_clear_hw_cntrs_82571(hw);
1014 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1015 * @hw: pointer to the HW structure
1017 * Initializes required hardware-dependent bits needed for normal operation.
1019 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1023 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1025 if (hw->mac.disable_hw_init_bits)
1028 /* Transmit Descriptor Control 0 */
1029 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1031 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1033 /* Transmit Descriptor Control 1 */
1034 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1036 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1038 /* Transmit Arbitration Control 0 */
1039 reg = E1000_READ_REG(hw, E1000_TARC(0));
1040 reg &= ~(0xF << 27); /* 30:27 */
1041 switch (hw->mac.type) {
1044 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1049 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1051 /* Transmit Arbitration Control 1 */
1052 reg = E1000_READ_REG(hw, E1000_TARC(1));
1053 switch (hw->mac.type) {
1056 reg &= ~((1 << 29) | (1 << 30));
1057 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1058 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1062 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1068 /* Device Control */
1069 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1070 reg = E1000_READ_REG(hw, E1000_CTRL);
1072 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1075 /* Extended Device Control */
1076 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1077 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1080 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1083 /* PCI-Ex Control Register */
1084 if (hw->mac.type == e1000_82574) {
1085 reg = E1000_READ_REG(hw, E1000_GCR);
1087 E1000_WRITE_REG(hw, E1000_GCR, reg);
1095 * e1000_clear_vfta_82571 - Clear VLAN filter table
1096 * @hw: pointer to the HW structure
1098 * Clears the register array which contains the VLAN filter table by
1099 * setting all the values to 0.
1101 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1105 u32 vfta_offset = 0;
1106 u32 vfta_bit_in_reg = 0;
1108 DEBUGFUNC("e1000_clear_vfta_82571");
1110 if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1111 if (hw->mng_cookie.vlan_id != 0) {
1113 * The VFTA is a 4096b bit-field, each identifying
1114 * a single VLAN ID. The following operations
1115 * determine which 32b entry (i.e. offset) into the
1116 * array we want to set the VLAN ID (i.e. bit) of
1117 * the manageability unit.
1119 vfta_offset = (hw->mng_cookie.vlan_id >>
1120 E1000_VFTA_ENTRY_SHIFT) &
1121 E1000_VFTA_ENTRY_MASK;
1122 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1123 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1126 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1128 * If the offset we want to clear is the same offset of the
1129 * manageability VLAN ID, then clear all bits except that of
1130 * the manageability unit.
1132 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1133 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1134 E1000_WRITE_FLUSH(hw);
1139 * e1000_check_mng_mode_82574 - Check manageability is enabled
1140 * @hw: pointer to the HW structure
1142 * Reads the NVM Initialization Control Word 2 and returns TRUE
1143 * (>0) if any manageability is enabled, else FALSE (0).
1145 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1149 DEBUGFUNC("e1000_check_mng_mode_82574");
1151 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1152 return ((data & E1000_NVM_INIT_CTRL2_MNGM) != 0);
1156 * e1000_led_on_82574 - Turn LED on
1157 * @hw: pointer to the HW structure
1161 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1166 DEBUGFUNC("e1000_led_on_82574");
1168 ctrl = hw->mac.ledctl_mode2;
1169 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1171 * If no link, then turn LED on by setting the invert bit
1172 * for each LED that's "on" (0x0E) in ledctl_mode2.
1174 for (i = 0; i < 4; i++)
1175 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1176 E1000_LEDCTL_MODE_LED_ON)
1177 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1179 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1181 return E1000_SUCCESS;
1185 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1186 * @hw: pointer to the HW structure
1187 * @mc_addr_list: array of multicast addresses to program
1188 * @mc_addr_count: number of multicast addresses to program
1189 * @rar_used_count: the first RAR register free to program
1190 * @rar_count: total number of supported Receive Address Registers
1192 * Updates the Receive Address Registers and Multicast Table Array.
1193 * The caller must have a packed mc_addr_list of multicast addresses.
1194 * The parameter rar_count will usually be hw->mac.rar_entry_count
1195 * unless there are workarounds that change this.
1197 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1198 u8 *mc_addr_list, u32 mc_addr_count,
1199 u32 rar_used_count, u32 rar_count)
1201 DEBUGFUNC("e1000_update_mc_addr_list_82571");
1203 if (e1000_get_laa_state_82571(hw))
1206 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1207 rar_used_count, rar_count);
1211 * e1000_setup_link_82571 - Setup flow control and link settings
1212 * @hw: pointer to the HW structure
1214 * Determines which flow control settings to use, then configures flow
1215 * control. Calls the appropriate media-specific link configuration
1216 * function. Assuming the adapter has a valid link partner, a valid link
1217 * should be established. Assumes the hardware has previously been reset
1218 * and the transmitter and receiver are not enabled.
1220 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1222 DEBUGFUNC("e1000_setup_link_82571");
1225 * 82573 does not have a word in the NVM to determine
1226 * the default flow control setting, so we explicitly
1229 if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1230 hw->fc.type == e1000_fc_default)
1231 hw->fc.type = e1000_fc_full;
1233 return e1000_setup_link_generic(hw);
1237 * e1000_setup_copper_link_82571 - Configure copper link settings
1238 * @hw: pointer to the HW structure
1240 * Configures the link for auto-neg or forced speed and duplex. Then we check
1241 * for link, once link is established calls to configure collision distance
1242 * and flow control are called.
1244 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1249 DEBUGFUNC("e1000_setup_copper_link_82571");
1251 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1252 ctrl |= E1000_CTRL_SLU;
1253 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1254 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1256 switch (hw->phy.type) {
1259 ret_val = e1000_copper_link_setup_m88(hw);
1261 case e1000_phy_igp_2:
1262 ret_val = e1000_copper_link_setup_igp(hw);
1263 /* Setup activity LED */
1264 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
1265 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1266 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1267 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
1270 ret_val = -E1000_ERR_PHY;
1277 ret_val = e1000_setup_copper_link_generic(hw);
1284 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1285 * @hw: pointer to the HW structure
1287 * Configures collision distance and flow control for fiber and serdes links.
1288 * Upon successful setup, poll for link.
1290 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1292 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1294 switch (hw->mac.type) {
1298 * If SerDes loopback mode is entered, there is no form
1299 * of reset to take the adapter out of that mode. So we
1300 * have to explicitly take the adapter out of loopback
1301 * mode. This prevents drivers from twiddling their thumbs
1302 * if another tool failed to take it out of loopback mode.
1304 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1310 return e1000_setup_fiber_serdes_link_generic(hw);
1314 * e1000_valid_led_default_82571 - Verify a valid default LED config
1315 * @hw: pointer to the HW structure
1316 * @data: pointer to the NVM (EEPROM)
1318 * Read the EEPROM for the current default LED configuration. If the
1319 * LED configuration is not valid, set to a valid LED configuration.
1321 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1325 DEBUGFUNC("e1000_valid_led_default_82571");
1327 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1329 DEBUGOUT("NVM Read Error\n");
1333 if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1334 *data == ID_LED_RESERVED_F746)
1335 *data = ID_LED_DEFAULT_82573;
1336 else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1337 *data = ID_LED_DEFAULT;
1343 * e1000_get_laa_state_82571 - Get locally administered address state
1344 * @hw: pointer to the HW structure
1346 * Retrieve and return the current locally administered address state.
1348 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1350 struct e1000_dev_spec_82571 *dev_spec;
1353 DEBUGFUNC("e1000_get_laa_state_82571");
1355 if (hw->mac.type != e1000_82571)
1358 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec;
1360 state = dev_spec->laa_is_present;
1367 * e1000_set_laa_state_82571 - Set locally administered address state
1368 * @hw: pointer to the HW structure
1369 * @state: enable/disable locally administered address
1371 * Enable/Disable the current locally administered address state.
1373 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1375 struct e1000_dev_spec_82571 *dev_spec;
1377 DEBUGFUNC("e1000_set_laa_state_82571");
1379 if (hw->mac.type != e1000_82571)
1382 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec;
1384 dev_spec->laa_is_present = state;
1386 /* If workaround is activated... */
1389 * Hold a copy of the LAA in RAR[14] This is done so that
1390 * between the time RAR[0] gets clobbered and the time it
1391 * gets fixed, the actual LAA is in one of the RARs and no
1392 * incoming packets directed to this port are dropped.
1393 * Eventually the LAA will be in RAR[0] and RAR[14].
1395 e1000_rar_set_generic(hw, hw->mac.addr,
1396 hw->mac.rar_entry_count - 1);
1404 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1405 * @hw: pointer to the HW structure
1407 * Verifies that the EEPROM has completed the update. After updating the
1408 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1409 * the checksum fix is not implemented, we need to set the bit and update
1410 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1411 * we need to return bad checksum.
1413 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1415 struct e1000_nvm_info *nvm = &hw->nvm;
1416 s32 ret_val = E1000_SUCCESS;
1419 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1421 if (nvm->type != e1000_nvm_flash_hw)
1425 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1426 * 10h-12h. Checksum may need to be fixed.
1428 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1432 if (!(data & 0x10)) {
1434 * Read 0x23 and check bit 15. This bit is a 1
1435 * when the checksum has already been fixed. If
1436 * the checksum is still wrong and this bit is a
1437 * 1, we need to return bad checksum. Otherwise,
1438 * we need to set this bit to a 1 and update the
1441 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1445 if (!(data & 0x8000)) {
1447 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1450 ret_val = nvm->ops.update(hw);
1459 * e1000_read_mac_addr_82571 - Read device MAC address
1460 * @hw: pointer to the HW structure
1462 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1464 s32 ret_val = E1000_SUCCESS;
1466 DEBUGFUNC("e1000_read_mac_addr_82571");
1467 if (e1000_check_alt_mac_addr_generic(hw))
1468 ret_val = e1000_read_mac_addr_generic(hw);
1474 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1475 * @hw: pointer to the HW structure
1477 * In the case of a PHY power down to save power, or to turn off link during a
1478 * driver unload, or wake on lan is not enabled, remove the link.
1480 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1482 struct e1000_phy_info *phy = &hw->phy;
1483 struct e1000_mac_info *mac = &hw->mac;
1485 if (!(phy->ops.check_reset_block))
1488 /* If the management interface is not enabled, then power down */
1489 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1490 e1000_power_down_phy_copper(hw);
1496 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1497 * @hw: pointer to the HW structure
1499 * Clears the hardware counters by reading the counter registers.
1501 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1505 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1507 e1000_clear_hw_cntrs_base_generic(hw);
1508 temp = E1000_READ_REG(hw, E1000_PRC64);
1509 temp = E1000_READ_REG(hw, E1000_PRC127);
1510 temp = E1000_READ_REG(hw, E1000_PRC255);
1511 temp = E1000_READ_REG(hw, E1000_PRC511);
1512 temp = E1000_READ_REG(hw, E1000_PRC1023);
1513 temp = E1000_READ_REG(hw, E1000_PRC1522);
1514 temp = E1000_READ_REG(hw, E1000_PTC64);
1515 temp = E1000_READ_REG(hw, E1000_PTC127);
1516 temp = E1000_READ_REG(hw, E1000_PTC255);
1517 temp = E1000_READ_REG(hw, E1000_PTC511);
1518 temp = E1000_READ_REG(hw, E1000_PTC1023);
1519 temp = E1000_READ_REG(hw, E1000_PTC1522);
1521 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1522 temp = E1000_READ_REG(hw, E1000_RXERRC);
1523 temp = E1000_READ_REG(hw, E1000_TNCRS);
1524 temp = E1000_READ_REG(hw, E1000_CEXTERR);
1525 temp = E1000_READ_REG(hw, E1000_TSCTC);
1526 temp = E1000_READ_REG(hw, E1000_TSCTFC);
1528 temp = E1000_READ_REG(hw, E1000_MGTPRC);
1529 temp = E1000_READ_REG(hw, E1000_MGTPDC);
1530 temp = E1000_READ_REG(hw, E1000_MGTPTC);
1532 temp = E1000_READ_REG(hw, E1000_IAC);
1533 temp = E1000_READ_REG(hw, E1000_ICRXOC);
1535 temp = E1000_READ_REG(hw, E1000_ICRXPTC);
1536 temp = E1000_READ_REG(hw, E1000_ICRXATC);
1537 temp = E1000_READ_REG(hw, E1000_ICTXPTC);
1538 temp = E1000_READ_REG(hw, E1000_ICTXATC);
1539 temp = E1000_READ_REG(hw, E1000_ICTXQEC);
1540 temp = E1000_READ_REG(hw, E1000_ICTXQMTC);
1541 temp = E1000_READ_REG(hw, E1000_ICRXDMTC);