sys/dev/e1000/e1000_82571.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 /* 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  55 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  56 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  57                                   u16 words, u16 *data);
  58 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  59 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  60 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  61 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  62                                           bool active);
  63 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  64 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  65 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  66 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  67 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  68 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  69 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  70 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  71 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  73 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  74 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  75 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  76 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  77 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  78 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  79                                           bool active);
  80 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  81                                           bool active);
  82 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  83 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  84                                        u16 words, u16 *data);
  85 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  86 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  87
  88 /**
  89  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  90  *  @hw: pointer to the HW structure
  91  **/
  92 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  93 {
  94         struct e1000_phy_info *phy = &hw->phy;
  95         s32 ret_val;
  96
  97         DEBUGFUNC("e1000_init_phy_params_82571");
  98
  99         if (hw->phy.media_type != e1000_media_type_copper) {
 100                 phy->type = e1000_phy_none;
 101                 return E1000_SUCCESS;
 102         }
 103
 104         phy->addr                       = 1;
 105         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 106         phy->reset_delay_us             = 100;
 107
 108         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
 109         phy->ops.reset                  = e1000_phy_hw_reset_generic;
 110         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
 111         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
 112         phy->ops.power_up               = e1000_power_up_phy_copper;
 113         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
 114
 115         switch (hw->mac.type) {
 116         case e1000_82571:
 117         case e1000_82572:
 118                 phy->type               = e1000_phy_igp_2;
 119                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
 120                 phy->ops.get_info       = e1000_get_phy_info_igp;
 121                 phy->ops.check_polarity = e1000_check_polarity_igp;
 122                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 123                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 124                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
 125                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
 126                 phy->ops.acquire        = e1000_get_hw_semaphore;
 127                 phy->ops.release        = e1000_put_hw_semaphore;
 128                 break;
 129         case e1000_82573:
 130                 phy->type               = e1000_phy_m88;
 131                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 132                 phy->ops.get_info       = e1000_get_phy_info_m88;
 133                 phy->ops.check_polarity = e1000_check_polarity_m88;
 134                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 135                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 136                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 137                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 138                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 139                 phy->ops.acquire        = e1000_get_hw_semaphore;
 140                 phy->ops.release        = e1000_put_hw_semaphore;
 141                 break;
 142         case e1000_82574:
 143         case e1000_82583:
 144
 145                 phy->type               = e1000_phy_bm;
 146                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 147                 phy->ops.get_info       = e1000_get_phy_info_m88;
 148                 phy->ops.check_polarity = e1000_check_polarity_m88;
 149                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 150                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 151                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 152                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 153                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 154                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 155                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 156                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 157                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 158                 break;
 159         default:
 160                 return -E1000_ERR_PHY;
 161                 break;
 162         }
 163
 164         /* This can only be done after all function pointers are setup. */
 165         ret_val = e1000_get_phy_id_82571(hw);
 166         if (ret_val) {
 167                 DEBUGOUT("Error getting PHY ID\n");
 168                 return ret_val;
 169         }
 170
 171         /* Verify phy id */
 172         switch (hw->mac.type) {
 173         case e1000_82571:
 174         case e1000_82572:
 175                 if (phy->id != IGP01E1000_I_PHY_ID)
 176                         ret_val = -E1000_ERR_PHY;
 177                 break;
 178         case e1000_82573:
 179                 if (phy->id != M88E1111_I_PHY_ID)
 180                         ret_val = -E1000_ERR_PHY;
 181                 break;
 182         case e1000_82574:
 183         case e1000_82583:
 184                 if (phy->id != BME1000_E_PHY_ID_R2)
 185                         ret_val = -E1000_ERR_PHY;
 186                 break;
 187         default:
 188                 ret_val = -E1000_ERR_PHY;
 189                 break;
 190         }
 191
 192         if (ret_val)
 193                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 194
 195         return ret_val;
 196 }
 197
 198 /**
 199  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 200  *  @hw: pointer to the HW structure
 201  **/
 202 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 203 {
 204         struct e1000_nvm_info *nvm = &hw->nvm;
 205         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 206         u16 size;
 207
 208         DEBUGFUNC("e1000_init_nvm_params_82571");
 209
 210         nvm->opcode_bits = 8;
 211         nvm->delay_usec = 1;
 212         switch (nvm->override) {
 213         case e1000_nvm_override_spi_large:
 214                 nvm->page_size = 32;
 215                 nvm->address_bits = 16;
 216                 break;
 217         case e1000_nvm_override_spi_small:
 218                 nvm->page_size = 8;
 219                 nvm->address_bits = 8;
 220                 break;
 221         default:
 222                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 223                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 224                 break;
 225         }
 226
 227         switch (hw->mac.type) {
 228         case e1000_82573:
 229         case e1000_82574:
 230         case e1000_82583:
 231                 if (((eecd >> 15) & 0x3) == 0x3) {
 232                         nvm->type = e1000_nvm_flash_hw;
 233                         nvm->word_size = 2048;
 234                         /* Autonomous Flash update bit must be cleared due
 235                          * to Flash update issue.
 236                          */
 237                         eecd &= ~E1000_EECD_AUPDEN;
 238                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 239                         break;
 240                 }
 241                 /* Fall Through */
 242         default:
 243                 nvm->type = e1000_nvm_eeprom_spi;
 244                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 245                              E1000_EECD_SIZE_EX_SHIFT);
 246                 /* Added to a constant, "size" becomes the left-shift value
 247                  * for setting word_size.
 248                  */
 249                 size += NVM_WORD_SIZE_BASE_SHIFT;
 250
 251                 /* EEPROM access above 16k is unsupported */
 252                 if (size > 14)
 253                         size = 14;
 254                 nvm->word_size = 1 << size;
 255                 break;
 256         }
 257
 258         /* Function Pointers */
 259         switch (hw->mac.type) {
 260         case e1000_82574:
 261         case e1000_82583:
 262                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 263                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 264                 break;
 265         default:
 266                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 267                 nvm->ops.release = e1000_release_nvm_82571;
 268                 break;
 269         }
 270         nvm->ops.read = e1000_read_nvm_eerd;
 271         nvm->ops.update = e1000_update_nvm_checksum_82571;
 272         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 273         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 274         nvm->ops.write = e1000_write_nvm_82571;
 275
 276         return E1000_SUCCESS;
 277 }
 278
 279 /**
 280  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 281  *  @hw: pointer to the HW structure
 282  **/
 283 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 284 {
 285         struct e1000_mac_info *mac = &hw->mac;
 286         u32 swsm = 0;
 287         u32 swsm2 = 0;
 288         bool force_clear_smbi = FALSE;
 289
 290         DEBUGFUNC("e1000_init_mac_params_82571");
 291
 292         /* Set media type and media-dependent function pointers */
 293         switch (hw->device_id) {
 294         case E1000_DEV_ID_82571EB_FIBER:
 295         case E1000_DEV_ID_82572EI_FIBER:
 296         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 297                 hw->phy.media_type = e1000_media_type_fiber;
 298                 mac->ops.setup_physical_interface =
 299                         e1000_setup_fiber_serdes_link_82571;
 300                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 301                 mac->ops.get_link_up_info =
 302                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 303                 break;
 304         case E1000_DEV_ID_82571EB_SERDES:
 305         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 306         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 307         case E1000_DEV_ID_82572EI_SERDES:
 308                 hw->phy.media_type = e1000_media_type_internal_serdes;
 309                 mac->ops.setup_physical_interface =
 310                         e1000_setup_fiber_serdes_link_82571;
 311                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 312                 mac->ops.get_link_up_info =
 313                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 314                 break;
 315         default:
 316                 hw->phy.media_type = e1000_media_type_copper;
 317                 mac->ops.setup_physical_interface =
 318                         e1000_setup_copper_link_82571;
 319                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 320                 mac->ops.get_link_up_info =
 321                         e1000_get_speed_and_duplex_copper_generic;
 322                 break;
 323         }
 324
 325         /* Set mta register count */
 326         mac->mta_reg_count = 128;
 327         /* Set rar entry count */
 328         mac->rar_entry_count = E1000_RAR_ENTRIES;
 329         /* Set if part includes ASF firmware */
 330         mac->asf_firmware_present = TRUE;
 331         /* Adaptive IFS supported */
 332         mac->adaptive_ifs = TRUE;
 333
 334         /* Function pointers */
 335
 336         /* bus type/speed/width */
 337         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 338         /* reset */
 339         mac->ops.reset_hw = e1000_reset_hw_82571;
 340         /* hw initialization */
 341         mac->ops.init_hw = e1000_init_hw_82571;
 342         /* link setup */
 343         mac->ops.setup_link = e1000_setup_link_82571;
 344         /* multicast address update */
 345         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 346         /* writing VFTA */
 347         mac->ops.write_vfta = e1000_write_vfta_generic;
 348         /* clearing VFTA */
 349         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 350         /* read mac address */
 351         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 352         /* ID LED init */
 353         mac->ops.id_led_init = e1000_id_led_init_generic;
 354         /* setup LED */
 355         mac->ops.setup_led = e1000_setup_led_generic;
 356         /* cleanup LED */
 357         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 358         /* turn off LED */
 359         mac->ops.led_off = e1000_led_off_generic;
 360         /* clear hardware counters */
 361         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 362
 363         /* MAC-specific function pointers */
 364         switch (hw->mac.type) {
 365         case e1000_82573:
 366                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 367                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 368                 mac->ops.led_on = e1000_led_on_generic;
 369                 mac->ops.blink_led = e1000_blink_led_generic;
 370
 371                 /* FWSM register */
 372                 mac->has_fwsm = TRUE;
 373                 /* ARC supported; valid only if manageability features are
 374                  * enabled.
 375                  */
 376                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 377                                               E1000_FWSM_MODE_MASK);
 378                 break;
 379         case e1000_82574:
 380         case e1000_82583:
 381                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 382                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 383                 mac->ops.led_on = e1000_led_on_82574;
 384                 break;
 385         default:
 386                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 387                 mac->ops.led_on = e1000_led_on_generic;
 388                 mac->ops.blink_led = e1000_blink_led_generic;
 389
 390                 /* FWSM register */
 391                 mac->has_fwsm = TRUE;
 392                 break;
 393         }
 394
 395         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 396          * first NVM or PHY access. This should be done for single-port
 397          * devices, and for one port only on dual-port devices so that
 398          * for those devices we can still use the SMBI lock to synchronize
 399          * inter-port accesses to the PHY & NVM.
 400          */
 401         switch (hw->mac.type) {
 402         case e1000_82571:
 403         case e1000_82572:
 404                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 405
 406                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 407                         /* Only do this for the first interface on this card */
 408                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 409                                         E1000_SWSM2_LOCK);
 410                         force_clear_smbi = TRUE;
 411                 } else {
 412                         force_clear_smbi = FALSE;
 413                 }
 414                 break;
 415         default:
 416                 force_clear_smbi = TRUE;
 417                 break;
 418         }
 419
 420         if (force_clear_smbi) {
 421                 /* Make sure SWSM.SMBI is clear */
 422                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 423                 if (swsm & E1000_SWSM_SMBI) {
 424                         /* This bit should not be set on a first interface, and
 425                          * indicates that the bootagent or EFI code has
 426                          * improperly left this bit enabled
 427                          */
 428                         DEBUGOUT("Please update your 82571 Bootagent\n");
 429                 }
 430                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 431         }
 432
 433         /* Initialze device specific counter of SMBI acquisition timeouts. */
 434          hw->dev_spec._82571.smb_counter = 0;
 435
 436         return E1000_SUCCESS;
 437 }
 438
 439 /**
 440  *  e1000_init_function_pointers_82571 - Init func ptrs.
 441  *  @hw: pointer to the HW structure
 442  *
 443  *  Called to initialize all function pointers and parameters.
 444  **/
 445 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 446 {
 447         DEBUGFUNC("e1000_init_function_pointers_82571");
 448
 449         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 450         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 451         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 452 }
 453
 454 /**
 455  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 456  *  @hw: pointer to the HW structure
 457  *
 458  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 459  *  revision in the hardware structure.
 460  **/
 461 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 462 {
 463         struct e1000_phy_info *phy = &hw->phy;
 464         s32 ret_val;
 465         u16 phy_id = 0;
 466
 467         DEBUGFUNC("e1000_get_phy_id_82571");
 468
 469         switch (hw->mac.type) {
 470         case e1000_82571:
 471         case e1000_82572:
 472                 /* The 82571 firmware may still be configuring the PHY.
 473                  * In this case, we cannot access the PHY until the
 474                  * configuration is done.  So we explicitly set the
 475                  * PHY ID.
 476                  */
 477                 phy->id = IGP01E1000_I_PHY_ID;
 478                 break;
 479         case e1000_82573:
 480                 return e1000_get_phy_id(hw);
 481                 break;
 482         case e1000_82574:
 483         case e1000_82583:
 484                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 485                 if (ret_val)
 486                         return ret_val;
 487
 488                 phy->id = (u32)(phy_id << 16);
 489                 usec_delay(20);
 490                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 491                 if (ret_val)
 492                         return ret_val;
 493
 494                 phy->id |= (u32)(phy_id);
 495                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 496                 break;
 497         default:
 498                 return -E1000_ERR_PHY;
 499                 break;
 500         }
 501
 502         return E1000_SUCCESS;
 503 }
 504
 505 /**
 506  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 507  *  @hw: pointer to the HW structure
 508  *
 509  *  Acquire the HW semaphore during reset.
 510  *
 511  **/
 512 static s32
 513 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 514 {
 515         u32 extcnf_ctrl;
 516         s32 i = 0;
 517         /* XXX assert that mutex is held */
 518         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 519
 520         ASSERT_CTX_LOCK_HELD(hw);
 521         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 522         do {
 523                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 524                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 525                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 526
 527                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 528                         break;
 529
 530                 msec_delay(2);
 531                 i++;
 532         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 533
 534         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 535                 /* Release semaphores */
 536                 e1000_put_hw_semaphore_82574(hw);
 537                 DEBUGOUT("Driver can't access the PHY\n");
 538                 return -E1000_ERR_PHY;
 539         }
 540
 541         return E1000_SUCCESS;
 542 }
 543
 544 /**
 545  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 546  *  @hw: pointer to the HW structure
 547  *
 548  *  Release hardware semaphore used during reset.
 549  *
 550  **/
 551 static void
 552 e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 553 {
 554         u32 extcnf_ctrl;
 555
 556         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 557
 558         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 559         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 560         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 561 }
 562
 563 /**
 564  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 565  *  @hw: pointer to the HW structure
 566  *  @active: TRUE to enable LPLU, FALSE to disable
 567  *
 568  *  Sets the LPLU D0 state according to the active flag.
 569  *  LPLU will not be activated unless the
 570  *  device autonegotiation advertisement meets standards of
 571  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 572  *  This is a function pointer entry point only called by
 573  *  PHY setup routines.
 574  **/
 575 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 576 {
 577         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 578
 579         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 580
 581         if (active)
 582                 data |= E1000_PHY_CTRL_D0A_LPLU;
 583         else
 584                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 585
 586         E1000_WRITE_REG(hw, E1000_POEMB, data);
 587         return E1000_SUCCESS;
 588 }
 589
 590 /**
 591  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 592  *  @hw: pointer to the HW structure
 593  *  @active: boolean used to enable/disable lplu
 594  *
 595  *  The low power link up (lplu) state is set to the power management level D3
 596  *  when active is TRUE, else clear lplu for D3. LPLU
 597  *  is used during Dx states where the power conservation is most important.
 598  *  During driver activity, SmartSpeed should be enabled so performance is
 599  *  maintained.
 600  **/
 601 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 602 {
 603         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 604
 605         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 606
 607         if (!active) {
 608                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 609         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 610                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 611                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 612                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 613         }
 614
 615         E1000_WRITE_REG(hw, E1000_POEMB, data);
 616         return E1000_SUCCESS;
 617 }
 618
 619 /**
 620  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 621  *  @hw: pointer to the HW structure
 622  *
 623  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 624  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 625  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 626  *  hardware semaphore.
 627  **/
 628 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 629 {
 630         s32 ret_val;
 631
 632         DEBUGFUNC("e1000_acquire_nvm_82571");
 633
 634         ret_val = e1000_get_hw_semaphore(hw);
 635         if (ret_val)
 636                 return ret_val;
 637
 638         switch (hw->mac.type) {
 639         case e1000_82573:
 640                 break;
 641         default:
 642                 ret_val = e1000_acquire_nvm_generic(hw);
 643                 break;
 644         }
 645
 646         if (ret_val)
 647                 e1000_put_hw_semaphore(hw);
 648
 649         return ret_val;
 650 }
 651
 652 /**
 653  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 654  *  @hw: pointer to the HW structure
 655  *
 656  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 657  **/
 658 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 659 {
 660         DEBUGFUNC("e1000_release_nvm_82571");
 661
 662         e1000_release_nvm_generic(hw);
 663         e1000_put_hw_semaphore(hw);
 664 }
 665
 666 /**
 667  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 668  *  @hw: pointer to the HW structure
 669  *  @offset: offset within the EEPROM to be written to
 670  *  @words: number of words to write
 671  *  @data: 16 bit word(s) to be written to the EEPROM
 672  *
 673  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 674  *
 675  *  If e1000_update_nvm_checksum is not called after this function, the
 676  *  EEPROM will most likely contain an invalid checksum.
 677  **/
 678 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 679                                  u16 *data)
 680 {
 681         s32 ret_val;
 682
 683         DEBUGFUNC("e1000_write_nvm_82571");
 684
 685         switch (hw->mac.type) {
 686         case e1000_82573:
 687         case e1000_82574:
 688         case e1000_82583:
 689                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 690                 break;
 691         case e1000_82571:
 692         case e1000_82572:
 693                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 694                 break;
 695         default:
 696                 ret_val = -E1000_ERR_NVM;
 697                 break;
 698         }
 699
 700         return ret_val;
 701 }
 702
 703 /**
 704  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 705  *  @hw: pointer to the HW structure
 706  *
 707  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 708  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 709  *  value to the EEPROM.
 710  **/
 711 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 712 {
 713         u32 eecd;
 714         s32 ret_val;
 715         u16 i;
 716
 717         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 718
 719         ret_val = e1000_update_nvm_checksum_generic(hw);
 720         if (ret_val)
 721                 return ret_val;
 722
 723         /* If our nvm is an EEPROM, then we're done
 724          * otherwise, commit the checksum to the flash NVM.
 725          */
 726         if (hw->nvm.type != e1000_nvm_flash_hw)
 727                 return E1000_SUCCESS;
 728
 729         /* Check for pending operations. */
 730         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 731                 msec_delay(1);
 732                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 733                         break;
 734         }
 735
 736         if (i == E1000_FLASH_UPDATES)
 737                 return -E1000_ERR_NVM;
 738
 739         /* Reset the firmware if using STM opcode. */
 740         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 741                 /* The enabling of and the actual reset must be done
 742                  * in two write cycles.
 743                  */
 744                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 745                 E1000_WRITE_FLUSH(hw);
 746                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 747         }
 748
 749         /* Commit the write to flash */
 750         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 751         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 752
 753         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 754                 msec_delay(1);
 755                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 756                         break;
 757         }
 758
 759         if (i == E1000_FLASH_UPDATES)
 760                 return -E1000_ERR_NVM;
 761
 762         return E1000_SUCCESS;
 763 }
 764
 765 /**
 766  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 767  *  @hw: pointer to the HW structure
 768  *
 769  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 770  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 771  **/
 772 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 773 {
 774         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 775
 776         if (hw->nvm.type == e1000_nvm_flash_hw)
 777                 e1000_fix_nvm_checksum_82571(hw);
 778
 779         return e1000_validate_nvm_checksum_generic(hw);
 780 }
 781
 782 /**
 783  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 784  *  @hw: pointer to the HW structure
 785  *  @offset: offset within the EEPROM to be written to
 786  *  @words: number of words to write
 787  *  @data: 16 bit word(s) to be written to the EEPROM
 788  *
 789  *  After checking for invalid values, poll the EEPROM to ensure the previous
 790  *  command has completed before trying to write the next word.  After write
 791  *  poll for completion.
 792  *
 793  *  If e1000_update_nvm_checksum is not called after this function, the
 794  *  EEPROM will most likely contain an invalid checksum.
 795  **/
 796 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 797                                       u16 words, u16 *data)
 798 {
 799         struct e1000_nvm_info *nvm = &hw->nvm;
 800         u32 i, eewr = 0;
 801         s32 ret_val = E1000_SUCCESS;
 802
 803         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 804
 805         /* A check for invalid values:  offset too large, too many words,
 806          * and not enough words.
 807          */
 808         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 809             (words == 0)) {
 810                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 811                 return -E1000_ERR_NVM;
 812         }
 813
 814         for (i = 0; i < words; i++) {
 815                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 816                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 817                         E1000_NVM_RW_REG_START);
 818
 819                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 820                 if (ret_val)
 821                         break;
 822
 823                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 824
 825                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 826                 if (ret_val)
 827                         break;
 828         }
 829
 830         return ret_val;
 831 }
 832
 833 /**
 834  *  e1000_get_cfg_done_82571 - Poll for configuration done
 835  *  @hw: pointer to the HW structure
 836  *
 837  *  Reads the management control register for the config done bit to be set.
 838  **/
 839 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 840 {
 841         s32 timeout = PHY_CFG_TIMEOUT;
 842
 843         DEBUGFUNC("e1000_get_cfg_done_82571");
 844
 845         while (timeout) {
 846                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 847                     E1000_NVM_CFG_DONE_PORT_0)
 848                         break;
 849                 msec_delay(1);
 850                 timeout--;
 851         }
 852         if (!timeout) {
 853                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 854                 return -E1000_ERR_RESET;
 855         }
 856
 857         return E1000_SUCCESS;
 858 }
 859
 860 /**
 861  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 862  *  @hw: pointer to the HW structure
 863  *  @active: TRUE to enable LPLU, FALSE to disable
 864  *
 865  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 866  *  this function also disables smart speed and vice versa.  LPLU will not be
 867  *  activated unless the device autonegotiation advertisement meets standards
 868  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 869  *  pointer entry point only called by PHY setup routines.
 870  **/
 871 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 872 {
 873         struct e1000_phy_info *phy = &hw->phy;
 874         s32 ret_val;
 875         u16 data;
 876
 877         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 878
 879         if (!(phy->ops.read_reg))
 880                 return E1000_SUCCESS;
 881
 882         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 883         if (ret_val)
 884                 return ret_val;
 885
 886         if (active) {
 887                 data |= IGP02E1000_PM_D0_LPLU;
 888                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 889                                              data);
 890                 if (ret_val)
 891                         return ret_val;
 892
 893                 /* When LPLU is enabled, we should disable SmartSpeed */
 894                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 895                                             &data);
 896                 if (ret_val)
 897                         return ret_val;
 898                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 899                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 900                                              data);
 901                 if (ret_val)
 902                         return ret_val;
 903         } else {
 904                 data &= ~IGP02E1000_PM_D0_LPLU;
 905                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 906                                              data);
 907                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 908                  * during Dx states where the power conservation is most
 909                  * important.  During driver activity we should enable
 910                  * SmartSpeed, so performance is maintained.
 911                  */
 912                 if (phy->smart_speed == e1000_smart_speed_on) {
 913                         ret_val = phy->ops.read_reg(hw,
 914                                                     IGP01E1000_PHY_PORT_CONFIG,
 915                                                     &data);
 916                         if (ret_val)
 917                                 return ret_val;
 918
 919                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 920                         ret_val = phy->ops.write_reg(hw,
 921                                                      IGP01E1000_PHY_PORT_CONFIG,
 922                                                      data);
 923                         if (ret_val)
 924                                 return ret_val;
 925                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 926                         ret_val = phy->ops.read_reg(hw,
 927                                                     IGP01E1000_PHY_PORT_CONFIG,
 928                                                     &data);
 929                         if (ret_val)
 930                                 return ret_val;
 931
 932                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 933                         ret_val = phy->ops.write_reg(hw,
 934                                                      IGP01E1000_PHY_PORT_CONFIG,
 935                                                      data);
 936                         if (ret_val)
 937                                 return ret_val;
 938                 }
 939         }
 940
 941         return E1000_SUCCESS;
 942 }
 943
 944 /**
 945  *  e1000_reset_hw_82571 - Reset hardware
 946  *  @hw: pointer to the HW structure
 947  *
 948  *  This resets the hardware into a known state.
 949  **/
 950 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 951 {
 952         u32 ctrl, ctrl_ext, eecd, tctl;
 953         s32 ret_val;
 954
 955         DEBUGFUNC("e1000_reset_hw_82571");
 956
 957         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 958          * on the last TLP read/write transaction when MAC is reset.
 959          */
 960         ret_val = e1000_disable_pcie_master_generic(hw);
 961         if (ret_val)
 962                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 963
 964         DEBUGOUT("Masking off all interrupts\n");
 965         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 966
 967         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 968         tctl = E1000_READ_REG(hw, E1000_TCTL);
 969         tctl &= ~E1000_TCTL_EN;
 970         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 971         E1000_WRITE_FLUSH(hw);
 972
 973         msec_delay(10);
 974
 975         /* Must acquire the MDIO ownership before MAC reset.
 976          * Ownership defaults to firmware after a reset.
 977          */
 978         switch (hw->mac.type) {
 979         case e1000_82573:
 980         case e1000_82574:
 981         case e1000_82583:
 982                 ret_val = e1000_get_hw_semaphore_82574(hw);
 983                 break;
 984         default:
 985                 break;
 986         }
 987
 988         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 989
 990         DEBUGOUT("Issuing a global reset to MAC\n");
 991         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 992
 993         /* Must release MDIO ownership and mutex after MAC reset. */
 994         switch (hw->mac.type) {
 995         case e1000_82573:
 996         case e1000_82574:
 997         case e1000_82583:
 998                 /* Release mutex only if the hw semaphore is acquired */
 999                 if (!ret_val)
1000                         e1000_put_hw_semaphore_82574(hw);
1001                 break;
1002         default:
1003                 panic("unknown mac type %x\n", hw->mac.type);
1004                 break;
1005         }
1006
1007         if (hw->nvm.type == e1000_nvm_flash_hw) {
1008                 usec_delay(10);
1009                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1010                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1011                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1012                 E1000_WRITE_FLUSH(hw);
1013         }
1014
1015         ret_val = e1000_get_auto_rd_done_generic(hw);
1016         if (ret_val)
1017                 /* We don't want to continue accessing MAC registers. */
1018                 return ret_val;
1019
1020         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1021          * Need to wait for Phy configuration completion before accessing
1022          * NVM and Phy.
1023          */
1024
1025         switch (hw->mac.type) {
1026         case e1000_82571:
1027         case e1000_82572:
1028                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1029                  * to access the EEPROM.
1030                  */
1031                 eecd = E1000_READ_REG(hw, E1000_EECD);
1032                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1033                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1034                 break;
1035         case e1000_82573:
1036         case e1000_82574:
1037         case e1000_82583:
1038                 msec_delay(25);
1039                 break;
1040         default:
1041                 break;
1042         }
1043
1044         /* Clear any pending interrupt events. */
1045         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1046         E1000_READ_REG(hw, E1000_ICR);
1047
1048         if (hw->mac.type == e1000_82571) {
1049                 /* Install any alternate MAC address into RAR0 */
1050                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1051                 if (ret_val)
1052                         return ret_val;
1053
1054                 e1000_set_laa_state_82571(hw, TRUE);
1055         }
1056
1057         /* Reinitialize the 82571 serdes link state machine */
1058         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1059                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1060
1061         return E1000_SUCCESS;
1062 }
1063
1064 /**
1065  *  e1000_init_hw_82571 - Initialize hardware
1066  *  @hw: pointer to the HW structure
1067  *
1068  *  This inits the hardware readying it for operation.
1069  **/
1070 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1071 {
1072         struct e1000_mac_info *mac = &hw->mac;
1073         u32 reg_data;
1074         s32 ret_val;
1075         u16 i, rar_count = mac->rar_entry_count;
1076
1077         DEBUGFUNC("e1000_init_hw_82571");
1078
1079         e1000_initialize_hw_bits_82571(hw);
1080
1081         /* Initialize identification LED */
1082         ret_val = mac->ops.id_led_init(hw);
1083         /* An error is not fatal and we should not stop init due to this */
1084         if (ret_val)
1085                 DEBUGOUT("Error initializing identification LED\n");
1086
1087         /* Disabling VLAN filtering */
1088         DEBUGOUT("Initializing the IEEE VLAN\n");
1089         mac->ops.clear_vfta(hw);
1090
1091         /* Setup the receive address.
1092          * If, however, a locally administered address was assigned to the
1093          * 82571, we must reserve a RAR for it to work around an issue where
1094          * resetting one port will reload the MAC on the other port.
1095          */
1096         if (e1000_get_laa_state_82571(hw))
1097                 rar_count--;
1098         e1000_init_rx_addrs_generic(hw, rar_count);
1099
1100         /* Zero out the Multicast HASH table */
1101         DEBUGOUT("Zeroing the MTA\n");
1102         for (i = 0; i < mac->mta_reg_count; i++)
1103                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1104
1105         /* Setup link and flow control */
1106         ret_val = mac->ops.setup_link(hw);
1107
1108         /* Set the transmit descriptor write-back policy */
1109         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1110         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1111                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1112         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1113
1114         /* ...for both queues. */
1115         switch (mac->type) {
1116         case e1000_82573:
1117                 e1000_enable_tx_pkt_filtering_generic(hw);
1118                 /* fall through */
1119         case e1000_82574:
1120         case e1000_82583:
1121                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1122                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1123                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1124                 break;
1125         default:
1126                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1127                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1128                             E1000_TXDCTL_FULL_TX_DESC_WB |
1129                             E1000_TXDCTL_COUNT_DESC);
1130                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1131                 break;
1132         }
1133
1134         /* Clear all of the statistics registers (clear on read).  It is
1135          * important that we do this after we have tried to establish link
1136          * because the symbol error count will increment wildly if there
1137          * is no link.
1138          */
1139         e1000_clear_hw_cntrs_82571(hw);
1140
1141         return ret_val;
1142 }
1143
1144 /**
1145  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1146  *  @hw: pointer to the HW structure
1147  *
1148  *  Initializes required hardware-dependent bits needed for normal operation.
1149  **/
1150 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1151 {
1152         u32 reg;
1153
1154         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1155
1156         /* Transmit Descriptor Control 0 */
1157         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1158         reg |= (1 << 22);
1159         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1160
1161         /* Transmit Descriptor Control 1 */
1162         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1163         reg |= (1 << 22);
1164         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1165
1166         /* Transmit Arbitration Control 0 */
1167         reg = E1000_READ_REG(hw, E1000_TARC(0));
1168         reg &= ~(0xF << 27); /* 30:27 */
1169         switch (hw->mac.type) {
1170         case e1000_82571:
1171         case e1000_82572:
1172                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1173                 break;
1174         case e1000_82574:
1175         case e1000_82583:
1176                 reg |= (1 << 26);
1177                 break;
1178         default:
1179                 break;
1180         }
1181         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1182
1183         /* Transmit Arbitration Control 1 */
1184         reg = E1000_READ_REG(hw, E1000_TARC(1));
1185         switch (hw->mac.type) {
1186         case e1000_82571:
1187         case e1000_82572:
1188                 reg &= ~((1 << 29) | (1 << 30));
1189                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1190                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1191                         reg &= ~(1 << 28);
1192                 else
1193                         reg |= (1 << 28);
1194                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1195                 break;
1196         default:
1197                 break;
1198         }
1199
1200         /* Device Control */
1201         switch (hw->mac.type) {
1202         case e1000_82573:
1203         case e1000_82574:
1204         case e1000_82583:
1205                 reg = E1000_READ_REG(hw, E1000_CTRL);
1206                 reg &= ~(1 << 29);
1207                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1208                 break;
1209         default:
1210                 break;
1211         }
1212
1213         /* Extended Device Control */
1214         switch (hw->mac.type) {
1215         case e1000_82573:
1216         case e1000_82574:
1217         case e1000_82583:
1218                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1219                 reg &= ~(1 << 23);
1220                 reg |= (1 << 22);
1221                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1222                 break;
1223         default:
1224                 break;
1225         }
1226
1227         if (hw->mac.type == e1000_82571) {
1228                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1229                 reg |= E1000_PBA_ECC_CORR_EN;
1230                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1231         }
1232
1233         /* Workaround for hardware errata.
1234          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1235          */
1236         if ((hw->mac.type == e1000_82571) ||
1237            (hw->mac.type == e1000_82572)) {
1238                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1239                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1240                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1241         }
1242
1243         /* Disable IPv6 extension header parsing because some malformed
1244          * IPv6 headers can hang the Rx.
1245          */
1246         if (hw->mac.type <= e1000_82573) {
1247                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1248                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1249                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1250         }
1251
1252         /* PCI-Ex Control Registers */
1253         switch (hw->mac.type) {
1254         case e1000_82574:
1255         case e1000_82583:
1256                 reg = E1000_READ_REG(hw, E1000_GCR);
1257                 reg |= (1 << 22);
1258                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1259
1260                 /* Workaround for hardware errata.
1261                  * apply workaround for hardware errata documented in errata
1262                  * docs Fixes issue where some error prone or unreliable PCIe
1263                  * completions are occurring, particularly with ASPM enabled.
1264                  * Without fix, issue can cause Tx timeouts.
1265                  */
1266                 reg = E1000_READ_REG(hw, E1000_GCR2);
1267                 reg |= 1;
1268                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1269                 break;
1270         default:
1271                 break;
1272         }
1273
1274         return;
1275 }
1276
1277 /**
1278  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1279  *  @hw: pointer to the HW structure
1280  *
1281  *  Clears the register array which contains the VLAN filter table by
1282  *  setting all the values to 0.
1283  **/
1284 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1285 {
1286         u32 offset;
1287         u32 vfta_value = 0;
1288         u32 vfta_offset = 0;
1289         u32 vfta_bit_in_reg = 0;
1290
1291         DEBUGFUNC("e1000_clear_vfta_82571");
1292
1293         switch (hw->mac.type) {
1294         case e1000_82573:
1295         case e1000_82574:
1296         case e1000_82583:
1297                 if (hw->mng_cookie.vlan_id != 0) {
1298                         /* The VFTA is a 4096b bit-field, each identifying
1299                          * a single VLAN ID.  The following operations
1300                          * determine which 32b entry (i.e. offset) into the
1301                          * array we want to set the VLAN ID (i.e. bit) of
1302                          * the manageability unit.
1303                          */
1304                         vfta_offset = (hw->mng_cookie.vlan_id >>
1305                                        E1000_VFTA_ENTRY_SHIFT) &
1306                             E1000_VFTA_ENTRY_MASK;
1307                         vfta_bit_in_reg =
1308                             1 << (hw->mng_cookie.vlan_id &
1309                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1310                 }
1311                 break;
1312         default:
1313                 break;
1314         }
1315         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1316                 /* If the offset we want to clear is the same offset of the
1317                  * manageability VLAN ID, then clear all bits except that of
1318                  * the manageability unit.
1319                  */
1320                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1321                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1322                 E1000_WRITE_FLUSH(hw);
1323         }
1324 }
1325
1326 /**
1327  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1328  *  @hw: pointer to the HW structure
1329  *
1330  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1331  *  (>0) if any manageability is enabled, else FALSE (0).
1332  **/
1333 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1334 {
1335         u16 data;
1336         s32 ret_val;
1337
1338         DEBUGFUNC("e1000_check_mng_mode_82574");
1339
1340         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1341         if (ret_val)
1342                 return FALSE;
1343
1344         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1345 }
1346
1347 /**
1348  *  e1000_led_on_82574 - Turn LED on
1349  *  @hw: pointer to the HW structure
1350  *
1351  *  Turn LED on.
1352  **/
1353 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1354 {
1355         u32 ctrl;
1356         u32 i;
1357
1358         DEBUGFUNC("e1000_led_on_82574");
1359
1360         ctrl = hw->mac.ledctl_mode2;
1361         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1362                 /* If no link, then turn LED on by setting the invert bit
1363                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1364                  */
1365                 for (i = 0; i < 4; i++)
1366                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1367                             E1000_LEDCTL_MODE_LED_ON)
1368                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1369         }
1370         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1371
1372         return E1000_SUCCESS;
1373 }
1374
1375 /**
1376  *  e1000_check_phy_82574 - check 82574 phy hung state
1377  *  @hw: pointer to the HW structure
1378  *
1379  *  Returns whether phy is hung or not
1380  **/
1381 bool e1000_check_phy_82574(struct e1000_hw *hw)
1382 {
1383         u16 status_1kbt = 0;
1384         u16 receive_errors = 0;
1385         s32 ret_val;
1386
1387         DEBUGFUNC("e1000_check_phy_82574");
1388
1389         /* Read PHY Receive Error counter first, if its is max - all F's then
1390          * read the Base1000T status register If both are max then PHY is hung.
1391          */
1392         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1393                                        &receive_errors);
1394         if (ret_val)
1395                 return FALSE;
1396         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1397                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1398                                                &status_1kbt);
1399                 if (ret_val)
1400                         return FALSE;
1401                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1402                     E1000_IDLE_ERROR_COUNT_MASK)
1403                         return TRUE;
1404         }
1405
1406         return FALSE;
1407 }
1408
1409
1410 /**
1411  *  e1000_setup_link_82571 - Setup flow control and link settings
1412  *  @hw: pointer to the HW structure
1413  *
1414  *  Determines which flow control settings to use, then configures flow
1415  *  control.  Calls the appropriate media-specific link configuration
1416  *  function.  Assuming the adapter has a valid link partner, a valid link
1417  *  should be established.  Assumes the hardware has previously been reset
1418  *  and the transmitter and receiver are not enabled.
1419  **/
1420 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1421 {
1422         DEBUGFUNC("e1000_setup_link_82571");
1423
1424         /* 82573 does not have a word in the NVM to determine
1425          * the default flow control setting, so we explicitly
1426          * set it to full.
1427          */
1428         switch (hw->mac.type) {
1429         case e1000_82573:
1430         case e1000_82574:
1431         case e1000_82583:
1432                 if (hw->fc.requested_mode == e1000_fc_default)
1433                         hw->fc.requested_mode = e1000_fc_full;
1434                 break;
1435         default:
1436                 break;
1437         }
1438
1439         return e1000_setup_link_generic(hw);
1440 }
1441
1442 /**
1443  *  e1000_setup_copper_link_82571 - Configure copper link settings
1444  *  @hw: pointer to the HW structure
1445  *
1446  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1447  *  for link, once link is established calls to configure collision distance
1448  *  and flow control are called.
1449  **/
1450 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1451 {
1452         u32 ctrl;
1453         s32 ret_val;
1454
1455         DEBUGFUNC("e1000_setup_copper_link_82571");
1456
1457         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1458         ctrl |= E1000_CTRL_SLU;
1459         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1460         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1461
1462         switch (hw->phy.type) {
1463         case e1000_phy_m88:
1464         case e1000_phy_bm:
1465                 ret_val = e1000_copper_link_setup_m88(hw);
1466                 break;
1467         case e1000_phy_igp_2:
1468                 ret_val = e1000_copper_link_setup_igp(hw);
1469                 break;
1470         default:
1471                 return -E1000_ERR_PHY;
1472                 break;
1473         }
1474
1475         if (ret_val)
1476                 return ret_val;
1477
1478         return e1000_setup_copper_link_generic(hw);
1479 }
1480
1481 /**
1482  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1483  *  @hw: pointer to the HW structure
1484  *
1485  *  Configures collision distance and flow control for fiber and serdes links.
1486  *  Upon successful setup, poll for link.
1487  **/
1488 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1489 {
1490         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1491
1492         switch (hw->mac.type) {
1493         case e1000_82571:
1494         case e1000_82572:
1495                 /* If SerDes loopback mode is entered, there is no form
1496                  * of reset to take the adapter out of that mode.  So we
1497                  * have to explicitly take the adapter out of loopback
1498                  * mode.  This prevents drivers from twiddling their thumbs
1499                  * if another tool failed to take it out of loopback mode.
1500                  */
1501                 E1000_WRITE_REG(hw, E1000_SCTL,
1502                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1503                 break;
1504         default:
1505                 break;
1506         }
1507
1508         return e1000_setup_fiber_serdes_link_generic(hw);
1509 }
1510
1511 /**
1512  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1513  *  @hw: pointer to the HW structure
1514  *
1515  *  Reports the link state as up or down.
1516  *
1517  *  If autonegotiation is supported by the link partner, the link state is
1518  *  determined by the result of autonegotiation. This is the most likely case.
1519  *  If autonegotiation is not supported by the link partner, and the link
1520  *  has a valid signal, force the link up.
1521  *
1522  *  The link state is represented internally here by 4 states:
1523  *
1524  *  1) down
1525  *  2) autoneg_progress
1526  *  3) autoneg_complete (the link successfully autonegotiated)
1527  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1528  *
1529  **/
1530 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1531 {
1532         struct e1000_mac_info *mac = &hw->mac;
1533         u32 rxcw;
1534         u32 ctrl;
1535         u32 status;
1536         u32 txcw;
1537         u32 i;
1538         s32 ret_val = E1000_SUCCESS;
1539
1540         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1541
1542         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1543         status = E1000_READ_REG(hw, E1000_STATUS);
1544         E1000_READ_REG(hw, E1000_RXCW);
1545         /* SYNCH bit and IV bit are sticky */
1546         usec_delay(10);
1547         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1548
1549         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1550                 /* Receiver is synchronized with no invalid bits.  */
1551                 switch (mac->serdes_link_state) {
1552                 case e1000_serdes_link_autoneg_complete:
1553                         if (!(status & E1000_STATUS_LU)) {
1554                                 /* We have lost link, retry autoneg before
1555                                  * reporting link failure
1556                                  */
1557                                 mac->serdes_link_state =
1558                                     e1000_serdes_link_autoneg_progress;
1559                                 mac->serdes_has_link = FALSE;
1560                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1561                         } else {
1562                                 mac->serdes_has_link = TRUE;
1563                         }
1564                         break;
1565
1566                 case e1000_serdes_link_forced_up:
1567                         /* If we are receiving /C/ ordered sets, re-enable
1568                          * auto-negotiation in the TXCW register and disable
1569                          * forced link in the Device Control register in an
1570                          * attempt to auto-negotiate with our link partner.
1571                          */
1572                         if (rxcw & E1000_RXCW_C) {
1573                                 /* Enable autoneg, and unforce link up */
1574                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1575                                 E1000_WRITE_REG(hw, E1000_CTRL,
1576                                     (ctrl & ~E1000_CTRL_SLU));
1577                                 mac->serdes_link_state =
1578                                     e1000_serdes_link_autoneg_progress;
1579                                 mac->serdes_has_link = FALSE;
1580                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1581                         } else {
1582                                 mac->serdes_has_link = TRUE;
1583                         }
1584                         break;
1585
1586                 case e1000_serdes_link_autoneg_progress:
1587                         if (rxcw & E1000_RXCW_C) {
1588                                 /* We received /C/ ordered sets, meaning the
1589                                  * link partner has autonegotiated, and we can
1590                                  * trust the Link Up (LU) status bit.
1591                                  */
1592                                 if (status & E1000_STATUS_LU) {
1593                                         mac->serdes_link_state =
1594                                             e1000_serdes_link_autoneg_complete;
1595                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1596                                         mac->serdes_has_link = TRUE;
1597                                 } else {
1598                                         /* Autoneg completed, but failed. */
1599                                         mac->serdes_link_state =
1600                                             e1000_serdes_link_down;
1601                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1602                                 }
1603                         } else {
1604                                 /* The link partner did not autoneg.
1605                                  * Force link up and full duplex, and change
1606                                  * state to forced.
1607                                  */
1608                                 E1000_WRITE_REG(hw, E1000_TXCW,
1609                                 (mac->txcw & ~E1000_TXCW_ANE));
1610                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1611                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1612
1613                                 /* Configure Flow Control after link up. */
1614                                 ret_val =
1615                                     e1000_config_fc_after_link_up_generic(hw);
1616                                 if (ret_val) {
1617                                         DEBUGOUT("Error config flow control\n");
1618                                         break;
1619                                 }
1620                                 mac->serdes_link_state =
1621                                                 e1000_serdes_link_forced_up;
1622                                 mac->serdes_has_link = TRUE;
1623                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1624                         }
1625                         break;
1626
1627                 case e1000_serdes_link_down:
1628                 default:
1629                         /* The link was down but the receiver has now gained
1630                          * valid sync, so lets see if we can bring the link
1631                          * up.
1632                          */
1633                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1634                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1635                                         ~E1000_CTRL_SLU));
1636                         mac->serdes_link_state =
1637                                         e1000_serdes_link_autoneg_progress;
1638                         mac->serdes_has_link = FALSE;
1639                         DEBUGOUT("DOWN      -> AN_PROG\n");
1640                         break;
1641                 }
1642         } else {
1643                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1644                         mac->serdes_has_link = FALSE;
1645                         mac->serdes_link_state = e1000_serdes_link_down;
1646                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1647                 } else {
1648                         /* Check several times, if SYNCH bit and CONFIG
1649                          * bit both are consistently 1 then simply ignore
1650                          * the IV bit and restart Autoneg
1651                          */
1652                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1653                                 usec_delay(10);
1654                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1655                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1656                                     (rxcw & E1000_RXCW_C))
1657                                         continue;
1658
1659                                 if (rxcw & E1000_RXCW_IV) {
1660                                         mac->serdes_has_link = FALSE;
1661                                         mac->serdes_link_state =
1662                                                         e1000_serdes_link_down;
1663                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1664                                         break;
1665                                 }
1666                         }
1667
1668                         if (i == AN_RETRY_COUNT) {
1669                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1670                                 txcw |= E1000_TXCW_ANE;
1671                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1672                                 mac->serdes_link_state =
1673                                         e1000_serdes_link_autoneg_progress;
1674                                 mac->serdes_has_link = FALSE;
1675                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1676                         }
1677                 }
1678         }
1679
1680         return ret_val;
1681 }
1682
1683 /**
1684  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1685  *  @hw: pointer to the HW structure
1686  *  @data: pointer to the NVM (EEPROM)
1687  *
1688  *  Read the EEPROM for the current default LED configuration.  If the
1689  *  LED configuration is not valid, set to a valid LED configuration.
1690  **/
1691 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1692 {
1693         s32 ret_val;
1694
1695         DEBUGFUNC("e1000_valid_led_default_82571");
1696
1697         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1698         if (ret_val) {
1699                 DEBUGOUT("NVM Read Error\n");
1700                 return ret_val;
1701         }
1702
1703         switch (hw->mac.type) {
1704         case e1000_82573:
1705         case e1000_82574:
1706         case e1000_82583:
1707                 if (*data == ID_LED_RESERVED_F746)
1708                         *data = ID_LED_DEFAULT_82573;
1709                 break;
1710         default:
1711                 if (*data == ID_LED_RESERVED_0000 ||
1712                     *data == ID_LED_RESERVED_FFFF)
1713                         *data = ID_LED_DEFAULT;
1714                 break;
1715         }
1716
1717         return E1000_SUCCESS;
1718 }
1719
1720 /**
1721  *  e1000_get_laa_state_82571 - Get locally administered address state
1722  *  @hw: pointer to the HW structure
1723  *
1724  *  Retrieve and return the current locally administered address state.
1725  **/
1726 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1727 {
1728         DEBUGFUNC("e1000_get_laa_state_82571");
1729
1730         if (hw->mac.type != e1000_82571)
1731                 return FALSE;
1732
1733         return hw->dev_spec._82571.laa_is_present;
1734 }
1735
1736 /**
1737  *  e1000_set_laa_state_82571 - Set locally administered address state
1738  *  @hw: pointer to the HW structure
1739  *  @state: enable/disable locally administered address
1740  *
1741  *  Enable/Disable the current locally administered address state.
1742  **/
1743 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1744 {
1745         DEBUGFUNC("e1000_set_laa_state_82571");
1746
1747         if (hw->mac.type != e1000_82571)
1748                 return;
1749
1750         hw->dev_spec._82571.laa_is_present = state;
1751
1752         /* If workaround is activated... */
1753         if (state)
1754                 /* Hold a copy of the LAA in RAR[14] This is done so that
1755                  * between the time RAR[0] gets clobbered and the time it
1756                  * gets fixed, the actual LAA is in one of the RARs and no
1757                  * incoming packets directed to this port are dropped.
1758                  * Eventually the LAA will be in RAR[0] and RAR[14].
1759                  */
1760                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1761                                     hw->mac.rar_entry_count - 1);
1762         return;
1763 }
1764
1765 /**
1766  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1767  *  @hw: pointer to the HW structure
1768  *
1769  *  Verifies that the EEPROM has completed the update.  After updating the
1770  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1771  *  the checksum fix is not implemented, we need to set the bit and update
1772  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1773  *  we need to return bad checksum.
1774  **/
1775 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1776 {
1777         struct e1000_nvm_info *nvm = &hw->nvm;
1778         s32 ret_val;
1779         u16 data;
1780
1781         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1782
1783         if (nvm->type != e1000_nvm_flash_hw)
1784                 return E1000_SUCCESS;
1785
1786         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1787          * 10h-12h.  Checksum may need to be fixed.
1788          */
1789         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1790         if (ret_val)
1791                 return ret_val;
1792
1793         if (!(data & 0x10)) {
1794                 /* Read 0x23 and check bit 15.  This bit is a 1
1795                  * when the checksum has already been fixed.  If
1796                  * the checksum is still wrong and this bit is a
1797                  * 1, we need to return bad checksum.  Otherwise,
1798                  * we need to set this bit to a 1 and update the
1799                  * checksum.
1800                  */
1801                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1802                 if (ret_val)
1803                         return ret_val;
1804
1805                 if (!(data & 0x8000)) {
1806                         data |= 0x8000;
1807                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1808                         if (ret_val)
1809                                 return ret_val;
1810                         ret_val = nvm->ops.update(hw);
1811                         if (ret_val)
1812                                 return ret_val;
1813                 }
1814         }
1815
1816         return E1000_SUCCESS;
1817 }
1818
1819
1820 /**
1821  *  e1000_read_mac_addr_82571 - Read device MAC address
1822  *  @hw: pointer to the HW structure
1823  **/
1824 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1825 {
1826         DEBUGFUNC("e1000_read_mac_addr_82571");
1827
1828         if (hw->mac.type == e1000_82571) {
1829                 s32 ret_val;
1830
1831                 /* If there's an alternate MAC address place it in RAR0
1832                  * so that it will override the Si installed default perm
1833                  * address.
1834                  */
1835                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1836                 if (ret_val)
1837                         return ret_val;
1838         }
1839
1840         return e1000_read_mac_addr_generic(hw);
1841 }
1842
1843 /**
1844  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1845  * @hw: pointer to the HW structure
1846  *
1847  * In the case of a PHY power down to save power, or to turn off link during a
1848  * driver unload, or wake on lan is not enabled, remove the link.
1849  **/
1850 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1851 {
1852         struct e1000_phy_info *phy = &hw->phy;
1853         struct e1000_mac_info *mac = &hw->mac;
1854
1855         if (!phy->ops.check_reset_block)
1856                 return;
1857
1858         /* If the management interface is not enabled, then power down */
1859         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1860                 e1000_power_down_phy_copper(hw);
1861
1862         return;
1863 }
1864
1865 /**
1866  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1867  *  @hw: pointer to the HW structure
1868  *
1869  *  Clears the hardware counters by reading the counter registers.
1870  **/
1871 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1872 {
1873         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1874
1875         e1000_clear_hw_cntrs_base_generic(hw);
1876
1877         E1000_READ_REG(hw, E1000_PRC64);
1878         E1000_READ_REG(hw, E1000_PRC127);
1879         E1000_READ_REG(hw, E1000_PRC255);
1880         E1000_READ_REG(hw, E1000_PRC511);
1881         E1000_READ_REG(hw, E1000_PRC1023);
1882         E1000_READ_REG(hw, E1000_PRC1522);
1883         E1000_READ_REG(hw, E1000_PTC64);
1884         E1000_READ_REG(hw, E1000_PTC127);
1885         E1000_READ_REG(hw, E1000_PTC255);
1886         E1000_READ_REG(hw, E1000_PTC511);
1887         E1000_READ_REG(hw, E1000_PTC1023);
1888         E1000_READ_REG(hw, E1000_PTC1522);
1889
1890         E1000_READ_REG(hw, E1000_ALGNERRC);
1891         E1000_READ_REG(hw, E1000_RXERRC);
1892         E1000_READ_REG(hw, E1000_TNCRS);
1893         E1000_READ_REG(hw, E1000_CEXTERR);
1894         E1000_READ_REG(hw, E1000_TSCTC);
1895         E1000_READ_REG(hw, E1000_TSCTFC);
1896
1897         E1000_READ_REG(hw, E1000_MGTPRC);
1898         E1000_READ_REG(hw, E1000_MGTPDC);
1899         E1000_READ_REG(hw, E1000_MGTPTC);
1900
1901         E1000_READ_REG(hw, E1000_IAC);
1902         E1000_READ_REG(hw, E1000_ICRXOC);
1903
1904         E1000_READ_REG(hw, E1000_ICRXPTC);
1905         E1000_READ_REG(hw, E1000_ICRXATC);
1906         E1000_READ_REG(hw, E1000_ICTXPTC);
1907         E1000_READ_REG(hw, E1000_ICTXATC);
1908         E1000_READ_REG(hw, E1000_ICTXQEC);
1909         E1000_READ_REG(hw, E1000_ICTXQMTC);
1910         E1000_READ_REG(hw, E1000_ICRXDMTC);
1911 }