1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
45 #include "e1000_api.h"
46 #include "e1000_i210.h"
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
56 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
57 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 u16 *speed, u16 *duplex);
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 static void e1000_i2c_start(struct e1000_hw *hw);
108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
117 static bool e1000_get_i2c_data(u32 *i2cctl);
119 static const u16 e1000_82580_rxpbs_table[] = {
120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
121 #define E1000_82580_RXPBS_TABLE_SIZE \
122 (sizeof(e1000_82580_rxpbs_table) / \
123 sizeof(e1000_82580_rxpbs_table[0]))
127 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
128 * @hw: pointer to the HW structure
130 * Called to determine if the I2C pins are being used for I2C or as an
131 * external MDIO interface since the two options are mutually exclusive.
133 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
136 bool ext_mdio = FALSE;
138 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
140 switch (hw->mac.type) {
143 reg = E1000_READ_REG(hw, E1000_MDIC);
144 ext_mdio = !!(reg & E1000_MDIC_DEST);
151 reg = E1000_READ_REG(hw, E1000_MDICNFG);
152 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
161 * e1000_init_phy_params_82575 - Init PHY func ptrs.
162 * @hw: pointer to the HW structure
164 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
166 struct e1000_phy_info *phy = &hw->phy;
167 s32 ret_val = E1000_SUCCESS;
170 DEBUGFUNC("e1000_init_phy_params_82575");
172 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
173 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
175 if (hw->phy.media_type != e1000_media_type_copper) {
176 phy->type = e1000_phy_none;
180 phy->ops.power_up = e1000_power_up_phy_copper;
181 phy->ops.power_down = e1000_power_down_phy_copper_82575;
183 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
184 phy->reset_delay_us = 100;
186 phy->ops.acquire = e1000_acquire_phy_82575;
187 phy->ops.check_reset_block = e1000_check_reset_block_generic;
188 phy->ops.commit = e1000_phy_sw_reset_generic;
189 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
190 phy->ops.release = e1000_release_phy_82575;
192 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
194 if (e1000_sgmii_active_82575(hw)) {
195 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
196 ctrl_ext |= E1000_CTRL_I2C_ENA;
198 phy->ops.reset = e1000_phy_hw_reset_generic;
199 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
203 e1000_reset_mdicnfg_82580(hw);
205 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
206 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
207 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
209 switch (hw->mac.type) {
213 phy->ops.read_reg = e1000_read_phy_reg_82580;
214 phy->ops.write_reg = e1000_write_phy_reg_82580;
218 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
219 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
222 phy->ops.read_reg = e1000_read_phy_reg_igp;
223 phy->ops.write_reg = e1000_write_phy_reg_igp;
227 /* Set phy->phy_addr and phy->id. */
228 ret_val = e1000_get_phy_id_82575(hw);
230 /* Verify phy id and set remaining function pointers */
232 case M88E1543_E_PHY_ID:
233 case M88E1512_E_PHY_ID:
234 case I347AT4_E_PHY_ID:
235 case M88E1112_E_PHY_ID:
236 case M88E1340M_E_PHY_ID:
237 case M88E1111_I_PHY_ID:
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 if (phy->id == I347AT4_E_PHY_ID ||
242 phy->id == M88E1112_E_PHY_ID ||
243 phy->id == M88E1340M_E_PHY_ID)
244 phy->ops.get_cable_length =
245 e1000_get_cable_length_m88_gen2;
246 else if (phy->id == M88E1543_E_PHY_ID ||
247 phy->id == M88E1512_E_PHY_ID)
248 phy->ops.get_cable_length =
249 e1000_get_cable_length_m88_gen2;
251 phy->ops.get_cable_length = e1000_get_cable_length_m88;
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
253 /* Check if this PHY is confgured for media swap. */
254 if (phy->id == M88E1112_E_PHY_ID) {
257 ret_val = phy->ops.write_reg(hw,
258 E1000_M88E1112_PAGE_ADDR,
263 ret_val = phy->ops.read_reg(hw,
264 E1000_M88E1112_MAC_CTRL_1,
269 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
270 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
271 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
272 data == E1000_M88E1112_AUTO_COPPER_BASEX)
273 hw->mac.ops.check_for_link =
274 e1000_check_for_link_media_swap;
276 if (phy->id == M88E1512_E_PHY_ID) {
277 ret_val = e1000_initialize_M88E1512_phy(hw);
282 case IGP03E1000_E_PHY_ID:
283 case IGP04E1000_E_PHY_ID:
284 phy->type = e1000_phy_igp_3;
285 phy->ops.check_polarity = e1000_check_polarity_igp;
286 phy->ops.get_info = e1000_get_phy_info_igp;
287 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
288 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
289 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
290 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
292 case I82580_I_PHY_ID:
294 phy->type = e1000_phy_82580;
295 phy->ops.check_polarity = e1000_check_polarity_82577;
296 phy->ops.force_speed_duplex =
297 e1000_phy_force_speed_duplex_82577;
298 phy->ops.get_cable_length = e1000_get_cable_length_82577;
299 phy->ops.get_info = e1000_get_phy_info_82577;
300 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
301 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
304 phy->type = e1000_phy_i210;
305 phy->ops.check_polarity = e1000_check_polarity_m88;
306 phy->ops.get_info = e1000_get_phy_info_m88;
307 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
308 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
309 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
310 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
313 ret_val = -E1000_ERR_PHY;
322 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
323 * @hw: pointer to the HW structure
325 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
327 struct e1000_nvm_info *nvm = &hw->nvm;
328 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
331 DEBUGFUNC("e1000_init_nvm_params_82575");
333 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
334 E1000_EECD_SIZE_EX_SHIFT);
336 * Added to a constant, "size" becomes the left-shift value
337 * for setting word_size.
339 size += NVM_WORD_SIZE_BASE_SHIFT;
341 /* Just in case size is out of range, cap it to the largest
342 * EEPROM size supported
347 nvm->word_size = 1 << size;
348 if (hw->mac.type < e1000_i210) {
349 nvm->opcode_bits = 8;
352 switch (nvm->override) {
353 case e1000_nvm_override_spi_large:
355 nvm->address_bits = 16;
357 case e1000_nvm_override_spi_small:
359 nvm->address_bits = 8;
362 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
363 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
367 if (nvm->word_size == (1 << 15))
368 nvm->page_size = 128;
370 nvm->type = e1000_nvm_eeprom_spi;
372 nvm->type = e1000_nvm_flash_hw;
375 /* Function Pointers */
376 nvm->ops.acquire = e1000_acquire_nvm_82575;
377 nvm->ops.release = e1000_release_nvm_82575;
378 if (nvm->word_size < (1 << 15))
379 nvm->ops.read = e1000_read_nvm_eerd;
381 nvm->ops.read = e1000_read_nvm_spi;
383 nvm->ops.write = e1000_write_nvm_spi;
384 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
385 nvm->ops.update = e1000_update_nvm_checksum_generic;
386 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
388 /* override generic family function pointers for specific descendants */
389 switch (hw->mac.type) {
391 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
392 nvm->ops.update = e1000_update_nvm_checksum_82580;
396 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
397 nvm->ops.update = e1000_update_nvm_checksum_i350;
403 return E1000_SUCCESS;
407 * e1000_init_mac_params_82575 - Init MAC func ptrs.
408 * @hw: pointer to the HW structure
410 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
412 struct e1000_mac_info *mac = &hw->mac;
413 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
415 DEBUGFUNC("e1000_init_mac_params_82575");
417 /* Derives media type */
418 e1000_get_media_type_82575(hw);
419 /* Set mta register count */
420 mac->mta_reg_count = 128;
421 /* Set uta register count */
422 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
423 /* Set rar entry count */
424 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
425 if (mac->type == e1000_82576)
426 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
427 if (mac->type == e1000_82580)
428 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
429 if (mac->type == e1000_i350 || mac->type == e1000_i354)
430 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
432 /* Enable EEE default settings for EEE supported devices */
433 if (mac->type >= e1000_i350)
434 dev_spec->eee_disable = FALSE;
436 /* Allow a single clear of the SW semaphore on I210 and newer */
437 if (mac->type >= e1000_i210)
438 dev_spec->clear_semaphore_once = TRUE;
440 /* Set if part includes ASF firmware */
441 mac->asf_firmware_present = TRUE;
443 mac->has_fwsm = TRUE;
444 /* ARC supported; valid only if manageability features are enabled. */
445 mac->arc_subsystem_valid =
446 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
448 /* Function pointers */
450 /* bus type/speed/width */
451 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
453 if (mac->type >= e1000_82580)
454 mac->ops.reset_hw = e1000_reset_hw_82580;
456 mac->ops.reset_hw = e1000_reset_hw_82575;
457 /* hw initialization */
458 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
459 mac->ops.init_hw = e1000_init_hw_i210;
461 mac->ops.init_hw = e1000_init_hw_82575;
463 mac->ops.setup_link = e1000_setup_link_generic;
464 /* physical interface link setup */
465 mac->ops.setup_physical_interface =
466 (hw->phy.media_type == e1000_media_type_copper)
467 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
468 /* physical interface shutdown */
469 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
470 /* physical interface power up */
471 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
473 mac->ops.check_for_link = e1000_check_for_link_82575;
474 /* read mac address */
475 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
476 /* configure collision distance */
477 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
478 /* multicast address update */
479 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
480 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
482 mac->ops.write_vfta = e1000_write_vfta_i350;
484 mac->ops.clear_vfta = e1000_clear_vfta_i350;
487 mac->ops.write_vfta = e1000_write_vfta_generic;
489 mac->ops.clear_vfta = e1000_clear_vfta_generic;
491 if (hw->mac.type >= e1000_82580)
492 mac->ops.validate_mdi_setting =
493 e1000_validate_mdi_setting_crossover_generic;
495 mac->ops.id_led_init = e1000_id_led_init_generic;
497 mac->ops.blink_led = e1000_blink_led_generic;
499 mac->ops.setup_led = e1000_setup_led_generic;
501 mac->ops.cleanup_led = e1000_cleanup_led_generic;
502 /* turn on/off LED */
503 mac->ops.led_on = e1000_led_on_generic;
504 mac->ops.led_off = e1000_led_off_generic;
505 /* clear hardware counters */
506 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
508 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
509 /* acquire SW_FW sync */
510 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
511 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
512 if (mac->type >= e1000_i210) {
513 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
514 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
517 /* set lan id for port to determine which phy lock to use */
518 hw->mac.ops.set_lan_id(hw);
520 return E1000_SUCCESS;
524 * e1000_init_function_pointers_82575 - Init func ptrs.
525 * @hw: pointer to the HW structure
527 * Called to initialize all function pointers and parameters.
529 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
531 DEBUGFUNC("e1000_init_function_pointers_82575");
533 hw->mac.ops.init_params = e1000_init_mac_params_82575;
534 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
535 hw->phy.ops.init_params = e1000_init_phy_params_82575;
536 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
540 * e1000_acquire_phy_82575 - Acquire rights to access PHY
541 * @hw: pointer to the HW structure
543 * Acquire access rights to the correct PHY.
545 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
547 u16 mask = E1000_SWFW_PHY0_SM;
549 DEBUGFUNC("e1000_acquire_phy_82575");
551 if (hw->bus.func == E1000_FUNC_1)
552 mask = E1000_SWFW_PHY1_SM;
553 else if (hw->bus.func == E1000_FUNC_2)
554 mask = E1000_SWFW_PHY2_SM;
555 else if (hw->bus.func == E1000_FUNC_3)
556 mask = E1000_SWFW_PHY3_SM;
558 return hw->mac.ops.acquire_swfw_sync(hw, mask);
562 * e1000_release_phy_82575 - Release rights to access PHY
563 * @hw: pointer to the HW structure
565 * A wrapper to release access rights to the correct PHY.
567 static void e1000_release_phy_82575(struct e1000_hw *hw)
569 u16 mask = E1000_SWFW_PHY0_SM;
571 DEBUGFUNC("e1000_release_phy_82575");
573 if (hw->bus.func == E1000_FUNC_1)
574 mask = E1000_SWFW_PHY1_SM;
575 else if (hw->bus.func == E1000_FUNC_2)
576 mask = E1000_SWFW_PHY2_SM;
577 else if (hw->bus.func == E1000_FUNC_3)
578 mask = E1000_SWFW_PHY3_SM;
580 hw->mac.ops.release_swfw_sync(hw, mask);
584 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
585 * @hw: pointer to the HW structure
586 * @offset: register offset to be read
587 * @data: pointer to the read data
589 * Reads the PHY register at offset using the serial gigabit media independent
590 * interface and stores the retrieved information in data.
592 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
595 s32 ret_val = -E1000_ERR_PARAM;
597 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
599 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
600 DEBUGOUT1("PHY Address %u is out of range\n", offset);
604 ret_val = hw->phy.ops.acquire(hw);
608 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
610 hw->phy.ops.release(hw);
617 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
618 * @hw: pointer to the HW structure
619 * @offset: register offset to write to
620 * @data: data to write at register offset
622 * Writes the data to PHY register at the offset using the serial gigabit
623 * media independent interface.
625 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
628 s32 ret_val = -E1000_ERR_PARAM;
630 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
632 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
633 DEBUGOUT1("PHY Address %d is out of range\n", offset);
637 ret_val = hw->phy.ops.acquire(hw);
641 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
643 hw->phy.ops.release(hw);
650 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
651 * @hw: pointer to the HW structure
653 * Retrieves the PHY address and ID for both PHY's which do and do not use
656 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
658 struct e1000_phy_info *phy = &hw->phy;
659 s32 ret_val = E1000_SUCCESS;
664 DEBUGFUNC("e1000_get_phy_id_82575");
666 /* some i354 devices need an extra read for phy id */
667 if (hw->mac.type == e1000_i354)
668 e1000_get_phy_id(hw);
671 * For SGMII PHYs, we try the list of possible addresses until
672 * we find one that works. For non-SGMII PHYs
673 * (e.g. integrated copper PHYs), an address of 1 should
674 * work. The result of this function should mean phy->phy_addr
675 * and phy->id are set correctly.
677 if (!e1000_sgmii_active_82575(hw)) {
679 ret_val = e1000_get_phy_id(hw);
683 if (e1000_sgmii_uses_mdio_82575(hw)) {
684 switch (hw->mac.type) {
687 mdic = E1000_READ_REG(hw, E1000_MDIC);
688 mdic &= E1000_MDIC_PHY_MASK;
689 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
696 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
697 mdic &= E1000_MDICNFG_PHY_MASK;
698 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
701 ret_val = -E1000_ERR_PHY;
705 ret_val = e1000_get_phy_id(hw);
709 /* Power on sgmii phy if it is disabled */
710 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
711 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
712 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
713 E1000_WRITE_FLUSH(hw);
717 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
718 * Therefore, we need to test 1-7
720 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
721 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
722 if (ret_val == E1000_SUCCESS) {
723 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
726 * At the time of this writing, The M88 part is
727 * the only supported SGMII PHY product.
729 if (phy_id == M88_VENDOR)
732 DEBUGOUT1("PHY address %u was unreadable\n",
737 /* A valid PHY type couldn't be found. */
738 if (phy->addr == 8) {
740 ret_val = -E1000_ERR_PHY;
742 ret_val = e1000_get_phy_id(hw);
745 /* restore previous sfp cage power state */
746 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
753 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
754 * @hw: pointer to the HW structure
756 * Resets the PHY using the serial gigabit media independent interface.
758 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
760 s32 ret_val = E1000_SUCCESS;
761 struct e1000_phy_info *phy = &hw->phy;
763 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
766 * This isn't a TRUE "hard" reset, but is the only reset
767 * available to us at this time.
770 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
772 if (!(hw->phy.ops.write_reg))
776 * SFP documentation requires the following to configure the SPF module
777 * to work on SGMII. No further documentation is given.
779 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
783 ret_val = hw->phy.ops.commit(hw);
787 if (phy->id == M88E1512_E_PHY_ID)
788 ret_val = e1000_initialize_M88E1512_phy(hw);
794 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
795 * @hw: pointer to the HW structure
796 * @active: TRUE to enable LPLU, FALSE to disable
798 * Sets the LPLU D0 state according to the active flag. When
799 * activating LPLU this function also disables smart speed
800 * and vice versa. LPLU will not be activated unless the
801 * device autonegotiation advertisement meets standards of
802 * either 10 or 10/100 or 10/100/1000 at all duplexes.
803 * This is a function pointer entry point only called by
804 * PHY setup routines.
806 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
808 struct e1000_phy_info *phy = &hw->phy;
809 s32 ret_val = E1000_SUCCESS;
812 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
814 if (!(hw->phy.ops.read_reg))
817 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
822 data |= IGP02E1000_PM_D0_LPLU;
823 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
828 /* When LPLU is enabled, we should disable SmartSpeed */
829 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
831 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
832 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
837 data &= ~IGP02E1000_PM_D0_LPLU;
838 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
841 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
842 * during Dx states where the power conservation is most
843 * important. During driver activity we should enable
844 * SmartSpeed, so performance is maintained.
846 if (phy->smart_speed == e1000_smart_speed_on) {
847 ret_val = phy->ops.read_reg(hw,
848 IGP01E1000_PHY_PORT_CONFIG,
853 data |= IGP01E1000_PSCFR_SMART_SPEED;
854 ret_val = phy->ops.write_reg(hw,
855 IGP01E1000_PHY_PORT_CONFIG,
859 } else if (phy->smart_speed == e1000_smart_speed_off) {
860 ret_val = phy->ops.read_reg(hw,
861 IGP01E1000_PHY_PORT_CONFIG,
866 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
867 ret_val = phy->ops.write_reg(hw,
868 IGP01E1000_PHY_PORT_CONFIG,
880 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
881 * @hw: pointer to the HW structure
882 * @active: TRUE to enable LPLU, FALSE to disable
884 * Sets the LPLU D0 state according to the active flag. When
885 * activating LPLU this function also disables smart speed
886 * and vice versa. LPLU will not be activated unless the
887 * device autonegotiation advertisement meets standards of
888 * either 10 or 10/100 or 10/100/1000 at all duplexes.
889 * This is a function pointer entry point only called by
890 * PHY setup routines.
892 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
894 struct e1000_phy_info *phy = &hw->phy;
897 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
899 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
902 data |= E1000_82580_PM_D0_LPLU;
904 /* When LPLU is enabled, we should disable SmartSpeed */
905 data &= ~E1000_82580_PM_SPD;
907 data &= ~E1000_82580_PM_D0_LPLU;
910 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
911 * during Dx states where the power conservation is most
912 * important. During driver activity we should enable
913 * SmartSpeed, so performance is maintained.
915 if (phy->smart_speed == e1000_smart_speed_on)
916 data |= E1000_82580_PM_SPD;
917 else if (phy->smart_speed == e1000_smart_speed_off)
918 data &= ~E1000_82580_PM_SPD;
921 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
922 return E1000_SUCCESS;
926 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
927 * @hw: pointer to the HW structure
928 * @active: boolean used to enable/disable lplu
930 * Success returns 0, Failure returns 1
932 * The low power link up (lplu) state is set to the power management level D3
933 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
934 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
935 * is used during Dx states where the power conservation is most important.
936 * During driver activity, SmartSpeed should be enabled so performance is
939 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
941 struct e1000_phy_info *phy = &hw->phy;
944 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
946 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
949 data &= ~E1000_82580_PM_D3_LPLU;
951 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
952 * during Dx states where the power conservation is most
953 * important. During driver activity we should enable
954 * SmartSpeed, so performance is maintained.
956 if (phy->smart_speed == e1000_smart_speed_on)
957 data |= E1000_82580_PM_SPD;
958 else if (phy->smart_speed == e1000_smart_speed_off)
959 data &= ~E1000_82580_PM_SPD;
960 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
961 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
962 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
963 data |= E1000_82580_PM_D3_LPLU;
964 /* When LPLU is enabled, we should disable SmartSpeed */
965 data &= ~E1000_82580_PM_SPD;
968 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
969 return E1000_SUCCESS;
973 * e1000_acquire_nvm_82575 - Request for access to EEPROM
974 * @hw: pointer to the HW structure
976 * Acquire the necessary semaphores for exclusive access to the EEPROM.
977 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
978 * Return successful if access grant bit set, else clear the request for
979 * EEPROM access and return -E1000_ERR_NVM (-1).
981 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
983 s32 ret_val = E1000_SUCCESS;
985 DEBUGFUNC("e1000_acquire_nvm_82575");
987 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
992 * Check if there is some access
993 * error this access may hook on
995 if (hw->mac.type == e1000_i350) {
996 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
997 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
998 E1000_EECD_TIMEOUT)) {
999 /* Clear all access error flags */
1000 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1001 E1000_EECD_ERROR_CLR);
1002 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1006 if (hw->mac.type == e1000_82580) {
1007 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1008 if (eecd & E1000_EECD_BLOCKED) {
1009 /* Clear access error flag */
1010 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1011 E1000_EECD_BLOCKED);
1012 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1016 ret_val = e1000_acquire_nvm_generic(hw);
1018 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1025 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1026 * @hw: pointer to the HW structure
1028 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1029 * then release the semaphores acquired.
1031 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1033 DEBUGFUNC("e1000_release_nvm_82575");
1035 e1000_release_nvm_generic(hw);
1037 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1041 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1042 * @hw: pointer to the HW structure
1043 * @mask: specifies which semaphore to acquire
1045 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1046 * will also specify which port we're acquiring the lock for.
1048 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1052 u32 fwmask = mask << 16;
1053 s32 ret_val = E1000_SUCCESS;
1054 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1056 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1058 while (i < timeout) {
1059 if (e1000_get_hw_semaphore_generic(hw)) {
1060 ret_val = -E1000_ERR_SWFW_SYNC;
1064 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1065 if (!(swfw_sync & (fwmask | swmask)))
1069 * Firmware currently using resource (fwmask)
1070 * or other software thread using resource (swmask)
1072 e1000_put_hw_semaphore_generic(hw);
1078 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1079 ret_val = -E1000_ERR_SWFW_SYNC;
1083 swfw_sync |= swmask;
1084 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1086 e1000_put_hw_semaphore_generic(hw);
1093 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1094 * @hw: pointer to the HW structure
1095 * @mask: specifies which semaphore to acquire
1097 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1098 * will also specify which port we're releasing the lock for.
1100 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1104 DEBUGFUNC("e1000_release_swfw_sync_82575");
1106 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1109 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1111 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1113 e1000_put_hw_semaphore_generic(hw);
1117 * e1000_get_cfg_done_82575 - Read config done bit
1118 * @hw: pointer to the HW structure
1120 * Read the management control register for the config done bit for
1121 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1122 * to read the config done bit, so an error is *ONLY* logged and returns
1123 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1124 * would not be able to be reset or change link.
1126 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1128 s32 timeout = PHY_CFG_TIMEOUT;
1129 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1131 DEBUGFUNC("e1000_get_cfg_done_82575");
1133 if (hw->bus.func == E1000_FUNC_1)
1134 mask = E1000_NVM_CFG_DONE_PORT_1;
1135 else if (hw->bus.func == E1000_FUNC_2)
1136 mask = E1000_NVM_CFG_DONE_PORT_2;
1137 else if (hw->bus.func == E1000_FUNC_3)
1138 mask = E1000_NVM_CFG_DONE_PORT_3;
1140 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1146 DEBUGOUT("MNG configuration cycle has not completed.\n");
1148 /* If EEPROM is not marked present, init the PHY manually */
1149 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1150 (hw->phy.type == e1000_phy_igp_3))
1151 e1000_phy_init_script_igp3(hw);
1153 return E1000_SUCCESS;
1157 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1158 * @hw: pointer to the HW structure
1159 * @speed: stores the current speed
1160 * @duplex: stores the current duplex
1162 * This is a wrapper function, if using the serial gigabit media independent
1163 * interface, use PCS to retrieve the link speed and duplex information.
1164 * Otherwise, use the generic function to get the link speed and duplex info.
1166 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1171 DEBUGFUNC("e1000_get_link_up_info_82575");
1173 if (hw->phy.media_type != e1000_media_type_copper)
1174 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1177 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1184 * e1000_check_for_link_82575 - Check for link
1185 * @hw: pointer to the HW structure
1187 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1188 * use the generic interface for determining link.
1190 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1195 DEBUGFUNC("e1000_check_for_link_82575");
1197 if (hw->phy.media_type != e1000_media_type_copper) {
1198 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1201 * Use this flag to determine if link needs to be checked or
1202 * not. If we have link clear the flag so that we do not
1203 * continue to check for link.
1205 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1208 * Configure Flow Control now that Auto-Neg has completed.
1209 * First, we need to restore the desired flow control
1210 * settings because we may have had to re-autoneg with a
1211 * different link partner.
1213 ret_val = e1000_config_fc_after_link_up_generic(hw);
1215 DEBUGOUT("Error configuring flow control\n");
1217 ret_val = e1000_check_for_copper_link_generic(hw);
1224 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1225 * @hw: pointer to the HW structure
1227 * Poll the M88E1112 interfaces to see which interface achieved link.
1229 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1231 struct e1000_phy_info *phy = &hw->phy;
1236 DEBUGFUNC("e1000_check_for_link_media_swap");
1238 /* Check the copper medium. */
1239 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1243 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1247 if (data & E1000_M88E1112_STATUS_LINK)
1248 port = E1000_MEDIA_PORT_COPPER;
1250 /* Check the other medium. */
1251 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1255 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1259 /* reset page to 0 */
1260 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1264 if (data & E1000_M88E1112_STATUS_LINK)
1265 port = E1000_MEDIA_PORT_OTHER;
1267 /* Determine if a swap needs to happen. */
1268 if (port && (hw->dev_spec._82575.media_port != port)) {
1269 hw->dev_spec._82575.media_port = port;
1270 hw->dev_spec._82575.media_changed = TRUE;
1272 ret_val = e1000_check_for_link_82575(hw);
1275 return E1000_SUCCESS;
1279 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1280 * @hw: pointer to the HW structure
1282 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1286 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1288 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1289 !e1000_sgmii_active_82575(hw))
1292 /* Enable PCS to turn on link */
1293 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1294 reg |= E1000_PCS_CFG_PCS_EN;
1295 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1297 /* Power up the laser */
1298 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1299 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1300 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1302 /* flush the write to verify completion */
1303 E1000_WRITE_FLUSH(hw);
1308 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1309 * @hw: pointer to the HW structure
1310 * @speed: stores the current speed
1311 * @duplex: stores the current duplex
1313 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1314 * duplex, then store the values in the pointers provided.
1316 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1317 u16 *speed, u16 *duplex)
1319 struct e1000_mac_info *mac = &hw->mac;
1323 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1326 * Read the PCS Status register for link state. For non-copper mode,
1327 * the status register is not accurate. The PCS status register is
1330 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1333 * The link up bit determines when link is up on autoneg.
1335 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1336 mac->serdes_has_link = TRUE;
1338 /* Detect and store PCS speed */
1339 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1340 *speed = SPEED_1000;
1341 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1346 /* Detect and store PCS duplex */
1347 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1348 *duplex = FULL_DUPLEX;
1350 *duplex = HALF_DUPLEX;
1352 /* Check if it is an I354 2.5Gb backplane connection. */
1353 if (mac->type == e1000_i354) {
1354 status = E1000_READ_REG(hw, E1000_STATUS);
1355 if ((status & E1000_STATUS_2P5_SKU) &&
1356 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1357 *speed = SPEED_2500;
1358 *duplex = FULL_DUPLEX;
1359 DEBUGOUT("2500 Mbs, ");
1360 DEBUGOUT("Full Duplex\n");
1365 mac->serdes_has_link = FALSE;
1370 return E1000_SUCCESS;
1374 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1375 * @hw: pointer to the HW structure
1377 * In the case of serdes shut down sfp and PCS on driver unload
1378 * when management pass thru is not enabled.
1380 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1384 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1386 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1387 !e1000_sgmii_active_82575(hw))
1390 if (!e1000_enable_mng_pass_thru(hw)) {
1391 /* Disable PCS to turn off link */
1392 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1393 reg &= ~E1000_PCS_CFG_PCS_EN;
1394 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1396 /* shutdown the laser */
1397 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1398 reg |= E1000_CTRL_EXT_SDP3_DATA;
1399 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1401 /* flush the write to verify completion */
1402 E1000_WRITE_FLUSH(hw);
1410 * e1000_reset_hw_82575 - Reset hardware
1411 * @hw: pointer to the HW structure
1413 * This resets the hardware into a known state.
1415 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1420 DEBUGFUNC("e1000_reset_hw_82575");
1423 * Prevent the PCI-E bus from sticking if there is no TLP connection
1424 * on the last TLP read/write transaction when MAC is reset.
1426 ret_val = e1000_disable_pcie_master_generic(hw);
1428 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1430 /* set the completion timeout for interface */
1431 ret_val = e1000_set_pcie_completion_timeout(hw);
1433 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1435 DEBUGOUT("Masking off all interrupts\n");
1436 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1438 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1439 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1440 E1000_WRITE_FLUSH(hw);
1444 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1446 DEBUGOUT("Issuing a global reset to MAC\n");
1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1449 ret_val = e1000_get_auto_rd_done_generic(hw);
1452 * When auto config read does not complete, do not
1453 * return with an error. This can happen in situations
1454 * where there is no eeprom and prevents getting link.
1456 DEBUGOUT("Auto Read Done did not complete\n");
1459 /* If EEPROM is not present, run manual init scripts */
1460 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1461 e1000_reset_init_script_82575(hw);
1463 /* Clear any pending interrupt events. */
1464 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1465 E1000_READ_REG(hw, E1000_ICR);
1467 /* Install any alternate MAC address into RAR0 */
1468 ret_val = e1000_check_alt_mac_addr_generic(hw);
1474 * e1000_init_hw_82575 - Initialize hardware
1475 * @hw: pointer to the HW structure
1477 * This inits the hardware readying it for operation.
1479 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1481 struct e1000_mac_info *mac = &hw->mac;
1483 u16 i, rar_count = mac->rar_entry_count;
1485 DEBUGFUNC("e1000_init_hw_82575");
1487 /* Initialize identification LED */
1488 ret_val = mac->ops.id_led_init(hw);
1490 DEBUGOUT("Error initializing identification LED\n");
1491 /* This is not fatal and we should not stop init due to this */
1494 /* Disabling VLAN filtering */
1495 DEBUGOUT("Initializing the IEEE VLAN\n");
1496 mac->ops.clear_vfta(hw);
1498 /* Setup the receive address */
1499 e1000_init_rx_addrs_generic(hw, rar_count);
1501 /* Zero out the Multicast HASH table */
1502 DEBUGOUT("Zeroing the MTA\n");
1503 for (i = 0; i < mac->mta_reg_count; i++)
1504 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1506 /* Zero out the Unicast HASH table */
1507 DEBUGOUT("Zeroing the UTA\n");
1508 for (i = 0; i < mac->uta_reg_count; i++)
1509 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1511 /* Setup link and flow control */
1512 ret_val = mac->ops.setup_link(hw);
1514 /* Set the default MTU size */
1515 hw->dev_spec._82575.mtu = 1500;
1518 * Clear all of the statistics registers (clear on read). It is
1519 * important that we do this after we have tried to establish link
1520 * because the symbol error count will increment wildly if there
1523 e1000_clear_hw_cntrs_82575(hw);
1529 * e1000_setup_copper_link_82575 - Configure copper link settings
1530 * @hw: pointer to the HW structure
1532 * Configures the link for auto-neg or forced speed and duplex. Then we check
1533 * for link, once link is established calls to configure collision distance
1534 * and flow control are called.
1536 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1542 DEBUGFUNC("e1000_setup_copper_link_82575");
1544 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1545 ctrl |= E1000_CTRL_SLU;
1546 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1547 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1549 /* Clear Go Link Disconnect bit on supported devices */
1550 switch (hw->mac.type) {
1555 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1556 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1557 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1563 ret_val = e1000_setup_serdes_link_82575(hw);
1567 if (e1000_sgmii_active_82575(hw)) {
1568 /* allow time for SFP cage time to power up phy */
1571 ret_val = hw->phy.ops.reset(hw);
1573 DEBUGOUT("Error resetting the PHY.\n");
1577 switch (hw->phy.type) {
1578 case e1000_phy_i210:
1580 switch (hw->phy.id) {
1581 case I347AT4_E_PHY_ID:
1582 case M88E1112_E_PHY_ID:
1583 case M88E1340M_E_PHY_ID:
1584 case M88E1543_E_PHY_ID:
1585 case M88E1512_E_PHY_ID:
1587 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1590 ret_val = e1000_copper_link_setup_m88(hw);
1594 case e1000_phy_igp_3:
1595 ret_val = e1000_copper_link_setup_igp(hw);
1597 case e1000_phy_82580:
1598 ret_val = e1000_copper_link_setup_82577(hw);
1601 ret_val = -E1000_ERR_PHY;
1608 ret_val = e1000_setup_copper_link_generic(hw);
1614 * e1000_setup_serdes_link_82575 - Setup link for serdes
1615 * @hw: pointer to the HW structure
1617 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1618 * used on copper connections where the serialized gigabit media independent
1619 * interface (sgmii), or serdes fiber is being used. Configures the link
1620 * for auto-negotiation or forces speed/duplex.
1622 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1624 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1626 s32 ret_val = E1000_SUCCESS;
1629 DEBUGFUNC("e1000_setup_serdes_link_82575");
1631 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1632 !e1000_sgmii_active_82575(hw))
1636 * On the 82575, SerDes loopback mode persists until it is
1637 * explicitly turned off or a power cycle is performed. A read to
1638 * the register does not indicate its status. Therefore, we ensure
1639 * loopback mode is disabled during initialization.
1641 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1643 /* power on the sfp cage if present */
1644 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1645 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1646 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1648 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1649 ctrl_reg |= E1000_CTRL_SLU;
1651 /* set both sw defined pins on 82575/82576*/
1652 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1653 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1655 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1657 /* default pcs_autoneg to the same setting as mac autoneg */
1658 pcs_autoneg = hw->mac.autoneg;
1660 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1661 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1662 /* sgmii mode lets the phy handle forcing speed/duplex */
1664 /* autoneg time out should be disabled for SGMII mode */
1665 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1667 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1668 /* disable PCS autoneg and support parallel detect only */
1669 pcs_autoneg = FALSE;
1670 /* fall through to default case */
1672 if (hw->mac.type == e1000_82575 ||
1673 hw->mac.type == e1000_82576) {
1674 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1676 DEBUGOUT("NVM Read Error\n");
1680 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1681 pcs_autoneg = FALSE;
1685 * non-SGMII modes only supports a speed of 1000/Full for the
1686 * link so it is best to just force the MAC and let the pcs
1687 * link either autoneg or be forced to 1000/Full
1689 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1690 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1692 /* set speed of 1000/Full if speed/duplex is forced */
1693 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1697 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1700 * New SerDes mode allows for forcing speed or autonegotiating speed
1701 * at 1gb. Autoneg should be default set by most drivers. This is the
1702 * mode that will be compatible with older link partners and switches.
1703 * However, both are supported by the hardware and some drivers/tools.
1705 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1706 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1709 /* Set PCS register for autoneg */
1710 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1711 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1713 /* Disable force flow control for autoneg */
1714 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1716 /* Configure flow control advertisement for autoneg */
1717 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1718 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1720 switch (hw->fc.requested_mode) {
1722 case e1000_fc_rx_pause:
1723 anadv_reg |= E1000_TXCW_ASM_DIR;
1724 anadv_reg |= E1000_TXCW_PAUSE;
1726 case e1000_fc_tx_pause:
1727 anadv_reg |= E1000_TXCW_ASM_DIR;
1733 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1735 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1737 /* Set PCS register for forced link */
1738 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1740 /* Force flow control for forced link */
1741 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1743 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1746 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1748 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1749 e1000_force_mac_fc_generic(hw);
1755 * e1000_get_media_type_82575 - derives current media type.
1756 * @hw: pointer to the HW structure
1758 * The media type is chosen reflecting few settings.
1759 * The following are taken into account:
1760 * - link mode set in the current port Init Control Word #3
1761 * - current link mode settings in CSR register
1762 * - MDIO vs. I2C PHY control interface chosen
1763 * - SFP module media type
1765 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1767 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1768 s32 ret_val = E1000_SUCCESS;
1772 /* Set internal phy as default */
1773 dev_spec->sgmii_active = FALSE;
1774 dev_spec->module_plugged = FALSE;
1776 /* Get CSR setting */
1777 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1779 /* extract link mode setting */
1780 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1782 switch (link_mode) {
1783 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1784 hw->phy.media_type = e1000_media_type_internal_serdes;
1786 case E1000_CTRL_EXT_LINK_MODE_GMII:
1787 hw->phy.media_type = e1000_media_type_copper;
1789 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1790 /* Get phy control interface type set (MDIO vs. I2C)*/
1791 if (e1000_sgmii_uses_mdio_82575(hw)) {
1792 hw->phy.media_type = e1000_media_type_copper;
1793 dev_spec->sgmii_active = TRUE;
1796 /* fall through for I2C based SGMII */
1797 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1798 /* read media type from SFP EEPROM */
1799 ret_val = e1000_set_sfp_media_type_82575(hw);
1800 if ((ret_val != E1000_SUCCESS) ||
1801 (hw->phy.media_type == e1000_media_type_unknown)) {
1803 * If media type was not identified then return media
1804 * type defined by the CTRL_EXT settings.
1806 hw->phy.media_type = e1000_media_type_internal_serdes;
1808 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1809 hw->phy.media_type = e1000_media_type_copper;
1810 dev_spec->sgmii_active = TRUE;
1816 /* do not change link mode for 100BaseFX */
1817 if (dev_spec->eth_flags.e100_base_fx)
1820 /* change current link mode setting */
1821 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1823 if (hw->phy.media_type == e1000_media_type_copper)
1824 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1826 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1828 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1837 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1838 * @hw: pointer to the HW structure
1840 * The media type is chosen based on SFP module.
1841 * compatibility flags retrieved from SFP ID EEPROM.
1843 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1845 s32 ret_val = E1000_ERR_CONFIG;
1847 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1848 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1849 u8 tranceiver_type = 0;
1852 /* Turn I2C interface ON and power on sfp cage */
1853 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1854 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1855 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1857 E1000_WRITE_FLUSH(hw);
1859 /* Read SFP module data */
1861 ret_val = e1000_read_sfp_data_byte(hw,
1862 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1864 if (ret_val == E1000_SUCCESS)
1869 if (ret_val != E1000_SUCCESS)
1872 ret_val = e1000_read_sfp_data_byte(hw,
1873 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1875 if (ret_val != E1000_SUCCESS)
1878 /* Check if there is some SFP module plugged and powered */
1879 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1880 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1881 dev_spec->module_plugged = TRUE;
1882 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1883 hw->phy.media_type = e1000_media_type_internal_serdes;
1884 } else if (eth_flags->e100_base_fx) {
1885 dev_spec->sgmii_active = TRUE;
1886 hw->phy.media_type = e1000_media_type_internal_serdes;
1887 } else if (eth_flags->e1000_base_t) {
1888 dev_spec->sgmii_active = TRUE;
1889 hw->phy.media_type = e1000_media_type_copper;
1891 hw->phy.media_type = e1000_media_type_unknown;
1892 DEBUGOUT("PHY module has not been recognized\n");
1896 hw->phy.media_type = e1000_media_type_unknown;
1898 ret_val = E1000_SUCCESS;
1900 /* Restore I2C interface setting */
1901 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1906 * e1000_valid_led_default_82575 - Verify a valid default LED config
1907 * @hw: pointer to the HW structure
1908 * @data: pointer to the NVM (EEPROM)
1910 * Read the EEPROM for the current default LED configuration. If the
1911 * LED configuration is not valid, set to a valid LED configuration.
1913 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1917 DEBUGFUNC("e1000_valid_led_default_82575");
1919 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1921 DEBUGOUT("NVM Read Error\n");
1925 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1926 switch (hw->phy.media_type) {
1927 case e1000_media_type_internal_serdes:
1928 *data = ID_LED_DEFAULT_82575_SERDES;
1930 case e1000_media_type_copper:
1932 *data = ID_LED_DEFAULT;
1941 * e1000_sgmii_active_82575 - Return sgmii state
1942 * @hw: pointer to the HW structure
1944 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1945 * which can be enabled for use in the embedded applications. Simply
1946 * return the current state of the sgmii interface.
1948 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1950 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1951 return dev_spec->sgmii_active;
1955 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1956 * @hw: pointer to the HW structure
1958 * Inits recommended HW defaults after a reset when there is no EEPROM
1959 * detected. This is only for the 82575.
1961 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1963 DEBUGFUNC("e1000_reset_init_script_82575");
1965 if (hw->mac.type == e1000_82575) {
1966 DEBUGOUT("Running reset init script for 82575\n");
1967 /* SerDes configuration via SERDESCTRL */
1968 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1969 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1970 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1971 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1973 /* CCM configuration via CCMCTL register */
1974 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1975 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1977 /* PCIe lanes configuration */
1978 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1979 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1980 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1981 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1983 /* PCIe PLL Configuration */
1984 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1985 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1986 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1989 return E1000_SUCCESS;
1993 * e1000_read_mac_addr_82575 - Read device MAC address
1994 * @hw: pointer to the HW structure
1996 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2000 DEBUGFUNC("e1000_read_mac_addr_82575");
2003 * If there's an alternate MAC address place it in RAR0
2004 * so that it will override the Si installed default perm
2007 ret_val = e1000_check_alt_mac_addr_generic(hw);
2011 ret_val = e1000_read_mac_addr_generic(hw);
2018 * e1000_config_collision_dist_82575 - Configure collision distance
2019 * @hw: pointer to the HW structure
2021 * Configures the collision distance to the default value and is used
2022 * during link setup.
2024 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2028 DEBUGFUNC("e1000_config_collision_dist_82575");
2030 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2032 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2033 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2035 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2036 E1000_WRITE_FLUSH(hw);
2040 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2041 * @hw: pointer to the HW structure
2043 * In the case of a PHY power down to save power, or to turn off link during a
2044 * driver unload, or wake on lan is not enabled, remove the link.
2046 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2048 struct e1000_phy_info *phy = &hw->phy;
2050 if (!(phy->ops.check_reset_block))
2053 /* If the management interface is not enabled, then power down */
2054 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2055 e1000_power_down_phy_copper(hw);
2061 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2062 * @hw: pointer to the HW structure
2064 * Clears the hardware counters by reading the counter registers.
2066 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2068 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2070 e1000_clear_hw_cntrs_base_generic(hw);
2072 E1000_READ_REG(hw, E1000_PRC64);
2073 E1000_READ_REG(hw, E1000_PRC127);
2074 E1000_READ_REG(hw, E1000_PRC255);
2075 E1000_READ_REG(hw, E1000_PRC511);
2076 E1000_READ_REG(hw, E1000_PRC1023);
2077 E1000_READ_REG(hw, E1000_PRC1522);
2078 E1000_READ_REG(hw, E1000_PTC64);
2079 E1000_READ_REG(hw, E1000_PTC127);
2080 E1000_READ_REG(hw, E1000_PTC255);
2081 E1000_READ_REG(hw, E1000_PTC511);
2082 E1000_READ_REG(hw, E1000_PTC1023);
2083 E1000_READ_REG(hw, E1000_PTC1522);
2085 E1000_READ_REG(hw, E1000_ALGNERRC);
2086 E1000_READ_REG(hw, E1000_RXERRC);
2087 E1000_READ_REG(hw, E1000_TNCRS);
2088 E1000_READ_REG(hw, E1000_CEXTERR);
2089 E1000_READ_REG(hw, E1000_TSCTC);
2090 E1000_READ_REG(hw, E1000_TSCTFC);
2092 E1000_READ_REG(hw, E1000_MGTPRC);
2093 E1000_READ_REG(hw, E1000_MGTPDC);
2094 E1000_READ_REG(hw, E1000_MGTPTC);
2096 E1000_READ_REG(hw, E1000_IAC);
2097 E1000_READ_REG(hw, E1000_ICRXOC);
2099 E1000_READ_REG(hw, E1000_ICRXPTC);
2100 E1000_READ_REG(hw, E1000_ICRXATC);
2101 E1000_READ_REG(hw, E1000_ICTXPTC);
2102 E1000_READ_REG(hw, E1000_ICTXATC);
2103 E1000_READ_REG(hw, E1000_ICTXQEC);
2104 E1000_READ_REG(hw, E1000_ICTXQMTC);
2105 E1000_READ_REG(hw, E1000_ICRXDMTC);
2107 E1000_READ_REG(hw, E1000_CBTMPC);
2108 E1000_READ_REG(hw, E1000_HTDPMC);
2109 E1000_READ_REG(hw, E1000_CBRMPC);
2110 E1000_READ_REG(hw, E1000_RPTHC);
2111 E1000_READ_REG(hw, E1000_HGPTC);
2112 E1000_READ_REG(hw, E1000_HTCBDPC);
2113 E1000_READ_REG(hw, E1000_HGORCL);
2114 E1000_READ_REG(hw, E1000_HGORCH);
2115 E1000_READ_REG(hw, E1000_HGOTCL);
2116 E1000_READ_REG(hw, E1000_HGOTCH);
2117 E1000_READ_REG(hw, E1000_LENERRS);
2119 /* This register should not be read in copper configurations */
2120 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2121 e1000_sgmii_active_82575(hw))
2122 E1000_READ_REG(hw, E1000_SCVPC);
2126 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2127 * @hw: pointer to the HW structure
2129 * After rx enable if managability is enabled then there is likely some
2130 * bad data at the start of the fifo and possibly in the DMA fifo. This
2131 * function clears the fifos and flushes any packets that came in as rx was
2134 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2136 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2139 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2140 if (hw->mac.type != e1000_82575 ||
2141 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2144 /* Disable all Rx queues */
2145 for (i = 0; i < 4; i++) {
2146 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2147 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2148 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2150 /* Poll all queues to verify they have shut down */
2151 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2154 for (i = 0; i < 4; i++)
2155 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2156 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2161 DEBUGOUT("Queue disable timed out after 10ms\n");
2163 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2164 * incoming packets are rejected. Set enable and wait 2ms so that
2165 * any packet that was coming in as RCTL.EN was set is flushed
2167 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2168 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2170 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2171 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2173 rctl = E1000_READ_REG(hw, E1000_RCTL);
2174 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2175 temp_rctl |= E1000_RCTL_LPE;
2177 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2178 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2179 E1000_WRITE_FLUSH(hw);
2182 /* Enable Rx queues that were previously enabled and restore our
2185 for (i = 0; i < 4; i++)
2186 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2187 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2188 E1000_WRITE_FLUSH(hw);
2190 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2191 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2193 /* Flush receive errors generated by workaround */
2194 E1000_READ_REG(hw, E1000_ROC);
2195 E1000_READ_REG(hw, E1000_RNBC);
2196 E1000_READ_REG(hw, E1000_MPC);
2200 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2201 * @hw: pointer to the HW structure
2203 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2204 * however the hardware default for these parts is 500us to 1ms which is less
2205 * than the 10ms recommended by the pci-e spec. To address this we need to
2206 * increase the value to either 10ms to 200ms for capability version 1 config,
2207 * or 16ms to 55ms for version 2.
2209 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2211 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2212 s32 ret_val = E1000_SUCCESS;
2215 /* only take action if timeout value is defaulted to 0 */
2216 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2220 * if capababilities version is type 1 we can write the
2221 * timeout of 10ms to 200ms through the GCR register
2223 if (!(gcr & E1000_GCR_CAP_VER2)) {
2224 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2229 * for version 2 capabilities we need to write the config space
2230 * directly in order to set the completion timeout value for
2233 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2238 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2240 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2243 /* disable completion timeout resend */
2244 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2246 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2251 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2252 * @hw: pointer to the hardware struct
2253 * @enable: state to enter, either enabled or disabled
2254 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2256 * enables/disables L2 switch anti-spoofing functionality.
2258 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2260 u32 reg_val, reg_offset;
2262 switch (hw->mac.type) {
2264 reg_offset = E1000_DTXSWC;
2268 reg_offset = E1000_TXSWC;
2274 reg_val = E1000_READ_REG(hw, reg_offset);
2276 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2277 E1000_DTXSWC_VLAN_SPOOF_MASK);
2278 /* The PF can spoof - it has to in order to
2279 * support emulation mode NICs
2281 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2283 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2284 E1000_DTXSWC_VLAN_SPOOF_MASK);
2286 E1000_WRITE_REG(hw, reg_offset, reg_val);
2290 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2291 * @hw: pointer to the hardware struct
2292 * @enable: state to enter, either enabled or disabled
2294 * enables/disables L2 switch loopback functionality.
2296 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2300 switch (hw->mac.type) {
2302 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2304 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2306 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2307 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2311 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2313 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2315 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2316 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2319 /* Currently no other hardware supports loopback */
2327 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2328 * @hw: pointer to the hardware struct
2329 * @enable: state to enter, either enabled or disabled
2331 * enables/disables replication of packets across multiple pools.
2333 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2335 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2338 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2340 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2342 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2346 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2347 * @hw: pointer to the HW structure
2348 * @offset: register offset to be read
2349 * @data: pointer to the read data
2351 * Reads the MDI control register in the PHY at offset and stores the
2352 * information read to data.
2354 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2358 DEBUGFUNC("e1000_read_phy_reg_82580");
2360 ret_val = hw->phy.ops.acquire(hw);
2364 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2366 hw->phy.ops.release(hw);
2373 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2374 * @hw: pointer to the HW structure
2375 * @offset: register offset to write to
2376 * @data: data to write to register at offset
2378 * Writes data to MDI control register in the PHY at offset.
2380 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2384 DEBUGFUNC("e1000_write_phy_reg_82580");
2386 ret_val = hw->phy.ops.acquire(hw);
2390 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2392 hw->phy.ops.release(hw);
2399 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2400 * @hw: pointer to the HW structure
2402 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2403 * the values found in the EEPROM. This addresses an issue in which these
2404 * bits are not restored from EEPROM after reset.
2406 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2408 s32 ret_val = E1000_SUCCESS;
2412 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2414 if (hw->mac.type != e1000_82580)
2416 if (!e1000_sgmii_active_82575(hw))
2419 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2420 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2423 DEBUGOUT("NVM Read Error\n");
2427 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2428 if (nvm_data & NVM_WORD24_EXT_MDIO)
2429 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2430 if (nvm_data & NVM_WORD24_COM_MDIO)
2431 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2432 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2438 * e1000_reset_hw_82580 - Reset hardware
2439 * @hw: pointer to the HW structure
2441 * This resets function or entire device (all ports, etc.)
2444 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2446 s32 ret_val = E1000_SUCCESS;
2447 /* BH SW mailbox bit in SW_FW_SYNC */
2448 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2450 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2452 DEBUGFUNC("e1000_reset_hw_82580");
2454 hw->dev_spec._82575.global_device_reset = FALSE;
2456 /* 82580 does not reliably do global_device_reset due to hw errata */
2457 if (hw->mac.type == e1000_82580)
2458 global_device_reset = FALSE;
2460 /* Get current control state. */
2461 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2464 * Prevent the PCI-E bus from sticking if there is no TLP connection
2465 * on the last TLP read/write transaction when MAC is reset.
2467 ret_val = e1000_disable_pcie_master_generic(hw);
2469 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2471 DEBUGOUT("Masking off all interrupts\n");
2472 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2473 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2474 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2475 E1000_WRITE_FLUSH(hw);
2479 /* Determine whether or not a global dev reset is requested */
2480 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2482 global_device_reset = FALSE;
2484 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2485 E1000_STAT_DEV_RST_SET))
2486 ctrl |= E1000_CTRL_DEV_RST;
2488 ctrl |= E1000_CTRL_RST;
2490 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2492 switch (hw->device_id) {
2493 case E1000_DEV_ID_DH89XXCC_SGMII:
2496 E1000_WRITE_FLUSH(hw);
2500 /* Add delay to insure DEV_RST or RST has time to complete */
2503 ret_val = e1000_get_auto_rd_done_generic(hw);
2506 * When auto config read does not complete, do not
2507 * return with an error. This can happen in situations
2508 * where there is no eeprom and prevents getting link.
2510 DEBUGOUT("Auto Read Done did not complete\n");
2513 /* clear global device reset status bit */
2514 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2516 /* Clear any pending interrupt events. */
2517 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2518 E1000_READ_REG(hw, E1000_ICR);
2520 ret_val = e1000_reset_mdicnfg_82580(hw);
2522 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2524 /* Install any alternate MAC address into RAR0 */
2525 ret_val = e1000_check_alt_mac_addr_generic(hw);
2527 /* Release semaphore */
2528 if (global_device_reset)
2529 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2535 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2536 * @data: data received by reading RXPBS register
2538 * The 82580 uses a table based approach for packet buffer allocation sizes.
2539 * This function converts the retrieved value into the correct table value
2540 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2541 * 0x0 36 72 144 1 2 4 8 16
2542 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2544 u16 e1000_rxpbs_adjust_82580(u32 data)
2548 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2549 ret_val = e1000_82580_rxpbs_table[data];
2555 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2557 * @hw: pointer to the HW structure
2558 * @offset: offset in words of the checksum protected region
2560 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2561 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2563 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2565 s32 ret_val = E1000_SUCCESS;
2569 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2571 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2572 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2574 DEBUGOUT("NVM Read Error\n");
2577 checksum += nvm_data;
2580 if (checksum != (u16) NVM_SUM) {
2581 DEBUGOUT("NVM Checksum Invalid\n");
2582 ret_val = -E1000_ERR_NVM;
2591 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2593 * @hw: pointer to the HW structure
2594 * @offset: offset in words of the checksum protected region
2596 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2597 * up to the checksum. Then calculates the EEPROM checksum and writes the
2598 * value to the EEPROM.
2600 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2606 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2608 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2609 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2611 DEBUGOUT("NVM Read Error while updating checksum.\n");
2614 checksum += nvm_data;
2616 checksum = (u16) NVM_SUM - checksum;
2617 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2620 DEBUGOUT("NVM Write Error while updating checksum.\n");
2627 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2628 * @hw: pointer to the HW structure
2630 * Calculates the EEPROM section checksum by reading/adding each word of
2631 * the EEPROM and then verifies that the sum of the EEPROM is
2634 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2637 u16 eeprom_regions_count = 1;
2641 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2643 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2645 DEBUGOUT("NVM Read Error\n");
2649 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2650 /* if chekcsums compatibility bit is set validate checksums
2651 * for all 4 ports. */
2652 eeprom_regions_count = 4;
2655 for (j = 0; j < eeprom_regions_count; j++) {
2656 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2657 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2659 if (ret_val != E1000_SUCCESS)
2668 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2669 * @hw: pointer to the HW structure
2671 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2672 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2673 * checksum and writes the value to the EEPROM.
2675 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2681 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2683 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2685 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2689 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2690 /* set compatibility bit to validate checksums appropriately */
2691 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2692 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2695 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2700 for (j = 0; j < 4; j++) {
2701 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2702 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2712 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2713 * @hw: pointer to the HW structure
2715 * Calculates the EEPROM section checksum by reading/adding each word of
2716 * the EEPROM and then verifies that the sum of the EEPROM is
2719 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2721 s32 ret_val = E1000_SUCCESS;
2725 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2727 for (j = 0; j < 4; j++) {
2728 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2729 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2731 if (ret_val != E1000_SUCCESS)
2740 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2741 * @hw: pointer to the HW structure
2743 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2744 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2745 * checksum and writes the value to the EEPROM.
2747 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2749 s32 ret_val = E1000_SUCCESS;
2753 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2755 for (j = 0; j < 4; j++) {
2756 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2757 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2758 if (ret_val != E1000_SUCCESS)
2767 * __e1000_access_emi_reg - Read/write EMI register
2768 * @hw: pointer to the HW structure
2769 * @addr: EMI address to program
2770 * @data: pointer to value to read/write from/to the EMI address
2771 * @read: boolean flag to indicate read or write
2773 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2774 u16 *data, bool read)
2778 DEBUGFUNC("__e1000_access_emi_reg");
2780 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2785 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2787 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2793 * e1000_read_emi_reg - Read Extended Management Interface register
2794 * @hw: pointer to the HW structure
2795 * @addr: EMI address to program
2796 * @data: value to be read from the EMI address
2798 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2800 DEBUGFUNC("e1000_read_emi_reg");
2802 return __e1000_access_emi_reg(hw, addr, data, TRUE);
2806 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2807 * @hw: pointer to the HW structure
2809 * Initialize Marverl 1512 to work correctly with Avoton.
2811 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2813 struct e1000_phy_info *phy = &hw->phy;
2814 s32 ret_val = E1000_SUCCESS;
2816 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2818 /* Check if this is correct PHY. */
2819 if (phy->id != M88E1512_E_PHY_ID)
2822 /* Switch to PHY page 0xFF. */
2823 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2827 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2831 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2835 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2839 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2843 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2847 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2851 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2855 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2859 /* Switch to PHY page 0xFB. */
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2868 /* Switch to PHY page 0x12. */
2869 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2873 /* Change mode to SGMII-to-Copper */
2874 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2878 /* Return the PHY to page 0. */
2879 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2883 ret_val = phy->ops.commit(hw);
2885 DEBUGOUT("Error committing the PHY changes\n");
2895 * e1000_set_eee_i350 - Enable/disable EEE support
2896 * @hw: pointer to the HW structure
2898 * Enable/disable EEE based on setting in dev_spec structure.
2901 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2905 DEBUGFUNC("e1000_set_eee_i350");
2907 if ((hw->mac.type < e1000_i350) ||
2908 (hw->phy.media_type != e1000_media_type_copper))
2910 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2911 eeer = E1000_READ_REG(hw, E1000_EEER);
2913 /* enable or disable per user setting */
2914 if (!(hw->dev_spec._82575.eee_disable)) {
2915 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2917 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2918 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2921 /* This bit should not be set in normal operation. */
2922 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2923 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2925 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2926 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2929 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2930 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2931 E1000_READ_REG(hw, E1000_IPCNFG);
2932 E1000_READ_REG(hw, E1000_EEER);
2935 return E1000_SUCCESS;
2939 * e1000_set_eee_i354 - Enable/disable EEE support
2940 * @hw: pointer to the HW structure
2942 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2945 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2947 struct e1000_phy_info *phy = &hw->phy;
2948 s32 ret_val = E1000_SUCCESS;
2951 DEBUGFUNC("e1000_set_eee_i354");
2953 if ((hw->phy.media_type != e1000_media_type_copper) ||
2954 ((phy->id != M88E1543_E_PHY_ID) &&
2955 (phy->id != M88E1512_E_PHY_ID)))
2958 if (!hw->dev_spec._82575.eee_disable) {
2959 /* Switch to PHY page 18. */
2960 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2964 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2969 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2970 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2975 /* Return the PHY to page 0. */
2976 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2980 /* Turn on EEE advertisement. */
2981 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2982 E1000_EEE_ADV_DEV_I354,
2987 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2988 E1000_EEE_ADV_1000_SUPPORTED;
2989 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2990 E1000_EEE_ADV_DEV_I354,
2993 /* Turn off EEE advertisement. */
2994 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2995 E1000_EEE_ADV_DEV_I354,
3000 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3001 E1000_EEE_ADV_1000_SUPPORTED);
3002 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3003 E1000_EEE_ADV_DEV_I354,
3012 * e1000_get_eee_status_i354 - Get EEE status
3013 * @hw: pointer to the HW structure
3014 * @status: EEE status
3016 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
3019 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3021 struct e1000_phy_info *phy = &hw->phy;
3022 s32 ret_val = E1000_SUCCESS;
3025 DEBUGFUNC("e1000_get_eee_status_i354");
3027 /* Check if EEE is supported on this device. */
3028 if ((hw->phy.media_type != e1000_media_type_copper) ||
3029 ((phy->id != M88E1543_E_PHY_ID) &&
3030 (phy->id != M88E1512_E_PHY_ID)))
3033 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3034 E1000_PCS_STATUS_DEV_I354,
3039 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3040 E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
3046 /* Due to a hw errata, if the host tries to configure the VFTA register
3047 * while performing queries from the BMC or DMA, then the VFTA in some
3048 * cases won't be written.
3052 * e1000_clear_vfta_i350 - Clear VLAN filter table
3053 * @hw: pointer to the HW structure
3055 * Clears the register array which contains the VLAN filter table by
3056 * setting all the values to 0.
3058 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3063 DEBUGFUNC("e1000_clear_vfta_350");
3065 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3066 for (i = 0; i < 10; i++)
3067 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3069 E1000_WRITE_FLUSH(hw);
3074 * e1000_write_vfta_i350 - Write value to VLAN filter table
3075 * @hw: pointer to the HW structure
3076 * @offset: register offset in VLAN filter table
3077 * @value: register value written to VLAN filter table
3079 * Writes value at the given offset in the register array which stores
3080 * the VLAN filter table.
3082 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3086 DEBUGFUNC("e1000_write_vfta_350");
3088 for (i = 0; i < 10; i++)
3089 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3091 E1000_WRITE_FLUSH(hw);
3096 * e1000_set_i2c_bb - Enable I2C bit-bang
3097 * @hw: pointer to the HW structure
3099 * Enable I2C bit-bang interface
3102 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3104 s32 ret_val = E1000_SUCCESS;
3105 u32 ctrl_ext, i2cparams;
3107 DEBUGFUNC("e1000_set_i2c_bb");
3109 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3110 ctrl_ext |= E1000_CTRL_I2C_ENA;
3111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3112 E1000_WRITE_FLUSH(hw);
3114 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3115 i2cparams |= E1000_I2CBB_EN;
3116 i2cparams |= E1000_I2C_DATA_OE_N;
3117 i2cparams |= E1000_I2C_CLK_OE_N;
3118 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3119 E1000_WRITE_FLUSH(hw);
3125 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3126 * @hw: pointer to hardware structure
3127 * @byte_offset: byte offset to read
3128 * @dev_addr: device address
3131 * Performs byte read operation over I2C interface at
3132 * a specified device address.
3134 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3135 u8 dev_addr, u8 *data)
3137 s32 status = E1000_SUCCESS;
3144 DEBUGFUNC("e1000_read_i2c_byte_generic");
3146 swfw_mask = E1000_SWFW_PHY0_SM;
3149 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3151 status = E1000_ERR_SWFW_SYNC;
3155 e1000_i2c_start(hw);
3157 /* Device Address and write indication */
3158 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3159 if (status != E1000_SUCCESS)
3162 status = e1000_get_i2c_ack(hw);
3163 if (status != E1000_SUCCESS)
3166 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3167 if (status != E1000_SUCCESS)
3170 status = e1000_get_i2c_ack(hw);
3171 if (status != E1000_SUCCESS)
3174 e1000_i2c_start(hw);
3176 /* Device Address and read indication */
3177 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3178 if (status != E1000_SUCCESS)
3181 status = e1000_get_i2c_ack(hw);
3182 if (status != E1000_SUCCESS)
3185 status = e1000_clock_in_i2c_byte(hw, data);
3186 if (status != E1000_SUCCESS)
3189 status = e1000_clock_out_i2c_bit(hw, nack);
3190 if (status != E1000_SUCCESS)
3197 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3199 e1000_i2c_bus_clear(hw);
3201 if (retry < max_retry)
3202 DEBUGOUT("I2C byte read error - Retrying.\n");
3204 DEBUGOUT("I2C byte read error.\n");
3206 } while (retry < max_retry);
3208 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3216 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3217 * @hw: pointer to hardware structure
3218 * @byte_offset: byte offset to write
3219 * @dev_addr: device address
3220 * @data: value to write
3222 * Performs byte write operation over I2C interface at
3223 * a specified device address.
3225 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3226 u8 dev_addr, u8 data)
3228 s32 status = E1000_SUCCESS;
3233 DEBUGFUNC("e1000_write_i2c_byte_generic");
3235 swfw_mask = E1000_SWFW_PHY0_SM;
3237 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3238 status = E1000_ERR_SWFW_SYNC;
3239 goto write_byte_out;
3243 e1000_i2c_start(hw);
3245 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3246 if (status != E1000_SUCCESS)
3249 status = e1000_get_i2c_ack(hw);
3250 if (status != E1000_SUCCESS)
3253 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3254 if (status != E1000_SUCCESS)
3257 status = e1000_get_i2c_ack(hw);
3258 if (status != E1000_SUCCESS)
3261 status = e1000_clock_out_i2c_byte(hw, data);
3262 if (status != E1000_SUCCESS)
3265 status = e1000_get_i2c_ack(hw);
3266 if (status != E1000_SUCCESS)
3273 e1000_i2c_bus_clear(hw);
3275 if (retry < max_retry)
3276 DEBUGOUT("I2C byte write error - Retrying.\n");
3278 DEBUGOUT("I2C byte write error.\n");
3279 } while (retry < max_retry);
3281 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3289 * e1000_i2c_start - Sets I2C start condition
3290 * @hw: pointer to hardware structure
3292 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3294 static void e1000_i2c_start(struct e1000_hw *hw)
3296 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3298 DEBUGFUNC("e1000_i2c_start");
3300 /* Start condition must begin with data and clock high */
3301 e1000_set_i2c_data(hw, &i2cctl, 1);
3302 e1000_raise_i2c_clk(hw, &i2cctl);
3304 /* Setup time for start condition (4.7us) */
3305 usec_delay(E1000_I2C_T_SU_STA);
3307 e1000_set_i2c_data(hw, &i2cctl, 0);
3309 /* Hold time for start condition (4us) */
3310 usec_delay(E1000_I2C_T_HD_STA);
3312 e1000_lower_i2c_clk(hw, &i2cctl);
3314 /* Minimum low period of clock is 4.7 us */
3315 usec_delay(E1000_I2C_T_LOW);
3320 * e1000_i2c_stop - Sets I2C stop condition
3321 * @hw: pointer to hardware structure
3323 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3325 static void e1000_i2c_stop(struct e1000_hw *hw)
3327 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3329 DEBUGFUNC("e1000_i2c_stop");
3331 /* Stop condition must begin with data low and clock high */
3332 e1000_set_i2c_data(hw, &i2cctl, 0);
3333 e1000_raise_i2c_clk(hw, &i2cctl);
3335 /* Setup time for stop condition (4us) */
3336 usec_delay(E1000_I2C_T_SU_STO);
3338 e1000_set_i2c_data(hw, &i2cctl, 1);
3340 /* bus free time between stop and start (4.7us)*/
3341 usec_delay(E1000_I2C_T_BUF);
3345 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3346 * @hw: pointer to hardware structure
3347 * @data: data byte to clock in
3349 * Clocks in one byte data via I2C data/clock
3351 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3356 DEBUGFUNC("e1000_clock_in_i2c_byte");
3359 for (i = 7; i >= 0; i--) {
3360 e1000_clock_in_i2c_bit(hw, &bit);
3364 return E1000_SUCCESS;
3368 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3369 * @hw: pointer to hardware structure
3370 * @data: data byte clocked out
3372 * Clocks out one byte data via I2C data/clock
3374 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3376 s32 status = E1000_SUCCESS;
3381 DEBUGFUNC("e1000_clock_out_i2c_byte");
3383 for (i = 7; i >= 0; i--) {
3384 bit = (data >> i) & 0x1;
3385 status = e1000_clock_out_i2c_bit(hw, bit);
3387 if (status != E1000_SUCCESS)
3391 /* Release SDA line (set high) */
3392 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3394 i2cctl |= E1000_I2C_DATA_OE_N;
3395 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3396 E1000_WRITE_FLUSH(hw);
3402 * e1000_get_i2c_ack - Polls for I2C ACK
3403 * @hw: pointer to hardware structure
3405 * Clocks in/out one bit via I2C data/clock
3407 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3409 s32 status = E1000_SUCCESS;
3411 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3415 DEBUGFUNC("e1000_get_i2c_ack");
3417 e1000_raise_i2c_clk(hw, &i2cctl);
3419 /* Minimum high period of clock is 4us */
3420 usec_delay(E1000_I2C_T_HIGH);
3422 /* Wait until SCL returns high */
3423 for (i = 0; i < timeout; i++) {
3425 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3426 if (i2cctl & E1000_I2C_CLK_IN)
3429 if (!(i2cctl & E1000_I2C_CLK_IN))
3430 return E1000_ERR_I2C;
3432 ack = e1000_get_i2c_data(&i2cctl);
3434 DEBUGOUT("I2C ack was not received.\n");
3435 status = E1000_ERR_I2C;
3438 e1000_lower_i2c_clk(hw, &i2cctl);
3440 /* Minimum low period of clock is 4.7 us */
3441 usec_delay(E1000_I2C_T_LOW);
3447 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3448 * @hw: pointer to hardware structure
3449 * @data: read data value
3451 * Clocks in one bit via I2C data/clock
3453 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3455 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3457 DEBUGFUNC("e1000_clock_in_i2c_bit");
3459 e1000_raise_i2c_clk(hw, &i2cctl);
3461 /* Minimum high period of clock is 4us */
3462 usec_delay(E1000_I2C_T_HIGH);
3464 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3465 *data = e1000_get_i2c_data(&i2cctl);
3467 e1000_lower_i2c_clk(hw, &i2cctl);
3469 /* Minimum low period of clock is 4.7 us */
3470 usec_delay(E1000_I2C_T_LOW);
3472 return E1000_SUCCESS;
3476 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3477 * @hw: pointer to hardware structure
3478 * @data: data value to write
3480 * Clocks out one bit via I2C data/clock
3482 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3485 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3487 DEBUGFUNC("e1000_clock_out_i2c_bit");
3489 status = e1000_set_i2c_data(hw, &i2cctl, data);
3490 if (status == E1000_SUCCESS) {
3491 e1000_raise_i2c_clk(hw, &i2cctl);
3493 /* Minimum high period of clock is 4us */
3494 usec_delay(E1000_I2C_T_HIGH);
3496 e1000_lower_i2c_clk(hw, &i2cctl);
3498 /* Minimum low period of clock is 4.7 us.
3499 * This also takes care of the data hold time.
3501 usec_delay(E1000_I2C_T_LOW);
3503 status = E1000_ERR_I2C;
3504 DEBUGOUT1("I2C data was not set to %X\n", data);
3510 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3511 * @hw: pointer to hardware structure
3512 * @i2cctl: Current value of I2CCTL register
3514 * Raises the I2C clock line '0'->'1'
3516 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3518 DEBUGFUNC("e1000_raise_i2c_clk");
3520 *i2cctl |= E1000_I2C_CLK_OUT;
3521 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3522 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3523 E1000_WRITE_FLUSH(hw);
3525 /* SCL rise time (1000ns) */
3526 usec_delay(E1000_I2C_T_RISE);
3530 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3531 * @hw: pointer to hardware structure
3532 * @i2cctl: Current value of I2CCTL register
3534 * Lowers the I2C clock line '1'->'0'
3536 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3539 DEBUGFUNC("e1000_lower_i2c_clk");
3541 *i2cctl &= ~E1000_I2C_CLK_OUT;
3542 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3543 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3544 E1000_WRITE_FLUSH(hw);
3546 /* SCL fall time (300ns) */
3547 usec_delay(E1000_I2C_T_FALL);
3551 * e1000_set_i2c_data - Sets the I2C data bit
3552 * @hw: pointer to hardware structure
3553 * @i2cctl: Current value of I2CCTL register
3554 * @data: I2C data value (0 or 1) to set
3556 * Sets the I2C data bit
3558 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3560 s32 status = E1000_SUCCESS;
3562 DEBUGFUNC("e1000_set_i2c_data");
3565 *i2cctl |= E1000_I2C_DATA_OUT;
3567 *i2cctl &= ~E1000_I2C_DATA_OUT;
3569 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3570 *i2cctl |= E1000_I2C_CLK_OE_N;
3571 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3572 E1000_WRITE_FLUSH(hw);
3574 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3575 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3577 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3578 if (data != e1000_get_i2c_data(i2cctl)) {
3579 status = E1000_ERR_I2C;
3580 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3587 * e1000_get_i2c_data - Reads the I2C SDA data bit
3588 * @hw: pointer to hardware structure
3589 * @i2cctl: Current value of I2CCTL register
3591 * Returns the I2C data bit value
3593 static bool e1000_get_i2c_data(u32 *i2cctl)
3597 DEBUGFUNC("e1000_get_i2c_data");
3599 if (*i2cctl & E1000_I2C_DATA_IN)
3608 * e1000_i2c_bus_clear - Clears the I2C bus
3609 * @hw: pointer to hardware structure
3611 * Clears the I2C bus by sending nine clock pulses.
3612 * Used when data line is stuck low.
3614 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3616 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3619 DEBUGFUNC("e1000_i2c_bus_clear");
3621 e1000_i2c_start(hw);
3623 e1000_set_i2c_data(hw, &i2cctl, 1);
3625 for (i = 0; i < 9; i++) {
3626 e1000_raise_i2c_clk(hw, &i2cctl);
3628 /* Min high period of clock is 4us */
3629 usec_delay(E1000_I2C_T_HIGH);
3631 e1000_lower_i2c_clk(hw, &i2cctl);
3633 /* Min low period of clock is 4.7us*/
3634 usec_delay(E1000_I2C_T_LOW);
3637 e1000_i2c_start(hw);
3639 /* Put the i2c bus back to default state */