1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
37 * 82575EB Gigabit Network Connection
38 * 82575EB Gigabit Backplane Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter
42 * 82580 Gigabit Network Connection
43 * I350 Gigabit Network Connection
46 #include "e1000_api.h"
47 #include "e1000_i210.h"
49 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
50 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
51 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 static void e1000_release_nvm_82575(struct e1000_hw *hw);
53 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
86 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
87 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
88 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
89 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
90 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
91 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
92 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
93 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
94 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
96 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
98 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
99 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
100 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
102 static void e1000_i2c_start(struct e1000_hw *hw);
103 static void e1000_i2c_stop(struct e1000_hw *hw);
104 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
105 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
106 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
107 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
108 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
109 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
111 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
112 static bool e1000_get_i2c_data(u32 *i2cctl);
114 static const u16 e1000_82580_rxpbs_table[] = {
115 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
116 #define E1000_82580_RXPBS_TABLE_SIZE \
117 (sizeof(e1000_82580_rxpbs_table) / \
118 sizeof(e1000_82580_rxpbs_table[0]))
122 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
123 * @hw: pointer to the HW structure
125 * Called to determine if the I2C pins are being used for I2C or as an
126 * external MDIO interface since the two options are mutually exclusive.
128 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
131 bool ext_mdio = false;
133 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
135 switch (hw->mac.type) {
138 reg = E1000_READ_REG(hw, E1000_MDIC);
139 ext_mdio = !!(reg & E1000_MDIC_DEST);
146 reg = E1000_READ_REG(hw, E1000_MDICNFG);
147 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
156 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
157 * @hw: pointer to the HW structure
159 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
161 struct e1000_phy_info *phy = &hw->phy;
162 s32 ret_val = E1000_SUCCESS;
165 DEBUGFUNC("e1000_init_phy_params_82575");
167 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
168 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
170 if (hw->phy.media_type != e1000_media_type_copper) {
171 phy->type = e1000_phy_none;
175 phy->ops.power_up = e1000_power_up_phy_copper;
176 phy->ops.power_down = e1000_power_down_phy_copper_base;
178 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
179 phy->reset_delay_us = 100;
181 phy->ops.acquire = e1000_acquire_phy_base;
182 phy->ops.check_reset_block = e1000_check_reset_block_generic;
183 phy->ops.commit = e1000_phy_sw_reset_generic;
184 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
185 phy->ops.release = e1000_release_phy_base;
187 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
189 if (e1000_sgmii_active_82575(hw)) {
190 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
191 ctrl_ext |= E1000_CTRL_I2C_ENA;
193 phy->ops.reset = e1000_phy_hw_reset_generic;
194 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
197 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
198 e1000_reset_mdicnfg_82580(hw);
200 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
201 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
202 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
204 switch (hw->mac.type) {
208 phy->ops.read_reg = e1000_read_phy_reg_82580;
209 phy->ops.write_reg = e1000_write_phy_reg_82580;
213 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
214 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
217 phy->ops.read_reg = e1000_read_phy_reg_igp;
218 phy->ops.write_reg = e1000_write_phy_reg_igp;
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = e1000_get_phy_id_82575(hw);
225 /* Verify phy id and set remaining function pointers */
227 case M88E1543_E_PHY_ID:
228 case M88E1512_E_PHY_ID:
229 case I347AT4_E_PHY_ID:
230 case M88E1112_E_PHY_ID:
231 case M88E1340M_E_PHY_ID:
232 phy->type = e1000_phy_m88;
233 phy->ops.check_polarity = e1000_check_polarity_m88;
234 phy->ops.get_info = e1000_get_phy_info_m88;
235 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
236 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
238 case M88E1111_I_PHY_ID:
239 phy->type = e1000_phy_m88;
240 phy->ops.check_polarity = e1000_check_polarity_m88;
241 phy->ops.get_info = e1000_get_phy_info_m88;
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
245 case IGP03E1000_E_PHY_ID:
246 case IGP04E1000_E_PHY_ID:
247 phy->type = e1000_phy_igp_3;
248 phy->ops.check_polarity = e1000_check_polarity_igp;
249 phy->ops.get_info = e1000_get_phy_info_igp;
250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
252 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
253 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
255 case I82580_I_PHY_ID:
257 phy->type = e1000_phy_82580;
258 phy->ops.check_polarity = e1000_check_polarity_82577;
259 phy->ops.get_info = e1000_get_phy_info_82577;
260 phy->ops.get_cable_length = e1000_get_cable_length_82577;
261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
263 phy->ops.force_speed_duplex =
264 e1000_phy_force_speed_duplex_82577;
267 phy->type = e1000_phy_i210;
268 phy->ops.check_polarity = e1000_check_polarity_m88;
269 phy->ops.get_info = e1000_get_phy_info_m88;
270 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
276 ret_val = -E1000_ERR_PHY;
280 /* Check if this PHY is configured for media swap. */
282 case M88E1112_E_PHY_ID:
286 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
289 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
294 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
295 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
296 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
297 data == E1000_M88E1112_AUTO_COPPER_BASEX)
298 hw->mac.ops.check_for_link =
299 e1000_check_for_link_media_swap;
302 case M88E1512_E_PHY_ID:
304 ret_val = e1000_initialize_M88E1512_phy(hw);
307 case M88E1543_E_PHY_ID:
309 ret_val = e1000_initialize_M88E1543_phy(hw);
321 * e1000_init_mac_params_82575 - Init MAC func ptrs.
322 * @hw: pointer to the HW structure
324 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
326 struct e1000_mac_info *mac = &hw->mac;
327 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
329 DEBUGFUNC("e1000_init_mac_params_82575");
331 /* Initialize function pointer */
332 e1000_init_mac_ops_generic(hw);
334 /* Derives media type */
335 e1000_get_media_type_82575(hw);
336 /* Set MTA register count */
337 mac->mta_reg_count = 128;
338 /* Set UTA register count */
339 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
340 /* Set RAR entry count */
341 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
342 if (mac->type == e1000_82576)
343 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
344 if (mac->type == e1000_82580)
345 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
346 if (mac->type == e1000_i350 || mac->type == e1000_i354)
347 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
349 /* Enable EEE default settings for EEE supported devices */
350 if (mac->type >= e1000_i350)
351 dev_spec->eee_disable = false;
353 /* Allow a single clear of the SW semaphore on I210 and newer */
354 if (mac->type >= e1000_i210)
355 dev_spec->clear_semaphore_once = true;
357 /* Set if part includes ASF firmware */
358 mac->asf_firmware_present = true;
360 mac->has_fwsm = true;
361 /* ARC supported; valid only if manageability features are enabled. */
362 mac->arc_subsystem_valid =
363 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
365 /* Function pointers */
367 /* bus type/speed/width */
368 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
370 if (mac->type >= e1000_82580)
371 mac->ops.reset_hw = e1000_reset_hw_82580;
373 mac->ops.reset_hw = e1000_reset_hw_82575;
374 /* HW initialization */
375 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
376 mac->ops.init_hw = e1000_init_hw_i210;
378 mac->ops.init_hw = e1000_init_hw_82575;
380 mac->ops.setup_link = e1000_setup_link_generic;
381 /* physical interface link setup */
382 mac->ops.setup_physical_interface =
383 (hw->phy.media_type == e1000_media_type_copper)
384 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
385 /* physical interface shutdown */
386 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
387 /* physical interface power up */
388 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
390 mac->ops.check_for_link = e1000_check_for_link_82575;
391 /* read mac address */
392 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
393 /* configure collision distance */
394 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
395 /* multicast address update */
396 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
397 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
399 mac->ops.write_vfta = e1000_write_vfta_i350;
401 mac->ops.clear_vfta = e1000_clear_vfta_i350;
404 mac->ops.write_vfta = e1000_write_vfta_generic;
406 mac->ops.clear_vfta = e1000_clear_vfta_generic;
408 if (hw->mac.type >= e1000_82580)
409 mac->ops.validate_mdi_setting =
410 e1000_validate_mdi_setting_crossover_generic;
412 mac->ops.id_led_init = e1000_id_led_init_generic;
414 mac->ops.blink_led = e1000_blink_led_generic;
416 mac->ops.setup_led = e1000_setup_led_generic;
418 mac->ops.cleanup_led = e1000_cleanup_led_generic;
419 /* turn on/off LED */
420 mac->ops.led_on = e1000_led_on_generic;
421 mac->ops.led_off = e1000_led_off_generic;
422 /* clear hardware counters */
423 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
425 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
426 /* acquire SW_FW sync */
427 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
428 /* release SW_FW sync */
429 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
431 /* set lan id for port to determine which phy lock to use */
432 hw->mac.ops.set_lan_id(hw);
434 return E1000_SUCCESS;
438 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
439 * @hw: pointer to the HW structure
441 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
443 struct e1000_nvm_info *nvm = &hw->nvm;
444 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
447 DEBUGFUNC("e1000_init_nvm_params_82575");
449 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
450 E1000_EECD_SIZE_EX_SHIFT);
451 /* Added to a constant, "size" becomes the left-shift value
452 * for setting word_size.
454 size += NVM_WORD_SIZE_BASE_SHIFT;
456 /* Just in case size is out of range, cap it to the largest
457 * EEPROM size supported
462 nvm->word_size = 1 << size;
463 if (hw->mac.type < e1000_i210) {
464 nvm->opcode_bits = 8;
467 switch (nvm->override) {
468 case e1000_nvm_override_spi_large:
470 nvm->address_bits = 16;
472 case e1000_nvm_override_spi_small:
474 nvm->address_bits = 8;
477 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
478 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
482 if (nvm->word_size == (1 << 15))
483 nvm->page_size = 128;
485 nvm->type = e1000_nvm_eeprom_spi;
487 nvm->type = e1000_nvm_flash_hw;
490 /* Function Pointers */
491 nvm->ops.acquire = e1000_acquire_nvm_82575;
492 nvm->ops.release = e1000_release_nvm_82575;
493 if (nvm->word_size < (1 << 15))
494 nvm->ops.read = e1000_read_nvm_eerd;
496 nvm->ops.read = e1000_read_nvm_spi;
498 nvm->ops.write = e1000_write_nvm_spi;
499 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
500 nvm->ops.update = e1000_update_nvm_checksum_generic;
501 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
503 /* override generic family function pointers for specific descendants */
504 switch (hw->mac.type) {
506 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
507 nvm->ops.update = e1000_update_nvm_checksum_82580;
510 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
511 nvm->ops.update = e1000_update_nvm_checksum_i350;
517 return E1000_SUCCESS;
521 * e1000_init_function_pointers_82575 - Init func ptrs.
522 * @hw: pointer to the HW structure
524 * Called to initialize all function pointers and parameters.
526 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
528 DEBUGFUNC("e1000_init_function_pointers_82575");
530 hw->mac.ops.init_params = e1000_init_mac_params_82575;
531 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
532 hw->phy.ops.init_params = e1000_init_phy_params_82575;
533 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
537 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
538 * @hw: pointer to the HW structure
539 * @offset: register offset to be read
540 * @data: pointer to the read data
542 * Reads the PHY register at offset using the serial gigabit media independent
543 * interface and stores the retrieved information in data.
545 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
548 s32 ret_val = -E1000_ERR_PARAM;
550 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
552 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
553 DEBUGOUT1("PHY Address %u is out of range\n", offset);
557 ret_val = hw->phy.ops.acquire(hw);
561 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
563 hw->phy.ops.release(hw);
570 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
571 * @hw: pointer to the HW structure
572 * @offset: register offset to write to
573 * @data: data to write at register offset
575 * Writes the data to PHY register at the offset using the serial gigabit
576 * media independent interface.
578 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
581 s32 ret_val = -E1000_ERR_PARAM;
583 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
585 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
586 DEBUGOUT1("PHY Address %d is out of range\n", offset);
590 ret_val = hw->phy.ops.acquire(hw);
594 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
596 hw->phy.ops.release(hw);
603 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
604 * @hw: pointer to the HW structure
606 * Retrieves the PHY address and ID for both PHY's which do and do not use
609 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
611 struct e1000_phy_info *phy = &hw->phy;
612 s32 ret_val = E1000_SUCCESS;
617 DEBUGFUNC("e1000_get_phy_id_82575");
619 /* some i354 devices need an extra read for phy id */
620 if (hw->mac.type == e1000_i354)
621 e1000_get_phy_id(hw);
624 * For SGMII PHYs, we try the list of possible addresses until
625 * we find one that works. For non-SGMII PHYs
626 * (e.g. integrated copper PHYs), an address of 1 should
627 * work. The result of this function should mean phy->phy_addr
628 * and phy->id are set correctly.
630 if (!e1000_sgmii_active_82575(hw)) {
632 ret_val = e1000_get_phy_id(hw);
636 if (e1000_sgmii_uses_mdio_82575(hw)) {
637 switch (hw->mac.type) {
640 mdic = E1000_READ_REG(hw, E1000_MDIC);
641 mdic &= E1000_MDIC_PHY_MASK;
642 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
649 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
650 mdic &= E1000_MDICNFG_PHY_MASK;
651 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
654 ret_val = -E1000_ERR_PHY;
658 ret_val = e1000_get_phy_id(hw);
662 /* Power on sgmii phy if it is disabled */
663 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
664 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
665 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
666 E1000_WRITE_FLUSH(hw);
670 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
671 * Therefore, we need to test 1-7
673 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
674 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
675 if (ret_val == E1000_SUCCESS) {
676 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
679 * At the time of this writing, The M88 part is
680 * the only supported SGMII PHY product.
682 if (phy_id == M88_VENDOR)
685 DEBUGOUT1("PHY address %u was unreadable\n",
690 /* A valid PHY type couldn't be found. */
691 if (phy->addr == 8) {
693 ret_val = -E1000_ERR_PHY;
695 ret_val = e1000_get_phy_id(hw);
698 /* restore previous sfp cage power state */
699 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
706 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
707 * @hw: pointer to the HW structure
709 * Resets the PHY using the serial gigabit media independent interface.
711 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
713 s32 ret_val = E1000_SUCCESS;
714 struct e1000_phy_info *phy = &hw->phy;
716 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
719 * This isn't a true "hard" reset, but is the only reset
720 * available to us at this time.
723 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
725 if (!(hw->phy.ops.write_reg))
729 * SFP documentation requires the following to configure the SPF module
730 * to work on SGMII. No further documentation is given.
732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
736 ret_val = hw->phy.ops.commit(hw);
740 if (phy->id == M88E1512_E_PHY_ID)
741 ret_val = e1000_initialize_M88E1512_phy(hw);
747 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
748 * @hw: pointer to the HW structure
749 * @active: true to enable LPLU, false to disable
751 * Sets the LPLU D0 state according to the active flag. When
752 * activating LPLU this function also disables smart speed
753 * and vice versa. LPLU will not be activated unless the
754 * device autonegotiation advertisement meets standards of
755 * either 10 or 10/100 or 10/100/1000 at all duplexes.
756 * This is a function pointer entry point only called by
757 * PHY setup routines.
759 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
761 struct e1000_phy_info *phy = &hw->phy;
762 s32 ret_val = E1000_SUCCESS;
765 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
767 if (!(hw->phy.ops.read_reg))
770 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
775 data |= IGP02E1000_PM_D0_LPLU;
776 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
781 /* When LPLU is enabled, we should disable SmartSpeed */
782 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
784 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
785 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
790 data &= ~IGP02E1000_PM_D0_LPLU;
791 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
794 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
795 * during Dx states where the power conservation is most
796 * important. During driver activity we should enable
797 * SmartSpeed, so performance is maintained.
799 if (phy->smart_speed == e1000_smart_speed_on) {
800 ret_val = phy->ops.read_reg(hw,
801 IGP01E1000_PHY_PORT_CONFIG,
806 data |= IGP01E1000_PSCFR_SMART_SPEED;
807 ret_val = phy->ops.write_reg(hw,
808 IGP01E1000_PHY_PORT_CONFIG,
812 } else if (phy->smart_speed == e1000_smart_speed_off) {
813 ret_val = phy->ops.read_reg(hw,
814 IGP01E1000_PHY_PORT_CONFIG,
819 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
820 ret_val = phy->ops.write_reg(hw,
821 IGP01E1000_PHY_PORT_CONFIG,
833 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
834 * @hw: pointer to the HW structure
835 * @active: true to enable LPLU, false to disable
837 * Sets the LPLU D0 state according to the active flag. When
838 * activating LPLU this function also disables smart speed
839 * and vice versa. LPLU will not be activated unless the
840 * device autonegotiation advertisement meets standards of
841 * either 10 or 10/100 or 10/100/1000 at all duplexes.
842 * This is a function pointer entry point only called by
843 * PHY setup routines.
845 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
847 struct e1000_phy_info *phy = &hw->phy;
850 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
852 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
855 data |= E1000_82580_PM_D0_LPLU;
857 /* When LPLU is enabled, we should disable SmartSpeed */
858 data &= ~E1000_82580_PM_SPD;
860 data &= ~E1000_82580_PM_D0_LPLU;
863 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
864 * during Dx states where the power conservation is most
865 * important. During driver activity we should enable
866 * SmartSpeed, so performance is maintained.
868 if (phy->smart_speed == e1000_smart_speed_on)
869 data |= E1000_82580_PM_SPD;
870 else if (phy->smart_speed == e1000_smart_speed_off)
871 data &= ~E1000_82580_PM_SPD;
874 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
875 return E1000_SUCCESS;
879 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
880 * @hw: pointer to the HW structure
881 * @active: boolean used to enable/disable lplu
883 * Success returns 0, Failure returns 1
885 * The low power link up (lplu) state is set to the power management level D3
886 * and SmartSpeed is disabled when active is true, else clear lplu for D3
887 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
888 * is used during Dx states where the power conservation is most important.
889 * During driver activity, SmartSpeed should be enabled so performance is
892 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
894 struct e1000_phy_info *phy = &hw->phy;
897 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
899 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
902 data &= ~E1000_82580_PM_D3_LPLU;
904 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
905 * during Dx states where the power conservation is most
906 * important. During driver activity we should enable
907 * SmartSpeed, so performance is maintained.
909 if (phy->smart_speed == e1000_smart_speed_on)
910 data |= E1000_82580_PM_SPD;
911 else if (phy->smart_speed == e1000_smart_speed_off)
912 data &= ~E1000_82580_PM_SPD;
913 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
914 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
915 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
916 data |= E1000_82580_PM_D3_LPLU;
917 /* When LPLU is enabled, we should disable SmartSpeed */
918 data &= ~E1000_82580_PM_SPD;
921 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
922 return E1000_SUCCESS;
926 * e1000_acquire_nvm_82575 - Request for access to EEPROM
927 * @hw: pointer to the HW structure
929 * Acquire the necessary semaphores for exclusive access to the EEPROM.
930 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
931 * Return successful if access grant bit set, else clear the request for
932 * EEPROM access and return -E1000_ERR_NVM (-1).
934 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
936 s32 ret_val = E1000_SUCCESS;
938 DEBUGFUNC("e1000_acquire_nvm_82575");
940 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
945 * Check if there is some access
946 * error this access may hook on
948 if (hw->mac.type == e1000_i350) {
949 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
950 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
951 E1000_EECD_TIMEOUT)) {
952 /* Clear all access error flags */
953 E1000_WRITE_REG(hw, E1000_EECD, eecd |
954 E1000_EECD_ERROR_CLR);
955 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
959 if (hw->mac.type == e1000_82580) {
960 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
961 if (eecd & E1000_EECD_BLOCKED) {
962 /* Clear access error flag */
963 E1000_WRITE_REG(hw, E1000_EECD, eecd |
965 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
969 ret_val = e1000_acquire_nvm_generic(hw);
971 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
978 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
979 * @hw: pointer to the HW structure
981 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
982 * then release the semaphores acquired.
984 static void e1000_release_nvm_82575(struct e1000_hw *hw)
986 DEBUGFUNC("e1000_release_nvm_82575");
988 e1000_release_nvm_generic(hw);
990 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
994 * e1000_get_cfg_done_82575 - Read config done bit
995 * @hw: pointer to the HW structure
997 * Read the management control register for the config done bit for
998 * completion status. NOTE: silicon which is EEPROM-less will fail trying
999 * to read the config done bit, so an error is *ONLY* logged and returns
1000 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1001 * would not be able to be reset or change link.
1003 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1005 s32 timeout = PHY_CFG_TIMEOUT;
1006 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1008 DEBUGFUNC("e1000_get_cfg_done_82575");
1010 if (hw->bus.func == E1000_FUNC_1)
1011 mask = E1000_NVM_CFG_DONE_PORT_1;
1012 else if (hw->bus.func == E1000_FUNC_2)
1013 mask = E1000_NVM_CFG_DONE_PORT_2;
1014 else if (hw->bus.func == E1000_FUNC_3)
1015 mask = E1000_NVM_CFG_DONE_PORT_3;
1017 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1023 DEBUGOUT("MNG configuration cycle has not completed.\n");
1025 /* If EEPROM is not marked present, init the PHY manually */
1026 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1027 (hw->phy.type == e1000_phy_igp_3))
1028 e1000_phy_init_script_igp3(hw);
1030 return E1000_SUCCESS;
1034 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1035 * @hw: pointer to the HW structure
1036 * @speed: stores the current speed
1037 * @duplex: stores the current duplex
1039 * This is a wrapper function, if using the serial gigabit media independent
1040 * interface, use PCS to retrieve the link speed and duplex information.
1041 * Otherwise, use the generic function to get the link speed and duplex info.
1043 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1048 DEBUGFUNC("e1000_get_link_up_info_82575");
1050 if (hw->phy.media_type != e1000_media_type_copper)
1051 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1054 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1061 * e1000_check_for_link_82575 - Check for link
1062 * @hw: pointer to the HW structure
1064 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1065 * use the generic interface for determining link.
1067 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1072 DEBUGFUNC("e1000_check_for_link_82575");
1074 if (hw->phy.media_type != e1000_media_type_copper) {
1075 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1078 * Use this flag to determine if link needs to be checked or
1079 * not. If we have link clear the flag so that we do not
1080 * continue to check for link.
1082 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1085 * Configure Flow Control now that Auto-Neg has completed.
1086 * First, we need to restore the desired flow control
1087 * settings because we may have had to re-autoneg with a
1088 * different link partner.
1090 ret_val = e1000_config_fc_after_link_up_generic(hw);
1092 DEBUGOUT("Error configuring flow control\n");
1094 ret_val = e1000_check_for_copper_link_generic(hw);
1101 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1102 * @hw: pointer to the HW structure
1104 * Poll the M88E1112 interfaces to see which interface achieved link.
1106 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1108 struct e1000_phy_info *phy = &hw->phy;
1113 DEBUGFUNC("e1000_check_for_link_media_swap");
1115 /* Check for copper. */
1116 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1120 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1124 if (data & E1000_M88E1112_STATUS_LINK)
1125 port = E1000_MEDIA_PORT_COPPER;
1127 /* Check for other. */
1128 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1132 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1136 if (data & E1000_M88E1112_STATUS_LINK)
1137 port = E1000_MEDIA_PORT_OTHER;
1139 /* Determine if a swap needs to happen. */
1140 if (port && (hw->dev_spec._82575.media_port != port)) {
1141 hw->dev_spec._82575.media_port = port;
1142 hw->dev_spec._82575.media_changed = true;
1145 if (port == E1000_MEDIA_PORT_COPPER) {
1146 /* reset page to 0 */
1147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1150 e1000_check_for_link_82575(hw);
1152 e1000_check_for_link_82575(hw);
1153 /* reset page to 0 */
1154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1159 return E1000_SUCCESS;
1163 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1164 * @hw: pointer to the HW structure
1166 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1170 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1172 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1173 !e1000_sgmii_active_82575(hw))
1176 /* Enable PCS to turn on link */
1177 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1178 reg |= E1000_PCS_CFG_PCS_EN;
1179 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1181 /* Power up the laser */
1182 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1183 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1184 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1186 /* flush the write to verify completion */
1187 E1000_WRITE_FLUSH(hw);
1192 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1193 * @hw: pointer to the HW structure
1194 * @speed: stores the current speed
1195 * @duplex: stores the current duplex
1197 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1198 * duplex, then store the values in the pointers provided.
1200 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1201 u16 *speed, u16 *duplex)
1203 struct e1000_mac_info *mac = &hw->mac;
1207 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1210 * Read the PCS Status register for link state. For non-copper mode,
1211 * the status register is not accurate. The PCS status register is
1214 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1217 * The link up bit determines when link is up on autoneg.
1219 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1220 mac->serdes_has_link = true;
1222 /* Detect and store PCS speed */
1223 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1224 *speed = SPEED_1000;
1225 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1230 /* Detect and store PCS duplex */
1231 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1232 *duplex = FULL_DUPLEX;
1234 *duplex = HALF_DUPLEX;
1236 /* Check if it is an I354 2.5Gb backplane connection. */
1237 if (mac->type == e1000_i354) {
1238 status = E1000_READ_REG(hw, E1000_STATUS);
1239 if ((status & E1000_STATUS_2P5_SKU) &&
1240 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1241 *speed = SPEED_2500;
1242 *duplex = FULL_DUPLEX;
1243 DEBUGOUT("2500 Mbs, ");
1244 DEBUGOUT("Full Duplex\n");
1249 mac->serdes_has_link = false;
1254 return E1000_SUCCESS;
1258 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1259 * @hw: pointer to the HW structure
1261 * In the case of serdes shut down sfp and PCS on driver unload
1262 * when management pass thru is not enabled.
1264 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1268 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 !e1000_sgmii_active_82575(hw))
1274 if (!e1000_enable_mng_pass_thru(hw)) {
1275 /* Disable PCS to turn off link */
1276 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1277 reg &= ~E1000_PCS_CFG_PCS_EN;
1278 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1280 /* shutdown the laser */
1281 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1282 reg |= E1000_CTRL_EXT_SDP3_DATA;
1283 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1285 /* flush the write to verify completion */
1286 E1000_WRITE_FLUSH(hw);
1294 * e1000_reset_hw_82575 - Reset hardware
1295 * @hw: pointer to the HW structure
1297 * This resets the hardware into a known state.
1299 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1304 DEBUGFUNC("e1000_reset_hw_82575");
1307 * Prevent the PCI-E bus from sticking if there is no TLP connection
1308 * on the last TLP read/write transaction when MAC is reset.
1310 ret_val = e1000_disable_pcie_master_generic(hw);
1312 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1314 /* set the completion timeout for interface */
1315 ret_val = e1000_set_pcie_completion_timeout(hw);
1317 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1319 DEBUGOUT("Masking off all interrupts\n");
1320 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1322 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1323 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1324 E1000_WRITE_FLUSH(hw);
1328 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1330 DEBUGOUT("Issuing a global reset to MAC\n");
1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1333 ret_val = e1000_get_auto_rd_done_generic(hw);
1336 * When auto config read does not complete, do not
1337 * return with an error. This can happen in situations
1338 * where there is no eeprom and prevents getting link.
1340 DEBUGOUT("Auto Read Done did not complete\n");
1343 /* If EEPROM is not present, run manual init scripts */
1344 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1345 e1000_reset_init_script_82575(hw);
1347 /* Clear any pending interrupt events. */
1348 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1349 E1000_READ_REG(hw, E1000_ICR);
1351 /* Install any alternate MAC address into RAR0 */
1352 ret_val = e1000_check_alt_mac_addr_generic(hw);
1358 * e1000_init_hw_82575 - Initialize hardware
1359 * @hw: pointer to the HW structure
1361 * This inits the hardware readying it for operation.
1363 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1365 struct e1000_mac_info *mac = &hw->mac;
1368 DEBUGFUNC("e1000_init_hw_82575");
1370 /* Initialize identification LED */
1371 ret_val = mac->ops.id_led_init(hw);
1373 DEBUGOUT("Error initializing identification LED\n");
1374 /* This is not fatal and we should not stop init due to this */
1377 /* Disabling VLAN filtering */
1378 DEBUGOUT("Initializing the IEEE VLAN\n");
1379 mac->ops.clear_vfta(hw);
1381 ret_val = e1000_init_hw_base(hw);
1383 /* Set the default MTU size */
1384 hw->dev_spec._82575.mtu = 1500;
1386 /* Clear all of the statistics registers (clear on read). It is
1387 * important that we do this after we have tried to establish link
1388 * because the symbol error count will increment wildly if there
1391 e1000_clear_hw_cntrs_82575(hw);
1396 * e1000_setup_copper_link_82575 - Configure copper link settings
1397 * @hw: pointer to the HW structure
1399 * Configures the link for auto-neg or forced speed and duplex. Then we check
1400 * for link, once link is established calls to configure collision distance
1401 * and flow control are called.
1403 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1409 DEBUGFUNC("e1000_setup_copper_link_82575");
1411 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1412 ctrl |= E1000_CTRL_SLU;
1413 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1414 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1416 /* Clear Go Link Disconnect bit on supported devices */
1417 switch (hw->mac.type) {
1422 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1430 ret_val = e1000_setup_serdes_link_82575(hw);
1434 if (e1000_sgmii_active_82575(hw)) {
1435 /* allow time for SFP cage time to power up phy */
1438 ret_val = hw->phy.ops.reset(hw);
1440 DEBUGOUT("Error resetting the PHY.\n");
1444 switch (hw->phy.type) {
1445 case e1000_phy_i210:
1448 switch (hw->phy.id) {
1449 case I347AT4_E_PHY_ID:
1451 case M88E1112_E_PHY_ID:
1453 case M88E1340M_E_PHY_ID:
1455 case M88E1543_E_PHY_ID:
1457 case M88E1512_E_PHY_ID:
1460 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1463 ret_val = e1000_copper_link_setup_m88(hw);
1467 case e1000_phy_igp_3:
1468 ret_val = e1000_copper_link_setup_igp(hw);
1470 case e1000_phy_82580:
1471 ret_val = e1000_copper_link_setup_82577(hw);
1474 ret_val = -E1000_ERR_PHY;
1481 ret_val = e1000_setup_copper_link_generic(hw);
1487 * e1000_setup_serdes_link_82575 - Setup link for serdes
1488 * @hw: pointer to the HW structure
1490 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1491 * used on copper connections where the serialized gigabit media independent
1492 * interface (sgmii), or serdes fiber is being used. Configures the link
1493 * for auto-negotiation or forces speed/duplex.
1495 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1497 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1499 s32 ret_val = E1000_SUCCESS;
1502 DEBUGFUNC("e1000_setup_serdes_link_82575");
1504 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1505 !e1000_sgmii_active_82575(hw))
1509 * On the 82575, SerDes loopback mode persists until it is
1510 * explicitly turned off or a power cycle is performed. A read to
1511 * the register does not indicate its status. Therefore, we ensure
1512 * loopback mode is disabled during initialization.
1514 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1516 /* power on the sfp cage if present */
1517 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1518 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1519 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1521 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1522 ctrl_reg |= E1000_CTRL_SLU;
1524 /* set both sw defined pins on 82575/82576*/
1525 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1526 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1528 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1530 /* default pcs_autoneg to the same setting as mac autoneg */
1531 pcs_autoneg = hw->mac.autoneg;
1533 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1534 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1535 /* sgmii mode lets the phy handle forcing speed/duplex */
1537 /* autoneg time out should be disabled for SGMII mode */
1538 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1540 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1541 /* disable PCS autoneg and support parallel detect only */
1542 pcs_autoneg = false;
1545 if (hw->mac.type == e1000_82575 ||
1546 hw->mac.type == e1000_82576) {
1547 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1549 DEBUGOUT("NVM Read Error\n");
1553 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1554 pcs_autoneg = false;
1558 * non-SGMII modes only supports a speed of 1000/Full for the
1559 * link so it is best to just force the MAC and let the pcs
1560 * link either autoneg or be forced to 1000/Full
1562 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1563 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1565 /* set speed of 1000/Full if speed/duplex is forced */
1566 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1570 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1573 * New SerDes mode allows for forcing speed or autonegotiating speed
1574 * at 1gb. Autoneg should be default set by most drivers. This is the
1575 * mode that will be compatible with older link partners and switches.
1576 * However, both are supported by the hardware and some drivers/tools.
1578 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1579 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1582 /* Set PCS register for autoneg */
1583 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1584 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1586 /* Disable force flow control for autoneg */
1587 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1589 /* Configure flow control advertisement for autoneg */
1590 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1591 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1593 switch (hw->fc.requested_mode) {
1595 case e1000_fc_rx_pause:
1596 anadv_reg |= E1000_TXCW_ASM_DIR;
1597 anadv_reg |= E1000_TXCW_PAUSE;
1599 case e1000_fc_tx_pause:
1600 anadv_reg |= E1000_TXCW_ASM_DIR;
1606 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1608 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1610 /* Set PCS register for forced link */
1611 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1613 /* Force flow control for forced link */
1614 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1616 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1619 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1621 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1622 e1000_force_mac_fc_generic(hw);
1628 * e1000_get_media_type_82575 - derives current media type.
1629 * @hw: pointer to the HW structure
1631 * The media type is chosen reflecting few settings.
1632 * The following are taken into account:
1633 * - link mode set in the current port Init Control Word #3
1634 * - current link mode settings in CSR register
1635 * - MDIO vs. I2C PHY control interface chosen
1636 * - SFP module media type
1638 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1640 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1641 s32 ret_val = E1000_SUCCESS;
1645 /* Set internal phy as default */
1646 dev_spec->sgmii_active = false;
1647 dev_spec->module_plugged = false;
1649 /* Get CSR setting */
1650 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1652 /* extract link mode setting */
1653 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1655 switch (link_mode) {
1656 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1657 hw->phy.media_type = e1000_media_type_internal_serdes;
1659 case E1000_CTRL_EXT_LINK_MODE_GMII:
1660 hw->phy.media_type = e1000_media_type_copper;
1662 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1663 /* Get phy control interface type set (MDIO vs. I2C)*/
1664 if (e1000_sgmii_uses_mdio_82575(hw)) {
1665 hw->phy.media_type = e1000_media_type_copper;
1666 dev_spec->sgmii_active = true;
1669 /* fall through for I2C based SGMII */
1671 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1672 /* read media type from SFP EEPROM */
1673 ret_val = e1000_set_sfp_media_type_82575(hw);
1674 if ((ret_val != E1000_SUCCESS) ||
1675 (hw->phy.media_type == e1000_media_type_unknown)) {
1677 * If media type was not identified then return media
1678 * type defined by the CTRL_EXT settings.
1680 hw->phy.media_type = e1000_media_type_internal_serdes;
1682 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1683 hw->phy.media_type = e1000_media_type_copper;
1684 dev_spec->sgmii_active = true;
1690 /* do not change link mode for 100BaseFX */
1691 if (dev_spec->eth_flags.e100_base_fx)
1694 /* change current link mode setting */
1695 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1697 if (hw->phy.media_type == e1000_media_type_copper)
1698 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1700 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1702 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1711 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1712 * @hw: pointer to the HW structure
1714 * The media type is chosen based on SFP module.
1715 * compatibility flags retrieved from SFP ID EEPROM.
1717 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1719 s32 ret_val = E1000_ERR_CONFIG;
1721 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1722 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1723 u8 tranceiver_type = 0;
1726 /* Turn I2C interface ON and power on sfp cage */
1727 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1728 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1729 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1731 E1000_WRITE_FLUSH(hw);
1733 /* Read SFP module data */
1735 ret_val = e1000_read_sfp_data_byte(hw,
1736 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1738 if (ret_val == E1000_SUCCESS)
1743 if (ret_val != E1000_SUCCESS)
1746 ret_val = e1000_read_sfp_data_byte(hw,
1747 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1749 if (ret_val != E1000_SUCCESS)
1752 /* Check if there is some SFP module plugged and powered */
1753 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1754 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1755 dev_spec->module_plugged = true;
1756 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1757 hw->phy.media_type = e1000_media_type_internal_serdes;
1758 } else if (eth_flags->e100_base_fx) {
1759 dev_spec->sgmii_active = true;
1760 hw->phy.media_type = e1000_media_type_internal_serdes;
1761 } else if (eth_flags->e1000_base_t) {
1762 dev_spec->sgmii_active = true;
1763 hw->phy.media_type = e1000_media_type_copper;
1765 hw->phy.media_type = e1000_media_type_unknown;
1766 DEBUGOUT("PHY module has not been recognized\n");
1770 hw->phy.media_type = e1000_media_type_unknown;
1772 ret_val = E1000_SUCCESS;
1774 /* Restore I2C interface setting */
1775 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1780 * e1000_valid_led_default_82575 - Verify a valid default LED config
1781 * @hw: pointer to the HW structure
1782 * @data: pointer to the NVM (EEPROM)
1784 * Read the EEPROM for the current default LED configuration. If the
1785 * LED configuration is not valid, set to a valid LED configuration.
1787 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1791 DEBUGFUNC("e1000_valid_led_default_82575");
1793 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1795 DEBUGOUT("NVM Read Error\n");
1799 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1800 switch (hw->phy.media_type) {
1801 case e1000_media_type_internal_serdes:
1802 *data = ID_LED_DEFAULT_82575_SERDES;
1804 case e1000_media_type_copper:
1806 *data = ID_LED_DEFAULT;
1815 * e1000_sgmii_active_82575 - Return sgmii state
1816 * @hw: pointer to the HW structure
1818 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1819 * which can be enabled for use in the embedded applications. Simply
1820 * return the current state of the sgmii interface.
1822 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1824 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1825 return dev_spec->sgmii_active;
1829 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1830 * @hw: pointer to the HW structure
1832 * Inits recommended HW defaults after a reset when there is no EEPROM
1833 * detected. This is only for the 82575.
1835 s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1837 DEBUGFUNC("e1000_reset_init_script_82575");
1839 if (hw->mac.type == e1000_82575) {
1840 DEBUGOUT("Running reset init script for 82575\n");
1841 /* SerDes configuration via SERDESCTRL */
1842 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1847 /* CCM configuration via CCMCTL register */
1848 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1851 /* PCIe lanes configuration */
1852 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1857 /* PCIe PLL Configuration */
1858 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1863 return E1000_SUCCESS;
1867 * e1000_read_mac_addr_82575 - Read device MAC address
1868 * @hw: pointer to the HW structure
1870 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1874 DEBUGFUNC("e1000_read_mac_addr_82575");
1877 * If there's an alternate MAC address place it in RAR0
1878 * so that it will override the Si installed default perm
1881 ret_val = e1000_check_alt_mac_addr_generic(hw);
1885 ret_val = e1000_read_mac_addr_generic(hw);
1892 * e1000_config_collision_dist_82575 - Configure collision distance
1893 * @hw: pointer to the HW structure
1895 * Configures the collision distance to the default value and is used
1896 * during link setup.
1898 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1902 DEBUGFUNC("e1000_config_collision_dist_82575");
1904 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1906 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1907 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1909 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1910 E1000_WRITE_FLUSH(hw);
1914 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1915 * @hw: pointer to the HW structure
1917 * Clears the hardware counters by reading the counter registers.
1919 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1921 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1923 e1000_clear_hw_cntrs_base_generic(hw);
1925 E1000_READ_REG(hw, E1000_PRC64);
1926 E1000_READ_REG(hw, E1000_PRC127);
1927 E1000_READ_REG(hw, E1000_PRC255);
1928 E1000_READ_REG(hw, E1000_PRC511);
1929 E1000_READ_REG(hw, E1000_PRC1023);
1930 E1000_READ_REG(hw, E1000_PRC1522);
1931 E1000_READ_REG(hw, E1000_PTC64);
1932 E1000_READ_REG(hw, E1000_PTC127);
1933 E1000_READ_REG(hw, E1000_PTC255);
1934 E1000_READ_REG(hw, E1000_PTC511);
1935 E1000_READ_REG(hw, E1000_PTC1023);
1936 E1000_READ_REG(hw, E1000_PTC1522);
1938 E1000_READ_REG(hw, E1000_ALGNERRC);
1939 E1000_READ_REG(hw, E1000_RXERRC);
1940 E1000_READ_REG(hw, E1000_TNCRS);
1941 E1000_READ_REG(hw, E1000_CEXTERR);
1942 E1000_READ_REG(hw, E1000_TSCTC);
1943 E1000_READ_REG(hw, E1000_TSCTFC);
1945 E1000_READ_REG(hw, E1000_MGTPRC);
1946 E1000_READ_REG(hw, E1000_MGTPDC);
1947 E1000_READ_REG(hw, E1000_MGTPTC);
1949 E1000_READ_REG(hw, E1000_IAC);
1950 E1000_READ_REG(hw, E1000_ICRXOC);
1952 E1000_READ_REG(hw, E1000_ICRXPTC);
1953 E1000_READ_REG(hw, E1000_ICRXATC);
1954 E1000_READ_REG(hw, E1000_ICTXPTC);
1955 E1000_READ_REG(hw, E1000_ICTXATC);
1956 E1000_READ_REG(hw, E1000_ICTXQEC);
1957 E1000_READ_REG(hw, E1000_ICTXQMTC);
1958 E1000_READ_REG(hw, E1000_ICRXDMTC);
1960 E1000_READ_REG(hw, E1000_CBTMPC);
1961 E1000_READ_REG(hw, E1000_HTDPMC);
1962 E1000_READ_REG(hw, E1000_CBRMPC);
1963 E1000_READ_REG(hw, E1000_RPTHC);
1964 E1000_READ_REG(hw, E1000_HGPTC);
1965 E1000_READ_REG(hw, E1000_HTCBDPC);
1966 E1000_READ_REG(hw, E1000_HGORCL);
1967 E1000_READ_REG(hw, E1000_HGORCH);
1968 E1000_READ_REG(hw, E1000_HGOTCL);
1969 E1000_READ_REG(hw, E1000_HGOTCH);
1970 E1000_READ_REG(hw, E1000_LENERRS);
1972 /* This register should not be read in copper configurations */
1973 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1974 e1000_sgmii_active_82575(hw))
1975 E1000_READ_REG(hw, E1000_SCVPC);
1979 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1980 * @hw: pointer to the HW structure
1982 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1983 * however the hardware default for these parts is 500us to 1ms which is less
1984 * than the 10ms recommended by the pci-e spec. To address this we need to
1985 * increase the value to either 10ms to 200ms for capability version 1 config,
1986 * or 16ms to 55ms for version 2.
1988 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1990 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1991 s32 ret_val = E1000_SUCCESS;
1994 /* only take action if timeout value is defaulted to 0 */
1995 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1999 * if capababilities version is type 1 we can write the
2000 * timeout of 10ms to 200ms through the GCR register
2002 if (!(gcr & E1000_GCR_CAP_VER2)) {
2003 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2008 * for version 2 capabilities we need to write the config space
2009 * directly in order to set the completion timeout value for
2012 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2017 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2019 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2022 /* disable completion timeout resend */
2023 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2025 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2030 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2031 * @hw: pointer to the hardware struct
2032 * @enable: state to enter, either enabled or disabled
2033 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2035 * enables/disables L2 switch anti-spoofing functionality.
2037 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2039 u32 reg_val, reg_offset;
2041 switch (hw->mac.type) {
2043 reg_offset = E1000_DTXSWC;
2047 reg_offset = E1000_TXSWC;
2053 reg_val = E1000_READ_REG(hw, reg_offset);
2055 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2056 E1000_DTXSWC_VLAN_SPOOF_MASK);
2057 /* The PF can spoof - it has to in order to
2058 * support emulation mode NICs
2060 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2062 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2063 E1000_DTXSWC_VLAN_SPOOF_MASK);
2065 E1000_WRITE_REG(hw, reg_offset, reg_val);
2069 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2070 * @hw: pointer to the hardware struct
2071 * @enable: state to enter, either enabled or disabled
2073 * enables/disables L2 switch loopback functionality.
2075 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2079 switch (hw->mac.type) {
2081 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2083 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2085 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2086 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2090 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2092 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2094 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2095 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2098 /* Currently no other hardware supports loopback */
2106 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2107 * @hw: pointer to the hardware struct
2108 * @enable: state to enter, either enabled or disabled
2110 * enables/disables replication of packets across multiple pools.
2112 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2114 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2117 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2119 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2121 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2125 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2126 * @hw: pointer to the HW structure
2127 * @offset: register offset to be read
2128 * @data: pointer to the read data
2130 * Reads the MDI control register in the PHY at offset and stores the
2131 * information read to data.
2133 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2137 DEBUGFUNC("e1000_read_phy_reg_82580");
2139 ret_val = hw->phy.ops.acquire(hw);
2143 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2145 hw->phy.ops.release(hw);
2152 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2153 * @hw: pointer to the HW structure
2154 * @offset: register offset to write to
2155 * @data: data to write to register at offset
2157 * Writes data to MDI control register in the PHY at offset.
2159 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2163 DEBUGFUNC("e1000_write_phy_reg_82580");
2165 ret_val = hw->phy.ops.acquire(hw);
2169 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2171 hw->phy.ops.release(hw);
2178 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2179 * @hw: pointer to the HW structure
2181 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2182 * the values found in the EEPROM. This addresses an issue in which these
2183 * bits are not restored from EEPROM after reset.
2185 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2187 s32 ret_val = E1000_SUCCESS;
2191 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2193 if (hw->mac.type != e1000_82580)
2195 if (!e1000_sgmii_active_82575(hw))
2198 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2199 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2202 DEBUGOUT("NVM Read Error\n");
2206 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2207 if (nvm_data & NVM_WORD24_EXT_MDIO)
2208 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2209 if (nvm_data & NVM_WORD24_COM_MDIO)
2210 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2211 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2217 * e1000_reset_hw_82580 - Reset hardware
2218 * @hw: pointer to the HW structure
2220 * This resets function or entire device (all ports, etc.)
2223 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2225 s32 ret_val = E1000_SUCCESS;
2226 /* BH SW mailbox bit in SW_FW_SYNC */
2227 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2229 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2231 DEBUGFUNC("e1000_reset_hw_82580");
2233 hw->dev_spec._82575.global_device_reset = false;
2235 /* 82580 does not reliably do global_device_reset due to hw errata */
2236 if (hw->mac.type == e1000_82580)
2237 global_device_reset = false;
2239 /* Get current control state. */
2240 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2243 * Prevent the PCI-E bus from sticking if there is no TLP connection
2244 * on the last TLP read/write transaction when MAC is reset.
2246 ret_val = e1000_disable_pcie_master_generic(hw);
2248 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2250 DEBUGOUT("Masking off all interrupts\n");
2251 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2252 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2253 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2254 E1000_WRITE_FLUSH(hw);
2258 /* Determine whether or not a global dev reset is requested */
2259 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2261 global_device_reset = false;
2263 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2264 E1000_STAT_DEV_RST_SET))
2265 ctrl |= E1000_CTRL_DEV_RST;
2267 ctrl |= E1000_CTRL_RST;
2269 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2271 switch (hw->device_id) {
2272 case E1000_DEV_ID_DH89XXCC_SGMII:
2275 E1000_WRITE_FLUSH(hw);
2279 /* Add delay to insure DEV_RST or RST has time to complete */
2282 ret_val = e1000_get_auto_rd_done_generic(hw);
2285 * When auto config read does not complete, do not
2286 * return with an error. This can happen in situations
2287 * where there is no eeprom and prevents getting link.
2289 DEBUGOUT("Auto Read Done did not complete\n");
2292 /* clear global device reset status bit */
2293 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2295 /* Clear any pending interrupt events. */
2296 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2297 E1000_READ_REG(hw, E1000_ICR);
2299 ret_val = e1000_reset_mdicnfg_82580(hw);
2301 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2303 /* Install any alternate MAC address into RAR0 */
2304 ret_val = e1000_check_alt_mac_addr_generic(hw);
2306 /* Release semaphore */
2307 if (global_device_reset)
2308 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2314 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2315 * @data: data received by reading RXPBS register
2317 * The 82580 uses a table based approach for packet buffer allocation sizes.
2318 * This function converts the retrieved value into the correct table value
2319 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2320 * 0x0 36 72 144 1 2 4 8 16
2321 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2323 u16 e1000_rxpbs_adjust_82580(u32 data)
2327 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2328 ret_val = e1000_82580_rxpbs_table[data];
2334 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2336 * @hw: pointer to the HW structure
2337 * @offset: offset in words of the checksum protected region
2339 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2340 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2342 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2344 s32 ret_val = E1000_SUCCESS;
2348 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2350 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2351 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2353 DEBUGOUT("NVM Read Error\n");
2356 checksum += nvm_data;
2359 if (checksum != (u16) NVM_SUM) {
2360 DEBUGOUT("NVM Checksum Invalid\n");
2361 ret_val = -E1000_ERR_NVM;
2370 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2372 * @hw: pointer to the HW structure
2373 * @offset: offset in words of the checksum protected region
2375 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2376 * up to the checksum. Then calculates the EEPROM checksum and writes the
2377 * value to the EEPROM.
2379 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2385 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2387 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2388 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2390 DEBUGOUT("NVM Read Error while updating checksum.\n");
2393 checksum += nvm_data;
2395 checksum = (u16) NVM_SUM - checksum;
2396 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2399 DEBUGOUT("NVM Write Error while updating checksum.\n");
2406 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2407 * @hw: pointer to the HW structure
2409 * Calculates the EEPROM section checksum by reading/adding each word of
2410 * the EEPROM and then verifies that the sum of the EEPROM is
2413 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2416 u16 eeprom_regions_count = 1;
2420 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2422 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2424 DEBUGOUT("NVM Read Error\n");
2428 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2429 /* if chekcsums compatibility bit is set validate checksums
2430 * for all 4 ports. */
2431 eeprom_regions_count = 4;
2434 for (j = 0; j < eeprom_regions_count; j++) {
2435 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2436 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2438 if (ret_val != E1000_SUCCESS)
2447 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2448 * @hw: pointer to the HW structure
2450 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2451 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2452 * checksum and writes the value to the EEPROM.
2454 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2460 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2462 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2464 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2468 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2469 /* set compatibility bit to validate checksums appropriately */
2470 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2471 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2474 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2479 for (j = 0; j < 4; j++) {
2480 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2481 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2491 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2492 * @hw: pointer to the HW structure
2494 * Calculates the EEPROM section checksum by reading/adding each word of
2495 * the EEPROM and then verifies that the sum of the EEPROM is
2498 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2500 s32 ret_val = E1000_SUCCESS;
2504 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2506 for (j = 0; j < 4; j++) {
2507 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2508 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2510 if (ret_val != E1000_SUCCESS)
2519 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2520 * @hw: pointer to the HW structure
2522 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2523 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2524 * checksum and writes the value to the EEPROM.
2526 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2528 s32 ret_val = E1000_SUCCESS;
2532 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2534 for (j = 0; j < 4; j++) {
2535 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2536 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2537 if (ret_val != E1000_SUCCESS)
2546 * __e1000_access_emi_reg - Read/write EMI register
2547 * @hw: pointer to the HW structure
2548 * @address: EMI address to program
2549 * @data: pointer to value to read/write from/to the EMI address
2550 * @read: boolean flag to indicate read or write
2552 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2553 u16 *data, bool read)
2557 DEBUGFUNC("__e1000_access_emi_reg");
2559 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2564 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2566 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2572 * e1000_read_emi_reg - Read Extended Management Interface register
2573 * @hw: pointer to the HW structure
2574 * @addr: EMI address to program
2575 * @data: value to be read from the EMI address
2577 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2579 DEBUGFUNC("e1000_read_emi_reg");
2581 return __e1000_access_emi_reg(hw, addr, data, true);
2585 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2586 * @hw: pointer to the HW structure
2588 * Initialize Marvell 1512 to work correctly with Avoton.
2590 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2592 struct e1000_phy_info *phy = &hw->phy;
2593 s32 ret_val = E1000_SUCCESS;
2595 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2597 /* Check if this is correct PHY. */
2598 if (phy->id != M88E1512_E_PHY_ID)
2601 /* Switch to PHY page 0xFF. */
2602 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2606 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2610 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2614 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2622 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2626 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2630 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2634 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2638 /* Switch to PHY page 0xFB. */
2639 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2643 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2647 /* Switch to PHY page 0x12. */
2648 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2652 /* Change mode to SGMII-to-Copper */
2653 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2657 /* Return the PHY to page 0. */
2658 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2662 ret_val = phy->ops.commit(hw);
2664 DEBUGOUT("Error committing the PHY changes\n");
2674 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2675 * @hw: pointer to the HW structure
2677 * Initialize Marvell 1543 to work correctly with Avoton.
2679 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2681 struct e1000_phy_info *phy = &hw->phy;
2682 s32 ret_val = E1000_SUCCESS;
2684 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2686 /* Check if this is correct PHY. */
2687 if (phy->id != M88E1543_E_PHY_ID)
2690 /* Switch to PHY page 0xFF. */
2691 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2695 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2699 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2703 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2707 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2711 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2715 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2719 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2723 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2727 /* Switch to PHY page 0xFB. */
2728 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2732 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2736 /* Switch to PHY page 0x12. */
2737 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2741 /* Change mode to SGMII-to-Copper */
2742 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2746 /* Switch to PHY page 1. */
2747 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2751 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2752 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2756 /* Return the PHY to page 0. */
2757 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2761 ret_val = phy->ops.commit(hw);
2763 DEBUGOUT("Error committing the PHY changes\n");
2773 * e1000_set_eee_i350 - Enable/disable EEE support
2774 * @hw: pointer to the HW structure
2775 * @adv1G: boolean flag enabling 1G EEE advertisement
2776 * @adv100M: boolean flag enabling 100M EEE advertisement
2778 * Enable/disable EEE based on setting in dev_spec structure.
2781 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2785 DEBUGFUNC("e1000_set_eee_i350");
2787 if ((hw->mac.type < e1000_i350) ||
2788 (hw->phy.media_type != e1000_media_type_copper))
2790 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2791 eeer = E1000_READ_REG(hw, E1000_EEER);
2793 /* enable or disable per user setting */
2794 if (!(hw->dev_spec._82575.eee_disable)) {
2795 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2798 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2800 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2803 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2805 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2807 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2810 /* This bit should not be set in normal operation. */
2811 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2812 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2814 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2815 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2818 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2819 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2820 E1000_READ_REG(hw, E1000_IPCNFG);
2821 E1000_READ_REG(hw, E1000_EEER);
2824 return E1000_SUCCESS;
2828 * e1000_set_eee_i354 - Enable/disable EEE support
2829 * @hw: pointer to the HW structure
2830 * @adv1G: boolean flag enabling 1G EEE advertisement
2831 * @adv100M: boolean flag enabling 100M EEE advertisement
2833 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2836 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2838 struct e1000_phy_info *phy = &hw->phy;
2839 s32 ret_val = E1000_SUCCESS;
2842 DEBUGFUNC("e1000_set_eee_i354");
2844 if ((hw->phy.media_type != e1000_media_type_copper) ||
2845 ((phy->id != M88E1543_E_PHY_ID) &&
2846 (phy->id != M88E1512_E_PHY_ID)))
2849 if (!hw->dev_spec._82575.eee_disable) {
2850 /* Switch to PHY page 18. */
2851 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2855 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2860 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2861 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2866 /* Return the PHY to page 0. */
2867 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2871 /* Turn on EEE advertisement. */
2872 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2873 E1000_EEE_ADV_DEV_I354,
2879 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2881 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2884 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2886 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2888 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2889 E1000_EEE_ADV_DEV_I354,
2892 /* Turn off EEE advertisement. */
2893 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2894 E1000_EEE_ADV_DEV_I354,
2899 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2900 E1000_EEE_ADV_1000_SUPPORTED);
2901 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2902 E1000_EEE_ADV_DEV_I354,
2911 * e1000_get_eee_status_i354 - Get EEE status
2912 * @hw: pointer to the HW structure
2913 * @status: EEE status
2915 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2918 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2920 struct e1000_phy_info *phy = &hw->phy;
2921 s32 ret_val = E1000_SUCCESS;
2924 DEBUGFUNC("e1000_get_eee_status_i354");
2926 /* Check if EEE is supported on this device. */
2927 if ((hw->phy.media_type != e1000_media_type_copper) ||
2928 ((phy->id != M88E1543_E_PHY_ID) &&
2929 (phy->id != M88E1512_E_PHY_ID)))
2932 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2933 E1000_PCS_STATUS_DEV_I354,
2938 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2939 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2945 /* Due to a hw errata, if the host tries to configure the VFTA register
2946 * while performing queries from the BMC or DMA, then the VFTA in some
2947 * cases won't be written.
2951 * e1000_clear_vfta_i350 - Clear VLAN filter table
2952 * @hw: pointer to the HW structure
2954 * Clears the register array which contains the VLAN filter table by
2955 * setting all the values to 0.
2957 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2962 DEBUGFUNC("e1000_clear_vfta_350");
2964 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2965 for (i = 0; i < 10; i++)
2966 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2968 E1000_WRITE_FLUSH(hw);
2973 * e1000_write_vfta_i350 - Write value to VLAN filter table
2974 * @hw: pointer to the HW structure
2975 * @offset: register offset in VLAN filter table
2976 * @value: register value written to VLAN filter table
2978 * Writes value at the given offset in the register array which stores
2979 * the VLAN filter table.
2981 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2985 DEBUGFUNC("e1000_write_vfta_350");
2987 for (i = 0; i < 10; i++)
2988 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2990 E1000_WRITE_FLUSH(hw);
2995 * e1000_set_i2c_bb - Enable I2C bit-bang
2996 * @hw: pointer to the HW structure
2998 * Enable I2C bit-bang interface
3001 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3003 s32 ret_val = E1000_SUCCESS;
3004 u32 ctrl_ext, i2cparams;
3006 DEBUGFUNC("e1000_set_i2c_bb");
3008 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3009 ctrl_ext |= E1000_CTRL_I2C_ENA;
3010 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3011 E1000_WRITE_FLUSH(hw);
3013 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3014 i2cparams |= E1000_I2CBB_EN;
3015 i2cparams |= E1000_I2C_DATA_OE_N;
3016 i2cparams |= E1000_I2C_CLK_OE_N;
3017 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3018 E1000_WRITE_FLUSH(hw);
3024 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3025 * @hw: pointer to hardware structure
3026 * @byte_offset: byte offset to read
3027 * @dev_addr: device address
3030 * Performs byte read operation over I2C interface at
3031 * a specified device address.
3033 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3034 u8 dev_addr, u8 *data)
3036 s32 status = E1000_SUCCESS;
3043 DEBUGFUNC("e1000_read_i2c_byte_generic");
3045 swfw_mask = E1000_SWFW_PHY0_SM;
3048 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3050 status = E1000_ERR_SWFW_SYNC;
3054 e1000_i2c_start(hw);
3056 /* Device Address and write indication */
3057 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3058 if (status != E1000_SUCCESS)
3061 status = e1000_get_i2c_ack(hw);
3062 if (status != E1000_SUCCESS)
3065 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3066 if (status != E1000_SUCCESS)
3069 status = e1000_get_i2c_ack(hw);
3070 if (status != E1000_SUCCESS)
3073 e1000_i2c_start(hw);
3075 /* Device Address and read indication */
3076 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3077 if (status != E1000_SUCCESS)
3080 status = e1000_get_i2c_ack(hw);
3081 if (status != E1000_SUCCESS)
3084 e1000_clock_in_i2c_byte(hw, data);
3086 status = e1000_clock_out_i2c_bit(hw, nack);
3087 if (status != E1000_SUCCESS)
3094 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3096 e1000_i2c_bus_clear(hw);
3098 if (retry < max_retry)
3099 DEBUGOUT("I2C byte read error - Retrying.\n");
3101 DEBUGOUT("I2C byte read error.\n");
3103 } while (retry < max_retry);
3105 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3113 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3114 * @hw: pointer to hardware structure
3115 * @byte_offset: byte offset to write
3116 * @dev_addr: device address
3117 * @data: value to write
3119 * Performs byte write operation over I2C interface at
3120 * a specified device address.
3122 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3123 u8 dev_addr, u8 data)
3125 s32 status = E1000_SUCCESS;
3130 DEBUGFUNC("e1000_write_i2c_byte_generic");
3132 swfw_mask = E1000_SWFW_PHY0_SM;
3134 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3135 status = E1000_ERR_SWFW_SYNC;
3136 goto write_byte_out;
3140 e1000_i2c_start(hw);
3142 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3143 if (status != E1000_SUCCESS)
3146 status = e1000_get_i2c_ack(hw);
3147 if (status != E1000_SUCCESS)
3150 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3151 if (status != E1000_SUCCESS)
3154 status = e1000_get_i2c_ack(hw);
3155 if (status != E1000_SUCCESS)
3158 status = e1000_clock_out_i2c_byte(hw, data);
3159 if (status != E1000_SUCCESS)
3162 status = e1000_get_i2c_ack(hw);
3163 if (status != E1000_SUCCESS)
3170 e1000_i2c_bus_clear(hw);
3172 if (retry < max_retry)
3173 DEBUGOUT("I2C byte write error - Retrying.\n");
3175 DEBUGOUT("I2C byte write error.\n");
3176 } while (retry < max_retry);
3178 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3186 * e1000_i2c_start - Sets I2C start condition
3187 * @hw: pointer to hardware structure
3189 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3191 static void e1000_i2c_start(struct e1000_hw *hw)
3193 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3195 DEBUGFUNC("e1000_i2c_start");
3197 /* Start condition must begin with data and clock high */
3198 e1000_set_i2c_data(hw, &i2cctl, 1);
3199 e1000_raise_i2c_clk(hw, &i2cctl);
3201 /* Setup time for start condition (4.7us) */
3202 usec_delay(E1000_I2C_T_SU_STA);
3204 e1000_set_i2c_data(hw, &i2cctl, 0);
3206 /* Hold time for start condition (4us) */
3207 usec_delay(E1000_I2C_T_HD_STA);
3209 e1000_lower_i2c_clk(hw, &i2cctl);
3211 /* Minimum low period of clock is 4.7 us */
3212 usec_delay(E1000_I2C_T_LOW);
3217 * e1000_i2c_stop - Sets I2C stop condition
3218 * @hw: pointer to hardware structure
3220 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3222 static void e1000_i2c_stop(struct e1000_hw *hw)
3224 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3226 DEBUGFUNC("e1000_i2c_stop");
3228 /* Stop condition must begin with data low and clock high */
3229 e1000_set_i2c_data(hw, &i2cctl, 0);
3230 e1000_raise_i2c_clk(hw, &i2cctl);
3232 /* Setup time for stop condition (4us) */
3233 usec_delay(E1000_I2C_T_SU_STO);
3235 e1000_set_i2c_data(hw, &i2cctl, 1);
3237 /* bus free time between stop and start (4.7us)*/
3238 usec_delay(E1000_I2C_T_BUF);
3242 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3243 * @hw: pointer to hardware structure
3244 * @data: data byte to clock in
3246 * Clocks in one byte data via I2C data/clock
3248 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3253 DEBUGFUNC("e1000_clock_in_i2c_byte");
3256 for (i = 7; i >= 0; i--) {
3257 e1000_clock_in_i2c_bit(hw, &bit);
3263 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3264 * @hw: pointer to hardware structure
3265 * @data: data byte clocked out
3267 * Clocks out one byte data via I2C data/clock
3269 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3271 s32 status = E1000_SUCCESS;
3276 DEBUGFUNC("e1000_clock_out_i2c_byte");
3278 for (i = 7; i >= 0; i--) {
3279 bit = (data >> i) & 0x1;
3280 status = e1000_clock_out_i2c_bit(hw, bit);
3282 if (status != E1000_SUCCESS)
3286 /* Release SDA line (set high) */
3287 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3289 i2cctl |= E1000_I2C_DATA_OE_N;
3290 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3291 E1000_WRITE_FLUSH(hw);
3297 * e1000_get_i2c_ack - Polls for I2C ACK
3298 * @hw: pointer to hardware structure
3300 * Clocks in/out one bit via I2C data/clock
3302 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3304 s32 status = E1000_SUCCESS;
3306 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3310 DEBUGFUNC("e1000_get_i2c_ack");
3312 e1000_raise_i2c_clk(hw, &i2cctl);
3314 /* Minimum high period of clock is 4us */
3315 usec_delay(E1000_I2C_T_HIGH);
3317 /* Wait until SCL returns high */
3318 for (i = 0; i < timeout; i++) {
3320 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3321 if (i2cctl & E1000_I2C_CLK_IN)
3324 if (!(i2cctl & E1000_I2C_CLK_IN))
3325 return E1000_ERR_I2C;
3327 ack = e1000_get_i2c_data(&i2cctl);
3329 DEBUGOUT("I2C ack was not received.\n");
3330 status = E1000_ERR_I2C;
3333 e1000_lower_i2c_clk(hw, &i2cctl);
3335 /* Minimum low period of clock is 4.7 us */
3336 usec_delay(E1000_I2C_T_LOW);
3342 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3343 * @hw: pointer to hardware structure
3344 * @data: read data value
3346 * Clocks in one bit via I2C data/clock
3348 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3350 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3352 DEBUGFUNC("e1000_clock_in_i2c_bit");
3354 e1000_raise_i2c_clk(hw, &i2cctl);
3356 /* Minimum high period of clock is 4us */
3357 usec_delay(E1000_I2C_T_HIGH);
3359 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3360 *data = e1000_get_i2c_data(&i2cctl);
3362 e1000_lower_i2c_clk(hw, &i2cctl);
3364 /* Minimum low period of clock is 4.7 us */
3365 usec_delay(E1000_I2C_T_LOW);
3369 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3370 * @hw: pointer to hardware structure
3371 * @data: data value to write
3373 * Clocks out one bit via I2C data/clock
3375 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3378 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3380 DEBUGFUNC("e1000_clock_out_i2c_bit");
3382 status = e1000_set_i2c_data(hw, &i2cctl, data);
3383 if (status == E1000_SUCCESS) {
3384 e1000_raise_i2c_clk(hw, &i2cctl);
3386 /* Minimum high period of clock is 4us */
3387 usec_delay(E1000_I2C_T_HIGH);
3389 e1000_lower_i2c_clk(hw, &i2cctl);
3391 /* Minimum low period of clock is 4.7 us.
3392 * This also takes care of the data hold time.
3394 usec_delay(E1000_I2C_T_LOW);
3396 status = E1000_ERR_I2C;
3397 DEBUGOUT1("I2C data was not set to %X\n", data);
3403 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3404 * @hw: pointer to hardware structure
3405 * @i2cctl: Current value of I2CCTL register
3407 * Raises the I2C clock line '0'->'1'
3409 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3411 DEBUGFUNC("e1000_raise_i2c_clk");
3413 *i2cctl |= E1000_I2C_CLK_OUT;
3414 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3415 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3416 E1000_WRITE_FLUSH(hw);
3418 /* SCL rise time (1000ns) */
3419 usec_delay(E1000_I2C_T_RISE);
3423 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3424 * @hw: pointer to hardware structure
3425 * @i2cctl: Current value of I2CCTL register
3427 * Lowers the I2C clock line '1'->'0'
3429 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3432 DEBUGFUNC("e1000_lower_i2c_clk");
3434 *i2cctl &= ~E1000_I2C_CLK_OUT;
3435 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3436 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3437 E1000_WRITE_FLUSH(hw);
3439 /* SCL fall time (300ns) */
3440 usec_delay(E1000_I2C_T_FALL);
3444 * e1000_set_i2c_data - Sets the I2C data bit
3445 * @hw: pointer to hardware structure
3446 * @i2cctl: Current value of I2CCTL register
3447 * @data: I2C data value (0 or 1) to set
3449 * Sets the I2C data bit
3451 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3453 s32 status = E1000_SUCCESS;
3455 DEBUGFUNC("e1000_set_i2c_data");
3458 *i2cctl |= E1000_I2C_DATA_OUT;
3460 *i2cctl &= ~E1000_I2C_DATA_OUT;
3462 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3463 *i2cctl |= E1000_I2C_CLK_OE_N;
3464 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3465 E1000_WRITE_FLUSH(hw);
3467 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3468 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3470 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3471 if (data != e1000_get_i2c_data(i2cctl)) {
3472 status = E1000_ERR_I2C;
3473 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3480 * e1000_get_i2c_data - Reads the I2C SDA data bit
3481 * @i2cctl: Current value of I2CCTL register
3483 * Returns the I2C data bit value
3485 static bool e1000_get_i2c_data(u32 *i2cctl)
3489 DEBUGFUNC("e1000_get_i2c_data");
3491 if (*i2cctl & E1000_I2C_DATA_IN)
3500 * e1000_i2c_bus_clear - Clears the I2C bus
3501 * @hw: pointer to hardware structure
3503 * Clears the I2C bus by sending nine clock pulses.
3504 * Used when data line is stuck low.
3506 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3508 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3511 DEBUGFUNC("e1000_i2c_bus_clear");
3513 e1000_i2c_start(hw);
3515 e1000_set_i2c_data(hw, &i2cctl, 1);
3517 for (i = 0; i < 9; i++) {
3518 e1000_raise_i2c_clk(hw, &i2cctl);
3520 /* Min high period of clock is 4us */
3521 usec_delay(E1000_I2C_T_HIGH);
3523 e1000_lower_i2c_clk(hw, &i2cctl);
3525 /* Min low period of clock is 4.7us*/
3526 usec_delay(E1000_I2C_T_LOW);
3529 e1000_i2c_start(hw);
3531 /* Put the i2c bus back to default state */