1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
37 * 82575EB Gigabit Network Connection
38 * 82575EB Gigabit Backplane Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter
42 * 82580 Gigabit Network Connection
43 * I350 Gigabit Network Connection
46 #include "e1000_api.h"
47 #include "e1000_i210.h"
49 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
50 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
51 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
52 static void e1000_release_phy_82575(struct e1000_hw *hw);
53 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
54 static void e1000_release_nvm_82575(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
56 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
57 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
58 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
60 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
61 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
63 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
64 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
65 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 *data);
67 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
68 u32 offset, u16 data);
69 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
71 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
73 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
75 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
76 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
77 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
79 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
80 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
81 u32 offset, u16 data);
82 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 u16 *speed, u16 *duplex);
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
105 static void e1000_i2c_start(struct e1000_hw *hw);
106 static void e1000_i2c_stop(struct e1000_hw *hw);
107 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
108 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
109 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
110 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
111 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
112 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
113 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
115 static bool e1000_get_i2c_data(u32 *i2cctl);
117 static const u16 e1000_82580_rxpbs_table[] = {
118 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
119 #define E1000_82580_RXPBS_TABLE_SIZE \
120 (sizeof(e1000_82580_rxpbs_table) / \
121 sizeof(e1000_82580_rxpbs_table[0]))
125 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
126 * @hw: pointer to the HW structure
128 * Called to determine if the I2C pins are being used for I2C or as an
129 * external MDIO interface since the two options are mutually exclusive.
131 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
134 bool ext_mdio = FALSE;
136 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138 switch (hw->mac.type) {
141 reg = E1000_READ_REG(hw, E1000_MDIC);
142 ext_mdio = !!(reg & E1000_MDIC_DEST);
149 reg = E1000_READ_REG(hw, E1000_MDICNFG);
150 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
159 * e1000_init_phy_params_82575 - Init PHY func ptrs.
160 * @hw: pointer to the HW structure
162 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
164 struct e1000_phy_info *phy = &hw->phy;
165 s32 ret_val = E1000_SUCCESS;
168 DEBUGFUNC("e1000_init_phy_params_82575");
170 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
173 if (hw->phy.media_type != e1000_media_type_copper) {
174 phy->type = e1000_phy_none;
178 phy->ops.power_up = e1000_power_up_phy_copper;
179 phy->ops.power_down = e1000_power_down_phy_copper_82575;
181 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
182 phy->reset_delay_us = 100;
184 phy->ops.acquire = e1000_acquire_phy_82575;
185 phy->ops.check_reset_block = e1000_check_reset_block_generic;
186 phy->ops.commit = e1000_phy_sw_reset_generic;
187 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
188 phy->ops.release = e1000_release_phy_82575;
190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
192 if (e1000_sgmii_active_82575(hw)) {
193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194 ctrl_ext |= E1000_CTRL_I2C_ENA;
196 phy->ops.reset = e1000_phy_hw_reset_generic;
197 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 e1000_reset_mdicnfg_82580(hw);
203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
207 switch (hw->mac.type) {
211 phy->ops.read_reg = e1000_read_phy_reg_82580;
212 phy->ops.write_reg = e1000_write_phy_reg_82580;
216 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
217 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
220 phy->ops.read_reg = e1000_read_phy_reg_igp;
221 phy->ops.write_reg = e1000_write_phy_reg_igp;
225 /* Set phy->phy_addr and phy->id. */
226 ret_val = e1000_get_phy_id_82575(hw);
228 /* Verify phy id and set remaining function pointers */
230 case M88E1543_E_PHY_ID:
231 case M88E1512_E_PHY_ID:
232 case I347AT4_E_PHY_ID:
233 case M88E1112_E_PHY_ID:
234 case M88E1340M_E_PHY_ID:
235 case M88E1111_I_PHY_ID:
236 phy->type = e1000_phy_m88;
237 phy->ops.check_polarity = e1000_check_polarity_m88;
238 phy->ops.get_info = e1000_get_phy_info_m88;
239 if (phy->id == I347AT4_E_PHY_ID ||
240 phy->id == M88E1112_E_PHY_ID ||
241 phy->id == M88E1340M_E_PHY_ID)
242 phy->ops.get_cable_length =
243 e1000_get_cable_length_m88_gen2;
244 else if (phy->id == M88E1543_E_PHY_ID ||
245 phy->id == M88E1512_E_PHY_ID)
246 phy->ops.get_cable_length =
247 e1000_get_cable_length_m88_gen2;
249 phy->ops.get_cable_length = e1000_get_cable_length_m88;
250 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
251 /* Check if this PHY is confgured for media swap. */
252 if (phy->id == M88E1112_E_PHY_ID) {
255 ret_val = phy->ops.write_reg(hw,
256 E1000_M88E1112_PAGE_ADDR,
261 ret_val = phy->ops.read_reg(hw,
262 E1000_M88E1112_MAC_CTRL_1,
267 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
268 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
269 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
270 data == E1000_M88E1112_AUTO_COPPER_BASEX)
271 hw->mac.ops.check_for_link =
272 e1000_check_for_link_media_swap;
274 if (phy->id == M88E1512_E_PHY_ID) {
275 ret_val = e1000_initialize_M88E1512_phy(hw);
279 if (phy->id == M88E1543_E_PHY_ID) {
280 ret_val = e1000_initialize_M88E1543_phy(hw);
285 case IGP03E1000_E_PHY_ID:
286 case IGP04E1000_E_PHY_ID:
287 phy->type = e1000_phy_igp_3;
288 phy->ops.check_polarity = e1000_check_polarity_igp;
289 phy->ops.get_info = e1000_get_phy_info_igp;
290 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
291 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
292 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
293 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
295 case I82580_I_PHY_ID:
297 phy->type = e1000_phy_82580;
298 phy->ops.check_polarity = e1000_check_polarity_82577;
299 phy->ops.force_speed_duplex =
300 e1000_phy_force_speed_duplex_82577;
301 phy->ops.get_cable_length = e1000_get_cable_length_82577;
302 phy->ops.get_info = e1000_get_phy_info_82577;
303 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
307 phy->type = e1000_phy_i210;
308 phy->ops.check_polarity = e1000_check_polarity_m88;
309 phy->ops.get_info = e1000_get_phy_info_m88;
310 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
311 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
312 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
313 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
316 ret_val = -E1000_ERR_PHY;
325 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
326 * @hw: pointer to the HW structure
328 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
330 struct e1000_nvm_info *nvm = &hw->nvm;
331 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
334 DEBUGFUNC("e1000_init_nvm_params_82575");
336 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
337 E1000_EECD_SIZE_EX_SHIFT);
339 * Added to a constant, "size" becomes the left-shift value
340 * for setting word_size.
342 size += NVM_WORD_SIZE_BASE_SHIFT;
344 /* Just in case size is out of range, cap it to the largest
345 * EEPROM size supported
350 nvm->word_size = 1 << size;
351 if (hw->mac.type < e1000_i210) {
352 nvm->opcode_bits = 8;
355 switch (nvm->override) {
356 case e1000_nvm_override_spi_large:
358 nvm->address_bits = 16;
360 case e1000_nvm_override_spi_small:
362 nvm->address_bits = 8;
365 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
366 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
370 if (nvm->word_size == (1 << 15))
371 nvm->page_size = 128;
373 nvm->type = e1000_nvm_eeprom_spi;
375 nvm->type = e1000_nvm_flash_hw;
378 /* Function Pointers */
379 nvm->ops.acquire = e1000_acquire_nvm_82575;
380 nvm->ops.release = e1000_release_nvm_82575;
381 if (nvm->word_size < (1 << 15))
382 nvm->ops.read = e1000_read_nvm_eerd;
384 nvm->ops.read = e1000_read_nvm_spi;
386 nvm->ops.write = e1000_write_nvm_spi;
387 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
388 nvm->ops.update = e1000_update_nvm_checksum_generic;
389 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
391 /* override generic family function pointers for specific descendants */
392 switch (hw->mac.type) {
394 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
395 nvm->ops.update = e1000_update_nvm_checksum_82580;
399 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
400 nvm->ops.update = e1000_update_nvm_checksum_i350;
406 return E1000_SUCCESS;
410 * e1000_init_mac_params_82575 - Init MAC func ptrs.
411 * @hw: pointer to the HW structure
413 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
415 struct e1000_mac_info *mac = &hw->mac;
416 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
418 DEBUGFUNC("e1000_init_mac_params_82575");
420 /* Derives media type */
421 e1000_get_media_type_82575(hw);
422 /* Set mta register count */
423 mac->mta_reg_count = 128;
424 /* Set uta register count */
425 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
426 /* Set rar entry count */
427 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
428 if (mac->type == e1000_82576)
429 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
430 if (mac->type == e1000_82580)
431 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
432 if (mac->type == e1000_i350 || mac->type == e1000_i354)
433 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
435 /* Enable EEE default settings for EEE supported devices */
436 if (mac->type >= e1000_i350)
437 dev_spec->eee_disable = FALSE;
439 /* Allow a single clear of the SW semaphore on I210 and newer */
440 if (mac->type >= e1000_i210)
441 dev_spec->clear_semaphore_once = TRUE;
443 /* Set if part includes ASF firmware */
444 mac->asf_firmware_present = TRUE;
446 mac->has_fwsm = TRUE;
447 /* ARC supported; valid only if manageability features are enabled. */
448 mac->arc_subsystem_valid =
449 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
451 /* Function pointers */
453 /* bus type/speed/width */
454 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
456 if (mac->type >= e1000_82580)
457 mac->ops.reset_hw = e1000_reset_hw_82580;
459 mac->ops.reset_hw = e1000_reset_hw_82575;
460 /* hw initialization */
461 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
462 mac->ops.init_hw = e1000_init_hw_i210;
464 mac->ops.init_hw = e1000_init_hw_82575;
466 mac->ops.setup_link = e1000_setup_link_generic;
467 /* physical interface link setup */
468 mac->ops.setup_physical_interface =
469 (hw->phy.media_type == e1000_media_type_copper)
470 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
471 /* physical interface shutdown */
472 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
473 /* physical interface power up */
474 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
476 mac->ops.check_for_link = e1000_check_for_link_82575;
477 /* read mac address */
478 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
479 /* configure collision distance */
480 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
481 /* multicast address update */
482 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
483 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
485 mac->ops.write_vfta = e1000_write_vfta_i350;
487 mac->ops.clear_vfta = e1000_clear_vfta_i350;
490 mac->ops.write_vfta = e1000_write_vfta_generic;
492 mac->ops.clear_vfta = e1000_clear_vfta_generic;
494 if (hw->mac.type >= e1000_82580)
495 mac->ops.validate_mdi_setting =
496 e1000_validate_mdi_setting_crossover_generic;
498 mac->ops.id_led_init = e1000_id_led_init_generic;
500 mac->ops.blink_led = e1000_blink_led_generic;
502 mac->ops.setup_led = e1000_setup_led_generic;
504 mac->ops.cleanup_led = e1000_cleanup_led_generic;
505 /* turn on/off LED */
506 mac->ops.led_on = e1000_led_on_generic;
507 mac->ops.led_off = e1000_led_off_generic;
508 /* clear hardware counters */
509 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
511 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
512 /* acquire SW_FW sync */
513 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
514 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
516 /* set lan id for port to determine which phy lock to use */
517 hw->mac.ops.set_lan_id(hw);
519 return E1000_SUCCESS;
523 * e1000_init_function_pointers_82575 - Init func ptrs.
524 * @hw: pointer to the HW structure
526 * Called to initialize all function pointers and parameters.
528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
530 DEBUGFUNC("e1000_init_function_pointers_82575");
532 hw->mac.ops.init_params = e1000_init_mac_params_82575;
533 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
534 hw->phy.ops.init_params = e1000_init_phy_params_82575;
535 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
539 * e1000_acquire_phy_82575 - Acquire rights to access PHY
540 * @hw: pointer to the HW structure
542 * Acquire access rights to the correct PHY.
544 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
546 u16 mask = E1000_SWFW_PHY0_SM;
548 DEBUGFUNC("e1000_acquire_phy_82575");
550 if (hw->bus.func == E1000_FUNC_1)
551 mask = E1000_SWFW_PHY1_SM;
552 else if (hw->bus.func == E1000_FUNC_2)
553 mask = E1000_SWFW_PHY2_SM;
554 else if (hw->bus.func == E1000_FUNC_3)
555 mask = E1000_SWFW_PHY3_SM;
557 return hw->mac.ops.acquire_swfw_sync(hw, mask);
561 * e1000_release_phy_82575 - Release rights to access PHY
562 * @hw: pointer to the HW structure
564 * A wrapper to release access rights to the correct PHY.
566 static void e1000_release_phy_82575(struct e1000_hw *hw)
568 u16 mask = E1000_SWFW_PHY0_SM;
570 DEBUGFUNC("e1000_release_phy_82575");
572 if (hw->bus.func == E1000_FUNC_1)
573 mask = E1000_SWFW_PHY1_SM;
574 else if (hw->bus.func == E1000_FUNC_2)
575 mask = E1000_SWFW_PHY2_SM;
576 else if (hw->bus.func == E1000_FUNC_3)
577 mask = E1000_SWFW_PHY3_SM;
579 hw->mac.ops.release_swfw_sync(hw, mask);
583 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
584 * @hw: pointer to the HW structure
585 * @offset: register offset to be read
586 * @data: pointer to the read data
588 * Reads the PHY register at offset using the serial gigabit media independent
589 * interface and stores the retrieved information in data.
591 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
594 s32 ret_val = -E1000_ERR_PARAM;
596 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
598 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
599 DEBUGOUT1("PHY Address %u is out of range\n", offset);
603 ret_val = hw->phy.ops.acquire(hw);
607 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
609 hw->phy.ops.release(hw);
616 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
617 * @hw: pointer to the HW structure
618 * @offset: register offset to write to
619 * @data: data to write at register offset
621 * Writes the data to PHY register at the offset using the serial gigabit
622 * media independent interface.
624 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
627 s32 ret_val = -E1000_ERR_PARAM;
629 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
631 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
632 DEBUGOUT1("PHY Address %d is out of range\n", offset);
636 ret_val = hw->phy.ops.acquire(hw);
640 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
642 hw->phy.ops.release(hw);
649 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
650 * @hw: pointer to the HW structure
652 * Retrieves the PHY address and ID for both PHY's which do and do not use
655 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
657 struct e1000_phy_info *phy = &hw->phy;
658 s32 ret_val = E1000_SUCCESS;
663 DEBUGFUNC("e1000_get_phy_id_82575");
665 /* some i354 devices need an extra read for phy id */
666 if (hw->mac.type == e1000_i354)
667 e1000_get_phy_id(hw);
670 * For SGMII PHYs, we try the list of possible addresses until
671 * we find one that works. For non-SGMII PHYs
672 * (e.g. integrated copper PHYs), an address of 1 should
673 * work. The result of this function should mean phy->phy_addr
674 * and phy->id are set correctly.
676 if (!e1000_sgmii_active_82575(hw)) {
678 ret_val = e1000_get_phy_id(hw);
682 if (e1000_sgmii_uses_mdio_82575(hw)) {
683 switch (hw->mac.type) {
686 mdic = E1000_READ_REG(hw, E1000_MDIC);
687 mdic &= E1000_MDIC_PHY_MASK;
688 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
695 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
696 mdic &= E1000_MDICNFG_PHY_MASK;
697 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
700 ret_val = -E1000_ERR_PHY;
704 ret_val = e1000_get_phy_id(hw);
708 /* Power on sgmii phy if it is disabled */
709 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
710 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
711 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
712 E1000_WRITE_FLUSH(hw);
716 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
717 * Therefore, we need to test 1-7
719 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
720 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
721 if (ret_val == E1000_SUCCESS) {
722 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
725 * At the time of this writing, The M88 part is
726 * the only supported SGMII PHY product.
728 if (phy_id == M88_VENDOR)
731 DEBUGOUT1("PHY address %u was unreadable\n",
736 /* A valid PHY type couldn't be found. */
737 if (phy->addr == 8) {
739 ret_val = -E1000_ERR_PHY;
741 ret_val = e1000_get_phy_id(hw);
744 /* restore previous sfp cage power state */
745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
752 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
753 * @hw: pointer to the HW structure
755 * Resets the PHY using the serial gigabit media independent interface.
757 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
759 s32 ret_val = E1000_SUCCESS;
760 struct e1000_phy_info *phy = &hw->phy;
762 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
765 * This isn't a TRUE "hard" reset, but is the only reset
766 * available to us at this time.
769 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
771 if (!(hw->phy.ops.write_reg))
775 * SFP documentation requires the following to configure the SPF module
776 * to work on SGMII. No further documentation is given.
778 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
782 ret_val = hw->phy.ops.commit(hw);
786 if (phy->id == M88E1512_E_PHY_ID)
787 ret_val = e1000_initialize_M88E1512_phy(hw);
793 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
794 * @hw: pointer to the HW structure
795 * @active: TRUE to enable LPLU, FALSE to disable
797 * Sets the LPLU D0 state according to the active flag. When
798 * activating LPLU this function also disables smart speed
799 * and vice versa. LPLU will not be activated unless the
800 * device autonegotiation advertisement meets standards of
801 * either 10 or 10/100 or 10/100/1000 at all duplexes.
802 * This is a function pointer entry point only called by
803 * PHY setup routines.
805 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
807 struct e1000_phy_info *phy = &hw->phy;
808 s32 ret_val = E1000_SUCCESS;
811 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
813 if (!(hw->phy.ops.read_reg))
816 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
821 data |= IGP02E1000_PM_D0_LPLU;
822 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827 /* When LPLU is enabled, we should disable SmartSpeed */
828 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
830 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
831 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836 data &= ~IGP02E1000_PM_D0_LPLU;
837 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
840 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
841 * during Dx states where the power conservation is most
842 * important. During driver activity we should enable
843 * SmartSpeed, so performance is maintained.
845 if (phy->smart_speed == e1000_smart_speed_on) {
846 ret_val = phy->ops.read_reg(hw,
847 IGP01E1000_PHY_PORT_CONFIG,
852 data |= IGP01E1000_PSCFR_SMART_SPEED;
853 ret_val = phy->ops.write_reg(hw,
854 IGP01E1000_PHY_PORT_CONFIG,
858 } else if (phy->smart_speed == e1000_smart_speed_off) {
859 ret_val = phy->ops.read_reg(hw,
860 IGP01E1000_PHY_PORT_CONFIG,
865 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
866 ret_val = phy->ops.write_reg(hw,
867 IGP01E1000_PHY_PORT_CONFIG,
879 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
880 * @hw: pointer to the HW structure
881 * @active: TRUE to enable LPLU, FALSE to disable
883 * Sets the LPLU D0 state according to the active flag. When
884 * activating LPLU this function also disables smart speed
885 * and vice versa. LPLU will not be activated unless the
886 * device autonegotiation advertisement meets standards of
887 * either 10 or 10/100 or 10/100/1000 at all duplexes.
888 * This is a function pointer entry point only called by
889 * PHY setup routines.
891 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
893 struct e1000_phy_info *phy = &hw->phy;
896 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
898 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
901 data |= E1000_82580_PM_D0_LPLU;
903 /* When LPLU is enabled, we should disable SmartSpeed */
904 data &= ~E1000_82580_PM_SPD;
906 data &= ~E1000_82580_PM_D0_LPLU;
909 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
910 * during Dx states where the power conservation is most
911 * important. During driver activity we should enable
912 * SmartSpeed, so performance is maintained.
914 if (phy->smart_speed == e1000_smart_speed_on)
915 data |= E1000_82580_PM_SPD;
916 else if (phy->smart_speed == e1000_smart_speed_off)
917 data &= ~E1000_82580_PM_SPD;
920 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
921 return E1000_SUCCESS;
925 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
926 * @hw: pointer to the HW structure
927 * @active: boolean used to enable/disable lplu
929 * Success returns 0, Failure returns 1
931 * The low power link up (lplu) state is set to the power management level D3
932 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
933 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
934 * is used during Dx states where the power conservation is most important.
935 * During driver activity, SmartSpeed should be enabled so performance is
938 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
940 struct e1000_phy_info *phy = &hw->phy;
943 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
945 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
948 data &= ~E1000_82580_PM_D3_LPLU;
950 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
951 * during Dx states where the power conservation is most
952 * important. During driver activity we should enable
953 * SmartSpeed, so performance is maintained.
955 if (phy->smart_speed == e1000_smart_speed_on)
956 data |= E1000_82580_PM_SPD;
957 else if (phy->smart_speed == e1000_smart_speed_off)
958 data &= ~E1000_82580_PM_SPD;
959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
962 data |= E1000_82580_PM_D3_LPLU;
963 /* When LPLU is enabled, we should disable SmartSpeed */
964 data &= ~E1000_82580_PM_SPD;
967 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
968 return E1000_SUCCESS;
972 * e1000_acquire_nvm_82575 - Request for access to EEPROM
973 * @hw: pointer to the HW structure
975 * Acquire the necessary semaphores for exclusive access to the EEPROM.
976 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
977 * Return successful if access grant bit set, else clear the request for
978 * EEPROM access and return -E1000_ERR_NVM (-1).
980 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
982 s32 ret_val = E1000_SUCCESS;
984 DEBUGFUNC("e1000_acquire_nvm_82575");
986 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
991 * Check if there is some access
992 * error this access may hook on
994 if (hw->mac.type == e1000_i350) {
995 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
996 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
997 E1000_EECD_TIMEOUT)) {
998 /* Clear all access error flags */
999 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000 E1000_EECD_ERROR_CLR);
1001 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1005 if (hw->mac.type == e1000_82580) {
1006 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1007 if (eecd & E1000_EECD_BLOCKED) {
1008 /* Clear access error flag */
1009 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010 E1000_EECD_BLOCKED);
1011 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1015 ret_val = e1000_acquire_nvm_generic(hw);
1017 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1024 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1025 * @hw: pointer to the HW structure
1027 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1028 * then release the semaphores acquired.
1030 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1032 DEBUGFUNC("e1000_release_nvm_82575");
1034 e1000_release_nvm_generic(hw);
1036 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1040 * e1000_get_cfg_done_82575 - Read config done bit
1041 * @hw: pointer to the HW structure
1043 * Read the management control register for the config done bit for
1044 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1045 * to read the config done bit, so an error is *ONLY* logged and returns
1046 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1047 * would not be able to be reset or change link.
1049 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1051 s32 timeout = PHY_CFG_TIMEOUT;
1052 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1054 DEBUGFUNC("e1000_get_cfg_done_82575");
1056 if (hw->bus.func == E1000_FUNC_1)
1057 mask = E1000_NVM_CFG_DONE_PORT_1;
1058 else if (hw->bus.func == E1000_FUNC_2)
1059 mask = E1000_NVM_CFG_DONE_PORT_2;
1060 else if (hw->bus.func == E1000_FUNC_3)
1061 mask = E1000_NVM_CFG_DONE_PORT_3;
1063 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1069 DEBUGOUT("MNG configuration cycle has not completed.\n");
1071 /* If EEPROM is not marked present, init the PHY manually */
1072 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1073 (hw->phy.type == e1000_phy_igp_3))
1074 e1000_phy_init_script_igp3(hw);
1076 return E1000_SUCCESS;
1080 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1081 * @hw: pointer to the HW structure
1082 * @speed: stores the current speed
1083 * @duplex: stores the current duplex
1085 * This is a wrapper function, if using the serial gigabit media independent
1086 * interface, use PCS to retrieve the link speed and duplex information.
1087 * Otherwise, use the generic function to get the link speed and duplex info.
1089 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1094 DEBUGFUNC("e1000_get_link_up_info_82575");
1096 if (hw->phy.media_type != e1000_media_type_copper)
1097 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1100 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1107 * e1000_check_for_link_82575 - Check for link
1108 * @hw: pointer to the HW structure
1110 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1111 * use the generic interface for determining link.
1113 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1118 DEBUGFUNC("e1000_check_for_link_82575");
1120 if (hw->phy.media_type != e1000_media_type_copper) {
1121 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1124 * Use this flag to determine if link needs to be checked or
1125 * not. If we have link clear the flag so that we do not
1126 * continue to check for link.
1128 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1131 * Configure Flow Control now that Auto-Neg has completed.
1132 * First, we need to restore the desired flow control
1133 * settings because we may have had to re-autoneg with a
1134 * different link partner.
1136 ret_val = e1000_config_fc_after_link_up_generic(hw);
1138 DEBUGOUT("Error configuring flow control\n");
1140 ret_val = e1000_check_for_copper_link_generic(hw);
1147 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1148 * @hw: pointer to the HW structure
1150 * Poll the M88E1112 interfaces to see which interface achieved link.
1152 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1154 struct e1000_phy_info *phy = &hw->phy;
1159 DEBUGFUNC("e1000_check_for_link_media_swap");
1161 /* Check for copper. */
1162 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1166 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1170 if (data & E1000_M88E1112_STATUS_LINK)
1171 port = E1000_MEDIA_PORT_COPPER;
1173 /* Check for other. */
1174 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1178 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1182 if (data & E1000_M88E1112_STATUS_LINK)
1183 port = E1000_MEDIA_PORT_OTHER;
1185 /* Determine if a swap needs to happen. */
1186 if (port && (hw->dev_spec._82575.media_port != port)) {
1187 hw->dev_spec._82575.media_port = port;
1188 hw->dev_spec._82575.media_changed = TRUE;
1191 if (port == E1000_MEDIA_PORT_COPPER) {
1192 /* reset page to 0 */
1193 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1196 e1000_check_for_link_82575(hw);
1198 e1000_check_for_link_82575(hw);
1199 /* reset page to 0 */
1200 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1205 return E1000_SUCCESS;
1209 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1210 * @hw: pointer to the HW structure
1212 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1216 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1218 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1219 !e1000_sgmii_active_82575(hw))
1222 /* Enable PCS to turn on link */
1223 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1224 reg |= E1000_PCS_CFG_PCS_EN;
1225 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1227 /* Power up the laser */
1228 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1229 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1230 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1232 /* flush the write to verify completion */
1233 E1000_WRITE_FLUSH(hw);
1238 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1239 * @hw: pointer to the HW structure
1240 * @speed: stores the current speed
1241 * @duplex: stores the current duplex
1243 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1244 * duplex, then store the values in the pointers provided.
1246 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1247 u16 *speed, u16 *duplex)
1249 struct e1000_mac_info *mac = &hw->mac;
1253 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1256 * Read the PCS Status register for link state. For non-copper mode,
1257 * the status register is not accurate. The PCS status register is
1260 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1263 * The link up bit determines when link is up on autoneg.
1265 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1266 mac->serdes_has_link = TRUE;
1268 /* Detect and store PCS speed */
1269 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1270 *speed = SPEED_1000;
1271 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1276 /* Detect and store PCS duplex */
1277 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1278 *duplex = FULL_DUPLEX;
1280 *duplex = HALF_DUPLEX;
1282 /* Check if it is an I354 2.5Gb backplane connection. */
1283 if (mac->type == e1000_i354) {
1284 status = E1000_READ_REG(hw, E1000_STATUS);
1285 if ((status & E1000_STATUS_2P5_SKU) &&
1286 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1287 *speed = SPEED_2500;
1288 *duplex = FULL_DUPLEX;
1289 DEBUGOUT("2500 Mbs, ");
1290 DEBUGOUT("Full Duplex\n");
1295 mac->serdes_has_link = FALSE;
1300 return E1000_SUCCESS;
1304 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1305 * @hw: pointer to the HW structure
1307 * In the case of serdes shut down sfp and PCS on driver unload
1308 * when management pass thru is not enabled.
1310 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1314 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1316 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1317 !e1000_sgmii_active_82575(hw))
1320 if (!e1000_enable_mng_pass_thru(hw)) {
1321 /* Disable PCS to turn off link */
1322 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1323 reg &= ~E1000_PCS_CFG_PCS_EN;
1324 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1326 /* shutdown the laser */
1327 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328 reg |= E1000_CTRL_EXT_SDP3_DATA;
1329 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1331 /* flush the write to verify completion */
1332 E1000_WRITE_FLUSH(hw);
1340 * e1000_reset_hw_82575 - Reset hardware
1341 * @hw: pointer to the HW structure
1343 * This resets the hardware into a known state.
1345 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1350 DEBUGFUNC("e1000_reset_hw_82575");
1353 * Prevent the PCI-E bus from sticking if there is no TLP connection
1354 * on the last TLP read/write transaction when MAC is reset.
1356 ret_val = e1000_disable_pcie_master_generic(hw);
1358 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1360 /* set the completion timeout for interface */
1361 ret_val = e1000_set_pcie_completion_timeout(hw);
1363 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1365 DEBUGOUT("Masking off all interrupts\n");
1366 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1368 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1369 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1370 E1000_WRITE_FLUSH(hw);
1374 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1376 DEBUGOUT("Issuing a global reset to MAC\n");
1377 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1379 ret_val = e1000_get_auto_rd_done_generic(hw);
1382 * When auto config read does not complete, do not
1383 * return with an error. This can happen in situations
1384 * where there is no eeprom and prevents getting link.
1386 DEBUGOUT("Auto Read Done did not complete\n");
1389 /* If EEPROM is not present, run manual init scripts */
1390 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1391 e1000_reset_init_script_82575(hw);
1393 /* Clear any pending interrupt events. */
1394 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1395 E1000_READ_REG(hw, E1000_ICR);
1397 /* Install any alternate MAC address into RAR0 */
1398 ret_val = e1000_check_alt_mac_addr_generic(hw);
1404 * e1000_init_hw_82575 - Initialize hardware
1405 * @hw: pointer to the HW structure
1407 * This inits the hardware readying it for operation.
1409 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1411 struct e1000_mac_info *mac = &hw->mac;
1413 u16 i, rar_count = mac->rar_entry_count;
1415 DEBUGFUNC("e1000_init_hw_82575");
1417 /* Initialize identification LED */
1418 ret_val = mac->ops.id_led_init(hw);
1420 DEBUGOUT("Error initializing identification LED\n");
1421 /* This is not fatal and we should not stop init due to this */
1424 /* Disabling VLAN filtering */
1425 DEBUGOUT("Initializing the IEEE VLAN\n");
1426 mac->ops.clear_vfta(hw);
1428 /* Setup the receive address */
1429 e1000_init_rx_addrs_generic(hw, rar_count);
1431 /* Zero out the Multicast HASH table */
1432 DEBUGOUT("Zeroing the MTA\n");
1433 for (i = 0; i < mac->mta_reg_count; i++)
1434 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1436 /* Zero out the Unicast HASH table */
1437 DEBUGOUT("Zeroing the UTA\n");
1438 for (i = 0; i < mac->uta_reg_count; i++)
1439 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1441 /* Setup link and flow control */
1442 ret_val = mac->ops.setup_link(hw);
1444 /* Set the default MTU size */
1445 hw->dev_spec._82575.mtu = 1500;
1448 * Clear all of the statistics registers (clear on read). It is
1449 * important that we do this after we have tried to establish link
1450 * because the symbol error count will increment wildly if there
1453 e1000_clear_hw_cntrs_82575(hw);
1459 * e1000_setup_copper_link_82575 - Configure copper link settings
1460 * @hw: pointer to the HW structure
1462 * Configures the link for auto-neg or forced speed and duplex. Then we check
1463 * for link, once link is established calls to configure collision distance
1464 * and flow control are called.
1466 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1472 DEBUGFUNC("e1000_setup_copper_link_82575");
1474 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1475 ctrl |= E1000_CTRL_SLU;
1476 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1477 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1479 /* Clear Go Link Disconnect bit on supported devices */
1480 switch (hw->mac.type) {
1485 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1486 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1487 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1493 ret_val = e1000_setup_serdes_link_82575(hw);
1497 if (e1000_sgmii_active_82575(hw)) {
1498 /* allow time for SFP cage time to power up phy */
1501 ret_val = hw->phy.ops.reset(hw);
1503 DEBUGOUT("Error resetting the PHY.\n");
1507 switch (hw->phy.type) {
1508 case e1000_phy_i210:
1510 switch (hw->phy.id) {
1511 case I347AT4_E_PHY_ID:
1512 case M88E1112_E_PHY_ID:
1513 case M88E1340M_E_PHY_ID:
1514 case M88E1543_E_PHY_ID:
1515 case M88E1512_E_PHY_ID:
1517 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1520 ret_val = e1000_copper_link_setup_m88(hw);
1524 case e1000_phy_igp_3:
1525 ret_val = e1000_copper_link_setup_igp(hw);
1527 case e1000_phy_82580:
1528 ret_val = e1000_copper_link_setup_82577(hw);
1531 ret_val = -E1000_ERR_PHY;
1538 ret_val = e1000_setup_copper_link_generic(hw);
1544 * e1000_setup_serdes_link_82575 - Setup link for serdes
1545 * @hw: pointer to the HW structure
1547 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1548 * used on copper connections where the serialized gigabit media independent
1549 * interface (sgmii), or serdes fiber is being used. Configures the link
1550 * for auto-negotiation or forces speed/duplex.
1552 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1554 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1556 s32 ret_val = E1000_SUCCESS;
1559 DEBUGFUNC("e1000_setup_serdes_link_82575");
1561 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1562 !e1000_sgmii_active_82575(hw))
1566 * On the 82575, SerDes loopback mode persists until it is
1567 * explicitly turned off or a power cycle is performed. A read to
1568 * the register does not indicate its status. Therefore, we ensure
1569 * loopback mode is disabled during initialization.
1571 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1573 /* power on the sfp cage if present */
1574 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1575 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1576 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1578 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1579 ctrl_reg |= E1000_CTRL_SLU;
1581 /* set both sw defined pins on 82575/82576*/
1582 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1583 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1585 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1587 /* default pcs_autoneg to the same setting as mac autoneg */
1588 pcs_autoneg = hw->mac.autoneg;
1590 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1591 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1592 /* sgmii mode lets the phy handle forcing speed/duplex */
1594 /* autoneg time out should be disabled for SGMII mode */
1595 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1597 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1598 /* disable PCS autoneg and support parallel detect only */
1599 pcs_autoneg = FALSE;
1602 if (hw->mac.type == e1000_82575 ||
1603 hw->mac.type == e1000_82576) {
1604 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1606 DEBUGOUT("NVM Read Error\n");
1610 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1611 pcs_autoneg = FALSE;
1615 * non-SGMII modes only supports a speed of 1000/Full for the
1616 * link so it is best to just force the MAC and let the pcs
1617 * link either autoneg or be forced to 1000/Full
1619 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1620 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1622 /* set speed of 1000/Full if speed/duplex is forced */
1623 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1627 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1630 * New SerDes mode allows for forcing speed or autonegotiating speed
1631 * at 1gb. Autoneg should be default set by most drivers. This is the
1632 * mode that will be compatible with older link partners and switches.
1633 * However, both are supported by the hardware and some drivers/tools.
1635 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1636 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1639 /* Set PCS register for autoneg */
1640 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1641 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1643 /* Disable force flow control for autoneg */
1644 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1646 /* Configure flow control advertisement for autoneg */
1647 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1648 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1650 switch (hw->fc.requested_mode) {
1652 case e1000_fc_rx_pause:
1653 anadv_reg |= E1000_TXCW_ASM_DIR;
1654 anadv_reg |= E1000_TXCW_PAUSE;
1656 case e1000_fc_tx_pause:
1657 anadv_reg |= E1000_TXCW_ASM_DIR;
1663 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1665 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1667 /* Set PCS register for forced link */
1668 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1670 /* Force flow control for forced link */
1671 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1673 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1676 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1678 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1679 e1000_force_mac_fc_generic(hw);
1685 * e1000_get_media_type_82575 - derives current media type.
1686 * @hw: pointer to the HW structure
1688 * The media type is chosen reflecting few settings.
1689 * The following are taken into account:
1690 * - link mode set in the current port Init Control Word #3
1691 * - current link mode settings in CSR register
1692 * - MDIO vs. I2C PHY control interface chosen
1693 * - SFP module media type
1695 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1697 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1698 s32 ret_val = E1000_SUCCESS;
1702 /* Set internal phy as default */
1703 dev_spec->sgmii_active = FALSE;
1704 dev_spec->module_plugged = FALSE;
1706 /* Get CSR setting */
1707 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1709 /* extract link mode setting */
1710 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1712 switch (link_mode) {
1713 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1714 hw->phy.media_type = e1000_media_type_internal_serdes;
1716 case E1000_CTRL_EXT_LINK_MODE_GMII:
1717 hw->phy.media_type = e1000_media_type_copper;
1719 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1720 /* Get phy control interface type set (MDIO vs. I2C)*/
1721 if (e1000_sgmii_uses_mdio_82575(hw)) {
1722 hw->phy.media_type = e1000_media_type_copper;
1723 dev_spec->sgmii_active = TRUE;
1726 /* fall through for I2C based SGMII */
1728 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1729 /* read media type from SFP EEPROM */
1730 ret_val = e1000_set_sfp_media_type_82575(hw);
1731 if ((ret_val != E1000_SUCCESS) ||
1732 (hw->phy.media_type == e1000_media_type_unknown)) {
1734 * If media type was not identified then return media
1735 * type defined by the CTRL_EXT settings.
1737 hw->phy.media_type = e1000_media_type_internal_serdes;
1739 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1740 hw->phy.media_type = e1000_media_type_copper;
1741 dev_spec->sgmii_active = TRUE;
1747 /* do not change link mode for 100BaseFX */
1748 if (dev_spec->eth_flags.e100_base_fx)
1751 /* change current link mode setting */
1752 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1754 if (hw->phy.media_type == e1000_media_type_copper)
1755 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1757 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1759 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1768 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1769 * @hw: pointer to the HW structure
1771 * The media type is chosen based on SFP module.
1772 * compatibility flags retrieved from SFP ID EEPROM.
1774 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1776 s32 ret_val = E1000_ERR_CONFIG;
1778 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1779 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1780 u8 tranceiver_type = 0;
1783 /* Turn I2C interface ON and power on sfp cage */
1784 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1785 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1786 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1788 E1000_WRITE_FLUSH(hw);
1790 /* Read SFP module data */
1792 ret_val = e1000_read_sfp_data_byte(hw,
1793 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1795 if (ret_val == E1000_SUCCESS)
1800 if (ret_val != E1000_SUCCESS)
1803 ret_val = e1000_read_sfp_data_byte(hw,
1804 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1806 if (ret_val != E1000_SUCCESS)
1809 /* Check if there is some SFP module plugged and powered */
1810 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1811 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1812 dev_spec->module_plugged = TRUE;
1813 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1814 hw->phy.media_type = e1000_media_type_internal_serdes;
1815 } else if (eth_flags->e100_base_fx) {
1816 dev_spec->sgmii_active = TRUE;
1817 hw->phy.media_type = e1000_media_type_internal_serdes;
1818 } else if (eth_flags->e1000_base_t) {
1819 dev_spec->sgmii_active = TRUE;
1820 hw->phy.media_type = e1000_media_type_copper;
1822 hw->phy.media_type = e1000_media_type_unknown;
1823 DEBUGOUT("PHY module has not been recognized\n");
1827 hw->phy.media_type = e1000_media_type_unknown;
1829 ret_val = E1000_SUCCESS;
1831 /* Restore I2C interface setting */
1832 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1837 * e1000_valid_led_default_82575 - Verify a valid default LED config
1838 * @hw: pointer to the HW structure
1839 * @data: pointer to the NVM (EEPROM)
1841 * Read the EEPROM for the current default LED configuration. If the
1842 * LED configuration is not valid, set to a valid LED configuration.
1844 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1848 DEBUGFUNC("e1000_valid_led_default_82575");
1850 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1852 DEBUGOUT("NVM Read Error\n");
1856 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1857 switch (hw->phy.media_type) {
1858 case e1000_media_type_internal_serdes:
1859 *data = ID_LED_DEFAULT_82575_SERDES;
1861 case e1000_media_type_copper:
1863 *data = ID_LED_DEFAULT;
1872 * e1000_sgmii_active_82575 - Return sgmii state
1873 * @hw: pointer to the HW structure
1875 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1876 * which can be enabled for use in the embedded applications. Simply
1877 * return the current state of the sgmii interface.
1879 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1881 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1882 return dev_spec->sgmii_active;
1886 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1887 * @hw: pointer to the HW structure
1889 * Inits recommended HW defaults after a reset when there is no EEPROM
1890 * detected. This is only for the 82575.
1892 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1894 DEBUGFUNC("e1000_reset_init_script_82575");
1896 if (hw->mac.type == e1000_82575) {
1897 DEBUGOUT("Running reset init script for 82575\n");
1898 /* SerDes configuration via SERDESCTRL */
1899 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1900 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1901 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1902 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1904 /* CCM configuration via CCMCTL register */
1905 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1906 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1908 /* PCIe lanes configuration */
1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1910 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1911 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1912 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1914 /* PCIe PLL Configuration */
1915 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1916 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1917 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1920 return E1000_SUCCESS;
1924 * e1000_read_mac_addr_82575 - Read device MAC address
1925 * @hw: pointer to the HW structure
1927 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1931 DEBUGFUNC("e1000_read_mac_addr_82575");
1934 * If there's an alternate MAC address place it in RAR0
1935 * so that it will override the Si installed default perm
1938 ret_val = e1000_check_alt_mac_addr_generic(hw);
1942 ret_val = e1000_read_mac_addr_generic(hw);
1949 * e1000_config_collision_dist_82575 - Configure collision distance
1950 * @hw: pointer to the HW structure
1952 * Configures the collision distance to the default value and is used
1953 * during link setup.
1955 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1959 DEBUGFUNC("e1000_config_collision_dist_82575");
1961 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1963 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1964 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1966 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1967 E1000_WRITE_FLUSH(hw);
1971 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1972 * @hw: pointer to the HW structure
1974 * In the case of a PHY power down to save power, or to turn off link during a
1975 * driver unload, or wake on lan is not enabled, remove the link.
1977 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1979 struct e1000_phy_info *phy = &hw->phy;
1981 if (!(phy->ops.check_reset_block))
1984 /* If the management interface is not enabled, then power down */
1985 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1986 e1000_power_down_phy_copper(hw);
1992 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1993 * @hw: pointer to the HW structure
1995 * Clears the hardware counters by reading the counter registers.
1997 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1999 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2001 e1000_clear_hw_cntrs_base_generic(hw);
2003 E1000_READ_REG(hw, E1000_PRC64);
2004 E1000_READ_REG(hw, E1000_PRC127);
2005 E1000_READ_REG(hw, E1000_PRC255);
2006 E1000_READ_REG(hw, E1000_PRC511);
2007 E1000_READ_REG(hw, E1000_PRC1023);
2008 E1000_READ_REG(hw, E1000_PRC1522);
2009 E1000_READ_REG(hw, E1000_PTC64);
2010 E1000_READ_REG(hw, E1000_PTC127);
2011 E1000_READ_REG(hw, E1000_PTC255);
2012 E1000_READ_REG(hw, E1000_PTC511);
2013 E1000_READ_REG(hw, E1000_PTC1023);
2014 E1000_READ_REG(hw, E1000_PTC1522);
2016 E1000_READ_REG(hw, E1000_ALGNERRC);
2017 E1000_READ_REG(hw, E1000_RXERRC);
2018 E1000_READ_REG(hw, E1000_TNCRS);
2019 E1000_READ_REG(hw, E1000_CEXTERR);
2020 E1000_READ_REG(hw, E1000_TSCTC);
2021 E1000_READ_REG(hw, E1000_TSCTFC);
2023 E1000_READ_REG(hw, E1000_MGTPRC);
2024 E1000_READ_REG(hw, E1000_MGTPDC);
2025 E1000_READ_REG(hw, E1000_MGTPTC);
2027 E1000_READ_REG(hw, E1000_IAC);
2028 E1000_READ_REG(hw, E1000_ICRXOC);
2030 E1000_READ_REG(hw, E1000_ICRXPTC);
2031 E1000_READ_REG(hw, E1000_ICRXATC);
2032 E1000_READ_REG(hw, E1000_ICTXPTC);
2033 E1000_READ_REG(hw, E1000_ICTXATC);
2034 E1000_READ_REG(hw, E1000_ICTXQEC);
2035 E1000_READ_REG(hw, E1000_ICTXQMTC);
2036 E1000_READ_REG(hw, E1000_ICRXDMTC);
2038 E1000_READ_REG(hw, E1000_CBTMPC);
2039 E1000_READ_REG(hw, E1000_HTDPMC);
2040 E1000_READ_REG(hw, E1000_CBRMPC);
2041 E1000_READ_REG(hw, E1000_RPTHC);
2042 E1000_READ_REG(hw, E1000_HGPTC);
2043 E1000_READ_REG(hw, E1000_HTCBDPC);
2044 E1000_READ_REG(hw, E1000_HGORCL);
2045 E1000_READ_REG(hw, E1000_HGORCH);
2046 E1000_READ_REG(hw, E1000_HGOTCL);
2047 E1000_READ_REG(hw, E1000_HGOTCH);
2048 E1000_READ_REG(hw, E1000_LENERRS);
2050 /* This register should not be read in copper configurations */
2051 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2052 e1000_sgmii_active_82575(hw))
2053 E1000_READ_REG(hw, E1000_SCVPC);
2057 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2058 * @hw: pointer to the HW structure
2060 * After Rx enable, if manageability is enabled then there is likely some
2061 * bad data at the start of the fifo and possibly in the DMA fifo. This
2062 * function clears the fifos and flushes any packets that came in as rx was
2065 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2067 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2070 DEBUGFUNC("e1000_rx_fifo_flush_82575");
2072 /* disable IPv6 options as per hardware errata */
2073 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2074 rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2075 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2077 if (hw->mac.type != e1000_82575 ||
2078 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2081 /* Disable all Rx queues */
2082 for (i = 0; i < 4; i++) {
2083 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2084 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2085 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2087 /* Poll all queues to verify they have shut down */
2088 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2091 for (i = 0; i < 4; i++)
2092 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2093 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2098 DEBUGOUT("Queue disable timed out after 10ms\n");
2100 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2101 * incoming packets are rejected. Set enable and wait 2ms so that
2102 * any packet that was coming in as RCTL.EN was set is flushed
2104 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2106 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2107 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2109 rctl = E1000_READ_REG(hw, E1000_RCTL);
2110 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2111 temp_rctl |= E1000_RCTL_LPE;
2113 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2114 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2115 E1000_WRITE_FLUSH(hw);
2118 /* Enable Rx queues that were previously enabled and restore our
2121 for (i = 0; i < 4; i++)
2122 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2123 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2124 E1000_WRITE_FLUSH(hw);
2126 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2127 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2129 /* Flush receive errors generated by workaround */
2130 E1000_READ_REG(hw, E1000_ROC);
2131 E1000_READ_REG(hw, E1000_RNBC);
2132 E1000_READ_REG(hw, E1000_MPC);
2136 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2137 * @hw: pointer to the HW structure
2139 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2140 * however the hardware default for these parts is 500us to 1ms which is less
2141 * than the 10ms recommended by the pci-e spec. To address this we need to
2142 * increase the value to either 10ms to 200ms for capability version 1 config,
2143 * or 16ms to 55ms for version 2.
2145 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2147 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2148 s32 ret_val = E1000_SUCCESS;
2151 /* only take action if timeout value is defaulted to 0 */
2152 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2156 * if capababilities version is type 1 we can write the
2157 * timeout of 10ms to 200ms through the GCR register
2159 if (!(gcr & E1000_GCR_CAP_VER2)) {
2160 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2165 * for version 2 capabilities we need to write the config space
2166 * directly in order to set the completion timeout value for
2169 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2174 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2176 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2179 /* disable completion timeout resend */
2180 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2182 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2187 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2188 * @hw: pointer to the hardware struct
2189 * @enable: state to enter, either enabled or disabled
2190 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2192 * enables/disables L2 switch anti-spoofing functionality.
2194 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2196 u32 reg_val, reg_offset;
2198 switch (hw->mac.type) {
2200 reg_offset = E1000_DTXSWC;
2204 reg_offset = E1000_TXSWC;
2210 reg_val = E1000_READ_REG(hw, reg_offset);
2212 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2213 E1000_DTXSWC_VLAN_SPOOF_MASK);
2214 /* The PF can spoof - it has to in order to
2215 * support emulation mode NICs
2217 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2219 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2220 E1000_DTXSWC_VLAN_SPOOF_MASK);
2222 E1000_WRITE_REG(hw, reg_offset, reg_val);
2226 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2227 * @hw: pointer to the hardware struct
2228 * @enable: state to enter, either enabled or disabled
2230 * enables/disables L2 switch loopback functionality.
2232 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2236 switch (hw->mac.type) {
2238 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2240 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2242 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2243 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2247 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2249 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2251 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2252 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2255 /* Currently no other hardware supports loopback */
2263 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2264 * @hw: pointer to the hardware struct
2265 * @enable: state to enter, either enabled or disabled
2267 * enables/disables replication of packets across multiple pools.
2269 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2271 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2274 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2276 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2278 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2282 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2283 * @hw: pointer to the HW structure
2284 * @offset: register offset to be read
2285 * @data: pointer to the read data
2287 * Reads the MDI control register in the PHY at offset and stores the
2288 * information read to data.
2290 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2294 DEBUGFUNC("e1000_read_phy_reg_82580");
2296 ret_val = hw->phy.ops.acquire(hw);
2300 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2302 hw->phy.ops.release(hw);
2309 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2310 * @hw: pointer to the HW structure
2311 * @offset: register offset to write to
2312 * @data: data to write to register at offset
2314 * Writes data to MDI control register in the PHY at offset.
2316 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2320 DEBUGFUNC("e1000_write_phy_reg_82580");
2322 ret_val = hw->phy.ops.acquire(hw);
2326 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2328 hw->phy.ops.release(hw);
2335 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2336 * @hw: pointer to the HW structure
2338 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2339 * the values found in the EEPROM. This addresses an issue in which these
2340 * bits are not restored from EEPROM after reset.
2342 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2344 s32 ret_val = E1000_SUCCESS;
2348 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2350 if (hw->mac.type != e1000_82580)
2352 if (!e1000_sgmii_active_82575(hw))
2355 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2356 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2359 DEBUGOUT("NVM Read Error\n");
2363 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2364 if (nvm_data & NVM_WORD24_EXT_MDIO)
2365 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2366 if (nvm_data & NVM_WORD24_COM_MDIO)
2367 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2368 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2374 * e1000_reset_hw_82580 - Reset hardware
2375 * @hw: pointer to the HW structure
2377 * This resets function or entire device (all ports, etc.)
2380 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2382 s32 ret_val = E1000_SUCCESS;
2383 /* BH SW mailbox bit in SW_FW_SYNC */
2384 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2386 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2388 DEBUGFUNC("e1000_reset_hw_82580");
2390 hw->dev_spec._82575.global_device_reset = FALSE;
2392 /* 82580 does not reliably do global_device_reset due to hw errata */
2393 if (hw->mac.type == e1000_82580)
2394 global_device_reset = FALSE;
2396 /* Get current control state. */
2397 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2400 * Prevent the PCI-E bus from sticking if there is no TLP connection
2401 * on the last TLP read/write transaction when MAC is reset.
2403 ret_val = e1000_disable_pcie_master_generic(hw);
2405 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2407 DEBUGOUT("Masking off all interrupts\n");
2408 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2409 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2410 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2411 E1000_WRITE_FLUSH(hw);
2415 /* Determine whether or not a global dev reset is requested */
2416 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2418 global_device_reset = FALSE;
2420 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2421 E1000_STAT_DEV_RST_SET))
2422 ctrl |= E1000_CTRL_DEV_RST;
2424 ctrl |= E1000_CTRL_RST;
2426 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2428 switch (hw->device_id) {
2429 case E1000_DEV_ID_DH89XXCC_SGMII:
2432 E1000_WRITE_FLUSH(hw);
2436 /* Add delay to insure DEV_RST or RST has time to complete */
2439 ret_val = e1000_get_auto_rd_done_generic(hw);
2442 * When auto config read does not complete, do not
2443 * return with an error. This can happen in situations
2444 * where there is no eeprom and prevents getting link.
2446 DEBUGOUT("Auto Read Done did not complete\n");
2449 /* clear global device reset status bit */
2450 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2452 /* Clear any pending interrupt events. */
2453 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2454 E1000_READ_REG(hw, E1000_ICR);
2456 ret_val = e1000_reset_mdicnfg_82580(hw);
2458 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2460 /* Install any alternate MAC address into RAR0 */
2461 ret_val = e1000_check_alt_mac_addr_generic(hw);
2463 /* Release semaphore */
2464 if (global_device_reset)
2465 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2471 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2472 * @data: data received by reading RXPBS register
2474 * The 82580 uses a table based approach for packet buffer allocation sizes.
2475 * This function converts the retrieved value into the correct table value
2476 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2477 * 0x0 36 72 144 1 2 4 8 16
2478 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2480 u16 e1000_rxpbs_adjust_82580(u32 data)
2484 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2485 ret_val = e1000_82580_rxpbs_table[data];
2491 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2493 * @hw: pointer to the HW structure
2494 * @offset: offset in words of the checksum protected region
2496 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2497 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2499 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2501 s32 ret_val = E1000_SUCCESS;
2505 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2507 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2508 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2510 DEBUGOUT("NVM Read Error\n");
2513 checksum += nvm_data;
2516 if (checksum != (u16) NVM_SUM) {
2517 DEBUGOUT("NVM Checksum Invalid\n");
2518 ret_val = -E1000_ERR_NVM;
2527 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2529 * @hw: pointer to the HW structure
2530 * @offset: offset in words of the checksum protected region
2532 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2533 * up to the checksum. Then calculates the EEPROM checksum and writes the
2534 * value to the EEPROM.
2536 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2542 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2544 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2545 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2547 DEBUGOUT("NVM Read Error while updating checksum.\n");
2550 checksum += nvm_data;
2552 checksum = (u16) NVM_SUM - checksum;
2553 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2556 DEBUGOUT("NVM Write Error while updating checksum.\n");
2563 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2564 * @hw: pointer to the HW structure
2566 * Calculates the EEPROM section checksum by reading/adding each word of
2567 * the EEPROM and then verifies that the sum of the EEPROM is
2570 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2573 u16 eeprom_regions_count = 1;
2577 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2579 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2581 DEBUGOUT("NVM Read Error\n");
2585 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2586 /* if chekcsums compatibility bit is set validate checksums
2587 * for all 4 ports. */
2588 eeprom_regions_count = 4;
2591 for (j = 0; j < eeprom_regions_count; j++) {
2592 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2593 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2595 if (ret_val != E1000_SUCCESS)
2604 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2605 * @hw: pointer to the HW structure
2607 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2608 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2609 * checksum and writes the value to the EEPROM.
2611 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2617 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2619 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2621 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2625 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2626 /* set compatibility bit to validate checksums appropriately */
2627 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2628 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2631 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2636 for (j = 0; j < 4; j++) {
2637 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2638 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2648 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2649 * @hw: pointer to the HW structure
2651 * Calculates the EEPROM section checksum by reading/adding each word of
2652 * the EEPROM and then verifies that the sum of the EEPROM is
2655 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2657 s32 ret_val = E1000_SUCCESS;
2661 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2663 for (j = 0; j < 4; j++) {
2664 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2665 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2667 if (ret_val != E1000_SUCCESS)
2676 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2677 * @hw: pointer to the HW structure
2679 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2680 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2681 * checksum and writes the value to the EEPROM.
2683 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2685 s32 ret_val = E1000_SUCCESS;
2689 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2691 for (j = 0; j < 4; j++) {
2692 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2693 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2694 if (ret_val != E1000_SUCCESS)
2703 * __e1000_access_emi_reg - Read/write EMI register
2704 * @hw: pointer to the HW structure
2705 * @addr: EMI address to program
2706 * @data: pointer to value to read/write from/to the EMI address
2707 * @read: boolean flag to indicate read or write
2709 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2710 u16 *data, bool read)
2714 DEBUGFUNC("__e1000_access_emi_reg");
2716 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2721 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2723 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2729 * e1000_read_emi_reg - Read Extended Management Interface register
2730 * @hw: pointer to the HW structure
2731 * @addr: EMI address to program
2732 * @data: value to be read from the EMI address
2734 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2736 DEBUGFUNC("e1000_read_emi_reg");
2738 return __e1000_access_emi_reg(hw, addr, data, TRUE);
2742 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2743 * @hw: pointer to the HW structure
2745 * Initialize Marvell 1512 to work correctly with Avoton.
2747 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2749 struct e1000_phy_info *phy = &hw->phy;
2750 s32 ret_val = E1000_SUCCESS;
2752 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2754 /* Check if this is correct PHY. */
2755 if (phy->id != M88E1512_E_PHY_ID)
2758 /* Switch to PHY page 0xFF. */
2759 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2763 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2767 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2771 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2775 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2779 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2783 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2787 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2791 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2795 /* Switch to PHY page 0xFB. */
2796 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2800 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2804 /* Switch to PHY page 0x12. */
2805 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2809 /* Change mode to SGMII-to-Copper */
2810 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2814 /* Return the PHY to page 0. */
2815 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2819 ret_val = phy->ops.commit(hw);
2821 DEBUGOUT("Error committing the PHY changes\n");
2831 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2832 * @hw: pointer to the HW structure
2834 * Initialize Marvell 1543 to work correctly with Avoton.
2836 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2838 struct e1000_phy_info *phy = &hw->phy;
2839 s32 ret_val = E1000_SUCCESS;
2841 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2843 /* Check if this is correct PHY. */
2844 if (phy->id != M88E1543_E_PHY_ID)
2847 /* Switch to PHY page 0xFF. */
2848 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2872 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2876 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2880 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2884 /* Switch to PHY page 0xFB. */
2885 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2889 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2893 /* Switch to PHY page 0x12. */
2894 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2898 /* Change mode to SGMII-to-Copper */
2899 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2903 /* Switch to PHY page 1. */
2904 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2908 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2909 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2913 /* Return the PHY to page 0. */
2914 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2918 ret_val = phy->ops.commit(hw);
2920 DEBUGOUT("Error committing the PHY changes\n");
2930 * e1000_set_eee_i350 - Enable/disable EEE support
2931 * @hw: pointer to the HW structure
2932 * @adv1g: boolean flag enabling 1G EEE advertisement
2933 * @adv100m: boolean flag enabling 100M EEE advertisement
2935 * Enable/disable EEE based on setting in dev_spec structure.
2938 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2942 DEBUGFUNC("e1000_set_eee_i350");
2944 if ((hw->mac.type < e1000_i350) ||
2945 (hw->phy.media_type != e1000_media_type_copper))
2947 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2948 eeer = E1000_READ_REG(hw, E1000_EEER);
2950 /* enable or disable per user setting */
2951 if (!(hw->dev_spec._82575.eee_disable)) {
2952 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2955 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2957 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2960 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2962 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2964 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2967 /* This bit should not be set in normal operation. */
2968 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2969 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2971 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2972 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2975 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2976 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2977 E1000_READ_REG(hw, E1000_IPCNFG);
2978 E1000_READ_REG(hw, E1000_EEER);
2981 return E1000_SUCCESS;
2985 * e1000_set_eee_i354 - Enable/disable EEE support
2986 * @hw: pointer to the HW structure
2987 * @adv1g: boolean flag enabling 1G EEE advertisement
2988 * @adv100m: boolean flag enabling 100M EEE advertisement
2990 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2993 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2995 struct e1000_phy_info *phy = &hw->phy;
2996 s32 ret_val = E1000_SUCCESS;
2999 DEBUGFUNC("e1000_set_eee_i354");
3001 if ((hw->phy.media_type != e1000_media_type_copper) ||
3002 ((phy->id != M88E1543_E_PHY_ID) &&
3003 (phy->id != M88E1512_E_PHY_ID)))
3006 if (!hw->dev_spec._82575.eee_disable) {
3007 /* Switch to PHY page 18. */
3008 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3012 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3017 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3018 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3023 /* Return the PHY to page 0. */
3024 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3028 /* Turn on EEE advertisement. */
3029 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3030 E1000_EEE_ADV_DEV_I354,
3036 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3038 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3041 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3043 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3045 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3046 E1000_EEE_ADV_DEV_I354,
3049 /* Turn off EEE advertisement. */
3050 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3051 E1000_EEE_ADV_DEV_I354,
3056 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3057 E1000_EEE_ADV_1000_SUPPORTED);
3058 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3059 E1000_EEE_ADV_DEV_I354,
3068 * e1000_get_eee_status_i354 - Get EEE status
3069 * @hw: pointer to the HW structure
3070 * @status: EEE status
3072 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
3075 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3077 struct e1000_phy_info *phy = &hw->phy;
3078 s32 ret_val = E1000_SUCCESS;
3081 DEBUGFUNC("e1000_get_eee_status_i354");
3083 /* Check if EEE is supported on this device. */
3084 if ((hw->phy.media_type != e1000_media_type_copper) ||
3085 ((phy->id != M88E1543_E_PHY_ID) &&
3086 (phy->id != M88E1512_E_PHY_ID)))
3089 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3090 E1000_PCS_STATUS_DEV_I354,
3095 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3096 E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
3102 /* Due to a hw errata, if the host tries to configure the VFTA register
3103 * while performing queries from the BMC or DMA, then the VFTA in some
3104 * cases won't be written.
3108 * e1000_clear_vfta_i350 - Clear VLAN filter table
3109 * @hw: pointer to the HW structure
3111 * Clears the register array which contains the VLAN filter table by
3112 * setting all the values to 0.
3114 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3119 DEBUGFUNC("e1000_clear_vfta_350");
3121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3122 for (i = 0; i < 10; i++)
3123 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3125 E1000_WRITE_FLUSH(hw);
3130 * e1000_write_vfta_i350 - Write value to VLAN filter table
3131 * @hw: pointer to the HW structure
3132 * @offset: register offset in VLAN filter table
3133 * @value: register value written to VLAN filter table
3135 * Writes value at the given offset in the register array which stores
3136 * the VLAN filter table.
3138 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3142 DEBUGFUNC("e1000_write_vfta_350");
3144 for (i = 0; i < 10; i++)
3145 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3147 E1000_WRITE_FLUSH(hw);
3152 * e1000_set_i2c_bb - Enable I2C bit-bang
3153 * @hw: pointer to the HW structure
3155 * Enable I2C bit-bang interface
3158 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3160 s32 ret_val = E1000_SUCCESS;
3161 u32 ctrl_ext, i2cparams;
3163 DEBUGFUNC("e1000_set_i2c_bb");
3165 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3166 ctrl_ext |= E1000_CTRL_I2C_ENA;
3167 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3168 E1000_WRITE_FLUSH(hw);
3170 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3171 i2cparams |= E1000_I2CBB_EN;
3172 i2cparams |= E1000_I2C_DATA_OE_N;
3173 i2cparams |= E1000_I2C_CLK_OE_N;
3174 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3175 E1000_WRITE_FLUSH(hw);
3181 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3182 * @hw: pointer to hardware structure
3183 * @byte_offset: byte offset to read
3184 * @dev_addr: device address
3187 * Performs byte read operation over I2C interface at
3188 * a specified device address.
3190 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3191 u8 dev_addr, u8 *data)
3193 s32 status = E1000_SUCCESS;
3200 DEBUGFUNC("e1000_read_i2c_byte_generic");
3202 swfw_mask = E1000_SWFW_PHY0_SM;
3205 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3207 status = E1000_ERR_SWFW_SYNC;
3211 e1000_i2c_start(hw);
3213 /* Device Address and write indication */
3214 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3215 if (status != E1000_SUCCESS)
3218 status = e1000_get_i2c_ack(hw);
3219 if (status != E1000_SUCCESS)
3222 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3223 if (status != E1000_SUCCESS)
3226 status = e1000_get_i2c_ack(hw);
3227 if (status != E1000_SUCCESS)
3230 e1000_i2c_start(hw);
3232 /* Device Address and read indication */
3233 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3234 if (status != E1000_SUCCESS)
3237 status = e1000_get_i2c_ack(hw);
3238 if (status != E1000_SUCCESS)
3241 status = e1000_clock_in_i2c_byte(hw, data);
3242 if (status != E1000_SUCCESS)
3245 status = e1000_clock_out_i2c_bit(hw, nack);
3246 if (status != E1000_SUCCESS)
3253 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3255 e1000_i2c_bus_clear(hw);
3257 if (retry < max_retry)
3258 DEBUGOUT("I2C byte read error - Retrying.\n");
3260 DEBUGOUT("I2C byte read error.\n");
3262 } while (retry < max_retry);
3264 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3272 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3273 * @hw: pointer to hardware structure
3274 * @byte_offset: byte offset to write
3275 * @dev_addr: device address
3276 * @data: value to write
3278 * Performs byte write operation over I2C interface at
3279 * a specified device address.
3281 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3282 u8 dev_addr, u8 data)
3284 s32 status = E1000_SUCCESS;
3289 DEBUGFUNC("e1000_write_i2c_byte_generic");
3291 swfw_mask = E1000_SWFW_PHY0_SM;
3293 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3294 status = E1000_ERR_SWFW_SYNC;
3295 goto write_byte_out;
3299 e1000_i2c_start(hw);
3301 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3302 if (status != E1000_SUCCESS)
3305 status = e1000_get_i2c_ack(hw);
3306 if (status != E1000_SUCCESS)
3309 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3310 if (status != E1000_SUCCESS)
3313 status = e1000_get_i2c_ack(hw);
3314 if (status != E1000_SUCCESS)
3317 status = e1000_clock_out_i2c_byte(hw, data);
3318 if (status != E1000_SUCCESS)
3321 status = e1000_get_i2c_ack(hw);
3322 if (status != E1000_SUCCESS)
3329 e1000_i2c_bus_clear(hw);
3331 if (retry < max_retry)
3332 DEBUGOUT("I2C byte write error - Retrying.\n");
3334 DEBUGOUT("I2C byte write error.\n");
3335 } while (retry < max_retry);
3337 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3345 * e1000_i2c_start - Sets I2C start condition
3346 * @hw: pointer to hardware structure
3348 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3350 static void e1000_i2c_start(struct e1000_hw *hw)
3352 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3354 DEBUGFUNC("e1000_i2c_start");
3356 /* Start condition must begin with data and clock high */
3357 e1000_set_i2c_data(hw, &i2cctl, 1);
3358 e1000_raise_i2c_clk(hw, &i2cctl);
3360 /* Setup time for start condition (4.7us) */
3361 usec_delay(E1000_I2C_T_SU_STA);
3363 e1000_set_i2c_data(hw, &i2cctl, 0);
3365 /* Hold time for start condition (4us) */
3366 usec_delay(E1000_I2C_T_HD_STA);
3368 e1000_lower_i2c_clk(hw, &i2cctl);
3370 /* Minimum low period of clock is 4.7 us */
3371 usec_delay(E1000_I2C_T_LOW);
3376 * e1000_i2c_stop - Sets I2C stop condition
3377 * @hw: pointer to hardware structure
3379 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3381 static void e1000_i2c_stop(struct e1000_hw *hw)
3383 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3385 DEBUGFUNC("e1000_i2c_stop");
3387 /* Stop condition must begin with data low and clock high */
3388 e1000_set_i2c_data(hw, &i2cctl, 0);
3389 e1000_raise_i2c_clk(hw, &i2cctl);
3391 /* Setup time for stop condition (4us) */
3392 usec_delay(E1000_I2C_T_SU_STO);
3394 e1000_set_i2c_data(hw, &i2cctl, 1);
3396 /* bus free time between stop and start (4.7us)*/
3397 usec_delay(E1000_I2C_T_BUF);
3401 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3402 * @hw: pointer to hardware structure
3403 * @data: data byte to clock in
3405 * Clocks in one byte data via I2C data/clock
3407 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3412 DEBUGFUNC("e1000_clock_in_i2c_byte");
3415 for (i = 7; i >= 0; i--) {
3416 e1000_clock_in_i2c_bit(hw, &bit);
3420 return E1000_SUCCESS;
3424 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3425 * @hw: pointer to hardware structure
3426 * @data: data byte clocked out
3428 * Clocks out one byte data via I2C data/clock
3430 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3432 s32 status = E1000_SUCCESS;
3437 DEBUGFUNC("e1000_clock_out_i2c_byte");
3439 for (i = 7; i >= 0; i--) {
3440 bit = (data >> i) & 0x1;
3441 status = e1000_clock_out_i2c_bit(hw, bit);
3443 if (status != E1000_SUCCESS)
3447 /* Release SDA line (set high) */
3448 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3450 i2cctl |= E1000_I2C_DATA_OE_N;
3451 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3452 E1000_WRITE_FLUSH(hw);
3458 * e1000_get_i2c_ack - Polls for I2C ACK
3459 * @hw: pointer to hardware structure
3461 * Clocks in/out one bit via I2C data/clock
3463 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3465 s32 status = E1000_SUCCESS;
3467 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3471 DEBUGFUNC("e1000_get_i2c_ack");
3473 e1000_raise_i2c_clk(hw, &i2cctl);
3475 /* Minimum high period of clock is 4us */
3476 usec_delay(E1000_I2C_T_HIGH);
3478 /* Wait until SCL returns high */
3479 for (i = 0; i < timeout; i++) {
3481 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3482 if (i2cctl & E1000_I2C_CLK_IN)
3485 if (!(i2cctl & E1000_I2C_CLK_IN))
3486 return E1000_ERR_I2C;
3488 ack = e1000_get_i2c_data(&i2cctl);
3490 DEBUGOUT("I2C ack was not received.\n");
3491 status = E1000_ERR_I2C;
3494 e1000_lower_i2c_clk(hw, &i2cctl);
3496 /* Minimum low period of clock is 4.7 us */
3497 usec_delay(E1000_I2C_T_LOW);
3503 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3504 * @hw: pointer to hardware structure
3505 * @data: read data value
3507 * Clocks in one bit via I2C data/clock
3509 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3511 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3513 DEBUGFUNC("e1000_clock_in_i2c_bit");
3515 e1000_raise_i2c_clk(hw, &i2cctl);
3517 /* Minimum high period of clock is 4us */
3518 usec_delay(E1000_I2C_T_HIGH);
3520 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3521 *data = e1000_get_i2c_data(&i2cctl);
3523 e1000_lower_i2c_clk(hw, &i2cctl);
3525 /* Minimum low period of clock is 4.7 us */
3526 usec_delay(E1000_I2C_T_LOW);
3528 return E1000_SUCCESS;
3532 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3533 * @hw: pointer to hardware structure
3534 * @data: data value to write
3536 * Clocks out one bit via I2C data/clock
3538 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3541 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3543 DEBUGFUNC("e1000_clock_out_i2c_bit");
3545 status = e1000_set_i2c_data(hw, &i2cctl, data);
3546 if (status == E1000_SUCCESS) {
3547 e1000_raise_i2c_clk(hw, &i2cctl);
3549 /* Minimum high period of clock is 4us */
3550 usec_delay(E1000_I2C_T_HIGH);
3552 e1000_lower_i2c_clk(hw, &i2cctl);
3554 /* Minimum low period of clock is 4.7 us.
3555 * This also takes care of the data hold time.
3557 usec_delay(E1000_I2C_T_LOW);
3559 status = E1000_ERR_I2C;
3560 DEBUGOUT1("I2C data was not set to %X\n", data);
3566 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3567 * @hw: pointer to hardware structure
3568 * @i2cctl: Current value of I2CCTL register
3570 * Raises the I2C clock line '0'->'1'
3572 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3574 DEBUGFUNC("e1000_raise_i2c_clk");
3576 *i2cctl |= E1000_I2C_CLK_OUT;
3577 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3578 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3579 E1000_WRITE_FLUSH(hw);
3581 /* SCL rise time (1000ns) */
3582 usec_delay(E1000_I2C_T_RISE);
3586 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3587 * @hw: pointer to hardware structure
3588 * @i2cctl: Current value of I2CCTL register
3590 * Lowers the I2C clock line '1'->'0'
3592 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3595 DEBUGFUNC("e1000_lower_i2c_clk");
3597 *i2cctl &= ~E1000_I2C_CLK_OUT;
3598 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3599 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3600 E1000_WRITE_FLUSH(hw);
3602 /* SCL fall time (300ns) */
3603 usec_delay(E1000_I2C_T_FALL);
3607 * e1000_set_i2c_data - Sets the I2C data bit
3608 * @hw: pointer to hardware structure
3609 * @i2cctl: Current value of I2CCTL register
3610 * @data: I2C data value (0 or 1) to set
3612 * Sets the I2C data bit
3614 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3616 s32 status = E1000_SUCCESS;
3618 DEBUGFUNC("e1000_set_i2c_data");
3621 *i2cctl |= E1000_I2C_DATA_OUT;
3623 *i2cctl &= ~E1000_I2C_DATA_OUT;
3625 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3626 *i2cctl |= E1000_I2C_CLK_OE_N;
3627 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3628 E1000_WRITE_FLUSH(hw);
3630 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3631 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3633 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3634 if (data != e1000_get_i2c_data(i2cctl)) {
3635 status = E1000_ERR_I2C;
3636 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3643 * e1000_get_i2c_data - Reads the I2C SDA data bit
3644 * @hw: pointer to hardware structure
3645 * @i2cctl: Current value of I2CCTL register
3647 * Returns the I2C data bit value
3649 static bool e1000_get_i2c_data(u32 *i2cctl)
3653 DEBUGFUNC("e1000_get_i2c_data");
3655 if (*i2cctl & E1000_I2C_DATA_IN)
3664 * e1000_i2c_bus_clear - Clears the I2C bus
3665 * @hw: pointer to hardware structure
3667 * Clears the I2C bus by sending nine clock pulses.
3668 * Used when data line is stuck low.
3670 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3672 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3675 DEBUGFUNC("e1000_i2c_bus_clear");
3677 e1000_i2c_start(hw);
3679 e1000_set_i2c_data(hw, &i2cctl, 1);
3681 for (i = 0; i < 9; i++) {
3682 e1000_raise_i2c_clk(hw, &i2cctl);
3684 /* Min high period of clock is 4us */
3685 usec_delay(E1000_I2C_T_HIGH);
3687 e1000_lower_i2c_clk(hw, &i2cctl);
3689 /* Min low period of clock is 4.7us*/
3690 usec_delay(E1000_I2C_T_LOW);
3693 e1000_i2c_start(hw);
3695 /* Put the i2c bus back to default state */